APA2057A

APA2057A
2.4W Stereo Audio Power Amplifier (with Gain Setting) & Capfree Headphone Driver Features General Description
The APA2057A is a monolithic integrated circuit, which combines a stereo power amplifier and a stereo output capacitor-less headphone amplifier. The stereo power amplifier provides 19-steps gain setting for flexible application. The headphone amplifier is ground-reference output, and no need the output capacitors for DC blocking. The advantages of eliminating the output capacitor are saving the cost, PCB s space and component height. Both the de-pop circuitry and the thermal shutdown protection circuitry are integrated in the APA2057A, which reduces pops and clicks noise during power on/ off and in shutdown mode. Thermal shutdown protects the chip from being destroyed by over-temperature failure. To simplify the audio system design in notebook computer applications, the APA2057A provides the internal gain setting, and these features can minimize components and PCB area. The APA2057A is available in both TSSOP-28P and TQFN5x5-28 packages. Both packages are characterized by space saving and thermal efficiency.
Operating Voltage HVDD= 3.0~3.6V VDD= 4.5~5.5V No Output Capacitor at Headphone Amplifier Required Meeting VISTA Requirement Low Distortion AMP mode THD+N=56dB, at VDD = 5V, RL = 4, PO=1.5W THD+N=64dB, at VDD = 5V, RL = 8, PO=0.9W HP mode THD+N=73dB, at HVDD=3.3V, RL=16 PO=125mW THD+N=77dB, at HVDD=3.3V, RL=32, PO=88mW THD+N=85dB, at HVDD=3.3V, RL=10k, VO=1.7Vrms Output Power at 1% THD+N 1.9W, at VDD = 5V, AMP mode, RL = 4 1.2W, at VDD = 5V, AMP mode, RL = 8 at 10% THD+N 2.4W at VDD = 5V, AMP mode, RL = 4 1.5W at VDD = 5V, AMP mode, RL = 8 Depop Circuitry Integrated Internal 19-steps Gain Setting for Flexible Application Thermal Shutdown Protection and Over Current Protection Circuitry High Supply Voltage Ripple Rejection Surface-Mount Packaging TSSOP-28P (with enhanced thermal pad) TQFN5x5-28 (with enhanced thermal pad) Lead Free Available (RoHS Compliant)
Applications
Note book PCs LCD monitor
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007 1 www.anpec.com.tw
APA2057A
Ordering and Marking Information
APA2057A Lead Free Code Handling Code Temperature Range Package Code APA2057A R :
APA2057A XXXXX
Package Code R : TSSOP-28P QB : TQFN5x5-28 Operating Ambient Temperature Range I : -40 to 85 C Handling Code TR : Tape & Reel Lead Free Code L : Lead Free Device XXXXX - Date Code XXXXX - Date Code
APA2057A QB :
APA2057A XXXXX
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the leadfree requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
Pin Configurations
28 INR_H 27 INR_A 26 GND 23 AMP_EN 25 VDD 24 BEEP VDD 1 GND 2 INR_A 3 INR_H 4 INL_A 5 INL_H 6 PGND 7 LOUT+ 8 LOUT- 9 PVDD 10 CVDD 11 CP+ 12 CGND 13 CP- 14 APA2057A 28 BEEP 27 AMP_EN 26 SET 25 BIAS 24 HP_EN 23 PGND 22 ROUT+ 21 ROUT20 PVDD 19 HVDD 18 HP_L 17 HP_R CP+ 8 CGND 9 CP- 10 CVSS 11 HVSS 12 HP_R 13 HP_L 14 16 HVSS 15 CVSS INL_A 1 INL_H 2 PGND 3 LOUT+ 4 LOUT- 5 PVDD 6 CVDD 7 APA2057A 21 BIAS 20 HP_EN 19 PGND 18 ROUT+ 17 ROUT16 PVDD 15 HVDD 22 SET
(TSSOP-28P) (Top view)
(TQFN5x5-28) (Top view)
= ThermalPad (connected the ThermalPad to GND plane for better heat dissipation)
Absolute Maximum Ratings (Note 1)

(Over operating free-air temperature range unless otherwise noted.)
Symbol VDD HVDD, VSS VSET, VAMP_EN, VHP_EN TA TJ Parameter Supply Voltage (PVDD, CVDD, VDD) Supply Voltage (HVDD) Supply Voltage (VSS) Input Voltage Operating Ambient Temperature Range Maximum Junction Temperature Rating -0.3 to 6 +0.3 to -6 0 to VDD+0.3V -40 to 85 150 C C Unit V V
Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007
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APA2057A
Absolute Maximum Ratings (Cont.)
Symbol TSTG TSDR PD Parameter Storage Temperature Range Maximum Lead Soldering Temperature Power Dissipation
(Note 1)
(Over operating free-air temperature range unless otherwise noted.)

Rating -65 to +150 260, 10 seconds Internally Limited Unit C C W
Note 1 : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol
(Note 2)
Parameter Value 45 43 Unit
o
JA
Thermal Resistance - Junction to Ambient (Note 2) TSSOP-28P TQFN5x5-28
C/W
Note 2 : 3.42 in2 printed circuit board with 2OZ trace and copper through 10 vias of 15mil diameter vias. The thermal pad on the TSSOP-28P & TQFN-28 packages with solder on the printed circuit board.
Recommended Operating Conditions

Min. Supply voltage, VDD Supply voltage, HVDD High level threshold voltage, VIH Low level threshold voltage, VIL Common mode input voltage, Vicm AMP_EN, HP_EN AMP_EN, HP_EN for Amplifier for Headphone Amplifier Shutdown Input Voltage (VSET) Gain Setting Fix Gain 2 4.5 4.5 3.0 2 0.8 VDD-1 HVDD-1 0.8 4.2 V V Max. 5.5 3.6 Unit V V V V V V
Electrical Characteristics
VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25C (unless otherwise noted).
APA2057A Min. 4.5 3.0 Only Speaker mode, AMP_EN = HP_EN = 0V Only Headphone mode, HP_EN = AMP_EN = 5V All Enable, HP_EN=5V and AMP_EN = 0V 17.5 0.15 12 3 20 3 Typ. Max. 5.5 3.6 29 1 20 5 35 5 mA
Symbol VDD HVDD IVDD IHVDD IVDD IHVDD IVDD IHVDD
Parameter Supply Voltage Headphone Amplifier supply voltage VDD Supply Current HVDD Supply Current VDD Supply Current HVDD Supply Current VDD Supply Current HVDD Supply Current
Test Condition
Unit V V
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APA2057A
Electrical Characteristics (Cont.)
Symbol ISD(HVDD) ISD(VDD) IAMP_EN IHP_EN Speaker mode THD+N =1%, Fin =1KHz RL =4 RL =8 THD+N =10%, Fin =1KHz RL =4 RL =8 RL =8, Gain =10.5dB Fin =1KHz PO = 1.5W, RL =4 PO = 0.9W, RL =8 Fin =1KHz, CB=2.2F, RL=8, PO=0.92W Fin =1KHz, CB=2.2F, RL =4, PO=1.5W CB =2.2F, RL =8, Fin =120Hz PO =0.8W, RL =8, A-weighted Filter Noise Output Voltage Gain =10.5dB, RL =8, CB =2.2F 0.15 0.06 80 83 70 90 80 dB dB V (rms) 1.9 1.2 2.4 1.5 10 mV % Parameter HVDD Shutdown Current VDD Shutdown Current Input current Input current Test Condition APA2057A Min. Typ. 50 1 1 10 15 Max. 90 10 Unit A A A
SET = 0V AMP_EN HP_EN,
PO
Output Power
1.0
1.3
VOS THD+N
Output Offset Voltage Total Harmonic Distortion plus Noise Channel Separation Power Supply Rejection Ratio
X talk PSRR S/N Vn
dB
Headphone mode THD+N = 1%, Fin =1KHz RL = 16 RL = 32 THD+N = 10%, Fin =1KHz RL =16 RL =32 RL =10K RL =32 Fin = 1KHz THD+N Total Harmonic Distortion plus Noise PO = 125mW, RL =16 PO = 88mW, RL =32 VO=1.7Vrms, RL=10k Fin =1KHz, RL =16, PO =125mW X talk Channel Separation Fin =1KHz, RL =32, PO =88mW Fin =1KHz, RL=10K, VO =1.7Vrms PSRR Power Supply Rejection Ratio CB = 2.2F, RL=32, Fin =120Hz 0.02 0.02 0.005 80 85 105 80 dB dB % THD+N=10% THD+N=1% -10 160 120 200 165 2.9 2.4 +10 Vrms mV
Po
Output Power
100
mW
150
Vo Vos
Output Voltage Swing Output Offset Voltage
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APA2057A
Electrical Characteristics (Cont.)
Symbol Headphone mode (Cont.) With A-weighted Filter S/N PO = 70mW, RL =32 VO =1.2Vrms, RL=10k Vn Rf Charge Pump Fosc CVSS Switching frequency Charge Dump Output Voltage (CVSS) Charge pump requirement resistance No load 460 540 -0.98 VDD 9 12 620 KHz V Noise Output Voltage Input Feedback Resistance CB =2.2F 38 95 92 30 40 42 V (rms) k dB Parameter Test Condition APA2057A Min. Typ. Max. Unit
Req Beep Vbeep TRES Attenuation Att(HP_EN)
Beep trigger level Beep response time RL = 32, VO = 1.1Vrms, Fin = 1KHz RL = 10K, VO = 1.1Vrms, Fin = 1KHz RL = 8, VO = 2Vrms, Fin = 1KHz RL = 4, VO = 2Vrms, Fin = 1KHz RL = 10K on the Headphone Mode, VO = 1.1Vrms, Fin = 1KHz RL = 8 on the AMP Mode, VO = 1Vrms, Fin = 1KHz AMP_EN = 0V, RL = 8
3 4
VPP ms
HP disable attenuation AMP disable attenuation Shutdown active
115 85 112 112 90
dB dB dB dB dB
Att(AMP_EN) Att_SD(HP_EN) Att_SD(AMP_EN)
Shutdown active
100
dB
Headphone to Speaker Crosstalk HP_EN = 5V, RL = 16, Fin = 1KHz, PO = 125mW Speaker to Headphone Crosstalk HP_EN = 5V, RL = 10K X talk Channel Separation AMP_EN = 0V, RL = 4, Fin = 1KHz, PO = 1.5W Amplifier Start up Time Tstart-up Start up time 120 msec 80 dB
X talk
Channel Separation
85
dB
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APA2057A
Gain Setting Table _AMP Mode
Gain (dB) -70 -7 -5 -3 -1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 10.5 Input Voltage (V SET ) Low (V) 0 2.04 2.15 2.28 2.39 2.51 2.62 2.74 2.86 2.97 3.09 3.21 3.33 3.45 3.56 3.68 3.80 3.92 4.02 4.15 4.26 H igh (V) 2.00 2.12 2.24 2.35 2.47 2.58 2.70 2.81 2.92 3.04 3.15 3.27 3.39 3.51 3.62 3.73 3.85 3.96 4.07 4.17 5.00 Hysteresis (mV) SD 47 36 41 41 35 41 48 43 47 45 54 59 64 53 59 66 69 64 76 94
(VDD=5V)
Recommended Voltage (V) 0.00 2.08 2.20 2.31 2.43 2.54 2.66 2.78 2.89 3.01 3.12 3.24 3.36 3.48 3.59 3.70 3.82 3.94 4.05 4.16 5.00
Recommend Resistances Value for Gain Setting

Gain (dB) -70 -7 -5 -3 -1 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 10.5 R1 (1%) 10K 18K 20K 18K 16K 15K 13K 24K 13K 13K 13K 16K 13K 13K 15K 13K 13K 13K 15K 13K 10K R# (1%) 0 13K 16K 16K 15K 16K 15K 30K 18K 20K 22K 30K 27K 30K 39k 39K 43K 50K 68K 68K >90K
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APA2057A
Typical Operating Characteristics
THD+N vs. Output Power
10
VDD =5V Fin=1KHz Cin=2.2F BW<80KHz AMP mode RL=8 RL=4

10
VDD =5V RL=4 Cin=2.2F BW<80KHz AMP mode
THD+N (%)
THD+N (%)
1
Fin=20KHz Fin=20Hz
0.1
Fin=1KHz
0.05
0.5
1.5
2.5
0.1 0.01
0.1
Output Power (W)
Output Power (W)
THD+N vs. Frequency

10
VDD =5V RL=4 Cin=2.2F PO=1.5W BW<80KHz AMP mode
Crosstalk vs. Frequency

+0 -10 -20
VDD =5V RL=4 Cin=2.2 uF PO=1.5W AMP mode
Crosstalk (dB)
-30 -40 -50 -60 -70 -80 -90
THD+N (%)
Right to Left
Left to Right
Right Channel Left Channel
0.1 20
100
1k
10k 20k
-100 20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Output Noise Voltage vs. Frequency

100
Frequency Response
+11
Gain
+30 +25
Output Noise Voltage (Vrms)
+10
Gain (dB)
+9
Phase
+15 +10 +5
10
+8
1 20
VDD =5V RL=4 Cin=2.2F A-weighted AMP mode
+7 +0 +6 10 -5 100k 200k
100
1k
10k 20k
100
1k
10k
Frequency (Hz)
Frequency (Hz)
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Phase (deg)
VDD =5V Cin =2.2F RL=4 PO=0.2W AMP mode
+20
APA2057A
Typical Operating Characteristics (Cont.)
10
VDD =5V RL=8 Cin=2.2F BW<80KHz AMP mode
THD+N vs. Frequency

10
VDD =5V RL=8 Cin=2.2F PO=0.92W BW<80KHz AMP mode
THD+N (%)
THD+N (%)
Fin=20KHz
Fin=20Hz
0.1 0.05 0.01
Fin=1KHz
0.1
0.1 1 5
Left Channel Right Channel
0.05 20
100
1k
10k 20k
Output Power (W)
Frequency (Hz)

+0 -10 -20 -30
100
VDD =5V RL=8 Cin=2.2F PO=0.92W AMP mode
-40 -50 -60 -70 -80

Right to Left Left to Right
Crosstalk (dB)
10
-90 -100 20
1
VDD =5V RL=8 Cin=2.2F A-weighted AMP mode
100
1k
10k 20k
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Frequency Response
+11
Gain

+30 +25
+0 -10 -20 -30
VDD =5V RL=4Ohm (AMP) RL=10K(HP) Cin=2.2F (AMP) PO=1.5W(AMP) AMP (active) mode HP Mode Right(AMP) to Right(HP) Left(AMP) to Left(HP) Left(AMP) to Right(HP)
+10
Phase (deg)
Crosstalk (dB)
Gain (dB)
+9
VDD =5V Cin =2.2F RL=8 PO=0.13W AMP mode
+20 +15 +10 +5
-40 -50 -60 -70 -80 -90 -100 -110 -120 20
+8
+7
Phase
+0 +6 10 -5 100k 200k
Right(AMP) to Left(HP)
100
1k
10k
100
1k
10k 20k
Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007 8
Frequency (Hz) www.anpec.com.tw
APA2057A
AMP Attenuation vs. Frequency
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 20 100 1k 10k 20k
VDD =5V RL=4 Cin=2.2F VO=2Vrms(F in=1KHz, AMP enable) AMP mode (disable)
AMP Attenuation vs. Frequency

+0 -10 -20
VDD =5V RL=8 Cin=2.2F VO=2Vrms(Fin=1KHz,AMP enable) AMP mode (disable)
AMP Attenuation (dB)
AMP Attenuation (dB)
-30 -40 -50 -60 -70 -80 -90 -100 -110 -120
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Shutdown Attenuation vs. Frequency

+0 -10
Shutdown Attenuation vs. Frequency

+0 -10 R =8 L -20 Cin=2.2F -40 -50 -60 -70 -80 -90 -100 -110
VDD =5V
Shutdown Attenuation (dB)
Shutdown Attenuation (dB)
-20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 20
VDD =5V RL=4 Cin=2.2F VO=1Vrms(F in=1KHz) Shutdown active AMP mode
-30 Shutdown active

AMP mode
VO=1Vrms(F in=1KHz)
100
1k
10k 20k
-120 20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Input Voltage vs. Output Voltage

3.5 3
VDD =5V RL=4 Cin=2.2F Fin=1KHz AMP mode

4 3.5
VDD =5V RL=8 Cin=2.2F Fin=1KHz AMP mode
Output Voltage (Vrms)
3 2.5 2 1.5 1 0.5
2.5 2 1.5 1 0.5
0.3
0.6
0.9
1.2
1.5
0.3
0.6
0.9
1.2
1.5
Input Voltage (Vrms) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007 9
Input Voltage (Vrms)
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APA2057A
THD+N vs. Output Voltage
10 T
10
VDD =5V HVDD=3.3V Fin=1KHz Cin=3.3F 1 BW<80KHz HP mode

VDD =5V HVDD=3.3V RL=16 Rin=39K Cin=3.3F BW<80KHz HP mode
RL=300
1
RL=32
THD+N (%)
0.1
RL=16
THD+N (%)
Fin=20KHz
0.1
Fin=20Hz
0.01
RL=10K
0.001 0
0.5
1.5
2.5
0.01 1m
Fin=1KHz
10m
100m
300m
Output Voltage (Volt)
Output Power (W)

10
THD+N vs. Frequency

10
VDD =5V HVDD=3.3V RL=16 Rin=39K Cin=3.3F PO=125mW HP mode
THD+N (%)
THD+N (%)
VDD=5V HVDD=3.3V RL=16 Rin=39K Cin=3.3F Fin=1KHz BW<80KHz HP mode
Stereo, in phase
0.1
BW<80KHz
0.1
Stereo, 180O out of phase
BW<22KHz
Mono
0.01
250m
0.01
50m
100m
150m
200m
0.005 20
100
1k
10k 20k
Output Power (W)
Frequency (Hz)

-10 HVDD=3.3V -20 Rin=39K
RL=16
Crosstalk (dB)
Cin=3.3F
+0
VDD=5V
100
-30 PO=125mW
HP mode
Right channel
-40 -50 -60 -70 -80 -90 -100 20 100 1k 10k 20k
Right to Left Left to Right
Left channel
10
VDD =5V HVDD =3.3V RL=16 Rin=39K Cin=3.3F A-wighted HP mode
1 20
100
1k
10k 20k
Frequency (Hz)
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APA2057A
Frequency Response
+0.2 +190
10

VDD=5V HVDD=3.3V RL=32 Rin=39K Cin=3.3F BW<80KHz HP mode
+0.1
Gain
+185
Phase (deg)
-0
VDD=5V HVDD=3.3V RL=16 Rin=39K Cin=3.3F PO=28mW HP mode
Phase
+180
THD+N (%)
Gain(dB)
Fin=20KHz
0.1
-0.1
+175
Fin=20Hz Fin=1KHz
-0.2 10
100
1k
10k
+170 100k 200k
0.01 1m
10m
100m 200m
Frequency (Hz)
Output Power (W)
10

VDD=5V HVDD=3.3V RL=32 Rin=39K Cin=3.3F Fin=1KHz BW<80KHz HP mode
THD+N vs. Frequency

10
THD+N (%)
THD+N (%)
0.1
BW<80KHz
0.1
Stereo, in phase
Stereo, 180O out of phase
0.01
Mono
BW<22KHz
0.01 0
50m
100m
150m
200m
0.001 20
100
1k
10k 20k
Output Power (W)
Frequency (Hz)

+0 -10 -20

100
Output Noise Voltage (V)
Right channel Left channel
Crosstalk (dB)
-30 -40 -50 -60 -70 -80 -90 -100 20
10
VDD =5V HVDD=3.3V RL=32 Rin=39K Cin=3.3F A-wighted HP mode
Right to Left
Left to Right
100
1k
10k 20k
1 20
100
1k
10k 20k
Frequency (Hz)
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APA2057A
Frequency Response
+0.2 +190 Gain

10 VDD=5V HVDD=3.3V RL=300 Rin=39K Cin=3.3F BW<80KHz HP mode
+0.1
+185
Phase (deg)
Phase -0 +180
THD+N (%)
Gain (dB)
0.1 Fin=20KHz 0.01 Fin=20Hz
-0.1
VDD =5V HVDD=3.3V RL=32 Rin=39K Cin=3.3F PO=13mW HP mode 10 100 1k 10k
+175
Fin=1KHz
+170 100k 200k
-0.2
0.001
0.5
1.5
2.5
Frequency (Hz)
THD+N vs. Frequency

10 VDD=5V HVDD=3.3V RL=300 Rin=39K Cin=3.3F VO=1.7Vrms BW<80KHz HP mode

+0 -10 -20 -30 VDD=5V HVDD=3.3V RL=300 Rin=39K Cin=3.3F VO=1.7Vrms BW<80KHz HP mode
Crosstalk (dB)
-40 -50 -60 -70 -80 -90 -100
THD+N (%)
0.1
0.01
Right Channel
Right to Left
Left Channel 0.001
-110 -120
10k 20k
Left to Right 20 100 1k 10k 20k
20
100
1k
Frequency (Hz)
Frequency (Hz)

100
+0.4
Frequency Response
+195
Gain
Right channel Left channel 10
+0
1 20
VDD =5V HVDD=3.3V RL=300 Rin=39K Cin=3.3F A-wighted HP mode 100 1k 10k 20k
VDD =5V HVDD=3.3V RL=300 Rin=39K Cin=3.3F VO=240mVrms HP mode Phase
Gain (dB)
+185
-0.2
+180
-0.4
10
100
1k
10k
+175 100k 200k
Frequency (Hz)
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Phase (deg)
+0.2
+190
APA2057A
10
THD+N vs. Frequency

10
VDD =5V HVDD=3.3V RL=10K Rin=39K Cin=3.3F VO=1.7Vrms BW<80KHz HP mode
THD+N (%)
THD+N (%)
VDD =5V HVDD=3.3V RL=10K Rin=39K Cin=3.3F BW<80KHz HP mode
0.1
Fin=20Hz
0.1
0.01
Fin=20KHz
0.01
Right channel
Left channel
Fin=1KHz
0.001 0
0.5
1.5
2.5
0.001 20
100
1k
10k 20k
Output Voltage (Volt)
Frequency (Hz)

+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 20 100 1k 10k 20k
Right to Left Left to Right VDD=5V HVDD=3.3V RL=10K Rin=39K Cin=3.3F VO=1.7Vrms BW<80KHz HP mode

100
Right channel Left channel
Crosstalk (dB)
10
VDD=5V HVDD=3.3V RL=10K Rin=39K Cin=3.3F A-wighted HP mode
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
Frequency Response
+0.4
Gain

+195
+0 -10
VDD =5V HVDD=3.3V RL=16 (HP) RL=8(AMP) Rin=39K(HP) Cin=3.3F (HP) PO=125mW(HP) AMP (active) mode HP Mode
+0.2
Crosstalk (dB)
Phase (deg)
+0
VDD=5V HVDD=3.3V RL=10K Rin=39K Cin=3.3F VO=240mVrms HP mode Phase
+190
-20 -30 -40 -50 -60 -70 -80 -90
Gain (dB)
+185
Left (HP) to Left (AMP)
Right (HP) to Left (AMP)
-0.2
+180
Left (HP) to Right (AMP)
Right (HP) to Right (AMP)
-0.4 10
100
1k
10k
+175 100k 200k
-100 20
100
1k
10k 20k
Frequency (Hz) www.anpec.com.tw
APA2057A
HP attenuation vs. Frequency
+0 -10 -20 VDD =5V HVDD=3.3V RL=32 Cin=3.3F VO=1Vrms(Fin=1KHz HP enable) HP mode (disable)
+0 -10 -20
HP attenuation vs. Frequency

VDD =5V HVDD=3.3V RL=10K Cin=3.3F VO=1Vrms(F in=1KHz HP enable) HP mode (disable)
HP attenuation (dB)
HP attenuation (dB)
-30 -40 -50 -60 -70 -80 -90 -100 -110 -120
-30 -40 -50 -60 -70 -80
Left channel Right channel 20 100 1k 10k 20k

-90 -100
Right channel
Left channel
Frequency (Hz)
20
100
1k
10k
20k
Frequency (Hz)
Shutdown attenuation vs. Frequency

+0 -10 -20 VDD =5V HVDD=3.3V RL=32 Cin=3.3F VO=1Vrms(Fin=1KHz) Shutdown active HP mode
Shutdown attenuation vs. Frequency

+0 -10 -20 VDD =5V HVDD=3.3V RL=10K Cin=3.3F VO=1Vrms(Fin=1KHz) Shutdown active HP mode
Shutdown attenuation (dB)
-30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 20
Shutdown attenuation (dB)
-30 -40 -50 -60 -70 -80 -90 -100 -110 -120
Left channel
Left channel
Right channel 20 100 1k 10k 20k
Right channel 100 1k 10k 20k
-130
Frequency (Hz)
Frequency (Hz)

2.5

3
VDD =5V HVDD=3.3V RL=32 Rin=39K Cin=3F Fin=1KHz HP mode Mono
VDD =5V HVDD=3.3V RL=16 Rin=39K Cin=3F Fin=1KHz HP mode
Mono
2.5 2 1.5 1 0.5 0
1.5
Stereo, in phase
Stereo, in phase
0.5
0.5
1.5
2.5
0.5
1.5
2.5
Input Voltage (Vrms) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007 14
Input Voltage (Vrms) www.anpec.com.tw
APA2057A
3
VDD =5V HVDD=3.3V RL=300 Rin=39K Cin=3F Fin=1KHz HP mode

3
VDD =5V HVDD=3.3V RL=10K Rin=39K Cin=3F Fin=1KHz HP mode Mono & Stereo, in phase
Mono
2.5
2.5
Stereo, in phase
2 1.5 1 0.5 0

3
2 1.5 1 0.5 0
0.5
1.5
2.5
0.5
1.5
2.5
PSRR vs. Frequency

+0 -10 RL=4
VDD=5V Cin=2.2F
PSRR vs. Frequency

+0 -10 -20 -30
VDD =5V RL=8 Cin=2.2F Vrr=200mVrms AMP mode
-20 Vrr=200mVrms
AMP mode
-30
PSRR (dB)
-50 -60 -70 -80 -90 -100 20 100

Right channel
PSRR (dB)
-40
-40 -50 -60 -70

Right channel
Left channel Vrr: Ripple Voltage on VDD
-80 -90 -100 20
Left channel Vrr: Ripple Voltage on VDD
1k
10k 20k
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
PSRR vs. Frequency

+0 -10 -20
VDD =5V HVDD=3.3V RL=32 Rin=39K Cin=3.3F Vrr=200mVrms HP mode
PSRR vs. Frequency

+0 -10 -20
VDD =5V HVDD=3.3V RL=10K Rin=39K Cin=3.3F Vrr=200mVrms HP mode
PSRR (dB)
-40 -50 -60 -70 -80 -90 -100 20

Left channel
PSRR (dB)
-30
-30 -40 -50 -60 -70 -80
Left channel
Right channel
Vrr: Ripple Voltage on HVDD
-90
Right channel
Vrr: Ripple Voltage on HVDD
100
1k
10k 20k
-100
20
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
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APA2057A
Supply Current vs. Supply Voltage
20 18
No Load AMP Mode
Shutdown Current vs. Supply Voltage

50
Amp mode HP mode No Load
Shutdown Current (A)
Supply Current (mA)
16 14 12 10 8 6 4 2 3.0
**AMP Mode disable VDD=5V IVDD=12mA HP Mode *HP Mode disable HVDD=3.3V IHVDD=0.15mA
40
ISD(VDD) 30
20
10 ISD(HVDD)
4.5 3.5 4.0 Supply Voltage (Volt)
5.0
5.5
3.0
3.5
4.0 4.5 5.0 Supply Voltage (Volt)
5.5
Power Dissipation vs. Output Power

1.4 1.2
RL=4
Power Dissipation vs. Output Power

400 350
RL=16
Power Dissipation (W)
Power Dissipation (mW)
300 250
RL=32
1.0 0.8 0.6 0.4 0.2 0.0 0.0

VDD =5V THD+N <1% AMP mode
200 150 100 50

VDD =5V HVDD=3.3V THD+N <1% HP mode
RL=8
0.5
1.0
1.5
2.0
0 0
50
100
150
200
Output Power (W)
Output Power (mW)
Output Power vs Load Resistance & Output Power vs Load Resistance

300 250
VDD =5V HVDD=3.3V Fin=1KHz BW<80KHZ HP mode
Charge Pump Capacitance

350 300
CF=CCO=2.2F THD+D=1%; Mono & Stereo, in phase VDD =5V Fin=1KHz BW<80KHZ HP mode
Output Power (mW)
200 150 100 50 0 10
Mono, THD+N=10%
Output Power (mW)
250 200 150 100 50 0 10

CF :Charge pump flying capacitor CCO:Charge pump output capacitor CF=CCO=1F THD+N=1%; Stereo, in phase CF=CCO=1F THD+N=1%; Mono
Mono, THD+N=1%
100
1000
20
30
40
50
60
70
80
90 100
Load Resistance ( ) Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007 16
Load Resistance ( ) www.anpec.com.tw
APA2057A
Operating Waveforms
Output Transient at Turn On
Output transient at Shutdown Release
VDD
5V/div
SD
5V/div
HP_Out
10mV/div
HP_Out
10mV/div
AMP_Out ((Out+)-(Out-))
AMP_Out
20mV/div
((Out+)-(Out-))
20mV/div
20ms/div
20ms/div
Output Transient at Turn Off
Output transient at Shutdown Active
VDD
5V/div
SD
5V/div
HP_Out
10mV/div
HP_Out
10mV/div
AMP_Out ((Out+)-(Out-)) 20mV/div
AMP_Out ((Out+)-(Out-)) 20mV/div
200ms/div
20ms/div
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APA2057A
Pin Descriptions
TSSOP-28 NO. 1 2 3 4 5 6 7,23 8 9 10,20 11 12 13 14 15 16 17 18 19 21 22 24 25 26 27 28 TQFN-28 NO. 25 26 27 28 1 2 3,19 4 5 6,16 7 8 9 10 11 12 13 14 15 17 18 20 21 22 23 24 Name VDD GND INR_A INR_H INL_A INL_H PGND LOUT+ LOUTPVDD CVDD CP+ CGND CPCVSS HVSS HP_R HP_L HV DD ROUTROUT+ HP_EN BIAS SET AMP_EN BEEP Function Description Power supply for control section Ground Right channel input terminal for speaker amplifier Right channel input terminal for headphone driver Left channel input terminal for speaker amplifier Left channel input terminal for headphone driver Power ground Left channel positive output for speaker Left channel negative output for speaker Power amplifier power supply Charge pump power supply Charge pump flying capacitor positive connection Charge pump ground Charge pump flying capacitor negative connection Charge pump output, connect to the HVSS Headphone amplifier negative power supply Right channel output for headphone Left channel output for headphone Headphone amplifier positive power supply Right channel negative output for speaker Right channel positive output for speaker Headphone driver enable pin, pull high to enable headphone mode Bias voltage generator It has 19 steps gain setting control from 2.0~4.2V; pull high to 5V is 10.5dB fix gain and pull low to 0V, the APA2057A enter shutdown mode. ISD = 80A Speaker driver enable pin, pull low to enable speaker mode PC BEEP Trigger signal input
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APA2057A
Block Diagram
ROUT+ INR_A
ROUTInternal gain setting INL_A LOUT+
LOUTSET SET BIAS AMP_EN SPK EN Rf(HP_R) HP EN *40k INR_H HP_R
HP_EN
Rf(HP_L)
INL_H
*40k HP_L
CVDD CP+ CPCGND Charge Pump Power Mamagement HVDD PVDD VDD
CVSS * The internal Rf's value has 10% variation by process
HVSS
PGND
GND
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APA2057A
Typical Application Circuit
ROUT+ Ci(AMP_R) R_ch for AMP 2.2F ROUTInternal gain setting Ci(AMP_L) L_ch for AMP 2.2F VDD(5V) 10K 10nF LOUTR1 SET SET BIAS Shutdown R# AMP_EN SPK EN CB HP_EN SET Recommended for de-pop 51k 4.7nF 39K Rf(HP_L) Sleeve Ci(HP_L) L_ch for HP 3.3F CVDD VDD(5V) CCPB 1F CCPF 1F CP+ CPCGND Charge Pump Power Management HVDD PVDD VDD CS(PVDD) 39K CVDD VDD(5V) HVDD(3.3V) Ri(HP_L) INL_H HP_L *40K Tip Headphone Jack INR_H HP_R R_ch for HP Ci(HP_R) 3.3F HP EN *40K Rf(HP_R) Pull-high HP_EN to enable headohone driver Ring 2.2F 4 INL_A INR_A 4 R_CH
LOUT+ L_CH
Ri(HP_R)
10F
CS(HVDD)
CS(VDD)
R#: For the gain setting of speaker driver that you need, refer to the Gain Setting Table s recommended voltage, and setting this voltage at SET pin s voltage =5R#/(R#+10K).
0.1F
0.1F
CVSS VSS
HVSS
PGND
GND
0.1F
CCPO 1F
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APA2057A
Application Information
Amplifier Mode Operation The APA2057A has two pairs of operational amplifiers internally, which allows different amplifier configurations.
VOUT HVDD/2
OUT+ OP1
Pre-amplifier Output signal
Headphone Mode Operation

HVDD
Figure 1: APA2057A internal configuration (each channel)
The OP1 and OP2 are all differential drive configurations. The differential drive configurations doubling the voltage swing on the load. Compare with the single-ending configuration, the differential gain for each channel is 2X (Gain of SE mode). By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration commonly referred to all differential mode is established. All differential mode operation is different from the classical single-ended SE amplifier configuration where one side of its load is connected to ground. A differential amplifier design has a few distinct advantages over the SE configuration, as it provides differential drive to the load, thus it is doubling the output swing for a specified supply voltage. The output power can be 4 times greater than the SE amplifier working under the same condition. A differential configuration, similar as the one used in APA2057A, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, ROUT-, LOUT+, and LOUT-, are biased at half-supply, there is no need for DC voltage across the load. This eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration.
Cap-free Headphone amplifier Figure 2: Cap-free Operation
+
Conventional Headphone amplifier
Vbias OP2
GND
HVDD
DIFF_AMP_CONFIG
VOUT GND
OUT-
VSS
The APA2057A s headphone amplifiers uses a charge pump to invert the positive power supply (CVDD) to negative power supply (CV SS), see Figure2. The headphone amplifiers operate at this bipolar power supply (HVDD & VSS), and the outputs reference refers to the ground. This feature eliminates the output capacitor that is using in conventional single-ended headphone amplifier. The headphone amplifier internal supply voltage comes from HVDD and VSS. For good AC performance, the HVDD connected to 3.3V is recommended. It can avoid the output over voltage for line out application. Charge Pump Flying Capacitor The flying capacitor (CCPF) affects the load transient of the charge pump. If the capacitor s value is too small, then that will degrade the charge pump s current driver capability and the performance of headphone amplifier. Increasing the flying capacitor s value will improve the load transient of charge pump. It is recommend to use the low ESR ceramic capacitors (X7R type is recommended) above 1f.
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APA2057A
Application Information (Cont.)
Charge Pump Output Capacitor The output capacitor (C CPO) s value affects the power ripple directly at CVSS(VSS). Increasing the value of output capacitor reduces the power ripple. The ESR of output capacitor affects the load transient of CVSS(V SS ). Lower ESR and greater than 1 f ceramic capacitor (X7R type is recommended) is recommendation. Charge Pump Bypass Capacitor The bypass capacitor (CCPB) relates with the charge pump switching transient. The capacitor s value is same as flying capacitor (1f). Place it close to the CVDD and PGND. Headphone Detection Input
HP_R Control pin 1K Ring
drive. Both amplifier and headphone ON mode: Pull low the AMP_EN and pull high the HP_EN control pins, then turn on both speaker drivers and headphone
drivers Both amplifier and headphone OFF mode: Pull high the AMP_EN and pull low the HP_EN control pins, then turn off both speaker drivers and headphone drivers
If the AMP_EN and HP_EN are connected together, then this pin will be connected to headphone jack s control pin (Figure 3), the APA2057A is switchable between Amplifier mode (Headphone mute), or Headphone mode (Amplifier mute). Gain Setting The gain for speaker drivers can be adjustable by applying DC voltage to SET pin. The APA2057A control consists 19 step gain settings from 2.0V~ 4.2V, and the gain is from -7dB to 16dB. Each gain step corresponds to a
HP_EN HP_L
HPD_Switch
1K Sleeve Tip Headphone Detection Headphone Jack with swich
specific input voltage range, as shown in Gain Setting Table. To minimize the effect of noise on the gain setting control, which can affect the selected gain level, hysteresis and clock delay are implemented. For the highest accuracy, the voltage shown in the recommended voltage column of the table is used to select a desired gain. This recommended voltage is exactly halfway between the two nearest transitions. The amount of hysteresis corresponds to half of the step width, as shown in Figure 4. Apply 0V to SET pin will place the APA2057A into shutdown mode, and when SD =5V, it allows the speaker driver at a fixed gain (AV=10.5dB).
20 10
Forward Backward
Figure 3 HPD configurations
The HP_EN will detect the voltage. If the voltage is less than 0.8V, the headphone amplifiers will be disabled; if greater than 2V, then the headphone amplifier will be enabled. In Figure 3, phone-jack with the control pin is used and connected to HP_EN input from control pin. When a headphone plug is inserted, the HP_EN will pull high internally which enables headphone amplifiers; without headphone plug, the HP_EN is pulled to GND. Operation Mode The APA2057A amplifier has two pairs of independent amplifier. One for stereo speaker is BTL structure, and the other for headphone is cap-less structure. Each pair has independent input pin; INR_A and INA_L are for stereo speaker drivers, and INR_H and INL_H are for stereo headphone drivers. Amplifier mode operation: Pull low the AMP_EN control pin can enable the stereo speaker driver. Headphone mode operation: Pull high the HP_EN control pin can enable the cap-less headphone
22
Gain (dB)
-10 -20 -30 -40 -50 -60 -70 0.0 1.0 2.0 3. 0 4.0 5.0
DC Volume (V) Figure 4: APA2057A Gain setting vs. SET pin Voltage
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APA2057A
Gain Setting (Cont.) For headphone driver, the internal feedback resistor is 40k (Rf(HP) external, 10% variation by process), so the headphone driver s gain is set by the input resistor (Ri(HP) external), the Table 1 lists the reference gain settings with external resistor for headphone driver (HP Mode).
HP Mode Gain Setting Table for Reference Ri(HP),external *Rf(HP),internal HP OUT (V/V) HP Gain(dB) (k) (k) 62 40 0.65 -3.8 50 40 0.80 -1.9 39 40 1.03 0.2 30 40 1.33 2.5 24 40 1.67 4.4 20 40 2.00 6.0 *The internal Rf's value has 10% variation by process.
Please note that it is important to confirm the capacitor polarity in the application. Note: The headphone dirver s input is ground reference, so please check the C s polarized at design.
i(HP)
Effective Bias Capacitor, CB As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as possible. The effect of a larger bypass capacitor is improved PSRR due to increased 1.8V bias voltage stability. Typical applications employ a 5V regulator with 2.2 F and a 0.1 F bypass capacitor, which aids in supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2057A. The selection of bypass capacitors, especially C B, is thus dependent upon desired PSRR requirements and click-and-pop performance. Power Supply Decoupling, Cs The APA2057A is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is as low as possible. Power supply decoupling also prevents the oscillations causing by long lead length between the amplifier and the speaker. The optimum decoupling is achieved by using two different types of capacitor that target on different types of noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low equivalentseries-resistance (ESR) ceramic capacitor, typically 0.1 F, is placed as close as possible to the device VDD lead works best (the pin1 (V ) and pin2 (GND) s capaciDD tor must short less than 1cm). For filtering lower-frequency noise signals, a large aluminum electrolytic capacitor of 10F or greater is placed near the audio power amplifier is recommended. Shutdown Function In order to reduce power consumption while not in use, the APA2057A contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns the amplifier off when a logic low is placed on the
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Table 1: Gain Setting Table for Reference
Input Capacitor, Ci In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the minimum input impedance Ri from a high-pass filter with the corner frequency are determined by the following equation:
F C (highpass) = 1 (2 R i(MIN) C i )
(1)
The value of Ci is important to consider as it directly affects the low frequency performance of the circuit. Consider the example where R i is 10k and the specification calls for a flat bass response down to 10Hz. Equation is reconfigured as below: 1 (2) Ci = (2 R iFc) Consider to input resistance variation, the Ci is 1.6F, so one would likely choose a value in the range of 2.2 F to 3.3 F. A further consideration for this capacitor is the leakage path from the input source through the input network (R i+R f , Ci ) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor should face the amplifier input. As the DC level is held at VDD/2, which is likely higher than the source DC level.
APA2057A
Shutdown Function (Cont.) SET pin. The trigger point between a logic high and logic low level is typically 2.0V. It is the best to switch between ground and the supply VDD to provide maximum device performance. By switching the SET pin to low, the amplifier enters a low-current consumption state, I DD<80 A. Even the APA2057A is in shutdown mode, PC_BEEP will keep detecting circuit. In normal operating, SET pin is pulled to high level to keep the IC out of the shutdown mode. The SET pin should be tied to a definite voltage to avoid unwanted state changes.The wake-up time of shutdown is about 150ms, and the shutdown release s pop is caused by the operational amplifier s offset. PC-BEEP Detection The APA2057A integrates a PCBEEP circuit detection for notebook PC using. When PC-BEEP signal drives to PCBEEP input pin, PCBEEP mode is active. The APA2057A will turn on speaker drivers and the internal gain is fixed as 0dB. The PCBEEP signal becomes power levels. Note that the efficiency of the amplifier is quite low for lower power levels and rises sharply as power to the load is increased resulting in nearly flat internal power dissipation over the normal operating range. Note that the internal dissipation at full output power is less than in the half power range. Calculating the efficiency for a specific system is the key to proper power supply design. For a stereo 1W audio system with 8W loads and a 5V supply, the maximum draw on the power supply is almost 3W.
Po (W) 0.25 0.50 1.00 1.25 Efficiency (%) 31.25 47.62 66.67 78.13 IDD(A) 0.16 0.21 0.30 0.32 VPP(V) 2.00 2.83 4.00 4.47 PD (W) 0.55 0.55 0.5 0.35
**High peak voltages cause the THD D+N to increase. to increase Table 2. Efficiency vs. Output Power in 5-V/8W Differential Amplifier Systems.
A final point to remember about linear amplifiers is how to manipulate the terms in the efficiency equation to utmost advantage when possible. Note that in equation, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other words, using the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. Power Dissipation Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. Equation 8 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving a 2 specified load. V PD,MAX = DD (8) 2RL SE mode: In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus the maximum power dissipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. 2 4VDD BTL mode: PD,MAX = 2 2p RL (9)
v the amplifiers input signal. If the amplifiers in the shutdown mode, it will be out of shutdown mode whenever
input impedance is 100K on PCBEEP input pin. Speaker Driver Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power supply to the power delivered to the load. The following equations are the basis for calculating amplifier efficiency. Efficiency = Where: PO = VOrms * VOrms (V * VP ) = P RL 2RL VP VOrms = 2 2VP Psup = VDD * IDD (AVG) = VDD * RL (4) (5) (6)
PCBEEP mode is enabled. The APA2057A will return to previous setting when it is out of PC BEEP mode. The
PO Psup
(3)
Since the APA2057A is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both of equations depending on the mode of operation. Even with this substantial increasing in power dissipation, the APA2057A does not require extra heatsink. The
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Efficiency of a Differential configuration: (V * V ) PO 2VP RL (7) = P P / VDD * = Psup 2RL RL 4VDD Table 1 calculates efficiencies for four different output
APA2057A
Power Dissipation (Cont.) power dissipation from equation 9, assuming a 5Vpower supply and an 8 load, must not be greater than the power dissipation that results from the equation 9: T -T (10) PD,MAX = J,MAX A JA For TSSOP-28 package with thermal pad, the thermal resistance (JA) is equal to 45oC/W. Since the maximum junction temperature (TJ,MAX) of APA2057A is 150C and the ambient temperature (TA) is defined by the power system design, the maximum power dissipation that the IC package is able to handle can be obtained from equation10. Once the power dissipation is greater than the maximum limit (PD,MAX), either the supply voltage (V DD) must be decreased, the load impedance (R L) must be increased or the ambient temperature should be reduced. Thermal Pad Considerations The thermal pad must be connected to ground. The package with thermal pad of the APA2057A requires special attention on thermal design. If the thermal design issues are not properly addressed, the APA2057A 4 will go into thermal shutdown when driving a 4 load. The thermal pad on the bottom of the APA2057A should be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 8 to 10 vias of 15 mil or smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to conduct heat away from the thermal pad should be as large as practical. If the ambient temperature is higher than 25C, a larger copper plane or forced-air cooling will be required to keep the APA2057A junction temperature below the thermal shutdown temperature (150C). In higher ambient temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of thermal shutdown. See Demo Board Circuit Layout as an example for PCB layout.
12mil Ground plane for ThermalPAD Exposed for thermal PAD connected 240 mil 15 mil Via diameter =15mil X10 70 mil 120 mil 180 mil Via diameter =25mil X4 70 mil
Figure 5: TSSOP-28P layout recommendation
Thermal Considerations Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. In the Power Dissipation vs. Output Power graph, the APA2057A is operating at a 5V supply and a 4 speaker that 2W output power peaks are available. The vertical axis gives the information of power dissipation (PD) in the IC with respect to each output driving power (PO) on the horizontal axis. This is valuable information when attempting to estimate the heat dissipation of the IC requirements for the amplifier system. Using the power dissipation curves for a 5V/4 system, the internal dissipation in the APA2057A and maximum ambient temperatures is shown in Table 3.
Peak output power (W) 2 2 2 2 2 Average output power (W) 1.95 1.17 0.74 0.43 0.19 Power Max. TA (C) dissipation (W/channel) With thermal pad 1.25 1.25 1.19 1.05 0.8 37 37 43 55 78
Table 3: APA2057A Power information, 5V/4, Stereo, Differential mode
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APA2057A
Thermal Considerations (Cont.)
Package TSSOP-28 TQFN -28 Table 4: Thermal resistance Table JA 45C/W 43C/W
This parameter is measured with the recommended copper heat sink pattern on a 2-layer PCB, 23cm 2 i n 5 . 7 m m * 4 m m in PCB, 2oz. Copper, 100mm 2 coverage. Airflow 0 CFM the maximum ambient temperature depends on the heat sink ability of the PCB system. To calculate maximum ambient temperatures, first consideration is that the numbers from the dissipation graphs are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given JA, the maximum allowable junction temperature (TJ,Max), and the total intemal dissipation (PD), the maximum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2057A is 150C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graph.
TA,Max = TJ,Max - JAPD
(11)
150 - 45(0.8*2) = 78C (with thermal pad)

NOTE: Internal dissipation of 0.8W is estimated for a 2W system with 15-dB headroom per channel.
Table 3 shows that for some applications, no airflow is required to keep junction temperatures in the specified range. The APA2057A is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150 C to prevent IC from damage. The information in table 3 was calculated for maximum listen volume with limited distortion. When the output level is reduced, the numbers in the table change significantly. Also, using 8 speakers will dramatically increase the thermal performance by increasing amplifier efficiency.
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APA2057A
Package Information
TSSOP-28P
D SEE VIEW A
D1
EXPOS ED PAD
E1 E
E2
c 0.25 VIEW A L GAUGE PLANE SEATING PLANE

0
S Y M B O L A A1 A2 b c D D1 E E1 E2 e L 0
TSSOP-28P MILLIMETERS MIN. MAX. 1.20 0.05 0.80 0.19 0.09 9.60 3.30 6.40 BSC 4.30 1.50 0.65 BSC 0.45 0 0.75 8 0.018 0 4.50 4.00 0.169 0.059 0.026 BSC 0.030 8 0.15 1.05 0.30 0.20 9.80 7.00 0.002 0.031 0.007 0.004 0.378 0.130 0.252 BSC 0.177 0.157 MIN. INCHES MAX. 0.047 0.006 0.041 0.012 0.008 0.386 0.276
Note : 1. Followed from JEDEC MO-153 AET. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side.
27
A1
A2 A
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APA2057A
Package Information
TQFN5x5-28
D2
S Y M B O L A A1 A3 b D D2 E E2 e L
TQFN5x5-28 MILLIMETERS MIN. 0.70 0.00 0.20 REF 0.18 5.00 BSC 3.50 5.00 BSC 3.50 0.50 BSC 0.35 0.45 0.014 3.80 0.138 0.020 BSC 0.018 3.80 0.138 0.197 BSC 0.150 0.30 0.007 0.197 BSC 0.150 MAX. 0.80 0.05 MIN. 0.028 0.000 0.008 REF 0.012 INCHES MAX. 0.031 0.002
28
E2
Pin 1 Corner
b A1 A3
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APA2057A
Carrier Tape & Reel Dimensions
OD0 P0 P2 P1 A E1 F K0 B SECTION A-A T B0 A0 OD1 B A SECTION B-B
d
Application
H A
T1
T1
E1
F 7.5 0.10 K0
330.0 2.00 50 MIN. TSSOP-28P P0 4.0 0.10 Application A P1 8.0 0.10 H
16.4+2.00 13.0+0.50 1.5 MIN. -0.00 -0.20 P2 2.0 0.10 T1 D0 1.5+0.10 -0.00 C D1 1.5 MIN. d
0.30 1.75 0.10 20.2 MIN. 16.0 T 0.6+0.00 -0.40 D A0 B0
6.90 0.20 10.2 0.20 1.50 0.20 W E1 F 5.5 0.10 K0
330.0 2.00 50 MIN. TQFN5x5-28 P0 4.0 0.10 P1 12.0 0.10
16.4+2.00 13.0+0.50 1.5 MIN. -0.00 -0.20 P2 2.0 0.10 D0 1.5+0.10 -0.00 D1 1.5 MIN.
0.30 1.75 0.10 20.2 MIN. 12.0 T 0.6+0.00 -0.40 A0 B0
5.30 0.20 5.30 0.20 1.30 0.20
(mm)
Devices Per Unit

Package Type TSSOP- 28P TQFN5x5-28 Unit Tape & Reel Tape & Reel Quantity 2000 2500
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APA2057A
Reflow Condition
TP
(IR/Convection or VPR Reflow)

tp Critical Zone TL to TP Ramp-up
TL
Temperature
tL Tsmax
Tsmin Ramp-down ts Preheat
25
t 25C to Peak
Reliability Test Program

Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78
Time
Description 245C, 5 sec 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA
Classification Reflow Profiles

Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Time 25C to Peak Temperature Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds 6C/second max. 6 minutes max. Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds 6C/second max. 8 minutes max.
Notes: All temperatures refer to topside of the package. Measured on the body surface.
Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007 30 www.anpec.com.tw
APA2057A
Classification Reflow Profiles (Cont.)
Table 1. SnPb Eutectic Process Package Peak Reflow Temperatures Package Thickness <2.5 mm 2.5 mm Volume mm <350 240 +0/-5C 225 +0/-5C
3
Volume mm 350 225 +0/-5C 225 +0/-5C
Table 2. Pb-free Process Package Classification Reflow Temperatures Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0C* 260 +0C* 260 +0C* 1.6 mm 2.5 mm 260 +0C* 250 +0C* 245 +0C* 2.5 mm 250 +0C* 245 +0C* 245 +0C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level. Package Thickness
3 3 3
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
31
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Note book PCs LCD monitor

(TSSOP-28P) (Top view)

(TQFN5x5-28) (Top view)

Absolute Maximum Ratings (Note 1)

Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007

(Over operating free-air temperature range unless otherwise noted.)

Thermal Resistance - Junction to Ambient (Note 2) TSSOP-28P TQFN5x5-28

Recommended Operating Conditions

Symbol VDD HVDD IVDD IHVDD IVDD IHVDD IVDD IHVDD

Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007

SET = 0V AMP_EN HP_EN,

X talk PSRR S/N Vn

Output Voltage Swing Output Offset Voltage

Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007

Req Beep Vbeep TRES Attenuation Att(HP_EN)

HP disable attenuation AMP disable attenuation Shutdown active

115 85 112 112 90

Att(AMP_EN) Att_SD(HP_EN) Att_SD(AMP_EN)

Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007

Recommend Resistances Value for Gain Setting

Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007

THD+N vs. Output Power

Output Power (W)

Output Power (W)

THD+N vs. Frequency

Crosstalk vs. Frequency

-30 -40 -50 -60 -70 -80 -90

Right Channel Left Channel

Output Noise Voltage vs. Frequency

Output Noise Voltage (Vrms)

VDD =5V RL=4 Cin=2.2F A-weighted AMP mode

Copyright ANPEC Electronics Corp. Rev. A.1 - Aug., 2007

VDD =5V Cin =2.2F RL=4 PO=0.2W AMP mode

THD+N vs. Frequency

0.1 0.05 0.01

Left Channel Right Channel

Output Power (W)

Crosstalk vs. Frequency

Output Noise Voltage vs. Frequency

-40 -50 -60 -70 -80

Output Noise Voltage (Vrms)

VDD =5V RL=8 Cin=2.2F A-weighted AMP mode

Crosstalk vs. Frequency

VDD =5V Cin =2.2F RL=8 PO=0.13W AMP mode

+20 +15 +10 +5

-40 -50 -60 -70 -80 -90 -100 -110 -120 20

Frequency (Hz) www.anpec.com.tw

AMP Attenuation vs. Frequency

AMP Attenuation (dB)

AMP Attenuation (dB)

Shutdown Attenuation vs. Frequency

Shutdown Attenuation vs. Frequency

Shutdown Attenuation (dB)

Shutdown Attenuation (dB)

-30 Shutdown active

Input Voltage vs. Output Voltage

Input Voltage vs. Output Voltage

Output Voltage (Vrms)

Output Voltage (Vrms)

3 2.5 2 1.5 1 0.5

2.5 2 1.5 1 0.5

Input Voltage (Vrms)

THD+N vs. Output Power