SERVICE MANUAL

ELECTRONIC CASH REGISTER

MODEL ER-A440
SRV Key PRINTER : LKGIM7113RCZZ : DP-730

("U" & "A" version)

CAUTION EXTREME CAUTION MUST BE TAKEN WHEN SERVICING THIS MACHINE. EVEN THOUGH THE MODE SWITCH IS IN THE OFF POSITION, VOLTAGE IS STILL SUPPLIED TO THE ENTIRE MACHINE. WHEN WORKING ON THIS MACHINE MAKE SURE THAT THE POWER CORD IS REMOVED FROM THE WALL OUTLET. CONTENTS

CHAPTER 1. SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 CHAPTER 2. OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 CHAPTER 3. SERVICE (SRV) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 CHAPTER 4. HARDWARE DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 CHAPTER 5. TEST FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 CHAPTER 6. DOWN LOAD FUNCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-1 CHAPTER 7. SERVICE PRECAUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-1 CHAPTER 8. CIRCUIT DIAGRAM & PWB LAYOUT . . . . . . . . . . . . . . . . . . . 8-1

PARTS GUIDE

Parts marked with " " is important for maintaining the safety of the set. Be sure to replace these parts with specified ones for maintaining the safety and performance of the set.

SHARP CORPORATION

This document has been published to be used for after sales service only. The contents are subject to change without notice.

CHAPTER 1. SPECIFICATIONS
1. Appearance/Rating
1) Rating
Power source Power consumption Operating temperature Operating humidity Physical dimensions, including the drawer Weight AC 120 V 10% 50/60Hz Standby: 11.5 W Maximum: 40 W (max.) 0C~40C (32F~104F) 10%~90% (RH) 420(W) ! 427(D) ! 292(H)mm 16.5(W) ! 16.8(D) ! 11.5(H)in. 28.7 lbs (13 kg)

2. Keyboard
1) Standard keyboard layout
PLU/SUB AUTO AUTO TAX1 TAX2 1 2 SHIFT SHIFT 15 14 13 12 11 20 19 18 TAX CONV CHK FS SHIFT FS TEND CH

5 CASH
RECEIOT JOURNAL

10 9 8 7 6

WYPL2

#
NS RA

CL
@/ FOR RFND VOID

7 4 1 0

8 5 2 00

9 6 3

4 3 2 1
Fig. 2-1

PCPT PRINT
WYPL2

#
WYPL2 WYPL2

MDSE SBTL 17 SBTL 16 CA/AT

%1 %2 PO

2) Key top name

Standard Key Top KEY TOP 0 to 9,00 CL @/FOR 1 to 20 R J RCPT # AUTO 1, 2 CASH # NS % 1, 2 PO 1, 2 RA VOID PLU/SUB SBTL CH CA/AT TAX1 SHIFT TAX2 SHIFT TAX DESCRIPTION Numeric keys Decimal point key Clear key Multiplication/split-pricing key Department 1 to 20 keys Receipt Paper Feed key Journal Paper Feed key Receipt print & on/off key Non-Add Code key Automatically Entry key 1, 2 Cashier code entry key No Sales key Discount key % key 1, 2 Paid Out key Received on Account key Void key PLU/Subdept code entry key Subtotal key Charge key Cash/amount tendered TAX1 shift key TAX2 shift key Tax key 11 KEY TOP PRINT RFND CONV CHK MDSE SBTL FS SHIFT FS TEND DESCRIPTION Validation print key Refund key Currency conversion key Check key Merchandise subtotal key Food stamp shift key Food stamp tendered key

Optional Key Top KEY TOP % 3, 4 2, 3, 4 AUTO 3 10 CA 2 CH 2 5 CR 3, 4 21 to 50 TAX3 SHIFT TAX4 SHIFT RA2 PO2 CONV2 4 CHK2 RFND SALE BIRTH 1 to 68 DESCRIPTION % key 3, 4 Discount key 2, 3, 4 Automatically entry key 3 10 Cash total 2 key Charge key 2 5 Credit key 3, 4 Department 21 to 50 key TAX3 shift key TAX4 shift key Received on account key 2 Paid out key 2 Currency conversion key 2 4 Check key 2 Refund sales key Birthday key Direct price lookup/Subdepartment keys

3. Mode switch
SRV MA SM OP
REG OP,X/Z OFF PGM1 PGM2 (SRV) (SRV') MGR X1/Z1 X2/Z2

Customer display (Pop-up display)

Fig. 4-2 7 segment display (LED) No. of positions Color of display Character size Display contents Display Position 1-8 4-10 10 10 10 10 Description 7 Yellow Green 14.2 (H) ! 8.0 (W) mm

Fig. 3-1 * The key can be removed in the REG or OFF position. * In the SRV mode, key inputs are prohibited and no display is made. * With the key in the off position power is not supplied to the main PWB. [Functions]

Amount Minus sign Error PGM Mode VOID Mode CA/AT CHK, CR SUB TOTAL/ short tender Change Department PLU Repeat Decimal point Receipt OFF Cashier No. VP compulsory Sentinel

Function for each key position SRV: SRV: System reset Service mode (Service programming)

10 10 9-10 5-10 8 3-1 9 2-3 10 10

: Floating E P u F: Lights up when a registration is finalized by depressing CA/AT, CHK, CR key o C: Light up whenever the change due amount appears in the display. No zero-suppressed No zero-suppressed Endless count, starting from 2. TAB () xx: free code U: Light up when the validation printing is compulsory Light up the decimal point

PGM2: Allows programming of an item that is not changed frequently, in addition to the PGM1 mode programming. department, PLU pricing, and discount rate setting).

PGM1: Allows programming of items frequently changed (e.g. OP, X/Z: Allows X or Z operation by servers or cashiers. REG: Allows registrations. MGR: Allows the operations, by authorized person such as a
manager (e.g. correction after transaction finished or cancellation of entry limits), which are not permitted to ordinary cashiers.

X1/Z1: Allows reading and resetting of a days sales total. X2/Z2: Allows reading or resetting sales totals in a specified
period.

5. Printer (DP-730)
1) Specifications Part number: No. of stations: Printing system: Direction of printing: Printing capacity:

OFF:

Switching off the display to prevent key board entries. (The setting turn off the AC power.)

DP-730 2 Mechanical serial dot Bidirectional Receipt 24 characters Journal 24 characters Validation 55 characters (one line only)

4. Display
1) Layout
Operator display

Character size:

1.36 (W) ! 2.75 (H) mm at 7 ! 7 dots Print pitch:

Fig. 4-1 7 segment display (LED) No. of positions Color of display Character size 10 Yellow Green 14.2 (H) ! 8.0 (W) mm

Column distance 1.59 mm Row distance 5.08 mm

Total number of dots: Font:

Receipt 108 dots/216 positions Journal 108 dots/216 positions Validation 248 dots/495 positions 7 ! 7 dots (including half dot) Space between characters 1 dot (2 positions)

12

Distance between dots: Journal near end sensor: Print speed: Paper feed speed:

0.353 mm (H) ! 0.353 mm (W) Service route option Approx. 3.0 lines/sec. Receipt Approx. 30 lines/sec. Journal Approx. 30 lines/sec.

Reliability:

MCBF 4 million lines (excluding the print head) Head life 50 million characters (at 4 dots/1 character/ 1 pin)

4) Inking Ink supply system: Form: Specification: Ribbon life: Print color:

Ink ribbon Cartridge/Endless ribbon Material Nylon Approx. 6 million characters Purple (single color)

5) Logo stamp: None 6) Cutter Method: Manual

Validation form sensor: 2) Printing area

Receipt/journal

Not setup

6. Drawer
87.08

1) Specification
(1) Drawer box and drawer
37.87 3.56

3.56

37.87

3.56

3.56

Model name Size Color Material Bell Release lever Drawer open sensor

4.2 44.5 0.5 44.5 0.5

SK-423 420 (W) ! 427 (L: included lock key) ! 112 (H: included rubber leg) GRAY 368 Metal Standard equipment; Situated at the bottom Standard equipment

2) Money case
Separation from the drawer Separation of the coin compartments from the money case Bill separator Number of compartments
For "U" Version
Bill compartments

RECEIPT

JOURNAL Unit : mm

For "U" version Allowed Disallowed

For "A" version Allowed Disallowed

Fig. 5-1 Validation form

5B/5C

YES 4B/8C
For "A" Version

Bill separator

70

87.08 (PRINT AREA)

20
22
5B/5C

Coin compartments

5B/8C

130 ~ 210
Unit : mm

3) Lock
Location of the lock Front Locking: Insert the drawer lock key into the lock and turn it 90 degrees counterclockwise. Insert the drawer lock key into the lock and turn it 90 degrees clockwise. Method of locking and unlocking

Fig. 5-2

3) Paper Paper roll dimensions: 44.50.5mm in width, 83mm in diameter Paper quality: Journal
Bond paper (paper thickness: 0.06 to 0.09mm, paper weight: 52.3 to 64g/m2) Validation form Thickness: 0.07 to 0.14mm Size: 130mm or more (W) ! 70mm or more (H) Key No.

Unlocking:

SK1-1

13

CHAPTER 2. OPTIONS
1. System configuration

(NOTE1) This symbol shows NEW MODEL LOCAL PURCHASE ER-A440 ER-03RA

COMPUTER

MASTER MACHINE

OPTION RAM

ER-01/02FD

COMMERCIAL PRODUCT

ER-04DW

3.5 inch FDD

CABLE

REMOTE DRAWER

Fig. 1-1

21

2. Options
No. 1 2 3 4 REMOTE DRAWER PRESETS LOADER KEY TOP KIT NAME EXPANSION RAM CHIP ER-03RA ER-04DW ER-01FD/02FD ER-11KT7 ER-12KT7 ER-22KT7 ER-11DK7G ER-51DK7G 5 6 COIN CASE COIN CASE ER-55CC2 ER-48CC2 FD unit 1 1 KYE TOP UNIT 1 2 KYE TOP UNIT 2 2 KYE TOP UNIT 1 1 DUMMY KYE KIT 5 1 DUMMY KYE KIT for "U" version for "A" version MODEL DESCRIPTION 512K bytes RAM CHIP

3. Service options
No. 1 2 3 4 5 SERVICE KEY MODE KEY GRIP COVER DRIP-PROOF KEYBOARD COVER JOURNAL NEAR END SENSOR TEXT PRESET KEYBOARD COVER NAME PARTS CODE PRICE RANK AF AL BE BB BH OP key only Include the switch cover DESCRIPTION

4. Service tools
No. 1 2 NAME RS-232 LOOP BACK CONNECTOR KEY TOP REMOVER PARTS CODE PRICE RANK BU BB DESCRIPTION

5. Supplies
No. 1 2 ROLL PAPER INK LIBBON NAME PARTS CODE PRICE RANK AR AZ 5 roll/pack DESCRIPTION

6. Options
For installation of the options, refer to the Installation Manual which is issued separately.

22

CHAPTER 3. SRV. RESET AND MASTER RESET

1. SRV. reset (Program Loop Reset)
Used to return the machine back to its operational state after a lockup has occurred.

[key setup procedure]

*2

MRS-2 executed

Key position set

Free key 0
Disable *1

Free key setup complete.

Procedure

Method 1
1) Unplug the AC cord from the wall outlet. 2) Set the mode switch to (SRV) position. 3) Plug in the AC cord to the wall outlet. 4) Turn to (SRV) position from (SRV) position.

NOTES: 1: When the 0 key is pressed, the key of the key number on display is disabled. 2: Push the key on the position to be assigned. With this, the key of the key number on display is assigned to that key position. Key number 1 2 3 4 5 6 7 8 9 Key name Numeric key "0" Numeric key "1" Numeric key "2" Numeric key "3" Numeric key "4" Numeric key "5" Numeric key "6" Numeric key "7" Numeric key "8" Key number 10 11 12 13 14 15 16 17 Key name Numeric key "9" Numeric key "00" Numeric key "000" Decimal point key CL key @/FOR key SBTL key CA/AT key

Method 2
1) Set the mode switch to PGM2 position. 2) Turn off the AC switch. 3) While holding down JOURNAL FEED key and RECEIPT FEED key, Turn on the AC switch. Note: When disassembling and reassembling always power up using method 1 only. Method 2 will not reset the CKDC8. Note: SRV programming job#926-B must be set to "4" to allow PGM program loop reset.

2. Master reset (All memory clear)

There are two possible methods to perform a master reset.

MRS-1
Used to clear all memory contents and return machine back to its initial settings and return keyboard back to default keyboard layout.

Procedure
1) Unplug the AC cord from the wall outlet. 2) Set the MODE switch to the (SRV) position. 3) Plug in the AC cord to the wall outlet. 4) While holding down JOURNAL FEED key, turn to (SRV) position from (SRV) position.

MRS-2
Used to clear all memory and keyboard contents. This reset returns all programming back to defaults. The keyboard must be entered by hand. This reset is used if an application needs different keyboard layout other than that supplied by a normal MRS-1.

Procedure
1) Unplug the AC cord from the wall outlet. 2) Set the MODE switch to the (SRV) position. 3) Plug in the AC cord to the wall outlet. 4) While holding down JOURNAL FEED key and RECEIPT FEED key, turn to (SRV) position from (SRV) position. 5) Key position assignment: After the execution of MRS-2, only the RECEIPT FEED and JOURNAL FEED keys can remain effective on key assignment. Any key can be assigned on any key position on the main keyboard.

31

CHAPTER 4. HARDWARE DESCRIPTION

1. Hard ware block diagram

STANDARD

OPTIONAL RAM 512KB ER-03RA:512KB

CPU DRAWER

RAM1 RAM2 32KBx2

STANDARD

PRINTER DP-730

GATE ARRAY MPCA7 ROM 256KB OPERATER DISPLAY 1 LINE 7SEG 10DIG CUSTOMER DISPLAY 1 LINE 7SEG 7DIG CKDC8 SWITCH

KEY BOARD

RS232
I/F

1 ports

Fig. 1-1

41

2. Description of main LSIs

2-1. CPU (HD6415108-10)
1) Pin configuration

112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85
84 83 82 81 80 78 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57

STBY MD2 MD1 MD0 VCC RFSH LWR HWR RD AS E X VSS XTAL EXTAL VSS TXD2 RXD2 TXD1 RXD1 SCK2 UASKC IRQ1 IRQ0 VCC AVCC AN3 AN2

RES NMI VSS P10 P11 P12 P13 P14 P15 P16 P17 D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 A7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

AN1 AN0 AVSS VSS P67 P66 P65 P64 P63 P62 P61 P60 P57/STOP P56 P55 P54 P53 P52 P51 P50 VSS P47 P46 P45 P44 P43 P42 P41

A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 A17 A18 A19 A20 A21 A22 A23 VSS WAIT BACK BREQ P33 P34 P35 P36 P37 VCC P40

29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

HD6415108-10 pin configuration Fig. 2-1

42

2) Block diagram
P17 P16 P15 P14 P13 P12 P11 P10

D7 D6 D5 D4 D3 D2 D1 D0

P27/A23
Data bus Port 1 Port 2

P26/A22 P25/A21 P24/A20 P23/A19 P22/A18 P21/A17 P20/A16

Data bus (Lower) Data bus (Upper)

EXTAL XTAL X E MD2 MD1 H8/500 CPU MD0 RES STBY NMI AS RD HWR Refresh controller Interruption controller DTC Clock oscillator Watch dog timer

A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 P37 P36 P35

Address bus

Port 3

LWR RFSH

16bit free running timer x 2ch

Address bus

P34 P33 BREQ

VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS AVCC AVSS Port 8

Wait state controller

8bit timer

BACK WAIT P47

A/D convertor

Serial communication interface x 2ch Port 4

FTI2 P45 FTI1 P43 P42 P41/TMCI P40

Port 7

Port 6

Port 5

STOP/P57

P67 P66 RS/P65 RR/P64 CD/P63 CS/P62 DR/P61 ER/P60

FMRS

TXD2

RXD2

TXD1

RXD1

IRQ2

IRQ1

SCK2

IRQ0

AN2

AN1

AN0

P73

P56

P54

P53

P52

P51

Fig. 2-2

43

P50

3) Pin description
PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 /BREQ P33 P34 P35 P36 P37 VCC P40 /BREQ DOPS /DR0 /DR1 NU NU VCC /IFV IN IN P17 D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 A17 A18 A19 A20 A21 A22 A23 VSS /WAIT D0 D1 D2 D3 D4 D5 D6 D7 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 A17 A18 A19 A20 A21 A22 A23 VSS /WAIT IN OUT IN IN OUT OUT IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT VSS P10 P11 P12 P13 P14 VSS ERC LDRQ /SHEN /FRES BUSY OUT OUT IN OUT IN IN IN IN I/O I/O I/O I/O I/O I/O I/O I/O SYMBOL SIGNAL NAME IN/ OUT IN IN FUNCTION RESET INPUT from CKDC WUTH BUFFER NON-MASKABLE INTERRUPT INPUT FOR SSP INTERRUPT INPUT GND EVENT READ CANCEL (to CKDC) LOAD REQUEST (to CKDC) SHIFT ENABLE (from CKDC) FISCAL MEMORY RESET (NU) FISCAL MEMORY BUSY (NU) Pull-up FISCAL MEMORY READY (NU) Pull-up POP-UP DISPLAY SENSOR (NU) Pull-up GND Nu DATA BUS 0 DATA BUS 1 DATA BUS 2 DATA BUS 3 DATA BUS 4 DATA BUS 5 DATA BUS 6 DATA BUS 7 GND ADDRESS BUS 0 ADDRESS BUS 1 ADDRESS BUS 2 ADDRESS BUS 3 ADDRESS BUS 4 ADDRESS BUS 5 ADDRESS BUS 6 ADDRESS BUS 7 ADDRESS BUS 8 ADDRESS BUS 9 ADDRESS BUS 10 ADDRESS BUS 11 ADDRESS BUS 12 ADDRESS BUS 13 ADDRESS BUS 14 ADDRESS BUS 15 GND ADDRESS BUS 16 ADDRESS BUS 17 ADDRESS BUS 18 ADDRESS BUS 19 ADDRESS BUS 20 ADDRESS BUS 21 ADDRESS BUS 22 ADDRESS BUS 23 GND Wait signal from MPCA Bus control request acknowl edge (Nu) Bus control request (Nu) pull-up Drawer open sencer signal Drawer open drive signal Option drawer 1 drive signal (Nu) GND (Nu) GND +5V Slip printer enable (Nu) pull-up Printer (Dp-730) timing signal from MPCA 96 97 98 99 VSS EXTAL XTAL VSS EXTAL XTAL VSS /AS /RD /WR /RFSH VCC MD0 MD1 MD2 /STBY IN IN IN IN OUT OUT OUT OUT OUT OUT OUT IN IN OUT 90 91 92 93 94 95 P82 P83 P84 P85 /iRQ2 SCK2 RXD TXD IN IN OUT IN OUT IN 77 78 79 80 81 82 83 84 85 86 87 88 89 VSS AVSS P70 P71 P72 P73 AVCC VCC P80 AVCC VCC /iRQ0 IN VSS AVSS VPJ VPR VPTEST IN IN IN IN IN IN OUT OUT IN IN 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 P47 VSS P50 P51 P52 P53 P54 P55 P56 P57 /NER VSS TRG1 /PSTOP /CKDCR2 OPDS FVPON FMRS /SLIPLMP /STOP OUT OUT OUT IN OUT IN OUT OUT OUT IN IN IN IN IN PIN No. 58 59 60 61 P45 /NEJ SYMBOL P42 P43 SIGNAL NAME /TOF /BOF IN/ OUT IN IN IN IN FUNCTION Slip TOF signal (Nu) pull-up Slip BOF signal (Nu) pull-up Printer (Dp-730) Reset signal from MPCA Near END signal jounal CKDC interface shift enable signal (NU) GND Near END signal receipt GND Dot pulse adjust signal Nu Nu Nu (GND) Nu Nu (GND) Nu Nu ER signal for RS232 (Equipment Ready) DR signal for RS232 (Data set Ready) CS signal for RS232 (Clear to Send) CD signal for RS232 (Carrier Detect) RR signal for RS232 (Ready to Receive) (Nu) RS signal for RS232 (Request to Send) CI signal for RS232 (Calling Indicator) Printer (Dp-730) Home position pulse GND GND Validation sensor journal (NU) GND Validation sensor receipt (NU) GND +24V test input Validation sense signal (Nu) GND +5V +5V Interrupt signal 0 from MPCA Interrupt signal from OPTION PWB Interrupt signal (Nu) pull-up CKDC & FMC i/F sync shift clock RS232C RECEIVE DATA RS232C SEND DATA CKDC, Fiscal memory unit I/F shift input data CKDC, Fiscal memory unit I/F shift output data GND X-TAL (14.7456MHz) X-TAL (14.7456MHz) GND System clock (7.3728MHz) E clock (NU) Address strobe Read Write Nu Refresh cycle (NU) +5V +5V (MODE 3) +5V (MODE 3) GND (MODE 3) +5V (Nu)

100 VSS 101 102 E 103 /AS 104 /RD 105 /HWR 106 /LWR 107 /RFSH 108 VCC 109 MD0 110 MD1 111 MD2 112 /STBY

44

2-2. G.A (MPCA7)

1) Pin configuration

RF JF PCUT FCUT VF STAMP SLF SLRS SLMTD RES TRG TRG POFF INT1 HTS1 SCK1 STH1 NU NU VCC GND NU VRESC SLTMG SLRST AS RD WR PHAI SDT7 SDT6 SDT5 GND SDT4 SDT3 SDT2 SDT1 D0 D1 D2

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

NU DOTEN TWAIT NU NU NU NU NU STH2 SCK2 HTS2 SLMTR SLMTS SLMTD RJMTR RAS3 NU GND VCC ASKRX NU NU NU RJMTD RJMTS DT5 DT6 DT7 GND DT1 DT2 DT3 DT4 RJTMG RJRST RAS1 RAS2 ROS2 ROS1 OPTCS

EXINT0 EXINT1 EXINT2 EXINT3 WRO RDO RA15 RA16 GND RA17 RA18 EXWAIT WAIT NU MCR1 NU DAX1 RCKX IRRX GND VCC UATX UARX UASCK IRTX RCO NU NU NU NU MA15 TEST MD0 MD1 IPLON INT4 PRST PTMG TRGI A23

D3 GND D4 D5 D6 D7 SSPRQ RESET INT2 INT3 RXDI TXDI SCKI IRQ0 A0 A1 A2 A3 A4 A5 GND VCC A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 NU

41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80

GATE ARRAY (LZ9AH39) MPCA7 Fig. 2-3

45

2) Block diagram

A23~A0 IRLON ROS1 ROS2 RAS1 RAS2 RAS3 OPTCS IRTX IRRX RCI ASKRX Address decode External CS Internal CS RASEL Image control SSP comparison register BAR. SSPRQ

I/R Control
D0~D7 Buffer TXDI SCKI RXDI HTS1 SCK1 STH1 HTS2 SCK2 STH2

AS RD WR RDO WRO RESET RES VRESC POFF MD0 MD1 WAIT EXWAIT WAIT control Read/write control

CHS serial select

Multiplexer

INT4 Divider INT1 INT2 INTO control INT3 EXINT0 EXINT1 EXINT2 EXINT3 CAPS select Print mode PMD IRQ0 TEST

MTD
RJRST SLRST *PRST RJTMG SLTMG PTMG Print gate Print pulse control Printer control port Motor drive MTD RJMTR SLMTD SLMTS SLMTR SLMTD

* Output selection with CAPS. PRST/PTMG.

DT1~9

SDT1~7

TRGI

DOTEN TRG

TRG

STAMP

PCUT

FCUT

JF

RF

SLRS

SLF

VF

Fig. 2-4

46

3) Pin description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 Signal name RF JF PCUT FCUT VF STAMP SLFS SLRS SLMTD RES TRG TRG POFF INT1 HTS1 SCK1 STH1 RAS VZ VCC GND INTMCR VRESC SLTMG SLRST AS RD WR SDT7 SDT6 SDT5 GND SDT4 SDT3 SDT2 SDT1 D0 D1 D2 D3 GND D4 D5 D6 D7 SPRQ RESET SHEN In/ Out Out Out Out Out Out Out Out Out Out Out Out Out In In Out Out In Out In In In In In In Out Out Out Out Out Out Out I/O I/O I/O I/O I/O I/O I/O I/O Out In In Function Receipt side paper feed solenoid Journal side paper feed solenoid Printer partial cut signal (NU) Printer auto cut signal (NU) Multi line validation paper feed (NU) Printer stamp signal (NU) Slip printer paper feed singnal (NU) Slip printer release signal (NU) Slip printer motor drive signal (NU) Peripheral output reset Dot head trigger signal (NU) Dot head trigger signal Power off signal input (NU) 8 bit serial port output (for CKDC8) Serial port shift clock output (for CKDC8) 8 bit serial port input (for CKDC8) Chip select (NU) Nu +5V GND Interrupt (NU) Turns active when reset and power down is met Slip printer timing signal (NU) Slip printer reset signal (NU) Address strobe Read strobe Write strobe () System clock (7.3728 MHz) Slip printer printhead drive signal (dot7) (NU) Slip printer printhead drive signal (dot6) (NU) Slip printer printhead drive signal (dot5) (NU) GND Slip printer printhead drive signal (dot4) (NU) Slip printer printhead drive signal (dot3) (NU) Slip printer printhead drive signal (dot2) (NU) Slip printer printhead drive signal (dot1) (NU) Data bus 0 Data bus 1 Data bus 2 Data bus 3 GND Data bus 4 Data bus 5 Data bus 6 Data bus 7 SSP interrupt request to CPU MPCA reset Shift enable from CKDC8 47 Pin No. 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 Signal name INT3 RXD2 TXD2 SCK2 IRQ0 A0 A1 A2 A3 A4 A5 GND VCC A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 LCDC A23 TRGI PTMG PRST RDY IPLON MD1 MD0 TEST MA15 MA18 MA19 RCVRDY1 RCVRDY2 RC0 IRTX UASCK UARX UATX VCC GND IRRX RCI DAX1 In/ Out In Out In In Out In In In In In In In In In In In In In In In In In In In In In In In In In Out Out In In In In In Function Interrupt signal (Nu) 8 bit serial port output to CPU 8 bit serial port input from CPU Serial port shift clock input from CPU. Interrupt request to CPU Address bus 0 Address bus 1 Address bus 2 Address bus 3 Address bus 4 Address bus 5 GND +5V Address bus 6 Address bus 7 Address bus 8 Address bus 9 Address bus 10 Address bus 11 Address bus 12 Address bus 13 Address bus 14 Address bus 15 Address bus 16 Address bus 17 Address bus 18 Address bus 19 Address bus 20 Address bus 21 Address bus 22 LCD CS (NU) Address bus 23 Dot pulse control/drive signal Printer timing signal Printer reset signal Ready from FMC unit To option connector (NU) Mode select input (+5V) Mode select input (GND) +5V Image address 15 (NU) Nu Nu Nu Nu Remote control encord signal for CPU I/R output for LED (NU) I/R serial data shift clock (NU) I/R serial data for CPU (NU) I/R serial data from CPU (NU) +5V GND I/R input from I/R unit (NU) I/R input from I/R unit (NU) System clock (7.3728MHz)

Pin No. 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160

Signal name DAX2 MCR1 MCR2 WAIT EXWAIT RA18 RA17 GND RA16 RA15 RDO WRO EXINT3 EXINT2 EXINT1 EXINT0 OPTCS ROS1 ROS2 RAS2 RAS1 RJRST RJTMG DT4 DT3 DT2 DT1 GND DT7 DT6 DT5 MTD MTD DOT9 DOT8 SYNC ASKRX VCC GND RAS3 RJMTR SLMTD SLMTS SLMTR HTS2 SCK2 STH2 LCDWT DOTEN RASP

In/ Out Out In Out Out Out Out Out Out In In In In Out Out Out Out Out In In Out Out Out Out Out Out Out Out Out Out Out Out In In In In Out Out In Out Nu Nu Nu

Function

2-3. CKDC8
1) Pin configulation
NU NU G10 G9 G8 G7 G6 G5 G4 G3 G2 G1 BUZ /POFF NU ST8
DP SA SB SC SD SE SF SG GND VDD KR4 KR10 KR11 NU HTS STH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

Wait request signal External wait control input signal Nu Nu GND Nu Nu Expansion RD signal Expansion WR signal Expansion interruption signal 3 Expansion interruption signal 2 Expansion interruption signal 1 Expansion interruption signal 0 Chip select base signal for expansion option ROM 1 chip select signal ROM 2 chip select signal (NU) RAM 2 chip select signal RAM 1 ship select signal Printer reset signal Printer timing signal Printer dot signal 4 Printer dot signal 3 Printer dot signal 2 Printer dot signal 1 GND Printer dot signal 7 Printer dot signal 6 Printer dot signal 5 Printer motor drive signal Printer motor drive signal Printer dot signal 9 (NU) Printer dot signal 8 (NU) Nu (+5V) I/R input from I/R unit (NU) +5V GND Nu Printer motor lock detection signal (NU) Nu Nu GND Serial output to FMC unit (NU) Serial clock to FMC unit (NU) Serial input to FMC unit (NU) pull-up Nu Nu Nu Nu Nu Nu Dot drive enable signal Nu 48 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 KR11 KR8 HTS STH /SCK ST0 ST1 ST2 ST3 ST4 ST5 VDD1 AXSS KR9 KR0 KR1 KR2 KR3 KR5 KR6 KR11 NU HTS STH /SCK ST0 ST1 ST2 ST3 ST4 ST5 VDD GND NU KR0 KR1 KR2 KR3 KR5 KR6 IN IN IN IN IN IN IN IN IN OUT IN SHIFT CLOCK OUT KEY STROBE 0 OUT KEY STROBE 1 OUT KEY STROBE 2 OUT KEY STROBE 3 OUT KEY STROBE 4 OUT KEY STROBE 5 VDD GND GND KEY RETURN 0 KEY RETURN 1 KEY RETURN 2 KEY RETURN 3 KEY RETURN 5 KEY RETURN 6 Option Option
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ST7 ST6 /RESETS /SHEN ERC LDRQ GND

CKDC8

GND

/RES0 VDD GND KR7

2) Pin assignment (CKDC8)

Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 SYMBOL DP A B C D E F G VSS0 VDD0 KR4 KR10 SIGNAL NAME DP SA SB SC SD SE SF SG GND VDD KR4 KR10 IN IN IN/ OUT FUNCTION

/SCK ST0 ST1 ST2 ST3 ST4 ST5 VDD GND NU KR0 KR1 KR2 KR3 KR5 KR6

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

OUT DISPLAY SEGMENT Dp OUT DISPLAY SEGMENT a OUT DISPLAY SEGMENT b OUT DISPLAY SEGMENT c OUT DISPLAY SEGMENT d OUT DISPLAY SEGMENT e OUT DISPLAY SEGMENT f OUT DISPLAY SEGMENT g GND VDD KEY RETURN 4 KEY RETURN (feed clerk MRS sw) KEY RETURN (MODE sw) GND

Pin No. 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

SYMBOL KR7 AVRF AVDD /RESET XT2 XT1 IC X2 X1 VSS1 LDRQ ERC SHEN /RES1 ST6 ST7 ST8 ST9 /POFF BUZ T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 ID

SIGNAL NAME KR7 GND VDD /RES0

IN/ OUT IN

FUNCTION KEY RETURN 7

2) CKDC8 oscillation circuit

X3 4.19MHz

IN 32. 768 KHz

X2

40 1 2 3 41

GND
CKDC 8

X1

4. 19 M Hz GND LDRQ ERC /SHEN /RESETS ST6 ST7 ST8 NU /POFF BUZ G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 NU NU IN IN LORD REQUEST EVENT READ CANCEL
XT1 38 C106 18P XT2 37

R164 330K

X2 32.768KHz

OUT SHIFT ENABLE OUT SYSTEM TO RESET OUT KEY STROBE 6 OUT KEY STROBE 7 OUT KEY STROBE 8 OUT KEY STROBE 9 IN POWER OFF

HD404728A91FS

C105 33P

Fig. 3-2 Two oscillators are connected to the CKDC8. The main clock X3 generates 4.19MHz which is used during power on. When power is turned off, the CKDC8 goes into the standby mode and the main clock stops. The sub-clock X2 generates 32.768KHz which is primarily used to update the internal RTC (real time clock). During the standby mode, it keeps oscillating to update the clock and monitoring the power recovery.

OUT BUZZER OUT DISPLAY DIGIT 1 OUT DISPLAY DIGIT 2 OUT DISPLAY DIGIT 3 OUT DISPLAY DIGIT 4 OUT DISPLAY DIGIT 5 OUT DISPLAY DIGIT 6 OUT DISPLAY DIGIT 7 OUT DISPLAY DIGIT 8 OUT DISPLAY DIGIT 9 OUT DISPLAY DIGIT 10 OUT DISPLAY DIGIT 11 OUT DISPLAY SEGMENT

4. Reset (POFF) circuit

+24V D7 1SS133 +5V

3. Clock generator
1) CPU (HD64151010FX)
X1
MPCA7 C208 1 50V

R12 8.2KG

R11 2.7K R10 R13 15KG 56K 3 2 R14 9.1KG ZD2 MTZ5.1A 8 + B 1 IC3A 4 KIA393F

R9 2.7K

/POFF

XTAL CPU
(HD64151010FX)

99
13

INT0

54

14.7456MHz

POFF
89 IRQ0 1

EXTAL

98 101 PHAI
CPU
72

IRQ0

C3 1000P

48

RESET (FROM CKDC 8)

STOP (TO CKDC 8)

Fig. 3-1 Basic clock is supplied from a 14.7456MHz ceramic oscillator. The CPU contains an oscillation circuit from which the basic clock is internally driven. If the CPU was not operating properly, the signal does not appear on this line in most cases. Fig. 4-1 In order to prevent memory loss at a time of power off and power supply failure of the ECR, the power supply condition is monitored at all times. When a power failure is met, the CPU suspends the execution of the current program and immediately executes the power-off program to save the data in the CPU registers in the external S-RAM with the signal STOP forced low to prepare for the power-off situation. The signal STOP is supplied to the CKDC8 as signal RESET to reset the devices.

49

This circuit monitors +24V supply voltage. The voltage at the () pin of the comparator IC3A is always maintained to 5.1V by means of the zener diode ZD2, while +24V supply voltage is divided through the resistors R12, R13, and R14, and is applied to the (+) pin. When normal +24V is in supply, 6.8V is supplied to the (+) pin, therefore, signal POFF is at a high level. When +24V supply voltage decreases due to a power off or any other reason, the voltage at the (+) pin also decreases. When +24V supply voltage drops, the voltage at the (+) pin drops below +5.1V, which causes POFF to go low, thus predicting the power-off situation.
VDD 4 5 VDD 9 10 IC10C 74HC00S R123 10K C88 1000P C86 1000P
14 14

0 page memory map

000000H

004000H

ROM image area 32KB

RAS3 VDD 1 8 2 IC10A 74HC00S

14

6 IC10B 74HC00S

/(RAS3./RESET)

008000H

CKDC8

RESETS

/RESET

RAM image area slightly smaller than32KB

C87 1000P

STOP

00F800H

The STOP signal from the CPU is converted into the RESETS signal by the CKDC6. The RESETS signal from the CKDC8 is converted into the RESET signal at the gate backed-up by the VRAM power, performing the system reset.

00FFFFH

RAM image area

00FE80H
NOT USE 1BFFFFH Internal I/O area

00FF80H
RAM area

5. Memory control
1) Memory map
All range memory map
000000H
Internal I/O External I/O Memory image area (*1) (*2) (*3)

1FFFFFH

00FFFFH

External I/O area (0 page)

Fig. 5-2

ROM image area: Image is formed in ROM area address

C00000H to C07FFFH. This area is identical to IPL ROM area which will beseparately developed.

RAM image area: Image is formed in RAM area address 1F0000H

to 1F7E7FH. ( Note) Note: Image can be formed in lower 32KB of RAS2.

1C0000H

ROM area memory map

C00000H

RAM area (10M byte)

ROS1 (256K Byte)

C00000H
ROM area (3M byte)

C40000H ROS2 (Not used)

FFFFFFH

Expansion I/O area (1M byte)

CA0000H

Fig. 5-1 ( 1) ( 2) ( 3) Internal I/O means the registers in the H8/510. External I/O means the base system I/O area to be addressed in page 0. "Memory image area" means the lower 32KB of ROM area which is projected to 000000H ~ 007FFFH for allowing reset start and other vector addressing, or the lower 32KB of RAM area which is projected to 008000H ~ 00FE7FH for allowing 0 page addressing of work RAM area. Expansion I/O means expansion I/O device area which isaddressed to area other than page 0.
EFFFFFH D00000H

ROS3 NOT USE

( 4)

Fig. 5-3

4 10

RAM area memory map

100000H

2) Block diagram
Data bus

ROS1

NOT USE
CPU MPCA7

ROM1

1C0000H RAS1 (Not use) 1F0000H RAS2 64K Byte 200000H

Address bus RAS2 (STANDARD) (OPTION) RAM1 RAM RAS3 RAM2

RAS3 512K Byte (OPTION) 280000H

Fig. 5-6

ROM control
C80000H~CFFFFFH ROS2

(MAX 2MB)
Address C00000H~C7FFFFH

400000H
A23~A14 Address decorder 000000H~007FFFH

ROS1

NOT USE

(IPLON)

BFFFFFH

Fig. 5-4 Note: RAS2 signal is formed as OR in the image area of 0 page. (lower32KB).

MPCA7

Fig. 5-7 IPLON: IPL board detection signal incorporated in the option slot. Note used in the ER-A445P. (Not used)

I/O area memory map

00FF80H (*1) MPCCS

Access is performed with two ROM chip select signals ROS1 and ROS2, which decode 512KB address area respectively to accessmax. 4MB ROM.

RAM control

00FFA0H NOT USE MCR1 (NOT USE) MCR2 (NOT USE) 00FFC0H (*2) OPCCS1 00FFD0H (*2) OPCCS2
1E0000H~1FFFFFH Address A23~A14 Address decorder 008000H~ 00F7FFH *1 RAS2 200000H~3FFFFFH 1C0000H~1DFFFFH RAS1 RAS3

00FFE0H NOT USE 00FFE8H NOT USE 00FFF0H NOT USE 00FFFFH
RESET S8F CK R DOI D Q Control register

Fig. 5-5 Note 1: MPCCS signal is the base signal for MPCA7 internal registerdecoding, and does not exist as an internal signal. Note 2: OPCCS1 and OPCCS2 signals are decoded in the OPC (optionperipheral controller) using the base signal OPTCS for optiondecoding. They does not exist as external signals.

MPCA7

Fig. 5-8 Access is performed with two RAM chip select signals, RAS2 and RAS3. The control register in MPCA7 allows selection of pageimage memory area. (RAS1 is selected for initializing.) : For 0 page image area, selection between RAS2 and RAS3 can bemade with the control register. The 0 page control registerperforms initializing at the timing of no stack processimmediately after resetting.

4 11

6. SSP circuit
1) Block diagram
This is the circuit employed to do the Special Service Preset(SSP). (Block diagram)
NMI SSPRQ

As the address detection system, the brake address register comparison system is employed though the mapping system was employed in the conventional monitor RAM. The address registerlocated in MPCA is always compared with the system address bus to monitor and generate NMI signal at a synchronized timing and togo to NMI exception process. In the exception process routine service routine, the entry address is checked to go to SSP sub routine. Entry to the break address register (BAR) is performed through address FFFF00H or later decoded in MPCA7.

A0~23

2) SSP register
The break address register (BAR) is accessed through direct address of FFFF00H~FFFFFFH. Entry number is 32 entry.
7 1 2 3 4 BAR0 0

D0~D7

CPU

MPCA7

FFFF00 H 1 2 3 4
SSPRQ (NMI)

Fig. 6-1 (MPCA7 block diagram)

Comparator O Coincide

BAR 0 D0~ D7 BAR N REGCS Decode

5 6 7

BAR1

Coincide

SPE (Enable register)

BAR2
A23~ A0 Control signal ROMCS

Fig. 6-2 Fig. 6-3 Each BAR is composed of 4 byte address. Bit composition is as follows:
A19 A18 A17 A16 A15 A8 A7 A2

EN

1 Upper bits

2 Intermediate bits

3 Lower bits

4 Enable register EN (bit7) = 1 Enable = 0 Inhibit

Don't care for "-----." < BAR composition >

Fig. 6-4 is the enable register. The entry registers of the break address are assigned to , , and . Each bit of address corresponds to each bit position, writing to , , and is performed without shifting. The corresponding area is 1MB space of ROS1 and ROS2.

4 12

3) SSP register access method

Access to SSP break address register is performed through the temporary register as shown below:
A19 A18 A17 A16 A15 A8 A7 A2

EN

Temporary

Temporary

WR 1 WR 2 3

Fig. 6-5 Enable flags can be accessed individually. can be accessed individually, writing to Though enable register brake address registers and is performed at the same time as writing to brake address register through the temporary register. Therefore, set and to temporary, then write into at last. Since the temporary register is commonly used by BAR sets, thefollowing register setting is performed after completion ofsetting of each break address register. Information on which brake register the SSP brake is detected in is read as binary data by reading address FFFFFFH (*1). Used in an expanded register. Normally is a reserve bit. Whenreading, fixed to 0. If there are 32 break registers, binary expression is made with the above 5 bits, and 0th is 00000B and 31st is 11111B. When detected simultaneously by two or more break registers, onewith the smaller BAR number is read as binary data. The brake signals (NMI) and the above detection data (CMP0~4) areheld until the above detection data are read. So read should bemade in the NMI sub routine. (Clear by FFFFFFH read.) 1: FFFFFFH is not fulldecoded. (FFFF00H~FFFFFFH). Therefore,unnecessary read access in parentheses should not be performed.

SSP control method

Access to the enable register and the brake address register is only possible when writing to them from the CPU.
bit 7 0 6 0 5 0 4 3 2 1 0

CMP4 CMP3 CMP2 CMP1 CMP0 (FFFFFFH)

7. PRINTER control circuit

1) Block diagram
Address bus

3) Printer motor drive circuit

Main PWB side
+24V

Printer side

CPU

Data bus

RECEIVER
MPCA7
PRINTER (DP-730) MPCA7

M C227

DRIVER
Speed limiter circuit COM 2.2K R128 C92 DP R127 Q7

MTD

Fig. 7-1

MTD

2) General description of the printer controller

The DP-730 is used as the R/J printer. The printer mechanical timing control is made by the CPU through MPCA7.
DP

Normal 555s (516~590s)

When the MTD is high, the motor rotates. When the MTD is low, the motor stops. 4 13

<Motor lock protection> When an abnormal load is applied to the mechanism, the DP (Dot Pulse) frequency is checked to prevent against the motor burn-out, the timing belt shift, and gear damage. If the following condition is made, the CPU stops the motor rotation. When starting the motor: When the cycle from starting to the 100th pulse of DP is 16ms. (The one pulse cycle of DP is normally 555us.) During constant rotation of the motor: When one pulse of DP is 1100us or more.
Relation ship among RP/HP/DP
RP OFF ON 1.5ms or above OFF HP ON 20 cycles of DP (TYP.11.1ms) 50s above DP OFF ON 555s(TYP.)(516~590S) #1 #2 #3 #4 Print area 50s above +5V GND +5V GND The first HP after turning OFF/ON RP. +5V GND

4) Printer sensor circuit

+5V +5V HP CPU R207 C93 Q6 R126 R206 HP

* The waveforms are those indicated with arrow in Fig.3-3.

5) Dot solenoid drive circuit

+5V

+24V

+5V R132 C91 Q8 R130 R131 R129 DP

+5V
R145 R146

RJTMG

VRESC

Q9

+5V R133 RJRST R1134 C228 RP

+5V
DOT1 ~DOT4

R149 R152

DOT1~DOT4

IC15

+5V
DOT5 ~DOT7

R153 R155

DOT5~DOT7

VPS MPCA7

VPJS(NU)
MPCA7

IC16

NOT USED

The DOT1 DOT7 (the dot solenoid drive signals from the MPCA7) are pulled up by the VRESE and converted into LOW by the driver IC. A +24V voltage is applied to the solenoid. This operates the dot wire.

The printer supplies the RP (Reset Pulse) signal, the HP (Home Position) signal, and the DP (Dot Pulse) signal) to control printing timing and conduction timing of solenoids. It also supplies the VPJ signal to detect the presence of validation paper. These sensor are photo interrupters. RP (RJRST) signal This signal is outputted once for every reciprocating motion of the print head. It indicates the reference position of the HP signal. The rear edge of RP (OFF -- ON) is used as the signal. HP signal The pulse signal is outputted from the slit in the disk installed to the DC motor shaft. It is used as the reference signal for starting counting of the DP signal. It is generated once for twenty DP signals. The rear edge of the HP signal (ON -- OFF) immediately after generation of the RP signal is used as the signal. DP (RJTMG) signal The pulse signal is outputted from the slit in the disk installed to the DC motor shaft. It is used as the control signal for the print solenoid and the paper feed solenoid. The front edge of the output signal (ON -- OFF) is used as the signal. VPJS (VPJ) signal The presence of a validation card is detected by interruption of the photo interrupter LED light by the validation card.

6) Paper feed circuit

+5V +24V R145 VRESC R146 F2 Q9 IC16 R156 PFJ0 PFJ0

IC18 R161 PFR0 Q11 PFR0

MPCA7

The PFJ0 (the journal paper fed signal from the MPCA7) and the PFR0 (the receipt paper feed signal) are pulled up by the VRESE and converted into LOW level. A +24V voltage is applied to the solenoid. This operates the paper feed solenoid.

4 14

7) Caution
CAUTION If fuse F2 should be blown, the dot head solenoid may be shorted. Be sure to check the head impedance and driver breakdown. When fuse F2 is blown: Remove F2, and perform the service resetting. The set the mode switch to a position other than SRV and SRV and turn off the power. Install fuse F2 (1A) and turn on the power. If the fuse blows with the above operation, driver 4AC16 may be shorted. Turn off the power. Disconnect the printer cable from the printer. Measure impedance between the printer body connector pin 5 and the following pins: 1, 3, 9, 11, 13, 21, 25 The impdenace must be 10.5 10%. If impedance is outside the above range, the dot solenoid is bad. Replace the dot head unit.

9. Key, display, time buzzer controls

MPCA7 HTS1 STH1 SCK1 RESET INT2 POFF HTS STH SCK RESET HTS STH SCK RES1

CPU

P11 P10 P12 RES P-OFF

LDRQ ERC SHEN

LDRQ ECR SHEN

POFF VDD

+24V

RES0

RES0

RESET

5 7 17 23 1 3 9 11 13 21 25

VCOM VCOM VCOM VCOM DOT3 DOT7 DOT5 DOT2 DOT1 DOT4 DOT6

ST0~ST7 KR0~KR7 KR10,KR11 Key board G1~G10 a~g,DP Driver Display VCC B BUZZER 2

ST0~ST7 KR0~7,KR10,KR11 Driver T0~T9 a~g,DP

DOT1~DOT7

CKDC 8

Fig. 9-1

1) Power on sequence
During service interruption, the CKDC8 senses POF within 500msec. When service interruption is cancelled by turning on the power, the CKDC8 cancels resetting of the CPU in the command mode. After initializing each port, the CPU reads the start condition (1 byte).

8. Drawer drive circuit

VRESC +24V 51 52 CPU TD62308F 50 R42 47K DOSP C97 1000P R144 1K R143 4.7K DR0 DR1 IC18 DRAW0 DRAW1 Drawer solenoid +24V

POF RES1 SHEN LDRQ 1 2 Start condition Next command

Fig. 9-2 Fig. 8-1 The drawer is directly supported by the CPU. No action starts when the power supply is not steady as the output stage of the driver is pulled VP by VRESC signal. Drawer open and close is sensed with the microswitch provided in the drawer whose signal is level converted with R74 and R73 and directly read by the CPU. After sampling POF High, the CKDC5 performs mode scan and key scan at , then cancels resetting of the CPU. After being cancelled, the CPU initializes each port at and reads the start condition. After being cancelled, the CPU reads the start condition without fail to set the sift mode. If, however, the first starting is made in other than SRV mode after the CKDC8 resets the CPU without request from the CPU, the CKDC8 sets the start condition supposing that starting is made in SRV mode.

4 15

2) Power off sequence

When the CPU senses a service interruption, it performs necessary procedures for CPU stop. Then the CPU outputs a reset request to the CKDC5. Reset request
SHEN SCK DON'T CARE

4) DISPLAY CONTROL
LED-display (for operator) G1-G10 SA-SG,DP CKDC5 Driver LED-display (for custmer)

Fig. 9-6
LDRQ TL TH RES1
TL+TH < = 140sec
Switching regulator ~ F2

CKDC8 directly drives the LED display unit.

20sec or more 20sec or more

10. Power supply circuit

+24V

Fig. 9-3 When the CPU senses a service interruption or an error, it performs necessary procedure for CPU stop and issues reset request. CPU procedures necessary for reset request All CPU interrupts are made DI. SCK is driven to low. Keep LDRQ at LOW level for 20usec or more and drive it HIGH. Loop to . During looping, access should not be made to external memory. It should be within 140usec from rising of one LDRQ to rising of another. When, however, the CKDC8 senses a service interruption at POF, it stops displaying. Service interruption procedure is performed after receiving reset request from the CPU. If reset request is not sent from the CPU within 100msec the service interruption procedure is started after 110 10msec to go into the stand-by mode.
POF

Power trans.

F1 ~

+ -

+5V Battery circuit DC-DC Converter circuit

VDD

Fig. 10-1 +24V: +5V: VDD: Printer, solenoid power VCC (Logic power) Battery charge, Battery back-uped power, CKDC-8 and RAM Back-up power

RES1 11010msec

Fig. 9-4

3) Key and switch scanning

356.25sec

ST0 38sec ST9

KR0~KR7 KR10,KR11

Fig. 9-5 As the strobe signal, 8 bits of ST0 - 8 are used. KR0 - KR7 are used as the key return signal. KR10 is used as the return signal of the paper feed key, cashier key and MRS switch. KR11 is used as the return signal of the mode switch.

4 16

CHAPTER 5. TEST FUNCTION

1. General
1) This diagnostic program has been developed for diagnosing machine functions in the field. The program is contained within the ER-A440. The diagnostic program is stored in the external ROM which will be executed by the CPU (H8/510) which requires the following diagnostic operations: a) Proper power supply voltages are mandatory for logic circuits (+5V, VDD, POFF, +12.5V, +24V). b) CPU input/output pins, CPU internal logic, CKDC8, MPCA7, system bus and common ROM/RAM must be working properly.

4. Test contents
[1] Display & Buzzer test
1) Key operation
100 CA/AT

2) Functional description
Display the following message on the front and the rear display boards.

1. 2. 3. 4. 5. 6. 7. 8. 9. 0.
A decimal point shifts from lower number of digit by one digit (per 200m sec.). Next, display the following segments (for approx. 1 sec.).

2. Operational procedure
To start the diagnostic program, you must enter the following command. 3-digit test item number key in the SRV mode. The key assignment must be properly set and the ROM and RAM must be operating properly to go into this mode. This is necessary because the control jumps to the program area in the SRV mode. A master reset must be performed before operating the ECR for the first time. After any option is installed, a program reset is required. When the master reset or program reset is performed, be sure to check the printout on the journal paper. Master reset: Journal print: Turn power on in the SRV mode and change it to the SRV mode with the JF key pressed. MASTER RESET ***

8. 8. 8. 8. 8. 8. 8. 8. 8. 8.
Repeat the above two kinds of displays. Sound a buzzer continuously during test.

3) Check items
a) The display must be correctly shown at each position. b) The luminosity of displays must be uniform and even at each position. c) Abnormal buzzer sound is not allowed.

4) Test termination
Press any key. The test terminates with the test and message printed

Program reset: Turn power on in the SRV mode and change it to the SRV mode. Journal print: PRG. RESET ***

100

3. Test command list

With the SRV mode and the following test code entry, the test start. CODE 100 101 102 104 105 106 108 109 110 111 120 130 150 200 500 DESCRIPTION Display & Buzzer test Key code & Cashier key test R/J printer test Keyboard test Mode switch test Printer sensor test Calendar osckllator test SSP test Drawer open sensor test (For standard drawer) Drawer open sensor test (For remote drawer) Standard RAM test Standard ROM test Printer dot pulse width adjustment Option RAM test RS-232 loop back test

[2] Key code & Cashier key test

1) Key operation
101 CA/AT

2) Functional description
Key code, MRS switch state and Cashier code are displayed.

Key code (Not used) (Not used)

51

3) Check items
a) Key code HARDWARE CODE" of the following keys will be displayed ever time the keys are pressed. "---" indicates that a key is struck twice and also that input data is not accepted. [KEY POSITION CODE] <ALL KEY>
65 66 R 74 14 04 J 43 23 13 63 33 24 03 62 42 22 12 61 32 72 02 52 41 21 11 51 31 71 01 60 50 20 10 40 30 70 00 68 55 45 76 15 26 67 56 35 75 05 25 58 57 46 36 16 06 77 48 47 28 17 07 78 38 37 27 18 08

3) Check items
a) The head of printing position must be exactly aligned for "RECEIPT" and "JOURNAL". b) Printed characters must be free of stain and blur.

4) Test termination
This check is terminated automatically.

[4] Keyboard test

1) Key operation
XXXX 104 CA/AT

XXXX: Sumcheck data Standard keyboard layout sumcheck data ER-A440 2266

<ER-A440 STANDARD KEY BOARD LAYOUT>

68 66 R 74 14 04 J 43 23 13 63 33 24 03 62 42 22 12 61 32 72 02 52 41 21 11 51 31 71 01 40 30 70 00 55 45 76 15 26 67 56 35 75 05 25 58 57 46 36 16 06 77 48 47 28 17 78 38 37 27 18 08

2) Functional description
Keyboard test is performed with the sumcheck data of key code. For sumcheck data, data are inputted to the upper upper four digits befor the diagnostics code. The data are compared with the added data which are added until the final key (TL) is pressed. if the data agree with the added data, the end print is made. If not, the error print is made. The su check data is obtained by totalizing all key hardware codes except for the (TL) key and converting the total into a decimal figure. [ALL KEY LAYOUT]

4) Test termination
Change the mode switch position other than SRV position to terminate the test. The test terminates with the test and message printed
R J 3F 3E 3D 34 2A 20 16 48 0C 02 29 15 33 4A 2B 21 1F 32 47 14

41 42 3C 28

44 37

43 38

3A 4D 4E 39 30 26 2E 2F 25 1C 1B 11 07 12 08

2D 23

1E 4C 4B 24 46 0F 05 1A 19 10 06

101

0E 17 04

18

0D 03

0B 01

0A 00

[STANDARD KEYBOARD LAYOUT]

[3] R/J printer test

1) Key operation

SUMCHECK DATA = 4A + 0E + 04 + 2B + 17 + = 2266

44 42 37 R J 3F 3E 3D 34 2A 20 16 48 0C 02 29 15 33 1F 47 28 43 38 3A 4D 4E 39 30 26 2E 2F 25 1C 1B 11 12 08

102

CA/AT

2D 23

A4 2B 21

1E 4C 4B 24 46 00 0F 05 1A 19 10 06

2) Functional description
Display the following message.

0E 17 04

18

0D 03

0B 01

1 2 3 4 5 6 7 8 9 0
Print the following characters.
<RECEIPT> ZZZZZZZZZZZZZZZZZZZZZZZZ ZZZZZZZZZZZZZZZZZZZZZZZZ ZZZZZZZZZZZZZZZZZZZZZZZZ 3 lines of Z(24 characters) are printed <JOURNAL> ZZZZZZZZZZZZZZZZZZZZZZZZ ZZZZZZZZZZZZZZZZZZZZZZZZ ZZZZZZZZZZZZZZZZZZZZZZZZ 3 lines of Z(24 characters) are printed

Display the following message on the front display.

1 0 4
Key code

52

3) Check items
a) Check of the display in the test and the content of end print.

2) Functional description
State of the paper near end sensor is sensed and displayed.

4) Test termination
This check is terminated automatically. The test terminates with the test and message printed
Normal end

1 0 6

X-X
JOURNAL side RECEIPT side

104
3) Check items
Error

X, Y

Description Paper near end sensor not detected. (Paper is existed) Paper near end sensor detected. (Paper is not existed)

E-----

104

C O

"C" is always display when no sensor is used.

[5] Mode switch test

1) Key operation
105 CA/AT

4) Test termination
Press any key. The test terminates with the test and message printed

106

2) Functional description
Display the following message on the front display.

[7] Calendar oscillator test

1 0 5

1) Key operation
108 CA/AT

When the Mode Switch is switched over in the following order, a numerical value corresponding to each position of mode switch is displayed at X.
Mode: x : SRV 0 SRV 0 PGM2 1 X2/Z2 7 PGM1 2 X1/Z1 6 OFF 9 MGR 5 OP X/Z 3 REG 4

2) Functional description
This program is used to test the calendar oscillator function. Display:

"TT TT" shows the current time. "" is blinking. (500ms ON and OFF)

3) Check items
a) Check of the display in the test and the content of end print.

3) Check items
Time elapsed after master reset must be displayed.

4) Test termination
The test terminates with the test and message printed
Normal end

4) Test termination
Press any key. The terminates with the test and message printed

105
Error

108

E-----

105

[8] SSP test

1)Key operation

[6] Printar sensor test

1) Key operation
106 CA/AT

109

CA/AT

2) Functional description
If an SSP is programmed, its contents are automatically chacked and the result is printed. Display:

1 0 9

53

3) Check items
Check printing of the termination message.

3) Check items
X O C Description Drawer open sensor detected. (Drawer opend) Drawer open sensor not detected. (Drawer closed)

4) Test termination
This check is terminated automatically. The test terminates with the test and message printed
Normal end

a) Check opening of the specified drawer. b) Check the display indication when the drawer is open and closed.

109
Error

4) Test termination
Press any key. The test terminates with the test and message printed

111

E----SSP table full

109

[11] Standard RAM test

109
1) Key operation
120 CA/AT

F-----

In this SSP check, set the data for check in the empty area of SSP entry REG and erase the data for check after completion of check. Therefore SSP setting before check is not cleard. If therefore there is no SSP entry REG remainedfor SSP check, F-print is performed to terminate the program without check.

2) Functional description
Perform the following check for the standard RAM 128 KByte SRAM. The memory contents should not be changed before and after the check. Perform the following processes for memory address to be checked (1E0000H~1F0000H). PASS1: Save memory data.

[9] Drawer open sensor test (For standard test)

1) Key operation
110 CA/AT

PASS2: Write data "0000H." PASS3: Read and compare data "0000H," write data "5555H."

2) Functional description
State of the drawer open sensor is sensed and displayed.

PASS4: Read and compare data "5555H," write data "AAAAH." PASS5: Read and compare data "AAAAH."

1 1 0
3) Check items
X O C

PASS6: Restore the memory data. If a compare error occurs in the check sequence PASS1-PASS6, an error print is made. If no error occurs through all address, the check ends normally. The following address check is performed further.

Description Drawer open sensor detected. (Drawer opend) Drawer open sensor not detected. (Drawer closed)

Check point address =

a) Check opening of the specified drawer. b) Check the display indication when the drawer is open and closed.

4) Test termination
Press any key. The test terminates with the test and message printed
7-SEGMENT DISPLAY:

1E0000H, 1E0001H 1E0002H, 1E0004H 1E0008H, 1E0010H 1E0020H, 1E0040H 1E0080H, 1E0100H 1E0200H, 1E0400H 1E0800H, 1E1000H 1E2000H, 1E4000H 1E8000H, 1F0000H

1 2 0

110
3) Check the following items:
Check the termination printout.

[10] Drawer open sensor test (For remote drawer)

1) Key operation
111 CA/AT

4) Test termination
The test terminates after printing the termination printout. Termination printout: Normal termination Abnormal termination 120 120

Ex

2) Functional description
State of the drawer open sensor is sensed and displayed. X = 01: Data check error 02: Address check error Note: When an error occurs, the error print is performed and the check is terminated. The error occurrence address is shown in . hexadecimal at positions shown with

1 1 1

54

[12] Standard ROM test

1) Key operation
130 CA/AT

2) Functional description
Adujustment width of TPW at the test point TP1. The pulse width of TPWW canw bwe adjusted using the 200K pot VR1.

2) Functional description
Sum check of the standard ROM (C00000H - C7FFFFH) is performed. If the lower two digits of SUM is 10H, it is normal.
7-SEGMENT DISPLAY:

1 3 0

3) Check the following items:

Check the printout after the test.

4) Test termination
The test automatically terminates with termination message. Normal termination print ROM1 Error termination print E ROM1 27020 130 27020 130

TP VR1

GND

Note: " " means the ROM version number. The underlined section (10 bytes) of code table is provided in the ROM as a standard and the table content is always printed. The table position is the upper 10 digits of the ROM address. The check sum correction address is the last address -0FH.

MAIN PWB

[13] Printer dot pulse width adjustment

1) Key operation
150 CA/AT

TPW=3703(s)

3) Check items
a) The pulse width of TPW must be adjusted to that at the above test point TP1.

4) Test termination
Do the program reset.

[14] Option RAM test

1) Key operation
200 CA/AT

JOB #NO. 200

RAM NO. Option RAM

Memory to be checked ER-03RA

Address area to be checked 200000H 27FFFFH

2) Content
The following check are performed for the optional RAM. The following process is performed for memory addresses to be checked. PASS1: memory data save PASS2: Data "0000H" write PASS3: Data "0000H" read and comparison, data "5555H" write PASS4: Data "5555H" read and comparison, data "AAAAH" write PASS5: Data "AAAAH" read and comparison PASS6: Memory data restore

55

If a compare error is found in the check sequence from PASS1 to PASS6, error print (error code E1) is performed. If there is no error found to the end of the last address, the operation is completed normally. Then the following address check is performed. " " shows a valid address, and "!" shows an invalid address. In case of an error, error code E2 is printed. Check Address 200000H 200001H 200002H 200004H 200008H 200010H 200020H 200040H 200080H 200100H 200200H 200400H 200800H 201000H 202000H 204000H 208000H 210000H 220000H 240000H 260000H
7-SEGMENT DISPLAY:

Display:

5 0 0
4) Test termination
This check is terminated automatically. The test terminates with the test and message printed
Normal end RS TEST Error RS TEST NG ER XX OK

JOB#201(ER-03RA)

XX: Error code E1 E2 E3 E4 E5 E6 ER-DR error ER-CI error RS-CD error RS-CS error SD-RD error (DATA error) SD-RD error (DATA error/Flaming error)

2 0 0

3) Check the following items.

Check the termination print.

4) Test termination
The test terminates after printing the termination printout. Termination print E01--E02--200 200 200 : Error address (data check error) (address check error) (normal end)

[15] RS-232 loop back test

Connect the loop back connector(UKOG-6705RCZZ) to RS232 connector.

1) Key operation
500 CA/AT

2) Functional description
Control signal check OUT PUT /ER /RS OFF OFF OFF ON ON OFF ON ON INPUT /DR OFF OFF ON ON /CI OFF OFF ON ON /CD OFF ON OFF ON /CS OFF ON OFF ON

Data communication check Perform 256-byte branch loop back test between SD and RD. DATA: $00 - $FF BAUD RATE: 9600 BPS

56

CHAPTER 6. DOWN LOAD FUNCTION

1. General
RAM data can be transmitted in the following two methods. Save the data before servicing as follows: ECR ECR

3. Location of connector pins

ECR-ECR cable
9PIN D-SUB ECR SD 3 3 9PIN D-SUB ECR SD

Cable: 9 pin D-SUB 9 pin D-SUB

ECR ECR

RD

RD

RTS

RTS

Fig. 1-1 ECR ER-02FD

DCD

DCD

Cable: 9 pin D-SUB 25 pin D-SUB

DTR

DTR

ECR

ER-02FD

DSR

DSR

Fig. 1-2

CTS

CTS

2. SIO interface specification

1) Operation: 2) Line configuration: 3) Data rate: 4) Sync mode: 5) Checking: 6) Code: 7) Bit sequence: 8) Line level: 9) Data forma: Simplex Direct connect 19200, 9600, 4800, 2400, 1200, 600, 300BPS (Selected by SRV JOB#903-A) Asynchronous Vertical parity (odd) 7 bits (ASCII) LSB first RS232 level

SG

SG

SD : TRANSMITTED DATA RD : RECEIVED DATA DTR: DATA TERMINAL READY DSR: DATA SET READY RTS: REQUEST TO SEND DCD: DATA CARRIER DETECTOR CTS: CLEAR TO SEND

Fig. 3-1

LSB b1 b2 b3 b4 b5 b6 b7

MSB P

Start bit

Parity bit

Stop bit

FIg. 2-1

61

ECR-ER-02FD cable
25PIN D-SUB ER-02FD SD 2 3 9PIN D-SUB ECR SD

5. Data format
A single byte image of the RAM data to be transmitted is divided into a high order 4 bits and low order 4 bits and converted into ASCII code. Then, the image of the memory is sent in the following format:
1
2 3 4

RD

Data (128bytes)

RD

Memory top address: 0000H FFFFH Top address of the memory to be transmitted in ASCII number.
RTS 4 7 RTS

Page:1F 27,00 Page of the memory to be transmitted in ASCII number.

DCD 8 1 DCD

Sum check End code: Hex 0D

DTR

20

DTR

NOTE:

In order that contents of RAM memory may not over-ride pages for
DSR 6 6 DSR

this job, RAM image is sent in unit of 64 bytes from the address 0000. In other words, 128 bytes are sent at one time on the transmit data format. RAM DATA FORMAT

CTS

CTS

Exhibit:
BD 7E 83 FC 03 B6

SG

SG
42 44 37 45 38 33 46 43 30 33 42 36

FG

FRAME GROUND is connected to the shield of the cable.

Code table HEX 0 1 2 3 4 5 6 7 ASCII 30 31 32 33 34 35 36 37 Character 0 1 2 3 4 5 6 7 HEX 8 9 A B C D E F ASCII 38 39 41 42 43 44 45 46 Character 8 9 A B C D E F

SD : TRANSMITTED DATA RD : RECEIVED DATA DTR: DATA TERMINAL READY DSR: DATA SET READY RTS: REQUEST TO SEND DCD: DATA CARRIER DETECTOR CTS: CLEAR TO SEND FG : FRAME GROUND

Fig. 3-2

4. Application specification
The following service (SRV) modes are available for the serial data transfer of the ECR 1) Data transmit (Source side)
All data 996
X

6. END record
30 30 30 30

CA/AT (Baud rate setting: #903-A) SBTL

End message: End massage: Sum check End code:

Fixed to 30303030. Fixed to 4646.

(Auto baud rate setting: ECR to ECR only)

X: 0=SSP DATA 2) Data receive (Target)

998
X

CR (0D)

CA/AT (Baud rate setting: #903-A) SBTL (Auto baud rate setting: ECR to ECR only)

62

7. Operational method
1) To prepare an ECR to receive data from another ECR or the ER-02FD, the memory size of the receiving unit must the same as or greater than the sending unit. 2) Master reset the receiving ECR. 3) Connect loader cable between ECRs. 4) Set the receiving ECR ready to receive.
998
X

8. Saving/Loading of data to/From the FD unit Configuration

1) Turn off the power switch of the ER-02FD, and set the DIP switches of the FD unit as follows:

ER-02FD (The ER-01FD functions of the ER-02FD are used.)

DS-1 1 2 3 4 5 6 7 8 OFF ON OFF ON OFF OFF OFF ON Data rate 4 6 OFF OFF ON OFF OFF ON ON ON Disk format CCP/M: OFF PC-DOS: ON DS-2 2 3 4 ON OFF OFF

CA/AT (Baud rate setting: #903-A) SBTL (Auto baud rate setting: ECR to ECR only)

1 X

5) Start the sending ECR.

All data 996
X

CA/AT (Baud rate setting: #903-A) SBTL

Rate [bps] 19200 9600 4800 2400

(Auto baud rate setting: ECR to ECR only)

X: 0 = SSP 6) Transmission status. Description of error status 1: Application error (Command error) 2: Application error (Parity error) 3: Application error (Check sum error) 4: Application error (Data size error) 5: Hard ware error 6: Power off error 7: Time out error 11: Application error (Transmit data size error) 12: Application error (Block sequence error) 7) Service reset the receiving ECR.

2) Connect the cable.

Saving data
1) Turn on the power switch and insert a floppy disk which has been formatted. 2) Start the SEND JOB on the ECR side as follows:
All data 996
X

CA/AT

X: 0 = SSP 3) Data transmission is started and the green lamp on the ER-02FD blinks.

Loading data
1) Turn on the power switch and insert the floppy disk which stores the data. 2) Start the RECEIVE JOB on the ECR side as follows:
998
X

CA/AT

3) Press the SEND key on the FD unit. 4) Data transmission is started and the Green lamp on the ER-02FD blinks. 5) Service reset the ECR.

63

CHAPTER 7. SERVICE PRECAUTION

1. Error code table
When the following error codes are displayed, press the key and take a proper action according to the table below. Error code E01 E02 E03 E04 E05 E07 E11 E12 E26 E27 E31 E32 E33 E34 E35 E36 E37 E39 E67 E76 E86 E87 E88 E94 Registration error Misoperation error Undefined code is entered. Paper empty Secret code error Memory is full. Compulsory depression of the i key for direct finalization Compulsory tendering File type error Power-off Compulsory non-add code entry No entry of your cashier code The current cashier code should not be changed. Overflow limitation error The open price entry is inhibited. The preset price entry is inhibited. The direct finalization is inhibited. Power-off during validation printing Registration buffer is full. The drawer is still opened. Communication error Data format error Time-out error Age verification error The dept./PLU is protected by the age limitation. Close the drawer. Enter a non-add code. Make a cashier code entry. Change a cashier after finalizing the transaction. Make a registration within a limit of entry. Make a preset price entry. Make an open price entry. Make a tendering operation. Print a validation again. Error status Make a correct key entry. Make a correct key entry. Enter a correct code, or declare it by the programming. Replace a journal paper roll with a new one. Enter a correct secret code. Expand the file within a capacity of memory. Press the i key and continue the operation. Make a tendering operation. Create files correctly. Action

2. Conditions for soldering circuit parts

To solder the following parts manually, follow the conditions described below. PARTS NAME Front LED (HDSP5621) Pop-up LED (HDSP-F501#S02) PARTS CODE LOCATION Front LED PWB: FND1-5 Pop-up LED PWB: FND1-10 CONDITIONS FOR SOLDERING 315C/2 sec. 315C/2 sec.

71

CHAPTER 8. CIRCUIT DIAGRAM & PWB LAYOUT

1/10

1. MAIN PWB CIRCUIT DIAGRAM POWER SUPPLY(MAIN PWB)

D
HEAT SINK Q2 C4153 L2 D3 1SR154-400 +5V VDD 1SR154-400 R8 180 ZD1 PTZ6.2A R216 150 C206 330uF/16V BT1 BATTERY C207 330uF/16V D4 R6 3.6KF 220uH R5 10 5 2 IC2 KA34063A R7 1KF C205 1000uF 16V D2 SFPL-52 3 4 VCH

F1

FUSE

6 1

CN1

+24V

GND

1 2

PS CN C1 0.1uF 50V C2 220P

100U/50V

FROM PS PWB

C
VBT CN2 2 1 BTCN C120

0.1uF/50V

81
<DOT PULSE ADJ>
+24V +5V +24V 1 D6 E102 R15 3.3K R16 62K +24V R13 15KG 7 6 IC3B 4 C4 ZD3 UDZ4.3B KIA393F R14 9.1KG ZD2 UDZ5.1B PE 3-4D 3 C208 1u/50V 2 4 IC3A KIA393F C3 1000P 8 1 /P0FF 3-8C TP R12 8.2KG 2 R17 2K R11 2.7K R10 56K D7 1SS353 R9 2.7K +5V

<P-OFF CIRCUIT>

+24V +5V

R18 130KF

D5

1SS353

VR1 200K 8

3-8D

TRG

Q3 KRC106S

10000P

CPU(HD6415108)
+5V +5V C51 0.1u OS R77 33 C43 330P R76 10K C42 330P R74 10K C41 330P R205 47 /AS 3-8C +5V +5V /RD 3-7D +5V /WR 3-7D R78 10K C52 0.1u C53 0.1u C209 100u10V C210 47u16V

2/10

+5V

RA1(R19~R26) 10K 1 2 3 4 5 6 7 8 9

D[0..7]

3-8C

D
R75 +5V 33 +5V OS 33u10V IC4 33 5-6A 3-8B /RESET NMI 8-4B 8-4B 8-8B 4-4C 4-4C 8-2B +5V 1 3 2 X1 14.7456MHz R69 4.7K FIL1 100P C232 R73 R165 4.7K

D0 D1 D2 D3 D4 D5 D6 D7

C5~C12 330PX8

+5V

R43~R50 10K X8 +5V R35~R42 10K X8

R72 10K PHAI C44 150P +5V R70 1K +5V R71 1K 3-8B 3-8C

ERC LDRQ /SHEN /FRES BUSY /RDY PDS

+5V

RA2(R27~R34) 10K 1 2 3 4 5 6 7 8 9

A[0..23]

33 33 33 33 33 33 33 33

R52 R53 R54 R55 R56 R57 R58 R59

C
TXD2 RXD2 TXD RXD SCK2 /IRQ1 /IRQ0 10-8C 10-8C 3-8B 6-2C 3-8B

3-8B

+5V 4.7KX4 R63 VPJ 7-4B

+5V

+5V

+5V

R67 10KF R68 R64 R65 R66 1.2KF

+24V

82
C13~C20 330PX8 +5V 3-4B +5V /WAIT CPU(HD6415108) R51 10K C37 100P 7-4A 7-7A 7-7A DOPS /DR0 /DR1

HP /RI /RSS +5V /CDS /CSS /DRS /ERS R62 10K

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15

7-4D

/STOP C40 330P TRGI +5V 3-4A

A16 A17 A18 A19 A20 A21 A22 A23

8-7B

C29~C36 330PX8

C21~C28 330PX8

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 /RES NMI VSS D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VSS A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 VSS A16 A17 A18 A19 A20 A21 A22 A23 VSS WAIT BACK BREQ DOPS P34 P35 P36(DR3) P37(DR4) VCC P40 R60 10K R61 10K STBY MD2 MD1 MD0 VCC RFSH LWR HWR RD AS E PHAI VSS XTAL EXTAL VSS TXD2 RXD2 TXD1 RXD1 SCK2 SCK1 IRQ1 IRQ0 VCC AVCC VPPS VPTEST VPR VPJ AVSS VSS HP P67 RCO P66 P65 P64 P63 P62 P61 P60 STOP P57 P56 FMRS P54 P53 P52 P51 TRGI VSS OPBS SHEN NEJ P44 P43 P42 P41 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57

/NER /PRST /NEJ /PTMG

7-1A 3-4A 7-1B 3-4A

<NOTE>

100

C45 C46 C47

1000P

R79 R80 R81

C38 330p

C39 330p

+5V

10K

R82 R83 R84

330P

C48 C49 C50

GATE ARRAY(MPCA7)

3/10

+5V

D
IC5 PE 1-4A +5V

R85 10K +5V

7-8B 7-8B

/ACUTO /VPF0

7-8A 7-7C 7-7A 6-2C 1-5A

PFR0 PFJ0 /STAMP0 /RES TRG

+5V R110 100 R109 R108 +5V C69 1000P C70 1000P C71 1000P R107 10K 100 100

+5V

+5V

+5V

+5V

C54 0.01u

R86 10K

R87 10K

R88 10K

R89 10K

R90 10K

FRD FSCK FSD

4-4C 4-4C 4-4C

1-1A

/POFF

8-4B 8-7A 8-4B

HTS /SCK STH

C55 330P +5V 7-7C R98 10K R99 10K R100 10K +5V +5V +5V +5V

C56 330P

C57 330P

C58 330P

C59 330P

7-6C VRESC 7-7B 7-7B 7-4B 7-4C

RAS3

5-8B

C
DOT1 DOT2 DOT3 DOT4

2-1D 2-1D 2-1D 2-1C

/AS /RD /WR PHAI

DOT8 DOT9 MTD /MTD DOT5 DOT6 DOT7 R101 10K

+5V

+5V

+5V

+5V

+5V

+5V

C
R102 10K R103 10K R104 10K R105 10K R106 10K R116 10K R217 10K

+5V

+5V

R91 10K

R92 10K

D[0..7]

2-8D

D0 D1 D2 D3

7-6D/B RJTMG(DP) RJRST(RP) RAS1 5-3D RAS2 5-5A /ROS1 /OPTCS /EXINT0 /TRQ1 /WR0 /RD0 5-7C 6-2C 6-2C 6-2C 6-2C

83
/WAIT 2-6B +5V +5V +5V C60 330P R95 10K R96 10K R97 10K MA15 5-8B /PRST /PTMG TRGI 2-2A 2-2A 2-2B G.A(MPCA7) +5V +5V R93 10K R94 10K /RDY

D4 D5 D6 D7

2-5C 5-6A 8-8B 2-1C 2-1C 2-1C 2-1C

NMI /RESET /SHEN RXD2 TXD2 SCK2 /IRQ0

A[0..23]

2-8C

A0 A1 A2 A3 A4 A5

C61 330P

C62 330P

C63 330P

C64 330P

C65 330P

C66 330P

C67 330P

C68 330P

C230 330P

A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 RF JF PCUT FCUT VF STAMP SLF SLRS SLMTD RES TRG TRG INT0 INT1 HTS1 SCK1 STH1 RASVZ N.U VCC VSS INTMCR VRESC SLTMG SLRST AS RD WR PHAI SDT7 SDT6 SDT5 VSS SDT4 SDT3 SDT2 SDT1 D0 D1 D2 D3 VSS D4 D5 D6 D7 SSPRQ RESET INT2 INT3 RXDI TXDI SCK1 IRQ0 A0 A1 A2 A3 A4 A5 VSS VCC A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 LCDC RASP DOTEN TWAIT N.U N.U N.U N.U N.U STH2 SCK2 HTS2 SLMTR SLMTS SLMTD RJMTR RAS3 NU VSS VCC ASKRX SYNC DOT8 DOT9 RJMTD RJMTS DOT5 DOT6 D0T7 VSS DOT1 DOT2 DOT3 DOT4 RJTMG RJRST RAS1 RAS2 ROS2 ROS1 OPTCS EXINT0 EXINT1 EXINT2 EXINT3 WR0 RD0 RA15 RA16 VSS RA17 RA18 EXWAIT WAIT MCR2 MCR1 DAX2 DAX1 RCRX IRRX VSS VCC UATX UARX UASCK IRTX RCO RCVRDY2 RCVRDY1 MA19 MA18 MA15 TEST MD0 MD1 IPLON INT4 PRST PTMG TRGI A23

160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

A23

+5V

C73 0.1u

C72 0.1u

C211 10u50V

4-4C

FMC CONTROL CIRCUIT (NOT USED)

4/10

D
+5V +5V +5V +5V

R118 56K

R119 56K

R120 56K

R121 56K

VCH

+24 CN3

IC6 KIA7812

1 Q4 KTA1664 /FRES 2-5C FSD 3-1D FRD 3-1D 3-1D FSCK 2-5C BUSY /RDY 3-3A 2-5C

C
R113 1.2K C213 10u/50V R114 3.3K

C212 0.33U/50V C74 0.1u/50V

R112 820

VR2 5K

R111 68

1 2 3 4 5 6 7 8 9 10 11

GND VPP VCH FRES FSD FRD FSCK BUSY RDY VCON VPF FMC CN

84
Q5 A1036 JP1 Q36 KRC106S R117 10K

+5V

R115 3.9K

Not moun ted

MEMORY

5/10

2-1D 2-1D

/RD /WR

2-8C

A[0..18]

D
+5V C79 100P A15 R125 IC7 ROM1 VDD VDD IC9 IC8 0 OHM C80 100P

2-8C 4-7D 3-8C 3-2C RAS2 3-1C RAS1

D[0..7]

C214 47u/16V

C75 0.1u A18 A17 A14 A13 A8 A9 A11 A13 A8 A9 A11 R124 0 OHM A13 A8 A9 A11

VCC A18/PGM A17 A14 A13 A8 A9 A11 4M VCC A15 CS2 WE A13 A8 A9 A11 OE A10 CS 24 23 22 21 20 19 18 17 D0 D1 D2 GND D7 D6 D5 D4 D3 16 1M SRAM VDD C77 0.1uF C216 10U/16V C78 0.1uF C217 10/16V VDD A10 2M OE A10 CE A10 A10 21 20 19 18 17 13 14 15 D0 D1 D2 GND 1M SRAM +5V C76 0.1uF C215 10U/16V 13 14 15 16 D7 D6 D5 D4 D3 D7 D6 D5 D4 D3 D0 D1 D2 21 20 19 18 17 D0 D1 D2 D7 D6 D5 D4 D3 OE A10 CS 24 23 22 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 24 23 22 D7 D6 D5 D4 D3 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 N.C A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0

A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 32P DIP

1 2 3 4 5 6 7 8 9 10 11 12 VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 VCC A15 CS2 WE A13 A8 A9 A11 32 31 30 29 28 27 26 25 N.C A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 1 2 3 4 5 6 7 8 9 10 11 12 32 31 30 29 28 27 26 25 32 31 30 29 28 27 26 25

1 2 3 4 5 6 7 8 9 10 11 12

D0 D1 D2 D7 D6 D5 D4 D3

13 14 15

16

85
VDD IC11 VDD 1 4 6 5 IC10B 74HC00S /RESET 2-5D 3-8B D0 D1 D2 /(RAS3./RESET) 6-4B 4 VCC /WE A13 A8 A9 A11 28 27 26 25 24 23 A13 A8 A9 A11 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 OE A10 CS 1 2 3 4 5 6 7 8 9 10 22 21 20 A10 11 12 13 14 D0 D1 D2 GND C87 1000P D7 D6 D5 D4 D3 RAM(256K) 19 18 17 16 15 D7 D6 D5 D4 D3 VDD IC13 3-1C RAS2 /RESET 1 2 3 4 5 6 7 8 A B C G2A G2B G1 Y7 GND VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 74HC138 16 15 14 13 12 11 10 9 C83 100P

3-1C

/ROS1

RESET

+5V C82 100p

R122 10K

3-1C

MA15 VDD IC12

C85 100P

B
VCC /WE A13 A8 A9 A11 28 27 26 25 24 23 A13 A8 A9 A11

3-2C

RAS3

VDD

VDD

1 4

7PIN:GND

1 4

A14 A12 A7 A6 A5 A4 A3 A2 A1 A0

1 2 3 4 5 6 7 8 9 10

A14 A12 A7 A6 A5 A4 A3 A2 A1 A0

OE A10 CS

22 21 20

A10

8-8B /RESETS

10

D0 D1 D2

11 12 13 14

D0 D1 D2 GND

IC10C 74HC00S

IC10A 74HC00S

D7 D6 D5 D4 D3 RAM(256K)

19 18 17 16 15

D7 D6 D5 D4 D3

R123 10K

C88 1000P

RESET

A
C84 100P

+5V

VDD

12

1 4

C86 1000P

11

13

IC10D 74HC00S

OPTION MEMORY (OPT CN)

6/10

A[0..18] CN4

VDD

C
IC14 RAM

VCC A15 CS2 WE A13 A8 A9 A11 A15 A17 /WR A13 A8 A9 A11 /WR 2-1D /RD A10 /RD 2-1D 5-6B /(RAS3./RESET) OE A10 CS 24 23 22

A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 N.C A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND C89 0.1uF VDD DIP C90 100P D7 D6 D5 D4 D3 D0 D1 D2 16 21 20 19 18 17 D7 D6 D5 D4 D3 13 14 15

1 2 3 4 5 6 7 8 9 10 11 12 32 31 30 29 28 27 26 25

86
C218 10uF/16V

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 EFT CN NOT MOUNTED

D[0..7]

8
+5V

PRINTER & SENSER

R206 2.7K R207 2-1B +5V +24V C93 1000P COM F2 FUSE 2.2K R131 2.7K R132 3-1C 5.6K R146 VRESC 1K R128 3-3C /MTD 27K 22K /DOT1 /DOT2 /DOT3 /DOT4 C92 M0.22UF Q7 C2412K R127 R130 3.3K 3-7C 10K C91 1000P C2412K Q8 R129 CN5 RJTMG(DP) R126 3.3K Q6 C2412K 5.6K HP

7/10

COM

+5V

1K

R145 5.6K

COM

Q9 A1036

IC15

3-3C 3-3C 3-3C 3-3C

DOT1 DOT2 DOT3 DOT4

R149 R150 R151 R152

M(+)

C227 M0.1U

D8 1SR154-400

C
IC16 /DOT5 /DOT6 /DOT7 /PFJ0 +5V

3-3C 3-3C 3-3C 3-8D

DOT5 DOT6 DOT7 PFJ0

R153 R154 R155 R156

C231 100PF

+24V R133 10K R134 5.6K C228 M103 C229 103 MTD MTD 3-3C /DOT8 /DOT9 /AUTO /VPF 3-1C RJRST(RP) IC17

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 +5V PR CN

87
R136 2-3C VPJ 5.6K C96 0 OHM +24V +24V CN7 IC18 1 DS 2 /DRAW0 3 +24V DR CN C98 0.1U/50V BD14 C121 0.1U R142 47K R144 1K CN6 2-6A DOPS 1 8 3 6 14 11 4 5 /STAMP /PFR0 /DRAW0 /DRAW1 TD62308F 16 9 2 7 10 15 12 13 1 DS 2 /DRAW1 3 +24V DR CN C122 0.1U

R147 22K

3-3C 3-3C

DOT8 DOT9

R157 R158

3-7D /ACUT0

R159

Q12 C2412K

+24V

R135 10K

R148 22K

Not moun ted

+5V R138 1K Q10 C2412K R137 3.3K CN8 NES0 2 1 GND NEJ CN R210 10K R139 1K +5V C94 1000P 2-2A NEJ

3-7D /VPF0

R160

Q13 C2412K

NOT USED
DS R143 4.7K C97 1000P +5V

R211 0ohm R212 0ohm

3-8D

/STAMP0

2-6A 2-6A

/DR0 /DR1

3-8D PFR0

R161

Q11 C2412K

R140 1K R141 CN9 NES1 2 1 GND NER CN 1K R213 10k +5V

2-2A NER C95 1000P

A
R214 0ohm

R215 0ohm

DISPLAY DRIVER(CKDC8)
VCH R170 12K R171 12K Q15 A1663 Q24 A1663 R180 220 R181 220 220 R182 R183 220 R185 220 R184 220 R189 220 R186 220 R188 220 KRC106SX10 Q25 Q30 Q31 Q33 Q34 Q26 Q27 Q28 Q29 Q32 R187 220 R173 12K Q17 A1663 Q18 A1663 Q19 A1663 Q20 A1663 Q21 A1663 Q22 A1663 R175 12K R179 12K Q23 A1663 R172 12K Q16 A1663 R174 12K R176 12K R177 12K R178 12K

8/10

VDD

C219 33u/10V OS G10 G6 G[1..10] C105 33p G10' G9' G8' G7' G6' G5' G4' G3' G2' G1' G9 G8 G7 G4 G5 G3 G2 G1

G[1'..10']

R168 330K X2 32.768KHZ C106 18p +5V

X3 4.19MHz 1 2 3 2 D10 1SS353 R169 1M BZ1 BUZZER 1

1-1A

/POFF

BD10

C
R166 2.2K BD7 BD6 BD5 KR3 KR2 KR1 9-8B 9-8B 9-8B CN10 R167 12K Q14 C2412K

BD9

9-8B KR5 9-8B KR6 9-8B KR7

BD8

VDD

VDD 3 3 3 5 3 3 3 4 4 5 3 2 2 3 2 1 1 7 8 9 0 1 2 0 9 8 BKKK URRR Z 3 2 1 BD4 KR0 CN10-A 9-8B

R162 10K

D9

88
CN10-B ST[0..9] KR11 KR10 9-8C 9-8C 9-8D BD3 BD2 KR0 KR9 KR8 ST9 ST8 ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 KR11 KR10 ERC LDRQ HTS STH 2-5C ERC 2-5C LDRQ HTS 3-8C STH 3-8C R164 330 C103 330P C104 330P R208 10K R209 10K / KS RC F G4 K 27 26 14 50 49 48 47 23 22 21 20 19 18 13 12 44 43 15 16 4 6 1 1 1 2 4 1 2 3 4 0 5 6 7 8 1 7 C102 330P DP' G' 1 0 BD1 Q35 KRC106S C107 1000P 7 DP SA..DP SG IC20

1SS353

CN11

9-8C

/RES0 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10

PDS

PDS JP2 NORMAL:G7'/FISCAL:PDS FRONT CN TO FRONT LED PWB POP CN(15P) TO POP UP LED PWB

G7'

G7'

/SHEN 2-5C 3-8B

/RESETS

5-8A

C99 330P

C100 2200P

C220

36 53 54 55 56 57 58 59 60 61 62 63 45 46 24 34 35 9 25

10U/16V

KKK/ XXI XX RRRPT T C2 1 7 6 5 O2 1 F /RESET T0 T1 T2 T3 T4 T5 T6 IC19 T7 T8 T9 CKDC8 T10 SHEN /RES1 VDD1 AVRF AVDD VSS0 AVSS V V S D SI D D 1 DPABC0 DE

DP SA SB SC

A'..DP' F' 1 1 C108 C109 E' 1 2 C110 D' 1 3 C111 C' 1 4 B' 1 5 C112 C113 A' 1 6 C114 1000PX7 6 5 4 3 2 1

VDD

C101 0.1U

SD C221 SE 10U/16V SF SG KR4 9-8B /SCK 3-8C

SF

SE

SD

SC

SB

SA

A
NU

KID65003P

KEY I/F(MAIN PWB)

9/10

8-4B

ST[0..9]

KEYBOARD D11 1 5 ST5 2 4 ST0 3 3 ST1 4 2 ST2 5 1 ST3 ST4 D17 D18 D19 D20 D21 1SS353X11 7 8 9 10 11 KEY CN 6 CLERK CN CL4 D16 CL3 D15 CL2 D14 CL1 D13 D U? ST0 CN12 ST1 P-ON (NU) ST2 V0 (NU) ST3 1 GND 1SS353X4 /RES0 ST0 ST1 ST2 SW1 6 KR11 ST3 ST4 KR10 MRS SW 10 11 MODE SW CN C234~C242 330PX9 ST7 ST6 ON ST5 R190~R198 47KX9 K R 0 K R 1 K R 2 K R 3 K R 4 K R 5 K R 6 K R 7 K R 1 0 1SS353 CN15 1 2 3 4 5 6 7 8 9 KEY CN ST6 D28 OFF 7 8 9 ST8 ST7 ST6 2 3 4 5 D25 CL4 D24 CL3 D23 CL2 D22 CL1 KR10 D12 CN14 KEY74

CN13 ST4

8-4B

KR10

8-8B

/RES0

Not used
ST5

89

8-4B

KR11

R199

47K

8-5C 8-8C 8-7A

KR[0..7]

RS232C

10/10

D
+5V C222

0.1U C223 0.1U 13 C224 0.1U

C225 12 C1+ C1C2+ C2T1IN T1OUT T2OUT T3OUT T4OUT R1IN R2IN R3IN R4IN R5IN /SHDN 25 18 23 27 4 9 28 R200 R201 R202 R203 R204 100X5 FL4 1 3 T2IN T3IN T4IN R1OUT R2OUT R3OUT R4OUT R5OUT /EN 2 FL1 V17 0.1U C226 15 16 7 6 20 21 8 5 26 22 19 24 0.1U 14 V C C V+

1 1 IC21

2-2B

/RSS

/RS FL2 /ER FL3 SD

2-2B

/ERS

2-1C

TXD

2-1C

RXD

RD FL5 /CD FL6 /CI FL7 /DR FL8 /CS

2-2B

/CDS

8 10
1 0 MAX211 C115 C116 C117 C118 FB C

2-2B

/RI

2-2B

/DRS

2-2B

/CSS

C119 1000PX5

CN16

RS CN

FL

+5V

/CI

FB

D-SUB 9Pin 1 /CD 2 RD 3 SD 4 /ER 5 GND 6 /DR 7 /RS 8 /CS 9

2. MAIN PWB LAYOUT

(1) SIDE A

8 11

(2) SIDE B

8 12

3. FRONT PWB/POP UP PWB

1/1

D
<POP UP LED PWB>
G1'..G8' G7' G6' G5' G4' G3' G2' G1'

G8'

FND4

FND3

FND2

FND1

CN1

R8 27 R2 27 R1 27

R7 27 R5 27 R3 27

R6 27

R4 27

8 13
F' E' D' C' B' A'

POP CN(NORMAL)

DP'

G'

A'..DP'

4. FRONT DISPLAY PWB

8 14

5. POP-UP PWB

1/1

DIG7' FND3 CN1 FND2 FND1

DIG6'

DIG5'

DIG4'

DIG3'

DIG2'

DIG1'

FND4

8 15
POP UP CN R16 27 27 27 27 27 R18 R20 R22 R24

R10

R12

R14

27

27

27

B
F' E' D' C' B' A'

DP'

G'

6. POP-UP DISPLAY PWB

8 16

7. PS PWB

1/1

Not used
CN17 1 2 CAR BT CN HEAT SINK L1 +24V 180uH BD1 4 F1 1 C2 4 C3 22UF/50v 6,8PIN:NC 2 4700UF/50V 2 CP301 3 IC1 LM2574HVN C1 M0.033u R1 18K 3 5 7 1 R2 10 D2 PS156R R3 22KF C4 2200uF/50V R4 1.2KF Q1 KTD998 3.15A 125V T2.5AL 250V

POWER UNIT

C
1 2

CN1

1 2

PS CN

+24V GND TO MAIN PWB

8 17

8. PS PWB

8 18

COPYRIGHT

1998 BY SHARP CORPORATION

All rights reserved. Printed in Japan. No part of this publication may be reproduced, stored in a retrieval system, or transmitted, in any form or by any means, electronic, mechanical, photocopying, recording, or otherwise, without prior written permission of the publisher.

SHARP CORPORATION Information Systems Group Quality & Reliability Control Center Yamatokoriyama, Nara 639-1103, Japan
1998 March Printed in Japan