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oI
R3
oI
+ I
R3
oR
3
oI
+
oI
BL
oI
(S)
A temperature-independent bandgap reference is obtained
by setting
v
rc]
1
u anu
I
R3
1
u Therefore,
I
R3
oR
3
oI
+
oI
BL
oI
= u (6)
Where R
3
is a positive-TC resistor, whereas V
EB3
is a negative-
TC voltage. Properly setting the value of R
3
yields a
temperature-independent voltage reference,
v
rc]
1
u .
Notably, R
3
not only compensates for the temperature variation
of V
EB3
, but also adjusts the output voltage as required.
B. Input Stage (OTA)
In order to reduce the noise from VIN, Operational
Transconductance Amplifier (OTA) architecture is
implemented in Fig. 1. The PMOS and NMOS devices is used
and optimized for differential pair and current mirrors in term
of noise, input offset and good matching. For low noise an
additional 5uA sink current (M11, M12, M13, M14) can be
used to increase the current in the differential pair, such as to
reduce its noise contribution.
C. Gain Control and Input-Offset
The first pole of the LDO is made by the output of the first
stage. We use a resistor (400kOhm) in series with M48 diode-
connected transistor (1/gm) to control the output impedance of
the first stage, and thus to control the gain of the first stage.
A positive feedback loop (gain=4/5) permits to reduce the input
offset voltage, by reducing the dc current which goes into the
output of the first stage so input offset voltage can be greatly
reduced, without reducing the stability of the open loop and
improves greatly the DC line, load and temperature regulation.
D. Low Output-Impedance Buffer Stage
The parasitic pole which is constituted by the input capacitance
of the power PMOS is made at higher frequency, by reducing
the impedance of the node common drain circuit and three
series diodes (M54, M55, M56) clamp the VGS of the power
PMOS during the startup of the LDO. In bypass mode, a small
current is sink into these three series diodes, such as to force a
VGS for the power PMOS, and have VOUT=VDD-Vdrop.
E. Stability and PSRR analysis
For stability analysis of the feedback loop, small signal
equivalent circuit of the proposed on-chip LDO is shown in
Fig. 3, where Gm is the transconductance of the input
differential pairs, R0, C0 are the resistor and capacitor at the
OTA output. C
out
is the on-chip output capacitor at the output
of the LDO.
The small signal loop gain at low frequency can be given as
bellow
A
Lu
= A
01A
A
P
= 0
m
R
0
g
mP
[
1
gdsP
(R
1
+ R
2
)
R
1
R
1
+R
2
(7)
Where A
OTA
and A
P
are the voltage gain of the OTA and pass
transistor respectively, g
mP
the transconductance of the pass
transistor.
The dominant and non-dominant poles of the feedback loop
can be given as
d
=
1
2n R
0
C
c
(8)
nd
=
1
2n _
1
gJsP
(R
1
+ R
2
)] C
out
(9)
The gain bandwidth product (GBW) of the feedback loop can
be obtained from equations (7) and (8)
0Bw = A
Lu
d
=
u
m
A
P
[
2nC
0
(10)
Since the operating state of the pass transistor is dramatically
changed with the load current, the small signal gain of the pass
transistor A
P
and the capacitor C
0
at the OTA output are
dramatically affected. Correspondingly, the non-dominant pole
f
nd
locating at the LDO voltage output will change with load
current, degrading the stability of the feedback loop.
To ensure the stability of the feedback loop and improve
the transient response, a Miller R-C compensation adopted for
the worst case frequency compensation. The non-dominant
pole f
nd
should be 2 times beyond the GBW given as bellow,
1
2n [
1
gdsP
(R
1
+R
2
)C
cut
> 2
u
m
A
P
[
2nC
0
(10)
The simulation demonstrates that the capacitor should be 0.5pF
and resistor 125K Ohm for a minimum load current of 100A.
The simulated frequency response of the feedback loop with
Miller compensation is given in Fig. 5,
The LDO voltage regulator with a high PSRR over a wide
frequency range shields noise-sensitive blocks from high
frequency ripples in the power supply [4]. However, several
paths between the input and output voltage of the LDO voltage
regulator cause finite PSR over a limited frequency range [9].
Considering the direct path through the transconductance gmP
and conductance gdsP of the pass transistor, The PSRR of the
proposed LDO voltage regulator can be approximately given as
PSRR =
1 + A
P
1 +
1
g
dsP
(R1 + R2)
+
1
sC
out
+
A
Lu
1 +
s
2nJ
,
(11)
To obtain a high PSRR over a wide frequency range, both high
loop gain and dominant pole of high frequency have to be
realized at the same time.
Fig.1. Architecture of the proposed low noise low dropout regulator
Fig.2. The schematic of bandgap reference Fig. 3. Small signal equivalent circuit
EAB
VSS
VDD
Vy Vx
Rb3
R3
Q3
M6
M5
M4 M3
Q1
Rb2
Ra1
M1 M2
Ra2
R2 Rb1
Q2
Vref
Vout
-gmP
gnd
R2
Cout
R1
C0
R0
R3
VFB
Vin
Gm
Cout
Compensation Network
Power
Transistor
LowOutput-Impedance Buffer
Input Satge (OTA)
M31
M29
M21
M15
M55
MP
M46
M47
M48 M49
M44
M37 M43
M39
M40
M41
M42
M26
M20
M18
M13 M14
M11 M9 M10
M7
M8
M4
M3
M1 M2
M6
M5
M12 M17
M19 M25
M28
M27
NOISE_LOW
IBIAS
M38 M36
M50
M52
M51
M54
M56
OLIN
OLOUT
OUTPUT
VDD
M16
M24
M23
M22
VSS
M30
M32
MOSCAP
Gain and Offset Gain Control
Referance
Voltage
Bandgap
(1.2)
Il oad
III. SIMULATION RESULTS
The LDO regulator was designed using
technology. Figure 4 shows the layout of the proposed LDO
regulator, with an area of 0.1mm
2
, including feedback resistors.
The DC load and line regulation performance of the LDO
regulator are 0.10% and 0.25%, respectively.
the proposed LDO regulator performance is shown in
The input voltage ranges from 2.7 to 5V. The quiescent current
is only 90 uA. The power supply rejection ratio (PSRR) is less
than -52dB for frequencies up to1kHz. The
noise at100Hz is approximately 65 nV/SqrtHz.
Fig.4. Layout of the proposed LDO
Fig.5 Typical Curve Open-Loop transfert function
Fig.6 Typical Curve PSRR
IMULATION RESULTS
The LDO regulator was designed using 90nm CMOS
Figure 4 shows the layout of the proposed LDO
, including feedback resistors.
The DC load and line regulation performance of the LDO
respectively. A summary of
the proposed LDO regulator performance is shown in Table1.
The quiescent current
The power supply rejection ratio (PSRR) is less
equivalent output
nV/SqrtHz.
Loop transfert function
Typical Curve PSRR
Fig.7 Typical Curve Output Noise
Fig.8 Typical Curve DC Line Regulation
Fig.9 Typical Curve DC load Regulation
Typical Curve Output Noise
Typical Curve DC Line Regulation
Typical Curve DC load Regulation
Fig.10 Typical Curve DC temperature regulation
IV. CONCLUSION
In this paper, a low noise, high PSRR low-
was presented. The proposed LDO is simulated using Cadence
Spectre simulator in a 90 nm 2P9M, CMOS
simulation results justify its low noise, low quiescent current,
ultra-low noise, high PSRR low dropout linear r
proposed LDO does not need large off-chip capacitor and is
thus suitable for portable electronics.
Table 1. Performance parameters
Parameters Simulation Result
VIN 2.7V to 5V
VOUT 1.5V
Quiescent current 90uA
Dropout voltage 100mV
Load regulation 0.25%
Line regulation 0.10%
Layout 0.1mm
2
Typical Curve DC temperature regulation
-dropout regulator
imulated using Cadence
CMOS process. The
low quiescent current,
low noise, high PSRR low dropout linear regulator. The
chip capacitor and is
Result
ACKNOWLEDGMENT
This work was supported by: le Centre National de la
Recherche Scientifique et Technique (CNRST Maroc)
the TIC R&D program.
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ACKNOWLEDGMENT
d by: le Centre National de la
Recherche Scientifique et Technique (CNRST Maroc) under
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