TRNG I HC CNG NGHIP TP HCM

KHOA CNG NGH IN T

Mc lc
Mc lc ........................................................................................................................ 1
Chng 1: Tng quan v cng ngh FPGA ................................................................... 4
I. Cu trc ca cc FPGA. ................................................................................................................................4
Cu trc tng th ca FPGA bao gm: .......................................................................................................4
- Cc khi Logic ........................................................................................................................................4
- H thng lin kt mch ...........................................................................................................................4
- Cc phn t tch hp sn .........................................................................................................................4
1.1. Cc khi logic cu hnh (configurable logic Block)..............................................................................5
1.2. Cc ngun kt ni (Router). ..................................................................................................................5
II. Phn loi FPGA ...........................................................................................................................................5
2.1. Cc cng ngh lp trnh FPGA. ............................................................................................................6
2.2 Cng ngh lp trnh dng RAM tnh. .....................................................................................................6
2.3. Cc thit b lp trnh cu ch ngch(Anti-fuse)......................................................................................7
2.4. Cng ngh lp trnh dng EPROM v EEPROM .................................................................................9
III. Ngn ng m t phn cng (HDL) ..........................................................................................................10
3.1. Cc u im ca VHDL ......................................................................................................................11
3.2. Cu trc mt m hnh h thng s dng ngn ng VHDL..................................................................11

Chng 2: Tm hiu Board DE2 ca Altera ................................................................. 12

I. Gii thiu ...................................................................................................................................................12
II. Thnh phn ................................................................................................................................................13
III. Cch hot ng.........................................................................................................................................15
3.1. Cu hnh FPGA trong ch JTGA ...................................................................................................16
3.2. Cu hnh FPGA trong ch AS ........................................................................................................16
3.3. iu khin DE2 s dng lin kt Terasic ............................................................................................17

3.4. Ng ra XSGA .......................................................................................................................................17

3.5. 24-bit Audio CODEC ..........................................................................................................................19
3.6. S dng LED v cc cng tc .............................................................................................................21
3.7. S dng led 7 on v module LCD ...................................................................................................24
3.8. S dng cc Headers m rng ............................................................................................................28
3.9. S dng cc Cng ni tip (RS232) ....................................................................................................29
3.10. S dng cc Cng ni tip (PS/2) .....................................................................................................30
3.11. S dng Fast Ethernet Netword Controller ......................................................................................30
3.12. B gii m TV....................................................................................................................................32
3.13. Thc hin mt b m ha TV ............................................................................................................34
3.14. S dng USB Host/Device.................................................................................................................35
3.15. S dng cng hng ngoi ..................................................................................................................36
3.16. S dng Using SDRAM/SRAM/Flash ...............................................................................................37
IV. Mt vi ng dng ....................................................................................................................................42
V. Cc phn mm h tr ................................................................................................................................44
5.1. Gii thiu ............................................................................................................................................44
5.2. Thit k mch. .....................................................................................................................................45
5.3. Cch thc m phng hot ng trong Quartus...................................................................................51

Chng 1: Tng quan v cng ngh FPGA

FPGA(field-programmable Gate Array) y l loi IC cho php ngi thit k lp trnh
thay i cc thit k ca mnh. FPGA xut hin nh mt gii php c bn cho vn tranh
th thi gian a ra th trng v ri ro ti chnh phi gnh chu trong qu trnh nghin
cu sn phm ca cng ngh in t. FPGA l loi thit b kh trnh (PLD) tin tin nht
hin nay ca ngnh cng ngh ch to IC chuyn bit m vn c gi l ASIC.

I. Cu trc ca cc FPGA.
Cu trc tng th ca FPGA bao gm:
-

Cc khi Logic
H thng lin kt mch
Cc phn t tch hp sn

FPGA l mch tch hp cha nhiu (64 n hn 10.000) logic (logic cell) ging nhau
c th xem l cc thnh phn chun. Mi logic gi mt hay mt s chc nng c lp.
Cc ging nhau c kt ni bi mt ma trn ng dn v chuyn mch kh trnh.
Ngi thc hin thit k bng cc c trng logic n ca mi v la chn ng cc
chuyn mch trong ma trn kt ni. Mng ca cc logic v kiu kt ni l kt cu xy
dng khi c bn trong mch logic. Cc thit k phc tp c to ra bng cch kt hp
cc khi c bn to ra cc mch c m t.
M hnh tng qut ca FPGA gm mt dy hai chiu cc khi logic (logic block) c
th c kt ni bng cc ngun kt ni chung. Cc ngun kt ni (segment) c th c

chiu di khc nhau. Bn trong cc kt ni l cc chuyn mch lp trnh c dng ni

cc khi logic cu hnh (configurable logic Block) cn thit qua cc chuyn mch. Cc
khi CLB cung cp cc phn t chc nng vi cu trc s dng logic. Cc khi vo/ra
(I/O block) cung cp giao din gia cc gi chn v ng tn hiu bn trong. Ti nguyn
kt ni kh trnh cung cp cc b phn truyn dn ti kt ni u vo v u ra ca cc
CLB v cc IOB trong mng ring.
Vy cu trc FPGA gm 3 phn t chnh:
- Cc khi logic cu hnh (CLB)
- Cc khi vo/ra (IOB)
- Cc kt ni
1.1. Cc khi logic cu hnh (configurable logic Block).
Cu trc v ni dung ca logic block c gi theo kin trc ca n. Kin trc ca
khi logic c th thit k theo nhiu cch khc nhau, c th l cc cng AND 2 ng nhp,
cc b dn knh (Multiplexer) hay cc bng tm kim (Look-up Table). Ngoi ra c th
cha cc flip-flop h tr cho vic thc hin mt cch tun t.
1.2. Cc ngun kt ni (Router).
Cc ngun kt ni c cu trc v ni dung c gi l kin trc ng (Routing
Architecture). Kin trc Routing gm cc on dy ni cc chuyn mch kh trnh. Cc
chuyn mch kh trnh c cu to khc nhau nh pass-transistor, c iu khin bi cc
cell SRAM, cc phn t cu ch nghch, EPROM transitor v EEPROM transistor. Ging
nh cc khi logic c nhiu cch khc nhau thit k cc routing. Mt s FPGA cung
cp nhiu kt ni n gin gia cc khi logic, mt s khc cung cp t kt ni hn nn
routing phc tp hn.

II. Phn loi FPGA

FPGA c nhiu loi khc nhau c cu trc v c tnh ring thy theo tng hng sn
xut , tuy nhin chng c 4 loi cnh sau: cu trc mng i xng (symmetrical Array) cu
trc PLD phn cp (hierachircal PLD), cu trc hang (Row base) v cu trc a cng (sea
of gage) m t di y.

2.1. Cc cng ngh lp trnh FPGA.

C nhiu cch thc hin cc phn t lp trnh, cc cng ngh lp trnh hin ang s
dng l: RAM tnh, cu ch nghch (anti-fuse), EPROM transistor v EEPROM transistor.
Mc d cng ngh lp trnh khc nhau, tt c cc phn t lp trnh u c th cu hnh
c trong mt trong hai trng thi ON v OFF. Cc phn t lp trnh c dng thc
hin cc kt ni lp trnh c gia cc FPGA, cn FPGA thng thng c th c hn
100.000 phn t lp trnh. V vy cc phn t lp trnh phi c nhng tnh cht sau:
- Cng chim t din tch ca chip cng tt.
- C tr khng thp khi trng thi ON v tr khng cao khi trng thi OFF.
- C in dung k sinh thp khi kt ni cc on dy.
- C th ch to mt cch tin cy s lng ln phn t lp trnh trn mt chip.
C th ty thuc vo ng dng c th v c cc s lng phn t lp trnh c th c
cc c tnh khc. V mt ch to, cc phn t lp trnh nu c th ch to theo cng ngh
CMOS chun l tt nht. Di y s trnh by chi tit cng ngh FPGA.
2.2 Cng ngh lp trnh dng RAM tnh.
Cng ngh lp trnh dng RAM tnh (SRAM) s dng cng ngh CMOS tiu chun.
Cc kt ni lp trnh c iu khin bng cc transistor khc trn chip hoc bt (On) cc
transistor truyn dn cng nh cc cng transistor to nn mt kt ni hay tt (Off)
ngt cc kt ni.

Trong trng hp transistor truyn dn v cng transistor nh hnh trn, phn t RAM
Cell iu khin cng truyn bt hoc tt. Khi tt gia hai dy ni vi cng truyn dn s
c mt tr khng rt cao. Khi bt n s to mt tr khng thp kt ni gia hai dy ni.
i vi b dn knh, SRAM Cell iu khin ng nhp no ca b dn knh s c ni
vi ng ra ca n. Cch ny thng dng kt ni ty chn t mt hay nhiu ng nhp
ca mt khi.
Trong cc FPGA s dng cng ngh lp trnh SRAM, cc khi logic c th kt hp vi
nhau qua cch kt hp c b dn knh (mutiplexer) v cng truyn dn(pas-gate). V
SRAM l b nh bay hi, cc FPGA ny phi c ti cu hnh mi khi cp ngun cho
chip. iu ny c ngha l h thng s dng cc chip ny phi c c ch lu tr thng
trc cho cc bit ca RAM Cell, chng hn nh ROM hay t a t. Cc bit ca RAM Cell
c th c np vo FPGA mt cch tun t hay nh a ch nh mt phn t ca mng
(theo cch thng thng ca mt RAM).
Cc chip c thc hin theo cng ngh SRAM c din tch kh ln, bi v cn t nht
5 transistor cho mi RAM Cell cng nh cc transistor cn thm cho cng truyn dn hay
b dn knh. u im ca k thut ny l cho php FPGA c th c ti cu hnh ngay
trn mch rt nhanh v n c th c ch to bng cng ngh CMOS chun
2.3. Cc thit b lp trnh cu ch ngch(Anti-fuse)
Cng ngh lp trnh anti-fuse c s dng trong cc FPGA ca Actel-Corp, Quick
Logic v Cross Point Solution. Tuy anti-fuse c s dng trong cc loi FPGA ny c
cu to khc nhau, nhng chc nng ca chng th nh nhau. Mt anti-fuse bnh thng
s trng thi cao, nhng c th b nng chy thnh trng thi in tr thp khi c lp
trnh in th cao. Di y s gii thiu anti-fuse ca Actel v Quick Logic.
Anti-fuse ca Actel c gi l PLICE. N cu trc hnh ch nht gm 3 lp:
- Lp di cng cha cc silic mang nhiu in tch dng(n+diffusion).
- Lp gia l mt lp in mi(Oxy-Nito-Oxy cch in)
- Lp trn cng l Poly-Silic.

Anti-fuse PLICE c lp trnh bng cch t mt in th cao thch hp(18V) gia

hai u ca anti-fuse v dng iu khin khong 5mA qua thit b. Dng v p ny to ra
mt nhit lng va bn trong lp in mi lm n nng chy v to ra mt lin kt
dn in gia cc in cc. Cc transistor chu c cc in th cao c ch to bn
trong FPGA p ng cho dng v in p ln. C hai lp di cng v trn cng
ca cu ch nghch s to ra mt lin kt ni c tr khng thp (300 n 500) gia hai
dy kim loi
Anti-fuse ca Quick Logic c gi l ViaLink. N tng t nh PLICE cng nh c
ba lp kim loi. Tuy nhin, ViaLink s dng kim loi mc 1 cho lp di cng. Khi
trng thi khng c lp trnh, anti-fuse c tr khng hang G, nhng khi lp trnh n s
to ra mt kt ni gia hai lp kim loi tr khng khong 80. Anti-fuse c ch to
bng cch thm ba mt n t bit trong quy trnh ch to CMOS thng thng.
ViaLink anti-fuse c lp trnh bng cch t mt in th 10V gia cc u ca n,
dng c cp , trng thi ca Silic v nh hnh s thay i v to ra mt lin kt in
gia hai lp kim loi. Din tch chip s dng k thut anti-fuse rt nh so vi cng ngh
khc. Tuy nhin, b li cn phi c khng gian ln cho cc transistor in th cao cn gi
cho dng v p cao lc lp trnh. Nhc im ca anti-fuse l quy trnh ch to chng phi
thay i so vi quy trnh ch to CMOS.

2.4. Cng ngh lp trnh dng EPROM v EEPROM

Cng ngh c dng trong cc FPGA ca Altera Corp v Plus Logic. Cng ngh ny
ging nh s dng b nh EPROM. Khng ging CMOS transistor n gin, mt
EPROM transistor gm hai cng, mt cng treo(floating-gate) v mt cng chn (selectgate). Cng ny c gi th v n khng c kt ni in n bt k mch no.

trng thi bnh thng khi khng c lp trnh, khng c in tch gia cng treo
v transistor c th chuyn sang trng thi On mt cch bnh thng bng cng chn. Khi
transistor c lp trnh bng mt dng in lnchy gia ngun v knh, mt in tch
c gi li cng treo(phi di nh sang tia cc tm s kch hot cc electron chuyn
t cng vo cht nn ca transistor).
EPROM transistor c s dng trong FPGA theo cch khc so vi SRAM v antifuse thay v dng cho lp trnh kt ni hai dy, EPROM transistor c s dng ko
xung cc ng nhp ca logic-block.
Nh hnh v 1.6, mt ng dy gi l word line (theo thut ng b nh) c ni
vi cng chn ca EPROM transistor, khi transistor cha lp trnh trng thi ON. Word
line c th lm cho bit line khng c ni vi ng nhp ca logic-block v b ko v
mc logic 0. Nhiu EPROM transistor thc hin cc kt ni cng mt bit line, khi mt
in the ni ln ngun ni vi bit line, m hnh khng nhng cho EPROM transistor thc
hin cc kt ni m cn thc hin cc chc nng logic AND ni dy (wired-AND). Nhc
im ca phng php ny l cc in tr tiu tn nng lng c nh.
Mt u im ca EPROM transistor l chng c th ti lp trnh m khng cn b nh
bn ngoi. Tuy nhin, khng ging SRAM, EPROM khng th c ti lp trnh ngay
trn bo mch.
Phng php dng EEPROM (c s dng trong cc FPGA ca Advanced Micro
Device-AND) tng t nh cng ngh EPROM, ngoi tr EEPROM transisitor chim gp
i in tch so vi EPROM transistor v cn nhiu ngun in th ( ti lp trnh) m
cc loi khc khng cn.
Cc cng ngh lp trnh FPGA c tm tt trong bng di y:

Cng ngh
lp trnh
Static
RAM Cell
PLICE
Anti-fuse

Tnh bay C
th
hi
lp trnh
C
Trong
mch
Khng
Khng

ViaLink

Khng

Ngoi
mch

EPROM

Khng

EEPROM

Khng

Ngoi
mch
Trong
mch

Din
chip
Ln

tch R(K)

C(pf)

1-2

10-20

Anti-fuse
nh
S
transistor
ln
Anti-fuse
nh
S
transistor
ln
Nh

300-500

3-5

50-80

1-3

2-4

10-20

2xEPROM

2-4

10-20

III. Ngn ng m t phn cng (HDL)

Ngn ng m t phn cng (HDL) l ngn ng lp trnh phn mm dng m hnh
hot ng mong mun ca phn cng. C hai kha cnh m HDL to iu kin m t
phn cng: m hnh hnh vi tru tng v m hnh cu trc phn cng.
M hnh hnh vi tru tng. Ngn ng m t phn cng tp iu kin d dng cho
vic m t tru tng hnh vi ca phn cng i vi cc mc ch c t (ch r chi tit k
thut). Hnh vi ny khng ch b chi phi bi cc kha cnh cu trc hoc thit k ca
nh phn cng.
M t cu trc phn cng. Cu trc phn cng c kh nng c m hnh trong ngn
ng m t phn cng m khng cn quan tm n hnh vi thit k.
VHDL c xem nh l s kt hp ca cc ngn ng sau: ngn ng tun t + ngn
ng ng thi + netlist + nh thi + m phng. Do cu trc VHDL cho php th hin
cch thc thc hin theo kiu song song hay tun t ca mt h thng s c hoc khng
c timing. N cng cho php v m hnh mt h thng bng cc lin kt ni ca cc thnh
phn.
VHDL c dnh cho tng hp mch (synthesis) cng nh m phng mch
(simulation). D VHDL c th m phng mt cch y , nhng khng phi tt c cc
cu trc u c VHDL tng hp.

3.1. Cc u im ca VHDL
- Chng trnh trong VHDL c th c vit theo nhiu cu trc khc nhau: Ngu
nhin, tun t, ni chn, nh thi ch r, ngn ng dng sng.
- VHDL l mt ngn ng phn cp, h thng s c th c m phng nh mt kt ni
cc khi m cc khi ny c thc hin vi cc khi con khc nh hn.
- Cung cp mt cch mm do cc phng thc thit k trn xung, di ln, hoc t
hp c hai.
- Cung cp c hai mode ng b v khng ng b.
- Linh hot trong k thut m phng s nh s dng biu trng thi, thut ton, hm
Boolean.
- C tnh i chng: VHDL c pht trin di s bo tr ca chnh ph M v hin
ny l mt tiu chun ca IEEE. VHDL c s h tr ca nhiu nh sn xut thit b
cng nh nhiu nh cung cp cng c thit k m phng h thng.
- VHDL cung cp 3 kiu mu vit khc nhau: structural, dataflow v behavioral.
- Khng gii hn v ln ca thit k khi s dng ngn ng.
- Kh nng nh nga kiu d liu mi cung cp mt cng c hu hiu cho thit k v
m phng cng ngh mi vi mt mc rt cao.
3.2. Cu trc mt m hnh h thng s dng ngn ng VHDL
VHDL l ngn ng m t phn cng do vy m n c th c s dng lm m
hnh ca mt h thng s. H thng s c th n gin l cc cng logic hay phc tp nh
mt h thng hon chnh. Cc khi xy dng nn ngn ng VHDL gi l cc khi thit
k. C 3 khi thit k chnh:
- Khai bo Entity (Thc T)
- Khai bo Arichitecture (Kin trc)
- Khai bo Configuration (Cu hnh)
i khi ta s dng cc gi (Packages) v m hnh kim tra hot ng ca h thng
(Testbench).

Chng 2: Tm hiu Board DE2 ca Altera

I. Gii thiu
Board DE2 l board mch phc v cho vic nghin cu v pht trin v cc lnh vc
lun l s hc (digital logic), t chc my tnh (computer organization) v FPGA

Gi: 10.100.000 VN
Model: Board FPGA
Hng sn xut: FPGA
http://linhkienmach.com/FPGA_DE2_Altera_Gia_Re

II. Thnh phn

Kit DE2 c rt nhiu tnh nng cho php cc nh thit k thc hin mt khi lng ln
cc h thng, mch chc nng t n gin n phc tp. Di y l cc tnh nng
c cung cp sn trn kit DE2:
- FPGA:
+ Vi mch FPGA Altera Cyclone II 2C35
+ Vi mch Altera Serial Configuration device - EPCS16
- Cc thit b xut nhp
+ USB Blaster
* Dng lp trnh v iu khin API ca ngi dng
* H tr cc ch JTAG v AS khi s dng NIOS II
+ B iu khin Cng 10/100 Ethernet.
* Tch hp MAC v PHY vi mt giao din x l chung
* H tr 100Base-T v cc ng dng 10Base-T.
* H tr ch hot ng song cng y ti 10Mb / s v 100MB / s, vi tnh
nng t ng MDIX
* Hon ton ph hp vi IEEE 802.3u Spec
* H tr cc chun giao thc IP/TCP/UDP
+ Cng VGA-out
+ B gii m TV v cng ni TV-in
* S dng ADI 7181B a nh dng SDTV Video Decoder
* H tr NTSC-(M, J, 4.43), PAL-(B / D / G / H / I / M / N), SECAM.
* Xung clock t ngun dao ng 27 Mhz
* Nhiu lp trnh tng t cc nh dng u vo: Composite video (CVBS), SVideo(Y/C) v cc thnh phn YprPb
* H tr cc nh dng u ra k thut s (8-bit/16-bit): ITU-R BT.656 YCrCb
04:02:02 ng ra + HS, VS, v FIELD
* ng dng: ghi DVD, mn hnh LCD TV, hp set-top, TV k thut s, Portable
+ B iu khin USB host/slave vi USB kiu A v kiu B
* Tun th y vi Universal Serial Bus Thng s k thut Rev 2.0
* H tr truyn d liu tc y v tc thp
* H tr c USB Host v thit b
* H tr hai cng USB (Mt loi A cho my ch v mt loi B cho cc thit b trn
DE2)
* Cung cp tc cao giao din song song vi hu ht cc CPU c sn, h tr
NIOS II Core
* H tr lp trnh I / O (PIO) hoc truy cp b nh trc tip (DMA)
+ Cng ni PS/2 chut/ bn phm
+ B gii m/m ha m thanh
* S dng Wolfson WM8731 24-bit sigma delta Best-Quality Audio CODEC

* jack cm line-in, line-out, v microphone

* Tn s ly mu 8 KHZ 96 KHz
* Cc ng dng cho my nghe nhc MP3 v ghi m, PDA, in thoi thng minh.
+ 2 Header m rng 40-pin vi lp bo v diode
+ Cng giao tip RS-232 v cng ni 9-pin
+ Cng giao tip hng ngoi: 115.2kb/s Infrared Transceiver
- B nh
+ SRAM 512 Kbyte
+ SDRAM 8 Mbyte
* Single Data Rate Synchronous Dynamic RAM memory chip
* T chc nh 1M x 4 x 16bit
* H tr lp trnh qua NIOS II and Terasic high-speed Multi-port SDRAM
Controller
+ B nh cc nhanh 1 Mbyte
* c trang b b nh Flash NAND 1Mbyte
* Giao din c thit k h tr ln n 4Mbye SDRAM
* Bus d liu 8-bit
* H tr truy cp thng qua c Nios II v Terasic high-speed Multi-port
SDRAM Controller
+ Khe cm SD card
* Cung cp ch SPI truy cp th SD
* H tr truy cp thng qua NIOS II vi Terasic SD Card Driver
- Switch, cc n LED, LCD, xung clock
+ 4 nt nhn, 18 nt gt
* Nt nhn chng di bi Schmitter trigger, bnh thng mc cao
+ 18 led , 9 led xanh, 8 led 7 on: dng cho led 32 mA
+ LCD 16x2
+ B dao ng 50-MHz v 27- MHz , u vo xung clock ngoi SMA

DE2 Block Diagram

III. Cch hot ng

s dng Board DE2 ta thc hin cc bc sau y:
1. Kt ni cp USB t my tnh n bng DE2
2. Kt ni cp chuyn i 9V cho Board DE2
3. Kt ni nn hnh LCD vi DE2
4. Kt ni tai nghe vi DE2
5. Nhn Power ON / OFF Bt DE2

6. Gt cng tc qua RUN

Khi Board DE2 c khi ng v chng ta s nhn thy
v nghe thy:
Tt c cc n LED dng ang nhp nhy.

 Tt c cc mn hnh 7-SEG sng t 0-F.

LCD 16x2 hin th " Welcome to the Altera DE2 Board ".
Mn hnh LCD hin th nh hnh bn
Chuyn SW17 v tr OFF (xung), bn s nghe thy mt m thanh 1-KHz.
Chuyn SW17 v tr ON (ln) v kt ni u ra ca mt my nghe nhc MP3 vi
Board DE2, bn s nghe thy m nhc t tai nghe ca bn nu bn chi nhc t my nghe
nhc MP3 ca bn (hoc my PC / iPod).
3.1. Cu hnh FPGA trong ch JTGA
* m bo in 9V c cung cp cho Board DE2.
* Kt ni cp USB vo cng USB Blaster ca DE2.
* Thit lp Switch (SW19) "RUN"
* By gi ngi dng c th s dng ch JTGA cu hnh FPGA s dng tp tin
SOF. Cc kt ni c th hin trong hnh 3.1.
* Sau khi ti bitstream xong, FPGA bt u chy theo bistream.

3.2. Cu hnh FPGA trong ch AS

Bitstream c th c ti v thng qua ch lp trnh ni tip (ch AS). Theo mc
nh , vic chuyn i c thit lp v tr ca RUN cho ch JTAG cc tp tin
bistream SOF c ti v trc tip n chip FPGA . Ch AS, ni POF bitstream c
ti v trc tip n da trn Flash-based, nn ch c s dng khi thit k c hon
thnh hoc cc thit k c kim tra khng cn my tnh.
Cu hnh ging trong ch JTAG ch khc Set the Switch (SW19) to PROG
position.
Lc ny ngi dng c th s dng ch AS cu hnh FPGA s dng POF file.

3.3. iu khin DE2 s dng lin kt Terasic

Trong board DE2 c mt lin kt c bit t MAX 3128 cho php ngi s dng chn
IO FPGA kim sot FPGA t my tnh s dng tp lnh.
DE2 Control Panel chia s cng mt lin kt JTAG v Nios II IDE iu khin cc
ng - ngi dng c th s dng ch mt trong ba lin kt bt k thi im no.

3.4. Ng ra XSGA
ADV7123 t cc thit b Analog c s dng cho 10-bit D / A chuyn i cho tn
hiu video
Cc tn hiu chuyn i sau c kt ni vi 15 chn D-Sub kt ni cho u ra
VGA. Cc mch XSGA c th h tr ln n 1600x1200 @ 100Hz.

Thi gian thi gian c hai trc ngang v dc c th c chia thnh bn khu vc:
H-Sync (a), cng sau (b), cng trc (d), v khong thi gian hin th (c).

3.5. 24-bit Audio CODEC

WM8731 c s dng thc hin 24-bit Audio CODEC trn DE2. Chip cung cp
jack line-in, line out v microphone. Tn s ly mu t 8KHZ n 96 Khz s dng bus
I2C.

3.6. S dng LED v cc cng tc

Board DE2 cung cp 4 nt nhn, mi nt nhn c x l chng di bng cc Schmitt
Trigger. Khi ta nhn nt nhn, ch 1 xung 0 c tc ng.

Ngoi ra cn c 18 cng tc set High/Low cho 18 GPIOs ca chip Cyclonell FPGA.

Board DE2 c 9 led xanh l v 18 led . Di y l s nguyn l:

3.7. S dng led 7 on v module LCD

Board DE2 c 8 led 7 on v 1 module 16x2. Module LCD c xy dng th vin font
bn trong, s dng gi tn hiu iu khin theo
S nguyn l v s chn:

3.8. S dng cc Headers m rng

Board DE2 cung cp cho ngi dng 40 chn Headers m rng. Mi header cung cp
ngun DC +5V (VCC5), DC + 3.3V (VCC33), 2 chn GND cho php ngi dng m
rng thm cc th con.

3.9. S dng cc Cng ni tip (RS232)

Board DE2 s dng chun 9 chn D-SUB kt ni cho RS-232 giao tip gia my tnh
v board. Chip truyn nhn d liu l MAX232

3.10. S dng cc Cng ni tip (PS/2)

Borard DE2 s dng chun PS/2 giao tip cho bn phm hoc chut PS/2

3.11. S dng Fast Ethernet Netword Controller

Board DE2 s dng DM9000A cho giao din Fast Ethernet. Cc DM9000A l mt
mch tch hp y v hiu qu chi ph thp, chip iu khin Fast Ethernet vi mt giao
din x l chung, mt <PHY 10/100, v 4K Dword SRAM. N c thit k vi cng
sut thp v qu trnh x l cao h tr 3.3V vi 5V IO. Hnh 3.13 cho thy s thit k
cho giao din Fast Ethernet cho DE2.

Figure 3.13 Fast Ethernet Solution for DE2

3.12. B gii m TV
Board DE2 c trang b ADV7181 nh chip gii m truyn hnh ca mnh. cc
ADV7181b gii m video c tch hp t ng pht hin v chuyn i mt tiu chun
tng t.
i truyn hnh tn hiu baseband tng thch vi cc tiu chun trn ton th gii
NTSC, PAL, v SECAM vo 4:02:02 video thnh phn d liu tng thch vi 16-bit/8bit CCIR601/CCIR656.
Giao din u ra k thut s linh hot cao, cho php hiu sut gii m video v chuyn
i trong dng kha h thng ng h trn. iu ny lm cho thit b l tng thch hp
cho mt lot cc ng dng vi cc c tnh video analog a dng, bao gm cc ngun
bng t, cc ngun pht sng, an ninh / gim st my nh, v h thng chuyn nghip.
Tt c cc thanh ghi trong b gii m truyn hnh ny c th c lp trnh bi I2C bus.

Figure 3.14 TV Decoder Circuits

3.13. Thc hin mt b m ha TV

Mc d Board DE2 khng c b m ha truyn hnh, ADV7123 cao cp (10-bit ADC
ba tc cao) c th c s dng thc hin mt truyn hnh chuyn nghip. M ha
vi phn x l k thut s thc hin bi m RTL trong FPGA.
Hnh 3.15 cho thy s khi ca mt b m ha truyn hnh c thc hin bng cch
s dng
ADV7123 v FPGA.

3.14. S dng USB Host/Device

Board DE2 cung cp c USB Host v cc thit b giao tip s dng chip iu khin
n Philips ISP 1362.
Cc my ch v thit b iu khin c tun th vi Universal Serial Bus thng s k
thut Rev 2.0, d liu h tr truyn tc y (12Mbit / s) v tc thp
(1.5Mbit/s).

3.15. S dng cng hng ngoi

Board DE2 cng cung cp mt phng tin truyn thng khng dy n gin s dng
mt b thu pht hng ngoi 115.2Kb / s Low Power

3.16. S dng Using SDRAM/SRAM/Flash

Board DE2 cung cp b nh 8Mbyte SDRAM, 512Kbyte SRAM v 1Mbyte Flash

IV. Mt vi ng dng
- ng dng lm TV box

- Chng trnh v bng chut USB (paintbrush)

- My ht Karaoke v my chi nahcj SD

V. Cc phn mm h tr
My tnh phi c ci t Quartus II s dng board DE2
5.1. Gii thiu
Quartus II l cng c phn mm pht trin ca hng Altera, cung cp mi trng thit
k ton din cho cc thit k SOPC (h thng trn 1 chip kh trnh - system on a
programmable chip).
y l phn mm ng gi tch hp y phc v cho thit k logic vi cc linh kin
logic kh trnh PLD ca Altera, gm cc dng APEX, Cyclone, FLEX, MAX, Stratix...
Quartus cung cp cc kh nng thit k logic sau:
- Mi trng thit k gm cc bn v, s khi, cng c son tho cc ngn ng:
AHDL, VHDL, v Verilog HDL.
- Thit k LogicLock.
- L cng c mnh tng hp logic.
- Kh nng m phng chc nng v thi gian.
- Phn tch thi gian.
- Phn tch logic nhng vi cng c phn tch SignalTap@ II.
- Cho php xut, to v kt ni cc file ngun to ra cc file chng trnh.
- T ng nh v li.
- Kh nng lp trnh v nhn din linh kin.
- Phn mm Quartus II s dng b tch hp NativeLink@ vi cc cng c thit k cung
cp vic truyn thng tin lin mch gia Quartus vi cc cng c thit k phn cng EDA
khc.
- Quartus II cng c th c cc file mch (netlist) EDIF chun, VHDL v Verilog HDL
cng nh to ra cc file netlist ny.
- Quartus II c mi trng thit k ha gip nh thit k d dng vit m, bin dch,
sot li, m phng...
Vi Quartus c th kt hp nhiu kiu file trong 1 d n thit k phn cp. C th dng
b cng c to s khi (Quartus Block Editor) to ra s khi m t thit k
mc cao, sau dng cc s khi khc, cc bn v nh: AHDL Text Design Files
(.tdf), EDIF Input Files (.edf), VHDL Design Files (.vhd), and Verilog HDL Design Files
(.v) to ra thnh phn thit k mc thp.
Quartus II cho php lm vic vi nhiu file cng thi im, son tho file thit k
trong khi vn c th bin dch hay chy m phng cc d n khc. Cng c bin dch
Quartus II nm trung tm h thng, cung cp quy trnh thit k mnh cho php ty bin
t c thit k ti u trong d n. Cng c nh v li t ng v cc bn tin cnh
bo khin vic pht hin v sa li tr nn n gin hn.

Sau khi ci Quartus II, giao din nh hnh v:

5.2. Thit k mch.

Mch in trong Quartus c th c thit k theo cc cch sau:
5.2.1. S khi (Block Diagram).
Trong cch m t ny, mch in to nn t cc cng logic ri rc, hay cc hm gm
nhiu cng logic tch hp (megafunctions). v mch theo cch ny, nhn New, chn
tab Device Design Files, chn Block Diagram/ Schematic File, hin:

Nhn chn Symbol Tool hin cc cng logic hay cc hm Megafuntions:

Khi chn xong cc cng logic hay hm th dng cc cng c ni dy v mch hon
chnh.
5.2.2. Cc file thit k.
Nhn New, chn tab Device Design Files, chn Verilog HDL (hay VHDL hay
AHDL). Vi cch ny, mch in c m t bi cc on m th hin cc u vo u
ra ca cc khi mch cng nh cch x s ca chng. Trong lun n ny, ly v d v thit
k mch m 4 bit dng Verilog HDL file.
To file mi:
T giao din ca Altera Quartus chn File/New Project Wizard. Hin:

Nhn Next/Next hin ra bng Thit lp linh kin (Family & Device Settings), chn
linh kin FPGA m ta dng, ri nhn Finish.
Lc ny, ta s c c Project u tin.

Thm file Thit k vo Project

Nhn File/New .
to ra file thit k cho D n, ta c th
dng
s

khi
(nhn
Block
Diagram/Schematic File) hay dng mt trong
cc ngn ng m t phn cng nh: AHDL,
Verilog HDL hay VHDL hoc c th dng
kiu EDIF. y, chn dng ngn ng
Verilog HDL.

- B m nh phn 4 bit:
Mt b m nh phn 4 bt gm 2 u vo: u vo xung m (clock), u vo xa b
m v 0 (clear) v 4 u ra nh phn Q0, Q1, Q2, Q

on m dng Verilog m t b m trn nh sau:

//4-bit Binary counter
module counter(Q , clock, clear);
// I/O ports
output [3:0] Q;
input clock, clear;
//output defined as register
reg [3:0] Q;
always @( posedge clear or negedge clock)
begin
if (clear)
Q <= 4'd0; //Nonblocking assignments are recommended
//for creating sequential logic such as flipflops
else

Q <= Q + 1;// Modulo 16 is not necessary because Q is a

// 4-bit value and wraps around.
end
endmodule
Dng b son tho sn c ca Quartus a on m ny vo file Verilog va to ra,
ri Save vi tn ph hp.

Dng on m mu ca Verilog.
Quartus to sn mt s on m Verilog mu h tr ngi thit k. Chn Edit/Insert
Template/ Verilog HDL. C kh nhiu khi c m t sn bng Verilog nh: b m,
ghi dch, b cng, cc khi nh RAM, ROM... y cng l cch ngi dng c th hc
thm v ngn ng Verilog.
Bin dch:

 bin dch File nhn Processing/Start Compilation. Quartus s bin dch file
dem4bit.v. Sau khi hon thnh, hin thng bo. Full Compilation was successful (Bin
dch thnh cng). Bin dch gm 4 qu trnh thnh phn:
Phn tch v tng hp (Analysis & Synthesis)
Qu trnh ny s xem xt thit k logic to ra c s d liu thit k, thc hin tng
hp logic v ti u ha thit k.
Fitter(cn i yu cu v ti nguyn)
Qu trnh ny c xem nh l t v tr (cng logic) v nh tuyn (gia chng) Place and Router. S dng c s d liu c to ra bi qu trnh phn tch v tng hp,
cng c Fitter s cn i gia cc yu cu v thi gian, logic ca D n thit k vi cc ti
nguyn kh dng ca linh kin. N s n nh mi hm logic n mt n v logic m ti
u nht v thi gian truyn v nh tuyn cng nh la chn ng ni ph hp v gn
chn linh kin.
Assembler. (hp dch)
Qu trnh hp dch da vo kt qu ca qu trnh Fitter s to ra hnh nh ca thit k,
c th trong cc dng sau: Programmer Object Files (.pof), SRAM Object Files
(.sof), Hexadecimal (Intel-Format) Output Files (.hexout), Tabular Text Files (.ttf),
and Raw Binary Files (.rbf).
Classic Timing Analyzer (Phn tch thi gian).
Phn tch thi gian cho php xc nh xung nhp, cc yu cu v thi gian vo/ra (I/O)
nhm tha mn mc ch nh thi. Qu trnh ny s xc nh tnh nng tc cho ton
b D n, cho tng khi thit k v cho vic truyn, nhn ca cc nt v chn linh kin.

5.3. Cch thc m phng hot ng trong Quartus.

Cng c Simulator tch hp sn trong Quartus II cho php m phng hot ng ca D
n (Project). Trc khi m phng cn to ra danh sch ng kt ni(netlist) bi vic
nhn Processing/Generate Functional Simulation Netlist.
c th quan st c dng sng m phng, cn to ra file khc lu tr dng sng, bi
vic chn File/New/Other Files/Vector Waveform File.
thm cc tn hiu vo/ra cho Vector Waveform File, chn Edit/ Insert Node or Bus,
nhn Node Finder.

Hnh v. Giao din Node Finder

Trong danh sch trn, chn 2 u vo Clear, Clock
v u ra Q, nhy p vo cc tn hiu . Cc tn hiu
ny s hin ra trong danh sch Selected Nodes. Nhn
OK.
n nh dng sng cho 2 tn hiu vo l Clock v
Clear, nh du chn vo dng sng, trn thanh
WaveForm Editor chn Overwrite Clock, hin :
Time Range chnh l khong thi gian mun quan st
dng sng. Chu k ca tn hiu cho trong Period, rng
xung trong Duty Cycle.

Hnh v. Giao din Waveform File.

C 2 kiu m phng trong Quartus l Functional v Timing. Vi kiu Functional, ch
kim tra hot ng thun ty logic, cn vi m phng Timing, kim tra hot ng logic
c tnh n yu t thi gian, nh: tr, qu ...
chy m phng, chn Processing/Start Simulation.