Li ni u phc tp ca mch tch hp gia tng rt ln trong hn 10 nm qua.

a.Vo thp nin 80, thit k mt con chip cha vi triu transistor kh tng tng ni.Ngy nay nhng mch tch hp c vi triu transistor l iu thng thy.S gia tng tnh phc tp trong mch tch hp ch yu l do kt qu ca vic tch hp nhiu chc nng trn mt chip n.Vi nhng thay i c bn ny, phng php thit k thng thng bng s mch (schematic) tr thnh mt cn tr cho nhng k s thit k. Thc s qu kh khn cho k s thit k c th "v bng tay" mt s lng ln nhng s mch cn thit cho mt chc nng mch mong mun. Thm vo , mch tch hp c y ra th trng vi tc nhanh lm co li khung thi gian ra th trng ca chip ( time to market). Ngi thit k b t di p lc thit k nhiu chip phc tp hn vi tc nhanh hn. Th tng tng k s thit k cn phi v hng triu transistor trong s mch. Cng vic ny gn nh l khng th. iu ny i hi mt phng php hiu qu v nng sut hn l cho php ngi thit k to ra s mch vi s lng ln cc cng trong mt khung thi gian hp l. Nhu cu ny dn n s php trin ca ngn ng m t phn cng. (Hardware Description Language) (HDL) Phng php mi ny cho php ngi thit k m ha chc nng logic ca mt mch trong HDL. M ny sau s c tng hp (synthesize) thnh nhng cng logic s dng cng c tng hp (synthesizer). C hai kiu ngn ng m t phn cng c dng trong cng nghip: Verilog v VHDL. Quyn sch ny ch trnh by v Verilog. Quyn sch ny c vit dnh cho sinh vin v k s hc vit m Verilog tng hp c (synthesizable Verilog code).Chng 1 gii thiu vic dng VHDL v Verilog. Chng 2 m t lung thit k vi mch ng dng c bit (ASIC). th lung (flow charts) v m t c dng gip ngi c hiu r v ASIC. Chng 3 trnh by nhng khi nim c bn v m Verilog. Chng ny ch ra cho ngi c vic s dng s (numbers), ghi ch (comments) v nhng kiu d liu trong Verilog. Vic s dng nhng primitive mc cng cng nh do ngi dng nh ngha cng s c gii thch trong chng ny. Chng 4 trnh by nhng thi quen thit k v phong cch vit m c dng cho tng hp. Cch t tn (naming convention), phn vng thit k, nh hng ca nhng vng lp nh th, to tn hiu xung ng h, s dng reset v danh sch nhy (sentivity list). Khi nim v cu lnh blocking (kha) v non-blocking s c trnh by chi tit. V d v dng sng c dng xuyn sut gip ngi c hiu nhng khi nim ny.Chng 4 cng trnh by nhng v d v phong

cch vit m thng dng cho nhng ton t Verilog. Khi nim v "cht suy ra" ( latch inference), mng b nh v my trng thi cng c trong chng ny.Thit k my trng thi bao gm c t thit k (design specifications), gin trng thi ch ra chc nng ca my trng thi, m tng hp c cho my trng thi cng vi testbench kim tra chc nng ca my trng thi. Chng 5 ch cho ngi c lm th no d n thit k mch nh th lp trnh c c thc hin. Chng ny bt u vi c t cho mch nh th lp trnh c (programmable timer). Sau s l vi kin trc (microarchitecture) c to ra t c t trn c dn ra. Gin s gip ngi c d hiu hn chc nng cn thit k. M Verilg, testbench kim tra v m phng mch cng vi dng sng ra (waveform) cng c thm vo. Chng 6 trnh by v nhng khi logic lp trnh c dnh cho giao tip ngoi vi (peripheral interface). Chng ny bt u bng c t thit k ri vi kin trc cng vi gin hng gip bn c hiu r vn hn. M Verilog, testbench v dng sng ra s c dng m t mch trong chng ny. Sch ny gm nhiu v d v c vit vi tc phong thc tin. C c thy 91 v d gip bn c hiu nhng khi nim cng nh phong cch lp trnh ang c trnh by. Bt u vi nhng m Verilog n gin tin dn v d thit k thc t phc tp.Chng 4 trnh by thit k my trng thi v h thng n giao thng thng minh. Chng 5 ni v mch nh th lp trnh c bt u vi c t thit k ri vi kin trc, m verilog v cui cng l testbench.Thit k ny ch ra cho ngi c lm th no m Verilog c vit kim tra nhng khng th tng h thnh mch thc c. Nhm gip bn c hiu hn v vic lm th no nhng thit k thc t c thit k : gin , dn sng v nhng gii thch chi tit kt qu m phng c a vo. Gii thiu K t u thp nin 80 khi m s mch c gii thiu nh mt cch hiu qu thit k nhng mch c mc tch hp quy m ln ( VLSI), n tr thnh phng php c ngi thit k ca th gii VLSI la chn. Tuy nhin, vic dng phng php ny t n gii hn vo cui thp nin 90 khi c ngy cng nhiu chc nng logic v c tnh c tch hp vo mt chip n. Ngy nay, a s nhng mch tch hp c chc nng c bit (ASIC) gm nhiu hn mt triu transistor. Thit k nhng mch ln nh th ny dng s mch (schematic capture) rt mt thi gian v khng cn hiu qu na. Do , cn mt cch thit k hiu qu hn. Phng php mi ny phi tng c hiu sut ca ngi thit k va cho php thit k d dng thm ch khi lm vic vi nhng mch ln.

T s i hi ny ny sinh vic chp nhn rng ri ngn ng m t phn cng (HDL). HDL cho php ngi thit k m t chc nng ca mt mch logic trong mt ngn ng d hiu. Vic m t sau s c m phng dng testbench. Sau khi m t HDL c kim tra v mt chc nng (functionality) n s c tng hp thnh nhng cng logic bng nhng cng c tng hp. Phng php ny gip ngi thit k thit k mch trong thi gian ngn hn. Thi gian c tit kim v ngi thit k khng cn quan tm n nhng phc tp bn trong tn ti trong mt mch c th. Phng php thit k mi ny c dng rng ri trong lnh vc thit k ASIC. N cho php ngi thit k thit k mt s ln nhng cng logic thc hin c tnh v chc nng logic mong mun ca chip ASIC. Nhng ngn ng m t phn cng c dng rng ri trong cng nghip ASIC l Verilog v VHDL. Mi ci c u khuyt im ring. Phong cch vit m cho hai ngn ng ny c nhng im tng ng cng nh khc bit. Chng 2 : LUNG THIT K ASIC Thit k ASIC da vo mt lung thit k s dng ngn ng m t phn cng.a s nhng cng c thit k in t t ng (EDA) c dng cho lung thit k ASIC u tng thch vi Verilog v VHDL. Trong lung ny, thit k cng nh thc thi (implementation) mt mch logic u c m ha dng Verilog hay VHDL. M phng (simulation) c thc thi kim tra chc nng ca mch logic.Tip theo s l tng hp. Tng hp (synthesis) l qu trnh bin i m HDL thnh cng logic. Sau khi tng hp, bc tip theo l APR (auto place route) [ sp xp cc linh kin v cch thc ni dy gia chng]. APR s c gii thch chi tit hn trong phn 2.6. Hnh v 2.1 ch ra mt gin ca mt lung thit k ASIC bt u vi c t ca mt thit k ASIC n m ha RTL (Register transfer level) [vit m Verilog m t mch] v cui cng l lm mu th chip tht trn silicon (tapeout) [i khi ngi ta cn gi l Prototype].

2.1 : c t (Specifications) Hnh 2.2 ch ra nhng bc u ca lung ASIC : c t ca mt thit k. y l bc u tin ca lung thit k ASIC. Vic thit k mt chip ASIC bt u t y.

c t l phn quan trng nht ca lung thit k ASIC. Trong bc ny, c tnh v chc nng ca chip ASIC c nh ngha. Ln k hoch cho chip (Chip Planning) cng c lm trong bc ny. [Lin quan n thi gian hon thnh d n, chi ph, din tch chip ...] Trong qu trnh ny, kin trc v vi kin trc c dn ra t nhng i hi v chc nng v c tnh (features). Vic dn ra ny (derivation) c bit quan trng bi kin trc ca mt thit k ng vai tr quan trng trong vic quyt nh kh nng v hiu sut (performance) ca thit k. Bao gm mc tiu th cng sut (power consumption), mc in p, nhng gii hn v nh th ( timing restrictions) v nhng tiu chun v hiu sut. T danh sch ny, kin trc chip s c phc tho nhp (draft). Kin trc ny sau phi c xem xt tt c nhng i hi v nh th, in p, tc v hiu sut ca thit k. Nhng m phng v kin trc cn c thc hin trn kin trc nhp bo m rng n tha mn tt c nhng c t mong mun. Trong qu trnh m phng kin trc, nh ngha kin trc s phi thay i nu kt qu m phng

cho thy n khng p ng nhng yu cu v c t.Mt khi tt c nhng yu cu c t c tha mn, vi kin trc (microarchitecture) c phc tho v nh ngha cho php thc thi kin trc t mt im thit k no . Vi kin trc l cha kha cho php giai on thit k c bt u. Vi kin trc chnh l im tip gip ca kin trc (Architecture) v mch thc t. N cng cho php bin i nhng khi nim v kin trc thnh nhng thc thi thit k kh d. 2.2 : M ha RTL Hnh v 2.4 ch ra bc th hai trong lung thit k ASIC. y l im khi u ca giai on thit k. Vi kin trc c bin i thnh mt thit k bng cch m t n di dng ngn ng RTL. [ Thc cht ch l m t li s khi mch, chc nng no bng ngn ng HDL] Nh cp trong phn 2.1 ( Bc 1 ca lung thit k ASIC) kin trc v vi kin trc c dn ra t c t. Trong bc 2, vi kin trc, thc thi tht s ca mch, c vit bng m RTL tng hp c. [Nhng m t c th tng hp thnh phn cng c, v trong ngn ng nh Verilog c rt nhiu thnh phn ch dng cho m phng m khng tng hp c.] C rt nhiu cch to ra m RTL. Mt s nh thit k dng cng c nhp thit k ha. Nhng cng c ha ny cho php ngi thit k dng nhng gin nt (bubble diagram), th lung [m t my trng thi] hay bng s tht (truth table) thc thi vi kin trc sau s to ra m Verilog hay VHDL. Tuy nhin, mt s nh thit k li thch vit m RTL thay v dng cng c ha. C hai phng php u kt thc vi kt qu l m RTL tng hp c m c th m t chc nng logic ca c t.

2.2.1 : Nhng kiu m Verilog : RTL, Hnh vi (Behavioral) v cu trc (strutural) Phn 2.2 trnh by v m RTL. Trong ngn ng Verilog, c ba kiu m. i vi a s trng hp tng hp th m RTL tng hp c s c dng. 2.3 : Testbench v m phng Hnh 2.5 ch ra bc 3 trong lung thit k ASIC lin quan n vic to testbench. Nhng m ny s dc dng m phng m RTL.

Testbench v c bn l mt mi trng ng xung quanh (wraparound) bao ly mt thit k, cho php thit k c m phng. N y tp hp xc nh nhng kch thch (stimulus) vo u vo (inputs) ca thit k, kim tra hay xem xt ng ra (outputs) ca thit k bo m rng dng sng hay vector kt qu (pattern) ph hp vi mong mun ca ngi thit k. M RTL v testbench c m phng dng b m phng HDL. Nu m RTL c vit bng Verilog th cn mt b m phng Verilog.Nu vit bng VHDL th tt nhin cn mt b m phng VHDL. Verilog XL ca Cadence, VCS ca Synopsys v ModelSim ca Mentor Graphic's l nhng b m phng ph bin nht trn th gii hin nay. NCSim ca Cadence v ModelSim ca Mentor Graphic's c kh nng m phng c Verilog v VHDL.Scirocco ca Synopsys l mt v d ca b m phng VHDL. Ngoi nhng cng c k trn cn rt nhiu nhng b m phng khc. Bt chp b m phng no c dng, kt qu cui cng l kim tra (verification) m RTL ca thit k da vo testbench c vit. Nu ngi thit k thy rng dng sng u ra hay vector kt qu (pattern) trong qu trnh m phng khng khp vi ci m h ch i th thit k cn phi c g ri (debug). S sai lch c th l do li trong testbench hay l bug trong m RTL. Ngi thit k cn xc nh v sa nhng li ny bng cch chnh li

testbench ( nu nguyn nhn l do Testbench) hay thay i m RTL nu sai nm m RTL. Sau khi hon tt vic thay i, ngi thit k phi chy m phng li. iu ny s c thc thi lin tc trong mt vng lp cho n khi ngi thit k tha mn vi kt qu m phng. iu ny c ngha l m RTL m t ng hnh vi logic ca thit k. 2.4 : Tng hp Hnh 2.6 ch ra bc th 4 trong lung thit k ASIC l tng hp. Trong bc ny, m RTL c tng hp. y l qu trnh m trong m RTL c bin i thnh cng logic. Cng logic c tng hp s c cng chc nng ging nh c m t trong m RTL.

Trong bc 4, mt cng c tng hp dng bin i m RTL thnh cng logic.Hai cng c c dng ph bin trong cng nghip l Design Compiler ca Synopsys v Ambit ca Cadence. Qu trnh tng hp cn hai tp tin u vo khc thc hin vic bin i t RTL thnh cng logic. Tp tin u vo u tin m cng c tng hp phi c trc khi thc hin vic bin i l tp tin "th vin cng ngh" (technology library file).

l tp tin th vin cha nhng cell chun. [Cell dng ch rt nhiu mc mch khc nhau, mt cng AND chng hn nhng c khi c mt khi RAM hay ALU cng gi l cell]. Trong qu trnh tng hp chc nng logic ca m RTL c bin i thnh nhng cng logic s dng nhng cell sn c trong tp tin th vin cng ngh. Tp tin u vo th hai l "tp tin gii hn" ( constraints file) gip quyt nh vic ti u mch logic tng hp.Tp tin ny thng cha nhng thng tin v nh th, yu cu ti v thut ton ti u m cng c tng hp cn ti u thit k thm ch c nhng nguyn tc thit k cng c xem xt trong qu trnh tng hp. Bc 4 l mt bc rt quan trng trong lung thit k ASIC. Bc ny bo m vic tng hp c ty bin nhm c c kt qu ti u nht c th. Da vo bn ti u ha cui cng, nu nhng yu cu v hiu sut hay tn dng din tch vn khng nm trong khong cho php ngi thit k phi xem xt li t kin trc n vi kin trc ca thit k. Ngi thit k phi nh gi li kin trc cng nh vi kin trc p ng nhng yu cu v din tch v hiu sut hay cha? Nu vn cha p ng yu cu th vic nh ngha li kin trc hay vi kin trc l vic lm bt buc tuy nhin vic lm ny s dn n vic phi bt u li t u, mt hnh ng rt mt thi gian. Thm ch nu vic thay i kin trc hay vi kin trc vn khng mang li kt qu mong mun th vic phi ngh n l sa cha specs. 2.5 : Phn tch nh th tin layout Khi tng hp c hon thnh trong bc 4, c s d liu cng vi nhng thng tin v nh th t bc 4 c dng phn tch nh th tnh (static timing analysis). Trong bc 5, phn tch nh th l tin layout v c s d liu khng cha thng tin v layout.( Hnh 2.7)

M hnh nh th c xy dng v phn tch nh th ca n c thc hin trn thit k. Thng th, phn tch nh th c thc hin trn tt c cc kha cnh ca in p v nhit . [Mc in p cp ngun v nhit trong mch hot ng] Vic lm ny nhm bt tt c nhng vi phm nh th trong thit k khi s dng trong nhng gii nhit hay in p xc nh. Bt k mt vi phm nh th no (timing violations) chng hn vi phm v thi gian setup v hold s phi sa bi ngi thit k. Cch thng dng nht sa nhng vi phm nh th ny l thc hin ty bin tng hp (synthesis tweaks) sa nhng ng sai nh th. Cch thng thng sa vi phm thi gian gi (hold time violation) l a thm nhng cell tr ( delay) vo trong ng m thi gian gi b vi phm. sa vi phm thi gian setup l gim tng tr trn ng vi pham nh th loi ny. Nhng ty bin tng hp ny sau s c dng tng hp li thit k v vic phn tch nh th tnh s c lm li ln na. Bc 5 trong lung thit k ASIC i khi thay i ty thuc vo d n thit k. Mt s d n thit k s nhy ti bc 6 d cho c nhng vi phm trong vic phn

tch nh th tin layout. L do l y ch l tin layout nhng k sinh lin kt ni ( interconnect parasitics) c dng trong phn tch nh th ch mang tnh c lng v c th khng chnh xc. Mt phng php thng dng hn trong bc 5 l sa nhng sai phm v nh th vt trn mt gi tr nh trc no . Ngi thit k thit lp mt gi tr x nano giy cho php vi phm nh th. ng no vi phm vt hn x nano giy s phi sa cn nhng ng vi phm t hn s khng sa.iu ny l do nhng k sinh dng trong nh th khng chnh xc do cha c thng tin back annotation [ thng tin truy vn ngc v nh th]. 2.6 : Sp xp v ni dy t ng ( Auto Place and Route) Mt khi phn tch nh th tin layout hon thnh, c s d liu tng hp cng vi nhng thng tin v nh th t tng hp c dng cho APR.( Hnh 2.8).

Trong bc ny, nhng cng logic c tng hp s c sp xp v ni dy. Qu trnh ny c rt nhiu s linh hot m ngi thit k c th dng sp t cng logic ca mi module con (submodule) da vo k hoch lm nn c nh t trc. (predefined floor plan) a s thit k c nhng ng gng ( critical paths) rt cht v mt nh th. Nhng ng ny c th c xc nh bi ngi thit k bng ng c mc u

tin cao ( high priority paths). Cng c APR s ni nhng ng c mc u tin cao trc nhm t n vic nh tuyn ti u. APR cng l bc lin quan n vic tng hp cy ng h ( clock tree) [ S phn b xung clock trong h thng]. a s nhng cng c APR c th thc hin vic nh tuyn "cy ng h" vi nhng thut ton c bit c xy dng sn. y l mt phn quan trng ca lung APR bi v vic xy dng "cy ng h" l rt tin quyt bi nu c nh tuyn ng s trnh c hin tng sai lch clock ( clock skew). 2.7 : Back Annotation Back Annotation l bc trong lung thit k ASIC k sinh RC trong layout c trch ra. (Hnh 2.9).

ng tr c tnh t nhng k sinh RC ny. i vi nhng thit k thp hn micro mt rt nhiu, nhng k sinh ny c th to ra s gia tng ng tr ng k. Nhng ng nh tuyn di s lm tng tr lin kt ni cho mt ng no . Mt cch tim tng, iu ny lm cho nhng ng trc y ( trong bc nh th tin layout) khng gng tr thnh gng v nh th. N cng lm cho nhng ng trc y tha mn nhng yu cu v nh th tr thnh ng gng v khng cn tha mn yu cu nh th na.

Back Annotation l mt bc quan trng lm cu ni cho s khc bit gia tng hp v layout.Trong qu trnh tng hp, nhng rng buc thit k c dng bi cng c tng hp to ra mch logic mong mun. Tuy nhin, nhng rng buc ny mang tnh c lng c p vo mi thit k. Nhng rng buc thc gy ra bi k sinh RC c th phn nh ng hay sai nhng rng buc trc . Nhiu kh nng nhng c lng ny l khng chnh xc. Kt qu l iu ny gy ra s sai khc gia tng hp v layout. Back annotation l bc cu ni gia chng. 2.8 : Phn tch nh th sau layout Phn tch nh th sau layout l mt bc quan trng trong lung thit k ASIC cho php "bt" nhng vi phm thi gian gi/xc lp ( hold/setup time violation) thc t. (Hnh 2.10)

Bc ny tng t nh phn tch nh th tin layout nhng c thm nhng thng tin v layout. Trong bc ny, thng tin tr lin kt ni tng ( net interconnection delay) t back annotation c a vo cng c phn tch nh th thc hin phn tch nh th sau layout. Bt k vi phm xc lp (setup time) cn phi sa bng cch ti u ha nhng ng sai xc lp gim ng tr. Nhng vi phm thi gian gi (hold time) c sa bng cch a thm nhng b m vo tng ng tr ln.

Ty bin tng hp sau layout c dng sa cha nhng sai phm nh th ny trong qu trnh tng hp li. iu ny cho php ti u ha nhng ng "tht bi". Khi tng hp sau layout hon tt, APR, back annotation v phn tch nh th c thc hin li trong mt vng lp cho n khi khng cn mt vi phm no v nh th. Thit k by gi sn sng cho vic kim tra logic. .9 : Kim tra Logic ( Logic Verification) Khi phn tch nh th sau layout hon tt, bc tip theo l kim tra logic. Hnh 2.11 m t iu ny.

Bc ny ng vai tr cht chn cui cng bo m thit k ng chc nng. Trong bc ny, thit k c m phng li s dng testbench c sn trong bc 3 nhng c thm thng tin nh th c c t layout. Mc d thit k c kim tra trong bc 3, thit k vn c th khng vt qua c "k st hch cui cng" ny trong bc 9. S tht bi ny c th l do glitch [xung xut hin do s chuyn i trng thi ca mt tn hiu gy ra cho u ra] hay iu kin chy ua ( race conditions) do k sinh layout. Nu tht bi xy ra ngi thit k phi i ngc li bc 2 ( RTL coding) hay bc 8.

Khi thit k cui cng qua c vng kim tra logic n c a i lm mu th ( tapeout). Chng 3 : M Verilog

3.1: Gii thiu nhng khi nim c bn ca Verilog Verilog l mt ngn ng m t phn cng c dng rng ri trong thit k mch s. N cng c dng m hnh ha c mch tng t. Bt chp Verilog c dng cho mch s hay mch tng t nhng khi nim c bn ca n vn p dng ng. Khi mt ngi thit k vit m Verilog iu quan trng l phi bit mt s nhng k hiu c bn c dng trong Verilog. 3.1.1 : C php Verilog Verilog l mt ngn ng m t phn cng (HDL) cho php ngi dng m t thit k phn cng. Ging nh tt c cc ngn ng khc c nhng c php phi tun th khi vit m Verilog. Tt c nhng c php Verilog bt u vi vic khai bo module. Mt module thc s l mt "chic hp en" hay "n v" cha thit k. Khai bo module phi bao gm cng giao tip ca module. (module's interface ports) module design_module_name(interface_port_list); trong design_module_name l tn ca module v interface_port_list l mt danh sch cha tt c ng vo, ng ra hay ng ra/vo (inouts) ca module. Mi cng c phn tch bng du phy (,). Kiu ca cng giao tip cng c khai bo. c th l ng vo (inputs), ng ra (outputs) hay inout cho nhng cng hai chiu. module DUT (A, B, C, D, E); input A, B, C; inout D; output B; Nu mt cng no c nhiu hn 1 bit ta phi dng k hiu "[" v "]" ch ra rng ca bus. module DUT (A, B, C, D, E);

input [3:0] A, B; input C; inout [7:0] D; output B; 3.1.2 : Ghi ch Khi vit m HDL cho mt thit k, s dng ghi ch s hnh thnh mt thi quen tt cho nhng nh thit k mch s. Ch ra cho ngi c ci m m Verilog th hin iu g l mt phng php tt, ng thi n cng l mt dng ti liu tt dnh cho vic tham kho sau ny. Verilog cho php ghi ch mt hng hay nhiu hng. Ghi ch mt hng s dng k hiu // trong nhng ghi ch nhiu hng m u vi k hiu /* v kt thc vi k hiu*/.V d : // This is a single line comment in Verilog //* This is a multiple line comments in Verilog. Notice that it begins with a certain symbol and ends with a certain symbol*// [Tt nhin bn hon ton c th vit comment bng ting Vit khng du.V l do hin th trong bi post nn ti dng k hiu //* v *// thc t bn phi dng l /* v */] 3.1.3 : Biu din s Verilog cho php mt di rt rng cc loi s khc nhau c dng trong khi vit m t. Ngi thit k c th chn dng s thc, s nguyn, s nh phn, s trong thang thi gian, s c du v s khng du. 1. S thc c khai bo trong Verilog dng t kha real.Verilog cho php s c khai bo dng thp phn hay nh dng khoa hc. [s c du chm ng]. S thc cng c th c khai bo vi gi tr m. module real_example(); real a,b,c; initial begin a=3.141593; b=314e-3; c=-1.11; end endmodule

2.S nguyn c khai bo trong Verilog dng t kha integer, cng c gi tr m v dng cho kiu s ny. module example(); integer i,j,k; initial begin i = 150; j = -150; k = -32; end endmodule 3.S c c s v c bn l nhng s nguyn nhng c khai bo dng mt c s nht nh. Chng c th l bt phn (octal), thp lc phn (hexadecimal), thp phn (decimal) hay nh phn(binary). S c c s c khai bo trong nh dng sau: <integer_name> = <bit_size>'<base_number><value>; trong <integer_name> l tn ca s nguyn m ta cn dng. <bit_size> l s bit nh phn dng biu din s nguyn. <base_number> l c s. l o nu l s bt phn, h nu l s thp lc phn, d cho s thp phn hay b cho s nh phn. <value> gi tr ca s nguyn. module example (); integer i,j,k,l; initial begin i = 5'b10111; // this is a binary number j = 5'o24; // this is an octal number k = 8'ha9; // This is a hex number l = 5'd24; // This is a decimal number end endmodule 4.S biu din thang thi gian Thi gian m phng trong Verilog c khai bo vi t kha time. n v cho thi gian c khai bo trong b nh hng bin dch (compiler directive).Khai bo thang thi gian tun th nh dng sau:

`timescale <reference_time>/<precision>; trong : <reference_time> v <precision> phi l nhng gi tr nguyn nh 1,10 hay 100. Tuy nhin n v thi gian c php khai bo cng vi nhng gi tr nguyn ny l fs (femto giy), ps (pico giy), ns(nano giy), us( micro giy), ms( mili giy) v s (giy). module example (); `timescale 100 us/1ns; // this is for //reference of 100 us and precision of 1ns [ c ngha l mi gi tr nguyn sau ny cc bn s dng s c nhn vi 100 us. V d bn khai bo tr l #20 ~~~> tc l thi gian tr thc s l 20 *100 = 20000 us. Nu trong qu trnh khai bo bn mun s dng s l chng hn #2.125 th s l ti a bn c th dng l 3 ch s v 1 us = 1000 ns] time t; initial begin t = $time; // $time is Verilog system function //that get the current simulation time end endmodule 3.1.4 Kiu d liu trong Verilog Verilog cho php hai kiu d liu l reg v net. Reg (vit tt ca register) l mt phn t lu tr ( storage element) n cho php gi tr c lu tr trong kiu gi liu ny. Nhng gi tr ny s c lu tr trong kiu d liu ny cho n khi c thay bng mt gi tr khc. Reg ch c dng trong nhng cu lnh ca khi always hayinitial. Kiu d liu thuc nhm net c dng nhiu nht l kiu wire thng dng biu din kt ni net. N ging nh mt ng dy ni trong phn cng do , gi tr trnwire lun c cp nht lin tc. Trong qu trnh m phng, nu khng c gi tr no c gn vo nhng i tng c khai bo kiu reg th gi tr mc nh l khng xc nh hay X. Tng t, nu khng c gi tr no c gn cho nhng i tng kiu wire th gi tr mc nh l trng thi th ba ( tri - state) hay Z ( Hi - Z). V d 3.1 : ch ra mt v d n gin dng wire trong khi v d 3.2 tng t 3.1

nhng khc ch l khai bo dnh cho bus 4 bit. V d 3.1 : M Verilog dng cho khai bo kiu wire module example (inputA, inputB, inputC, outputA); input inputA, inputB, inputC; output outputA; wire temp; assign temp = inputB | inputC; assign outputA = inputA & temp; endmodule V d 3.1 : M Verilog dng cho khai bo kiu wire vi bus 4 bit module example (inputA, inputB, inputC, outputA); input [3:0] inputA, inputB, inputC; output [3:0] outputA; wire [3:0] temp; assign temp = inputB | inputC; assign outputA = inputA & temp; endmodule V d 3.3 Ch ra mt phng php thng dng s dng reg trong v d 3.4 tng t 3.3 nhng dng cho bus 8 bit. V d 3.3 : Khai bo dng reg module example (inputA, inputB, inputC, outputA); input inputA, inputB, inputC; output outputA; reg outputA,temp; always @ (inputA, inputB, inputC) begin if (inputA) temp = 1'b0; else begin if (inputB & inputC) temp = 1'b1; else

temp = 1'b0; end end // more source code here always @ (temp or inputC or inputA) begin if (temp) outputA = inputC; else outputA = inputA; end endmodule V d 3.4 : Khai bo dng reg vi bus 8 bit module example (inputA, inputB, inputC, outputA); input [7:0] inputA, inputB, inputC; output [7:0]outputA; reg [7:0] outputA,temp; always @ (inputA, inputB, inputC) begin if (inputA) temp = 8'b1111_0000; // du gch di dng phn tch s cho d c else begin if (inputB & inputC) temp = 1'b1010_0101;

else temp = 1'b1010_1111; end end // more source code here always @ (temp or inputC or inputA) begin if (temp == 8'b1101_1011) outputA = inputC; else outputA = inputA; end endmodule Ngoi khai kiu reg v wire cn c 10 kiu d liu khc c dng trong Verilog. 1.Supply1 nh tn ch ra, n c dng cho nhng net c kt ni n ngun VCC. Ta dng t kha supply1 khi khai bo gi tr net ny. V d : supply1VCC. 2.Supply0 dng cho nhng net no s ni vi t ( ground). Ta dng t kha supply0 khi khai bo net no c kiu ny. V d : supply0 GND. 3.tri l mt kiu net dng khai bo mt net c nhiu hn 1 driver mun ly n. [ driver y bn c th tng tng l nhng li xe, cn kiu net y ging nh mt chic xe hi m nhng ti x ny cng ngi trn cabin v ai cng c th cm li n]. Trong v d 3.5 ta s thy net temp c li bi nhiu driver. V d 3.5 : M Verilog dng khai bo ba trng thi module example ( inputA, inputB, inputC, outputA); input inputA, inputB, inputC;

output outputA; tri temp; assign temp = inputA & ~inputB; // Verilog code here assign temp = inputA | ~inputB; assign outputA = temp & inputC; endmodule Kiu tri c th tng hp c. Tuy nhin, ta nn trnh dng kiu tri khi vit m Verilog. Nu mt nt (node) no c li bi nhiu driver khc nhau th nt ch nn c li bi nhng b li ba trng thi. [ Tc l trong mt thi im nht nh ch c mt driver li tn hiu m thi ty thuc vo tn hiu cho php trong nhng ng ba trng thi. Ta s bn v vn ny sau]. 4.trior cng l loi net c nhiu ng li u vo. Tuy nhin n khc kiu tri bi n l mt kiu net kt ni OR. iu ny c ngha l nu bt k mt driver no trong s cc driver ang li kiu net ny mc logic 1 th lp tc kiu net ny s cho gi tr logic 1. trior khng tng hp c v khng dng trong m tng hp khi vit m t. 5. triand cng dng nh loi net cho php nhiu driver. Tuy nhin, n khc kiu tri ch n thuc loi net kt ni AND. iu ny c ngha l bt k mt trong s cc driver ang li n c gi tr logic 0 th lp tc kiu net ny c gi tr logic 0. triand cng khng tng hp c v khng dng trong vit m tng hp. 6.trireg cng l loi net cho php nhiu driver nhng khc ch n l kiu net mang tnh dung ( capacitive). iu ny c ngha l net ny c kh nng lu tr gi tr. Nu nhng driver ang li net ny c gi tr Hi-Z hay tng tr cao th net trireg vn gi gi tr trc . V cng ging nh nhng kiu net trc, y cng l loi net khng tng hp c. 7.tri1 l loi net cho php nhiu driver tuy nhin khc vi tri ch tri1 s gi mc logic 1 nu nhng driver ang li n trng thi Hi-Z hay tng tr cao.y cng l mt loi net na khng tng hp c. 8.tri0 Ging nh tri1 tuy nhin net s gi mc logic 0 nu cc driver li n u ang trng thi Hi-Z hay tng tr cao. 9.wand dng cho net c cu hnh ni dy kiu AND trong nu bt k driver no trong nhng driver ang li wand c mc logic 0 th wand s mc logic 0.wand c th tng hp c.

10.wor ging nh wand ngoi tr nu bt k driver no trong s nhng driver ang li wor c mc logic 1 th wor lp tc c mc 1.y l loi wor tng hp c. u : Khi vit m tng hp kiu d liu thng dng cho nhm kiu net l wire. Nhng kiu d liu wor,wand hay tri u c th tng hp c nhng ta nn trnh dng nhng kiu net ny trong khi vit m tng hp. Nhng loi net trior,trireg,triand,tri1, tri0 u khng th tng hp c.

Trong Verilog net hay reg c mt trong bn gi tr sau : 1 --- biu din mc logic 1. 0 --- biu din mc logic 0. X --- biu din trng thi bt k. ( Don't care) Z --- biu din trng thi tng tr cao (Hi - Z). i vi nhng net cho php nhiu driver li n th mi driver c th li mt trong 4 gi tr c ch ra trn, vy gi tr no s c li vo net ? Gi s net C c li bi hai driver A v B. C hai driver ny u c th li 1 trong bn gi tr 0,1,X v Z v do c th c n 16 t hp c th cc gi tr trn cc driver. Gi tr cui cng trn net C s ph thuc vo kiu m net C c khai bo. Ta s da vo nhng bng tm tt gi tr ra :

3.1.5 : Sc tn hiu ( Signal Strength) Phn 3.1.3 trnh by chi tit v nhng kiu khai bo khc nhau ca mt net cng nh vic dng reg trong Verilog. Mi kiu net hay reg c th c mt trong cc gi tr 0, 1, X, Z.Mc d gi tr ca net hay reg b gii hn bi 4 gi tr , ta vn c dng 8 mc sc tn hiu ( signal strength) khc nhau. Mc "mnh" (strength) ca mtwire hay reg thng c dng trong trng hp c tranh chp (contention) xy ra. Lu : Trong kh vit m tng hp th rt t khi "tnh mnh" (strength) c s dng do strength c dng gii quyt vn tranh chp trong mch logic. Tuy nhin, khi vit m tng hp th tt nht l trnh xy ra tranh chp trong mch thit k. Mt v d c "tranh chp" s c trnh by chi tit chng 5. V d 3.6 ch ra mt cch n gin gn mc strength vo ng ra ca thit k : module example ( inputA, inputB, inputC, outputA, outputB); input inputA, inputB, inputC; output outputA, outputB; and (strong1, weak0) and_gate_instance (outputA, inputA, inputB); or (weak1, weak0) or_gate_instance (outputB, inputB, inputC); endmodule Trong qu trnh tng hp, cng c tng hp s b qua nhng gn strength.V d ny s c tng hp thnh mt cng AND v mt cng OR.

3.2 Verilog gate - level primitive [primitive l nhng khi c xy dng sn trong Verilog nh cng NOT, AND, NOR ... ngi dng ch cn nm c php khai bo ca n l c th s dng c trong thit k ca mnh m khng cn phi khai bo trc] Verilog cho php nhng primitive mc cng (gate-level) c th hin trong m t thit k. Nhng primitive ny l nhng thnh phn c sn trong Verilog v khng cn i hi bt k mt thit lp c bit no. Mt s primitive c th tng hp c cn mt s th khng. Danh sch nhng primitive mc cng c th dng trong Verilog c trnh by di y : 1.pmos Primitive ny biu din mt transistor PMOS c hai ng vo v 1 ng ra.C php khai bo nh sau : pmos pmos_instance (output_signal, input_signal, gate_signal); trong pmos_instance l tn ca th hin biu din transistor pmos, output_signal l tn ca net c ni vo ng ra ca pmos transistor, input_signal l tn canet ni vi ng vo ca transistor pmos v gate_signal l tn ca net ni vo cc cng (Gate) ca transistor pmos.

2.nmos l t kha dng khai bo mt transistor nmos vi c php sau : nmos pmos_instance (output_signal, input_signal, gate_signal); vi nhng gii thch v tn hiu ni vo cc ng ca nmos ging nh vi pmos

3.cmos primitive ny dng biu din mt transistor cmos cng truyn (passgate) vi m hnh di y : cmos cmos_instance (output_signal, input_signal, NGate_signal, PGate_signal);

trong output_signal l tn ca net ni vo ng ra ca cmos cng truyn ny, input_signal l tn net ni vo ng vo ca cmos, NGate_signal l tn net ni vo phn iu khin bn N ca cmos v PGate_signal dnh cho iu khin bn P. 4.rpmos hot ng ging nh pmos nhng c tnh tr hn pmos do ng ra ca rpmos c sc tn hiu yu hn pmos. 5.rnmos hot ng ging nh pmos nhng c tnh tr hn nmos do ng ra ca rpmos c sc tn hiu yu hn nmos. 6.rcmos Cng ging nh cmos nhng v c tnh tr nn ng ra c sc tn hiu yu

hn cmos. 7.pullup nh tn ch ra pullup dng biu din mt nt "ko ln" vi c php: pullup pullup_instance (signal_name); trong signal_name l tn ca tn hiu b "ko ln". 8.pulldown tng t nh pullup.Bn c t suy ra cch s dng primitive ny. 9.tran Primitive ny biu din mt kha hai chiu cho php d liu chuyn ng theo c hai chiu gia hai net. M hnh ha nh sau : tran tran_instance (netA, netB); 10.rtran Ging nh tran ngoi tr do c tnh tr nn sc tn hiu ng ra yu hn tn hiu ra ca tran. 11.tranif0 hot ng ging nh tran c iu n ch cho php truyn d liu nu tn hiu Gate_control mc logic 0. M hnh nh sau : tranif0 tranif0_instance (netA, netB, Gate_control); 12.tranif1 hot ng ging nh tran c iu n ch cho php truyn d liu nu tn hiu Gate_control mc logic 1. M hnh nh sau : tranif1 tranif1_instance (netA, netB, Gate_control); 13.rtranif0 hot ng ging tranif0 ngoi tr do c tnh tr nn ng ra c sc tn hiu yu hn so vi tranif0. 14.rtranif1 hot ng ging tranif1 ngoi tr do c tnh tr nn ng ra c sc tn hiu yu hn so vi tranif1. 15.notif0 primitive ny biu din mt cng ba trng thi o. N c 2 ng vo v 1 ng ra c th m hnh nh sau : notif0 notif0_instance (output_signal, input_signal, control_signal);

16.notif1 primitive ny biu din mt cng ba trng thi o. N c 2 ng vo v 1 ng ra c th m hnh nh sau : notif1 notif1_instance (output_signal, input_signal, control_signal);

17.bufif0 primitive ny biu din mt cng ba trng thi. N c 2 ng vo v 1 ng ra c th m hnh nh sau : bufif0 bufif0_instance ( output_signal, input_signal, control_signal);

18.bufif1 primitive ny biu din mt cng ba trng thi. N c 2 ng vo v 1 ng ra c th m hnh nh sau : bufif1 bufif1_instance ( output_signal, input_signal, control_signal);

19.buf Primitive ny dng biu din mt b m. Vi c php buf buf_instance (output_signal, input_signal); 20. not Primitive ny dng biu din mt cng o. N c mt ng vo v 1 hay nhiu ng ra. not not_instance (output_signal1, output_signal2, ...., input_signal); 21. and Primitive ny dng biu din cng AND. N c hai hay nhiu ng vo v 1 ng ra.c m hnh nh sau : and and_instance (output_signal, input_signal1, input_signal2,...); 22.nand l primitive dng biu din mt cng nand vi 2 hay nhiu ng vo v

1 ng ra. nand nand_instance ( output_signal, input_signal1, input_signal2,...); 23.nor l primitive dng biu din mt cng NOR v cng c mt ng ra cng hai hay nhiu ng vo. nor nor_instance (output_signal, input_signal1, input_signal2 ...); 24.or, xor,xnor u l nhng primitive dng biu din cng logic vi 2 hay nhiu ng vo v 1 ng ra. 3.3 Primitive do ngi dng nh ngha Trong phn 3.2 ta trnh by v nhng primitive mc cng c xy dng sn trong Verilog. Ngoi nhng primitive ny, ngi thit k cng c th to ra nhng primitive ca ring mnh, nhng primitive ny c gi l primitive do ngi dng nh ngha. ( User-defined primitive) Ni chung, primitive do ngi dng nh ngha ( UDP) l mt module v c m t bi ngi dng. Module ny c dng trong Verilog bng cch th hin n. C hai kiu UDP m ngi thit k c th to ra, UDP t hp v UDP tun t. 3.3.1 : UDP t hp UDP t hp m t mt module c tnh cht t hp. iu ny c ngha l module UDP cha nhng phn t logic t hp to ra ng ra. V d 3.7 ch ra c php m t mt UDP t hp V d 3.7 : primitive <primitive_UDP_name> (<output_port_list>,<input_port_list>); output <output_port_list>; input <input_port_list>; table <Truth_table_format_description_of_combinational_U DP_functionality>; endtable endprimitive trong : <primitive_UPD_name> l tn ca primitive ang c nh ngha.

<output_port_list> l tn ca nhng cng ng ra ca UPD primitive.Lu l primitive ch c mt ng ra v ng ra ny ch c rng 1 bit. <input_port_list> l tn ca nhng ng vo. Lu l mi ng vo cng ch c rng 1 bit. <Truth_table_format_description_of_combinational_f unctionality> l bng s tht m t chc nng ca primitive c nh ngha. Mt v d v bng s tht c minh ha bng bng 3.7

M Verilog miu t primitive c nh ngha bng bng 3.7 primitive udp_gate (outputA, inputA, inputB, inputC); output outputA; input inputA, inputB, inputC; table // inputA inputB inputC outputA 0 0 0 : 0; 0 0 1 : 0; 0 1 0 : 1; 0 1 1 : 1; 1 0 0 : 0; 1 0 1 : 0; 1 1 0 : 1; 1 1 1 : 1;

endtable endprimitive // to create a module that instantiates the UDP primitive module example (input1, input2, input3, output1); input input1, input2, input3; output output1; wire output1; upd_gate udp_gate_instance (output1, input1, input2, input3); endmodule .3.2 : UDP tun t UDP tun t m t mt module c bn cht tun t. iu ny c ngha l module UDP cha mt phn t nh ( storage element) m c th lu mt gi tr. C php nh ngha UDP tun t ging nh UDP t hp ngoi tr trong c khai bo reg. Bng 3.18 trnh by bng s tht ca mt con cht (latch) m UDP nh ngha.

primitive udp_latch (Q, data, clock); output Q; input data, clock; reg Q; // Declare Q with a reg type to store values

initial Q = 0; table // data clock Q(current) Q(next) 0 0 : ? : -; 0 1 : ? : 0; 1 0 : ? : -; 1 1 : ? : 1; endtable endprimitive // create a module that instantiate the sequential udp above module example (qout, indata, inclock); input indata, inclock; wire qout; udp_latch (qout, indata, inclock); endmodule [V d minh ha trong bng trn trnh by m t ca mt con cht tch cc theo mc logic 1 ca xung clock, tc l khi xung clock gi gi tr logic 1 th ng ra Q s c cp nht gi tr mi ng vo, cn nu khng th ng ra Q vn gi gi tr c] Bng 3.19 v v d di y s trnh by mt phn t logic kch bng cnh ging nh mt Flip Flop

primitive udp_pos_flop ( Q, data, clock); output Q; input data, clock; reg Q; initial Q = 0; table // data clock Q(current) Q(next) 0 (01) : ? : 0; 1 (01) : ? : 1; // no change in output values 0 (0x) : ? : -; 0 (0x) : ? : -; // no change for negative edge 0 (10) : ? : -; 0 (10) : ? : -; // no change for change in data (??) ? : ? : -; endtable endprimitive // to create a module that instantiates the sequential UDP primitive

module example ( qout, indata, inclock); input indata, inclock; output qout; wire qout; udp_pos_flop (qout, indata, inclock); endmodule [Lu : rt t khi ta dng UDP trong vit m t Verilog. Nu cn dng mt dng i tng no kiu primitive ta s khai bo n di dng mt module hon chnh v th hin module ny trong module m ta cn dng.] Chng 4 : Phong cch Coding --- Phng php tng hp Phong cch coding ng vai tr quan trng trong lung thit k ASIC. Nhng m HDL "ti" thng khng mang li s thun li trong vic ti u ha. Gi tr logic c to ra t nhng cng c tng hp ph thuc rt ln vo cch m m c vit. Nhng m vit "ti" cng s dn n nhng mch logic khng ti u nh ngi ta vn ni : " Rc vo th rc ra" ( Garbage in, Garbage out) C nhng nguyn tc chung cn tun th khi i vo phong cch lp trnh. Bng cch tun theo nhng nguyn tc ny, s c mt phong cch vit m tt v xuyn sut thng nht.iu ny dn n kt qu tng hp s ti u. 4.1 : Cch t tn ( Naming Convention) i vi mt d n thit k, mt thng l t tn tt l mt iu cn thit. Cch t tn thng thng l phn khng c xem trng khi vit m HDL. C c mt cch t tn tt dng nh khng quan trng nhng nu khng c mt cch t tn no c th gy ra nhiu vn cho nhng bc thit k sau c bit l trong qu trnh tch hp chip. Vic kt ni tt c cc tn hiu gia cc module ca ton b chip s rt kh khn nu tn ca tn hiu khng thng nht. Bng cch nh ngha mt chnh sch t tn, mt tp hp nhng quy nh c p dng khi ngi thit k t tn cc cng ca mt module. Nu mi module trong cng mt chip tun th tp hp quy nh th s d kt ni cc tn hiu trong chip hn.

Hnh trn l gin ch ra mt chip cha hai module, module A v module B. i vi chip ny, gi s ta tun th nhng nguyn tc t tn sau : 1. Ba k t u tin ca chip phi l ch vit hoa. 2. K t u tin phi biu din tn ca module m tn hiu l ng ra t . 3. K t th 3 phi biu din tn ca module m t tn hiu l ng vo ti n. 4. K t th 2 phi l con s 2. 5. K t th 4 tr i l tn ca tn hiu v phi vit thng. 6. Tn hiu truyn ti ng ra mc chip phi c 4 k t u l "OUT_".Tn tn hiu sau 4 k t ny phi l ch thng. 7. Tn hiu truyn t ng vo mc chip ti mt module no trong chip phi c 3 ch ci u l "IN_" v tn tn hiu sau 3 k t ny phi l ch vit thng. 8. Bt k tn hiu no tch cc thp phi kt thc vi ch "I". Da vo nhng quy nh t tn ny, tn ca tn hiu "IN_enable","IN_data" v "OUT_data" l tn hiu ng vo v ng ra mc chip. Tn ca tn hiu c lin kt ni gia module A v module B l "A2Ben","A2Bdata" v B2AshkI". Nhng quy tc t tn dng y ch l mt v d. Mt d n thit k thc s c th dng nhng nguyn tc ging nh trn v cng c th khc. V d 4.1 trnh by m Verilog cho module A v module B v chip cng nhng lin kt ni gia chng. module module_A (IN_enable, IN_data, B2AshkI, A2Ben, A2Bdata); input IN_enable, IN_data, B2AshkI; output A2Ben, A2Bdata; // your Verilog code for module_A endmodule module module_B (A2Ben, A2Bdata, B2AshkI, OUT_data);

input A2Ben, A2Bdata; output B2AshkI, OUT_data; // your Verilog code for module_A endmodule module fullchip ( IN_enable, IN_data, OUT_data); input IN_enable, IN_data; output OUT_data; wire A2Ben, A2Bdata, A2BshkI; module_A module_A_instance ( IN_enable, IN_data, B2AshkI, A2Ben, A2Bdata); module_B module_B_instance (A2Ben, A2Bdata, B2AshkI, OUT_data); endmodule 4.2 : Phn vng thit k ( Design Partition) Trong thc tin thit k ngi thit k thng phn chia thit k ca mnh ra thnh nhiu module nh hn. Mi module c phn chia theo chc nng v c tnh ring ca n. C mt phn chia thit k hp l, ngi thit k c th "r" thi k thnh nhng module nh hn do d qun l hn. Theo cch ny ngi thit k c th xc nh chc nng ca mi module v vit m t HDL cho tng module ring bit. Tuy nhin, ngi thit k cn cn thn khi phn vng thit k. Mi module khng th qu nh cng khng th qu ln. Phn vng module qu nh s lm cho vic tng hp khng ti u, module qu ln th kh vit m v cng khng mang li thun li trong qu trnh tng hp mch. Kch thc module hp l s d qun l v cho phpo tng hp tt hn, mt tiu chun trong phn chia l khong 5000 n 15000 cng cho mt module ring l. Mt im na cn quan tm khi tin hnh phn vng thit k l to ra nhng khi kt ni. Phn vng thnh nhiu khi c th xy ra tnh hung trong ny sinh nhu cu to ra nhiu ng kt ni hn gia cc khi. Nhng tn hiu b sung thm ny c th gy ra s tc nghn trong giai on layout v c qu nhiu ng an xen nhau. Do vy, i hi ngi thit k phi c hiu bit su sc v y v kin trc v vi kin trc ca thit k trc khi c phn vng n. Phn vng tt s mang n u im v qun l trong khi phn vng khng tt s to ra s tc nghn

(congestion) trong giai on layout v lm cho vic qun l thit k tr nn kh khn hn rt nhiu. .3 : Clock a s thit k ASIC c t nht mt xung clock, mt s khc c nhiu hn. Nu thit k l n clock ( single clock) hay a clock ( multi -clock), ngi thit k cn xem nhng khi clock ny nh clock ton cc ( global clock). Ton cc ngha l mi clock c nh tuyn qua tt c cc module trong thit k vi tn hiu clock xut pht t mt module clock. Module clock to ra clock ton cc khng tng hp c v c thit k dng s mch. Nhng khi clock tun t s c tch hp vi nhng khi logic khc mc chip. Lu : nhng khi tng t ( analogue block) khng th tng hp c. Trong lung thit k ASIC nhng khi tng t c thit k c lp v c tch hp vi khi logic mc tch hp chip. Ngi c nn ghi ch li nhng khi ny trong qu trnh vit m. Ta dng hnh v di y minh ha :

Da vo hnh trn module A ti module F tng hp c mi module s c m ha trong HDL c kim tra dng HDL testbench v tng hp. Trong qu trnh tch hp mc chip nhng module clock s c kt ni vi nhng module logic khc. Khi ngi thit k m ha module A ti module F, anh ta/ ch ta gi s u vo clock l u vo clock ton cc c th tha mn tt c nhng i hi v sai lch clock ( clock skew). Ng vo clock ton cc c gi s c chu k c xc nh trong c t thit k. Vi nhng gi s ny, ngi thit k khng th m tn hiu xung clock t bn trong. Ni cch khc tn hiu xung clock c mc nh l bt bin. Xem tn hiu xung clock l bt bin l mt quan im thc tin. Bng cch khng m clock, ngi thit k gi s tn hiu clock c th tha mn tt c nhng i hi v c t m thng thng khng c c trong thc t. Sai lch clock ( clock skew) ph thuc vo vic sp t cc cell v vic nh tuyn tn hiu clock. Do , trong qu trnh m ha v tng hp, ta s xem clock l bt bin v trnh m clock loi b hiu ng sai lch clock. Cng vic ny s c thc hin trong qu trnh tng hp "cy clock" l mt phn cng vic trong bc APR ca lung thit k ASIC trnh by trc trong chng 2. Thm vo , ty bin chu k xung clock c c tn hiu clock mong mun ch nh hng n module tng t trong hnh v trn. Hnh v 4.3 l mt thit k l tng trong tn hiu clock c kt ni trc tip vi Flip Flop dng trong thit k m khng c bt k mt b m hay cng logic no trn ng clock. Ngi thit k nn c gng t n m hnh l tng ny trong thit k mi khi c th.

u im chnh ca vic to ra nhng m hnh thit k l tng nh trn l vic to iu kin cho cng c APR tng hp "cy clock" ( clock tree) v a vo nhng b m clock mi khi cn thit. Lm c nh vy th nhng thay i trong sai lch clock ( clock skew) c th c loi b trong giai on vit m HDL. 4.3.1 : Tn hiu clock c to ra bn trong Mt tn hiu clock c to ra bn trong ( internally generated clock) nn dng cng t cng tt. L tng th thit k tng hp khng c bt k mt clock no thuc loi ny. Nhng thit k c Flip Flop hay cht ( latch) c clock bng loi clock ny s lm phc tp qu trnh phn tch nh th bi rt kh rng buc tn hiu clock c to ra bn trong trong qu trnh tng hp. Hnh 4.4 trnh by ng ra ca mt Flip Flop ang c dng lm tn hiu clock cho mt flip flop khc.

Nhng thit k nh th ny s lm phc tp qu trnh rng buc nh th. a s nhng cng c phn tch v tng hp gp kh khn vi kiu clock c to t bn trong ny. M Verilog cho thit k hnh 4.4 module internal_clock ( input1, input2, clock, output1); input input1, input2, clock; output output1; reg internal, output1; always @ ( posedge clock) begin internal <= input2; end always @ ( posedge internal) begin output1 <= input1; end endmodule

4.3.2 : Gated Clock Mt thit k c mt tn hiu cho php nhm "cho php" mt xung clock bn trong da vo clock ton cc c gi l "gated clock". Cm t ny ch ra rng tn hiu clock ton cc b gn vi mt tn hiu no to ra tn hiu clock bn trong. Thit k c gated clock thng c dng khi ngi thit k mun tt tn hiu clock di mt iu kin no do mc ch tit kim nng lng. Hnh 4.5 ch ra mt v d c flip flop c clock bi mt tn hiu gated clock c to ra t iu kin AND ca tn hiu "enable" v clock.

Da vo v d ca hnh 4.5 ta thy c rt nhiu cch c th dng to ra gated clock trong thit k. Phng php thng dng nht l dng php gn boolean v th hin cng. V d 4.3 trnh by m Verilog dng php gn Boolean cn v d 4.4 dng phng php th hin cng. V d 4.3 : Dng php gn Boolean module gated_clock ( input1, enable, clock, output1); input input1, enable, clock; output output1; wire gated; reg output1; assign gated = clock & enable; always @ ( posedge gated) begin output1 <= input1; end endmodule

V d 4.4 : Dng phng php th hin cng module gated_clock ( input1, enable, clock, output1); input input1, enable, clock; output output1; wire gated; reg output1; AND_gate AND_instance (.I1(clock), .I2(enable), .O(gated)); always @ ( posedge gated) begin output1 <= input1; end endmodule [Tt nhin bn phi c mt module khai bo AND_gate trc v tin cho cc bn theo di ti trnh by lun y.] module AND_gate (I1, I2, O); input I1, I2; output O; assign O = I1&I2; endmodule Trong hai phng php th cch th hin cng c u thch hn khi lm vic vi gated clock bi khi th hin cng cho php ngi thit k qun l c kh nngfanout ca tn hiu b gated. V d : ta gi s rng tn hiu gated dng li 32 flip flops nh trong hnh 4.6 :

Da vo hnh 4.6 ta thy l mc fanout ln n 32 ca tn hiu gated c th l gy qu ti cho cng logic AND dn n hin tng skew ( sai lch) trn tn hiu gated rt ln. Tt nhin ngi thit k c th m tn hiu gated trong qu trnh tng hp tuy nhin m tn hiu gated thng khng c khuyn khch do y l tn hiu clock. Do vy bt k vic m tn hiu gated no cng s c lm trong giai on APR. Do , mt phng php tt hn s l cch th hin cng. Phng php ny cho php ngi thit k iu khin kh nng ti trn cng AND li tn hiu gated. S dng cng mt v d trong hnh 4.6 ngi thit k c th phn tn hiu gated thnh nhiu tn hiu v mi tn hiu s ch li mt s flip flop gii hn.

Da vo hnh 4.7 tn hiu clock v tn hiu enable c dng to ra 8 tn hiu gated phn bit t gated1 n gated8. Mi tn hiu gated ch li 4 flip flop. lm c iu ny ngi thit k th hin 8 cng AND ring bit to ra 8 tn hiu gated khc nhau. Cc ny cho php gim ti trn mi tn hiu gated v cho php ngi thit k kim sot c hin tng skew trn tn hiu gated. V d 4.5 trnh by m Verilog phng php th hin cng cho php kim sot skew trn tn hiu gated. V d 4.5 : M Verilog th hin cng trong thit k gated clock module gated_clock ( input1, enable, clock, output1); input [31:0] input1; input enable, clock; output [31:0] output1; wire gated1, gated5, gated2, gated3, gated4, gated6, gated7, gated8; reg output1; AND_gated AND_instance1 ( .I1(clock), .I2 (enable), .O(gated4)); AND_gated AND_instance9 ( .I1(clock), .I2 (enable), .O(gated3)); AND_gated AND_instance10 ( .I1(clock), .I2 (enable), .O(gated3));

AND_gated AND_instance11 ( .I1(clock), .I2 (enable), .O(gated3)); AND_gated AND_instance12 ( .I1(clock), .I2 (enable), .O(gated4)); AND_gated AND_instance13 ( .I1(clock), .I2 (enable), .O(gated4)); AND_gated AND_instance14 ( .I1(clock), .I2 (enable), .O(gated4)); AND_gated AND_instance15 ( .I1(clock), .I2 (enable), .O(gated4)); AND_gated AND_instance16 ( .I1(clock), .I2 (enable), .O(gated5)); AND_gated AND_instance17 ( .I1(clock), .I2 (enable), .O(gated5)); AND_gated AND_instance18 ( .I1(clock), .I2 (enable), .O(gated5)); AND_gated AND_instance19 ( .I1(clock), .I2 (enable), .O(gated5)); AND_gated AND_instance20 ( .I1(clock), .I2 (enable), .O(gated6)); AND_gated AND_instance21 ( .I1(clock), .I2 (enable), .O(gated6)); AND_gated AND_instance22 ( .I1(clock), .I2 (enable), .O(gated6)); AND_gated AND_instance23 ( .I1(clock), .I2 (enable), .O(gated6)); AND_gated AND_instance24 ( .I1(clock), .I2 (enable), .O(gated7)); AND_gated AND_instance25 ( .I1(clock), .I2 (enable), .O(gated7)); AND_gated AND_instance26 ( .I1(clock), .I2 (enable), .O(gated7)); AND_gated AND_instance27 ( .I1(clock), .I2 (enable), .O(gated7)); AND_gated AND_instance28 ( .I1(clock), .I2 (enable), .O(gated8)); AND_gated AND_instance29 ( .I1(clock), .I2 (enable), .O(gated8)); AND_gated AND_instance30 ( .I1(clock), .I2 (enable), .O(gated8)); AND_gated AND_instance31 ( .I1(clock), .I2 (enable), .O(gated8)); AND_gated AND_instance32 ( .I1(clock), .I2 (enable), .O(gated1)); AND_gated AND_instance2 ( .I1(clock), .I2 (enable), .O(gated1)); AND_gated AND_instance3 ( .I1(clock), .I2 (enable), .O(gated1)); AND_gated AND_instance4 ( .I1(clock), .I2 (enable), .O(gated1)); AND_gated AND_instance5 ( .I1(clock), .I2 (enable), .O(gated2)); AND_gated AND_instance6 ( .I1(clock), .I2 (enable), .O(gated2)); AND_gated AND_instance6 ( .I1(clock), .I2 (enable), .O(gated2)); AND_gated AND_instance7 ( .I1(clock), .I2 (enable), .O(gated2)); always @ ( gated1) begin output1[3:0] <= input1 [3:0]; end always @ ( gated2) begin output1[7:4] <= input1 [7:4];

end always @ ( gated3) begin output1[11:8] <= input1 [11:8]; end always @ ( gated4) begin output1[15:12] <= input1 [15:12]; end always @ ( gated5) begin output1[19:16] <= input1 [19:16]; end always @ ( gated6) begin output1[23:20] <= input1 [23:20]; end always @ ( gated7) begin output1[27:24] <= input1 [27:24]; end always @ ( gated8)

begin output1[31:28] <= input1 [31:28]; end 4.4: Reset Mi thit k c mt s tn hiu reset l mt i hi thng thy v thit k lun cn phi "reset" v mt trng thi bit trong nhng iu kin c th no . C hai kiu reset : reset ng b v reset bt ng b. C hai u reset thit k nhng nh hng ca chng rt khc nhau. 4.4.1 : Reset bt ng b ( asynchronous reset) Reset bt ng b xy ra bt k lc no m khng c bt k tham kho no v nh th ca tn hiu ny vi nhng tn hiu khc v x ra c lp vi bt k iu kin hay tn hiu no khc trong mch. Hnh 4.8 ch ra mt v d n gin vi reset ginh cho flip flop. Ng ra ca Flip Flop mc logic 0 mi khi c tn hiu reset mc 1 [ Ngi ta gi tn hiu reset kiu ny l reset tch cc cao]. V d 4.6 l m Verilog cho kiu reset bt ng b ny.

V d 4.6 : M Verilog cho reset bt ng b

module asynchronous_reset ( input1, reset, clock, output1); input input1, reset, clock; output output1; reg output1; always @ ( posedge clock or posedge reset) begin if (reset) output1 <= 1'b0; else output1 <= input1; end endmodule 4.4.2 : Reset ng b Reset ng b l reset xy ra cnh ln ( rising edge) hay cnh xung (falling edge) ca tn hiu xung clock. iu ny c ngha l reset ng b ch c xy ra cnh ca clock hay ni cch khc reset ny "tham kho nh th" ca tn hiu clock v khng th xy ra c lp vi tn hiu clock. Hnh 4.9 ch ra mt v d n gin ca thit k c reset ng b. Gi tr ng ra ca flip flop c cp nht cnh ln ca xung clock. Ng ra ca flip flop s mc logic 0 nu trong cnh ln ca clock tn hiu reset c mc logic 1 nu khng th gi tr ng ra ca flip flop s l gi tr logic ca ng vo cnh ln ca xung clock.

module synchronous_reset ( input1, reset, clock, output1); input input1, reset, clock; output reg output1; always @ ( posedge clock) if ( reset) output1 <= 1'b0; else output1 <= input1; endmodule 4.5 : Vng lp nh th ( Timing Loop) Vng lp nh th l nhng vng lp trong thit k c ng ra ca mch logic t hp c hi tip ngc li thnh mt phn ca ng vo t hp. i vi nhng thit k tng hp th khng c c nhng vng lp nh th ny. Nu c nhng vng lp nh th kiu ny s lm phc tp qu trnh phn tch nh th do ng ra c a ngc tr li ng vo. Hnh 4.10 trnh by mt v d c vng lp nh th lu vic ng ra ca mch o c a ngc v nh ng vo ca cng AND.

Khi thit k mt mch c vng lp nh th ngi ta khuyn nn chia n ra bi mt phn t tun t. iu ny bo m vng lp nh th m c th gy ra glitch c th c chia thnh hai phn : phn trc tun t v sau tun t. module timing_loop ( inputA, inputB, outputA); input inputA, inputB; output outputA; wire tempA, tempB; assign tempA = inputA & outputA; assign tempB = ~(tempA | inputB); assign outputA = ~tempB; endmodule 4.6 : Cu lnh blocking v non blocking Blocking v Non blocking l nhng cu lnh gn th tc c dng trong m Verilog. C hai php gn ny c dng trong nhng cu lnh gn tun t. Mi cu lnh gn blocking hay non blocking c nhng c tnh v hnh vi khc nhau. Cu lnh gn blocking c biu din bng k hiu "=". Khi mt cu lnh blocking c dng cu lnh s c thc thi trc khi b m phng ( simulator) i ti cu lnh tip theo ni cch khc, cu lnh blocking thc s l tun t. Cu lnh non blocking c biu din bng k hiu "<=". Khi mt cu lnh gn non blocking c dng cu lnh ny c ln k hoch ( scheduled) v thc thi cng vi nhng cu lnh non blocking khc. iu ny c ngha l non blocking cho php nhiu php gn c ln k hoch v thc thi cng vi nhau kt qu l cu lnh gn non blocking khng ph thuc vo th t php gn c vit

trong m t Verilog. Nhng v d t 4.8 n 4.15 s gii thch s khc bit gia cu lnh gn blocking v non blocking. Lu : cu lnh gn blocking v non blocking ch c trong m Verilog trong khi VHDL khng cn khi nim ny. [ Thc ra khi tng hp th d vit m non blocking hay blocking th mch cng s nh nhau, chia thnh hai loi nh th ny nhm to iu kin cho vic m phng] V d 4.8 trnh by m Verilog ca mt thit k n gin dng cu lnh gn non blocking. Module ny v c bn l mt thit k thanh ghi c reset ng b. module non_blocking ( clock, input1, reset, output1, output2, output3); input reset, clock; input [3:0] input1; output [3:0] output1, output2, output3; always @ ( posedge clock) begin if (reset) begin output1 <= 4'b0000; output2 <= 4'b0000; output3 <= 4'b0000; end else begin output1 <= input1; output2 <= output1; output3 <= output2; end end endmodule V d 4.9 : Thay i th t gn ca nhng php gn non blocking module non_blocking ( clock, input1, reset, output1, output2, output3);

input reset, clock; input [3:0] input1; output [3:0] output1, output2, output3; always @ ( posedge clock) begin if (reset) begin output1 <= 4'b0000; output2 <= 4'b0000; output3 <= 4'b0000; end else begin output1 <= input1; output3 <= output2; // Rearrange this line output2 <= output1; end end endmodule V d 4.10 : module non_blocking ( clock, input1, reset, output1, output2, output3); input reset, clock; input [3:0] input1; output [3:0] output1, output2, output3; always @ ( posedge clock) begin if (reset) begin output1 <= 4'b0000;

output2 <= 4'b0000; output3 <= 4'b0000; end else begin output2 <= output1; output3 <= output2; // Rearrange this block output1 <= input1; end end endmodule Ta s thy l m Verilog trong c hai v d trn cho cng mt kt qu m phng ngoi tr vic th t sp xp ca chng c khc nhau. Ta s dng mt testbench n gin kim tra nhng thit k ny. V d 4.11 : Testbench cho nhng v d trn module nonblocking_tb (); reg [3:0] input1; reg clock, reset; wire [3:0] output1, output2, output3; // Generating initial stimulus for inputs and global clock initial begin clock = 0; input1 = 0; forever #50 clock = ~clock; // for clock end // Test vectors

initial begin #10; reset = 0; #10; reset = 1; #10; input1 = 1; #50; input1 = 2; #200; $finish; end // This is where the design under test is instantiated non_blocking nonblocking_instance ( clock, input1, reset, output1, output2, output3); endmodule Kt qu m phng di hnh thc gin sng ( waveform diagram)

[Ta nhn thy rng mc d th t ca nhng cu lnh trong php gn non blocking thay i nhng kt qu m phng vi cng mt testbench c kt qu ging nhau. iu ny cho chng ta thy l php gn non blocking khng ph thuc vo th t sp xp ca cc cu lnh] Nhng v d tip theo t 4.12 n 4.13 l cng mt dng m Verilog nh nhng v d trc nhng cu lnh blocking c dng thay v nonblocking V d 4.12 module non_blocking ( clock, input1, reset, output1, output2, output3); input reset, clock; input [3:0] input1; output [3:0] output1, output2, output3; always @ ( posedge clock) begin if (reset) begin

output1 = 4'b0000; output2 = 4'b0000; output3 = 4'b0000; end else begin output1 = input1; output2 = output1; output3 = output2; end end endmodule V d 4.13 : Thay i th t module non_blocking ( clock, input1, reset, output1, output2, output3); input reset, clock; input [3:0] input1; output [3:0] output1, output2, output3; always @ ( posedge clock) begin if (reset) begin output1 = 4'b0000; output2 = 4'b0000; output3 = 4'b0000; end else begin output1 = input1;

output3 = output2; // This line is rearranged output2 = output1; end end endmodule V d 4.14 module non_blocking ( clock, input1, reset, output1, output2, output3); input reset, clock; input [3:0] input1; output [3:0] output1, output2, output3; always @ ( posedge clock) begin if (reset) begin output1 = 4'b0000; output2 = 4'b0000; output3 = 4'b0000; end else begin output2 = output1; output3 = output2; output1 = input1; end end endmodule Ta s dng cng mt testbench nh trong v d trc v quan st cc kt qu

module nonblocking_tb (); reg [3:0] input1; reg clock, reset; wire [3:0] output1, output2, output3; // Generating initial stimulus for inputs and global clock initial begin clock = 0; input1 = 0; forever #50 clock = ~clock; // for clock end // Test vectors initial begin #10; reset = 0; #10; reset = 1; #10; input1 = 1; #50; input1 = 2; #200; $finish; end // This is where the design under test is instantiated non_blocking nonblocking_instance ( clock, input1, reset, output1, output2, output3); endmodule Kt qu m phng s rt khc so vi nhng trng hp dng cu lnh

nonblocking

Nh vy ta c th nhn ra mt iu l : khi m phng thanh ghi th trong khi always ta s dng nhng cu lnh gn non blocking trong khi ta s dng cu lnh blocking cho trng hp m t mch t hp. 4.7 : Danh sch nhy ( Sentivity list) Verilog dng danh sch nhy ( sentivity list) quyt nh xem mt khi lnh tun t no s c thc hin trong mt chu k m phng. i vi Verilog danh sch nhy i hi mt cu lnh always. V d : 4.16 trnh by m Verilog cho mt module thit k c mt khi always. Khi ny s c tnh ton bi b m phng mi khi c mt s thay i no ca nhng tn hiu tng ng trong danh sch nhy. module senselist ( X, Y, Z, AB); input X, Y, Z; output AB;

always @ ( X, Y, Z) begin // design source code end endmodule Da vo v d trn, ta thy danh sch nhy c 3 tn hiu l X, Y, Z. Khi lnh tun t trong always s c tnh ton bi b m phng khi c mt s thay i ca mt tn hiu no trong danh sch nhy. Mt danh sch tn hiu khng y trong danh sch nhy cho mt khi always no s gy ra sai trong qu trnh m phng, n cng c th to ra s khng thng nht kt qu tng hp v m phng. Do iu quan trng l lun phi a tt c nhng tn hiu c lin quan vo trong danh sch nhy ca khi always. Sau y ta s ch ra hai v d ca vic dng danh sch nhy. Trng hp u l danh sch nhy y cn li l trng hp khng y . Trng hp y : module sense ( inputA, inputB, inputC, outputA); input inputA, inputB, inputC; output outputC; reg outputA; always @ ( inputA, inputB, inputC) begin if(inputA & inputB & inputC) outputA = 0; else outputA = 1; end endmodule Trng hp khng y : module sense ( inputA, inputB, inputC, outputA); input inputA, inputB, inputC;

output outputC; reg outputA; always @ ( inputA or inputB) begin if(inputA & inputB & inputC) outputA = 0; else outputA = 1; end endmodule Testbench dng m phng c hai trng trn : module sense_tb(); reg inputA, inputB, inputC; wire outputA; integer i; initial begin for ( i = 0; i < 8; i = i +1) begin {inputA, inputB, inputC} = i; // Concatenation bus #100; end end // This is where you instantiated design under test sense sense_instance ( .inputA(inputA), .inputB(inputB), .inputC(inputC), .outputA(outputA)); // Using explicit port map initial begin $monitor ( " inputA %b, inputB %b, inputC %b, outputA %b", inputA, inputB, inputC,outputA); end endmodule

Kt qu m phng v tng hp ca hai thit k ny khc nhau

4.8 Ton t Verilog Verilog cho php s dng mt s ln nhng ton t, l thnh phn c bn nht khi vit m Verilog. Ton t cho php ngi thit k t c nhng chc nng khc nhau trong m t HDL. Tt c nhng ton t ca Verilog u c th tng hp c v c phn vo nhng nhm khc nhau vi mi nhm c nhng chc nng nht nh. 4.8.1 : Ton t iu kin ( Conditional Operators) Ton t iu kin thng c dng m t nhng mch t hp v hot ng ging nh nhng chuyn mch. Mt ton t iu kin bao gm ba ton hng (operand) Biu thc u vo. Tn hiu iu khin chn la s quyt nh tn hiu ng vo no c truyn ti ng ra. Biu thc ng ra

C php ca ton t iu kin nh sau : assign output_signal = control_signal ? input1 : input2; trong output_signal l ng ra ca cu lnh iu kin; control_signal l tn hiu chn ng vo input1 hy input2 c truyn ti ng ra. Di y l module dng minh ho vic s dng ton t iu kin trong vit m Verilog.

module conditional ( inputA, inputB, controlC, outputA); input inputA, inputB, inputC; output outputA; wire outputA; assign outputA = controlC ? inputA : inputB; endmodule Khi v d trn c tng hp s cho ra mch nh hnh 4.7 : thc s l mt mch dn knh ( Multiplexer). Do khi ta cn thit k mt mch dn knh th nn s dng ton t iu kin.

4.8.2 : Ton t ghp bus Nhiu tn hiu c th c ghp to thnh bus, iu ny c thc hin trong Verilog bng ton t ghp ( concatenation operator). C php s dng ton t ny nh sau : assign signal_bus = {signal1, signal2, signal3}; trong signal_bus l tn ca bus c ghp c ba bit cn signal1, signal2, signal3 l nhng tn hiu c ghp vi nhau. V d 4.18 : Ghp bus 3 v 4 bit module concatenation ( inputA, inputB, inputC, inputD, outputA, outputB); input inputA, inputB, inputC, inputD; output [2:0] outputA; output [3:0] outputB; wire [2:0] outputA; wire [2:0] outputB; assign outputA = {inputA, inputB, inputC}; assign outputB = {inputA, inputB, inputC, inputD}; endmodule

4.8.3 : Ton t dch Ton t dch c th c thc hin trong Verilog dng hai loi ton t l dch tri ( shift left) v dch phi ( shift right). V d 4.19 s trnh by m Verilog dng ton t dch tri dch tri ba bit tn hiu bus tempA bi mt bit sang tri. V d 4.19 : Minh ha ton t dch tri module shift_left ( inputA, inputB, outputA); input [2:0] inputA, inputB; output [2:0] outputA; wire [2:0] outputA; wire [2:0] tempA; assign tempA = inputA & inputB; assign outputA = tempA << 1; // This is the shift left operator endmodule Sau khi tng hp ta s c mch nh hnh v 4.18

Tip theo ta s vit testbench nhm m phng ton t dch tri trn

module shift_left_tb(); reg [2:0] inputA_reg, inputB_reg; wire [2:0] outputA_wire; integer i,j; initial begin for ( i = 0; i < 8; i = i + 1) begin // To force stimulus to inputA input_regA = i; // To force stimulus to inputB for ( j = 0; j < 8; j = j +1 ) begin inputB_reg = j; #10; end end end // This is where you instantiated design under test shift_left DUT ( .inputA ( inputA_reg), .inputB( inputB_reg), .outputA(outputA_wire)); initial begin $monitor ( " inputA %b%b%b, inputB %b%b%b, tempA %b%b%b, outputA %b%b%b", inputA_reg[2], inputA_reg[1], inputA_reg[0],inputB_reg[2],inputB_reg[1],inputB_reg[0],DUT.tempA[2],DUT.te mpA[1],DUT.tempA[0],outputA_wire[2],outputA_wire[1],outputA_wire[0]); end endmodule Kt qu m phng nh sau :

Tip theo s l module minh ha vic s dng ton t dch phi ( shift right) module shift_right ( inputA, inputB, outputA); input [2:0] inputA, inputB; output [2:0] outputA; wire [2:0] outputA; wire [2:0] tempA; assign tempA = inputA & inputB; assign outputA = tempA >> 1; // This is the shift left operator endmodule Kt qu tng hp ra mch logic

Testbench dng m phng ton t trn module shift_right_tb(); reg [2:0] inputA_reg, inputB_reg; wire [2:0] outputA_wire; integer i,j; initial begin for ( i = 0; i < 8; i = i + 1) begin // To force stimulus to inputA input_regA = i; // To force stimulus to inputB for ( j = 0; j < 8; j = j +1 ) begin inputB_reg = j; #10; end end end // This is where you instantiated design under test

shift_right DUT ( .inputA ( inputA_reg), .inputB( inputB_reg), .outputA(outputA_wire)); initial begin $monitor ( " inputA %b%b%b, inputB %b%b%b, tempA %b%b%b, outputA %b%b%b", inputA_reg[2], inputA_reg[1], inputA_reg[0],inputB_reg[2],inputB_reg[1],inputB_reg[0],DUT.tempA[2],DUT.te mpA[1],DUT.tempA[0],outputA_wire[2],outputA_wire[1],outputA_wire[0]); end endmodule Kt qu m phng

4.8.4 : Ton t ton hc Verilog cho php 5 ton t ton hc khc nhau, bao gm : Ton t cng ( Addition Operator) Ton t tr ( Subtraction Operator) Ton t nhn ( Multiplication Operator) Ton t chia ( Division Operator) Ton t ly d ( Modulus Operator) Khi dng nhng ton t ny ngi thit k cn cn thn v mch logic c to ra trong qu trnh tng hp c th khc nu nhng rng buc v thit k c dng. 4.8.4.1 : Ton t cng Nh tn ch ra, ton t ny cho php thc hin php ton cng v c m trong Verilog dng k hiu "+". module addition ( inputA, inputB, outputA); input inputA, inputB; output [1:0] outputA; wire outputA; assign outputA = inputA + inputB; endmodule Hnh v 4.20 ch ra s c tng hp ca module trn:

V d 4.26 l m Testbench dng m phng hot ng ca mch cng va thit k trn : module addition_tb(); reg inputA_reg, inputB_reg; wire [1:0] outputA_wire; integer i,j; initial begin for ( i = 0; i < 2; i = i +1) begin inputA_reg = i; for ( j =0; j <2; j = j+1) begin inputB_reg = i; #10; // delay for 10 time units end end end // This is where you instantiated your design under test

addition DUT (.inputA ( inputA_reg), .inputB(inputB_reg), .outputA(outputA_wire)); initial begin $monitor ( "inputA %b inputB %b outputA %b%b", inputA_reg, inputB_reg, outputA_wire[1],outputA_wire[0]); end endmodule Kt qu m phng

4.8.4.2 : Ton t tr Nh tn ch ra, ton t ny cho php thc hin php ton tr v c m trong Verilog dng k hiu "-". module subtraction ( inputA, inputB, outputA); input inputA, inputB; output [1:0] outputA; wire outputA; assign outputA = inputA - inputB; endmodule Hnh v 4.29 ch ra s c tng hp ca module trn:

V d 4.26 l m Testbench dng m phng hot ng ca mch tr va thit k trn : module subtraction_tb(); reg inputA_reg, inputB_reg; wire [1:0] outputA_wire; integer i,j; initial begin for ( i = 0; i < 2; i = i +1) begin inputA_reg = i; for ( j =0; j <2; j = j+1) begin inputB_reg = i; #10; // delay for 10 time units end end end // This is where you instantiated your design under test subtraction DUT (.inputA ( inputA_reg), .inputB(inputB_reg), .outputA(outputA_wire)); initial

begin $monitor ( "inputA %b inputB %b outputA %b%b", inputA_reg, inputB_reg, outputA_wire[1],outputA_wire[0]); end endmodule Kt qu m phng

4.8.4.2 : Ton t nhn Nh tn ch ra, ton t ny cho php thc hin php ton nhn v c m trong Verilog dng k hiu "*". module multiplication ( inputA, inputB, outputA); input [1:0] inputA, inputB; output [3:0] outputA; wire outputA; assign outputA = inputA * inputB; endmodule Hnh v 4.22 ch ra s c tng hp ca module trn:

V d 4.32 l m Testbench dng m phng hot ng ca mch tr va thit k trn : module multiplication_tb(); reg [1:0] inputA_reg, inputB_reg; wire [3:0] outputA_wire; integer i,j; initial begin for ( i = 0; i < 4; i = i +1) begin inputA_reg = i; for ( j =0; j <4; j = j+1) begin inputB_reg = i; #10; // delay for 10 time units

end end end // This is where you instantiated your design under test multiplication DUT (.inputA ( inputA_reg), .inputB(inputB_reg), .outputA(outputA_wire)); initial begin $monitor ( "inputA %h inputB %h outputA %h", inputA_reg, inputB_reg, outputA_wire); end endmodule Kt qu m phng

4.8.5 : Ton t chia Nh tn ch ra ton t chia cho php ta thc hin php ton chia m ha trong Verilog dng k hiu "/". Phi cn thn khi dng ton t chia trong m

Verilog tng hp c. Ton t chia ch c th dng vi hng s ch khng phi trn bin, nu ton t chia c thc hin trn mt gi tr khng phi l hng s th cng c s khng th tng hp c. V d : 4.34 trnh by v ton t chia trong Verilog module division ( inputA, inputB, outputA, outputB); input [3:0] inputA; input [3:0] inputB; output [3:0] outputA; output [3:0] outputB; reg [3:0] outputA, outputB; always @ ( inputA or inputB) begin if (inputA == 4'b1010) outputA = 3/3; else outputA = 0; if (inputB == 4'b0011) output = 8/5; else outputB = 0; end endmodule Hnh v 4.23 l mch tng hp c ca ton t chia trn

V d 4.35 l testbench dng m phng m Verilog ca ton t chia. module division_tb(); reg [3:0] inputA_reg, inputB_reg; wire [3:0] outputA_wire, outputB_wire; integer i,j; initial begin for ( i = 0; i <16; i = i +1) begin inputA_reg = i; for ( j =0; j <16; j = j +1) begin

inputB_reg = j; #10; end end end division DUT (.inputA(inputA_reg), .inputB(inputB_reg), .outputA(outputA_wire), .outputB(outputB_wire)); initial begin $monitor ("inputA %h, inputB %h, outputA %h, outputB %h", inputA_reg, inputB_reg, outputA_wire, outputB_wire); end endmodule Kt qu m phng bng ActiveHDL 7.2 Student Edition

4.8.5 : Ton t ly phn d ( modulus) Nh tn ch ra ton t ly phn d cho php ta thc hin php ton lt d c m ha trong Verilog dng k hiu "%". Phi cn thn khi dng ton t ly d trong m Verilog tng hp c. Ton t ly d ch c th dng vi hng s ch khng phi trn bin, nu ton t ly d c thc hin trn mt gi tr khng phi l hng s th cng c s khng th tng hp c. V d : 4.34 trnh by v ton t chia trong Verilog module modulus ( inputA, inputB, outputA, outputB);

input [3:0] inputA; input [3:0] inputB; output [3:0] outputA; output [3:0] outputB; reg [3:0] outputA, outputB; always @ ( inputA or inputB) begin if (inputA == 4'b1010) outputA = 8%3; else outputA = 0; if (inputB == 4'b0011) output = 20%7; else outputB = 0; end endmodule Hnh v 4.23 l mch tng hp c ca ton t chia trn

V d 4.35 l testbench dng m phng m Verilog ca ton t chia. module modulus_tb(); reg [3:0] inputA_reg, inputB_reg; wire [3:0] outputA_wire, outputB_wire; integer i,j; initial begin for ( i = 0; i <16; i = i +1) begin inputA_reg = i; for ( j =0; j <16; j = j +1) begin

inputB_reg = j; #10; end end end modulus DUT (.inputA(inputA_reg), .inputB(inputB_reg), .outputA(outputA_wire), .outputB(outputB_wire)); initial begin $monitor ("inputA %h, inputB %h, outputA %h, outputB %h", inputA_reg, inputB_reg, outputA_wire, outputB_wire); end endmodule Kt qu m phng bng ActiveHDL 7.2 Student Edition

4.8.7 : Ton t logic Ton t logic tc ng ln mt nhm ton hng v kt qu tr v l gi tr nh phn 0 hay 1. Ton hng c th n bit hay a bit nhng kt qu lun l n bit. C ba loi ton t logic khc nhau c dng trong Verilog. && : y l ton t logic AND thc hin chc nng hm AND v tr v gi tr dn bit. || : Ton t OR thc hin php ton OR v cng tr v mt gi tr n bit. ! : Thc hin ton t logic NOT, n thc hin php o mt hm no v tr v gi tr n bit. V d : 4.40 l m Verilog minh ha vic dng ton t logic

module example (inputA, inputB, inputC, inputD, outputA, outputB, outputC, outputD); input inputA, inputB, inputC; input [2:0] inputD; output outputA, outputB, outputC; output [2:0] outputD; // for logical AND assign outputA = inputA && inputB; // for logical OR assign outputB = inputA || inputB; // for logical NOT assign outputC = !inputC; // for vector format assign outputD = {inputA, inputB, inputC} && inputD; endmodule Mch tng hp c

Testbench m phng mch thit k trn module logical_tb(); reg inputA_reg, inputB_reg, inputC_reg; reg [2:0] inputD_reg; wire outputA_wire, outputB_wire, outputC_wire; wire outputD_wire; integer i,j; initial begin for (i=0;i<8;i=i+1) begin {inputA_reg, inputB_reg, inputC_reg} =i; for(j=0;j<8;j=j+1) begin inputD_reg =j; #10; end

end end // Instantiating your design here example DUT (.inputA(inputA_reg), .inputB(inputB_reg), .inputC(inputC_reg), .inputD(inputD_reg), .outputA(outputA_wire), .outputB(outputB_wire), .outputC(outputC_wire),.outputD(outputD_wire)); initial begin $monitor ("inputA %b, inputB %b, inputC %b, inputD %h, outputA %b, outputB %b, outputC %b, outputD %h",inputA_reg, inputB_reg, inputC_reg, inputD_reg, outputA_wire, outputB_wire, outputC_wire, outputD_wire); end endmodule Kt qu m phng bng Active HDL student Edition

4.8.8 : Ton t Bitwise Ton t bitwise ging nh ton t logic ngoi tr ton t ny tc ng ln bus v tr v gi tr bus. V d, nu mt ton t bitwise c dng trn hai ton hng 3 bit kt qu ca ton hng cng s c 3 bit. C 4 kiu ton hng bitwise : & y l ton t bitwise AND. N thc hin hm AND v tr v mt gi tr tng ng vi ng rng ca ton hng. | y l ton t bitwise OR. N thc hin hm OR v tr v mt gi tr tng ng vi ng rng ca ton hng.

~ y l ton t bitwise NOT. N thc hin hm NOT v tr v mt gi tr tng ng vi ng rng ca ton hng. ^ y l ton t bitwise XOR. N thc hin hm XOR v tr v mt gi tr tng ng vi ng rng ca ton hng. V d 4.43 ch ra m Verilog dng cho ton t bitwise. Gin hnh 4.26 trnh by mch logic tng hp c t m Verilog. module bitwise ( inputA, inputB, inputC, inputD, outputA, outputB, outputC, outputD, outputE); input inputA, inputB, inputC ; input [2:0] inputD; output outputA, outputB, outputC, outputE; output [2:0] outputD; wire outputA, ouputB, outputC, outputE; wire [2:0] ouputD; // for bitwise AND assign outputA = inputA & inputB; // for bitwise OR assign outputB = inputA | inputB; // for bitwise NOT assign outputC = ~inputC; // for bitwise XOR assign outputE = inputA^inputB; // for vector format assign ouputD = {inputA, inputB, inputC} & inputD; endmodule

Download bitwise.v http://www.box.net/shared/00frcb60zv Mch tng hp c ca m trn

Verilog Testbench cho v d v ton t bitwise module bitwise_tb (); reg inputA_reg, inputB_reg, inputC_reg; reg [2:0] inputD; wire outputA_wire, outputB_wire, outputC_wire, outputD_wire; wire [2:0] outputD_wire; integer i,j; initial begin for ( i=0; i <8; i = i+1) begin {inputA_reg, inputB_reg, inputC_reg} = i; for ( j = 0; j <8; j = j +1) begin inputD_reg = j; #10; end end end // This is where you instantiate your design under test bitwise DUT (.inputA(inputA_reg), .inputB(inputB_reg), .inputC(inputC_reg),.inputD(inputD_reg), .outputA(outputA_wire), .ouputB(outputB_wire), .outputC(outputC_wire), .outputD(outputD_wire),.outputE(outputE_wire)); initial begin $monitor ("inputA %b, inputB %b, inputC %b, inputD %h, outputA %b, outputB %b, outputC %b, outputD %h, outputE %b", inputA_reg, inputB_reg, inputC_reg,

inputD_reg, outputA_wire, outputB_wire, outputC_wire, outputD_wire, outputE_wire); end endmodule Download bitwise_tb.v http://www.box.net/shared/hbm45yk9bz Kt qu m phng bng ActiveHDL

4.8.9 : Ton t bng ( Equality operator) Ton t bng c dng trong vic so snh cc ton hng. C hai kiu ton t bng trong m Verilog: 1. Ton t bng logic ( logical equality) c biu din bng du "==" cho php so snh bng v "!=" cho php ton khng bng. Nhng k hiu ny c dng thng xuyn trong m Verilog. Ton t bng logic c th to ra cc gi tr logic 0, 1 hay khng xc nh (X) (unknown). Php so snh cho kt qu l X khi bt k ton hng no trong php so snh c gi tr khng xc nh hay ang trng thi tng tr cao. ( High Z). Nu ton hng c gi tr bn bit "1001" v ton hng B c gi tr "1010" th kt qu ca php so snh "A==B" s cho kt qu logic 0. Mt khc, nu php so snh l "A!=B" th kt qu l 1. 2. Ton t bng trong cu lnh case c biu din bng k hiu "===" cho php so snh bng v "!==" cho php so snh khng bng. Ton t so snh bng trong cu lnh case lun to ra kt qu l 0 hay 1 v khng th to ra kt qu khng xc nh (unknown). Ton t ny so snh c gi tr X v Z. Nu ton hng A c gi tr 4 bit l "1xz0" v ton hng B c gi tr "1xz0" th php so snh "A===B" s cho kt qu 1 mt khc php ton "A!==B" s cho kt qu l 0 (false). Ngi thit k cn ch l ton t so snh bng trong cu lnh case khng tng hp c bi ta khng th to ra mch logic c th nhn dng c trng thi khng xc nh hay tng tr cao. M verilog cho minh ha vic s dng ton t so snh bng module logicalequal (inputA, inputB, inputC, inputD, outputA, outputB); input inputA, inputB, inputC, inputD;

output outputA, outputB; wire outputA, outputB; assign outputA = (inputA ==inputB); assign outputB = (inputC != inputD); endmodule Download logicalequal.v http://www.box.net/shared/5xszrlt04y Mch tng hp c

V d bn di l m Testbench dng m phng hot ng ca module logicalequal trn module logical_tb(); reg inputA_reg, inputB_reg, inputC_reg, inputD_reg; wire outputA_wire, outputB_wire; integer i; initial begin for(i =0; i<16;i=i+1) begin {inputA_reg, inputB_reg, inputC_reg, inputD_reg} = i; #10; end end // This is where you instantiate your DUT logicalequal DUT (.inputA(inputA_reg), .inputB(inputB_reg), .inputC(inputC_reg), inputD(inputD_reg), .outputA(outputA_wire), .outputB(outputB_wire)); initial

begin $monitor ( "inputA %b, inputB %b, inputC %b, inputD %b, outputA %b, outputB %b", inputA_reg, inputB_reg, inputC_reg, inputD_reg, outputA_wire, outputB_wire); end Download logical_tb.v http://www.box.net/shared/psen86gkvr Kt qu m phng bng ActiveHDL

4.8.10 : Ton t rt gn ( Reduction Operators) Ton t rt gn c cng chc nng ging nh ton t logic ngoi tr vic ton t ny tc ng ln bit ca bn thn ton hng. Kt qu c c t ton t l n bit. Nhng kiu ton t suy ra khc nhau trong Verilog bao gm : & : Ton t suy ra AND

| : Ton t suy ra OR ^ : Ton t suy ra XOR ~& : Ton t suy ra NAND ~| : Ton t suy ra NOR ~^ : Ton t suy ra XNOR

Hnh di y ch ra mch c tng hp cho ton t suy ra :

V d 4.49 M Verilog dng ton t suy ra module reduction ( inputA, inputB, inputC, outputA, outputB, outputC); input [3:0] inputA, inputB, inputC; output outputA, outputB, outputC; wire outputA, outputB, outputC; // for reduction AND assign outputA = &inputA; //for reduction OR assign outputB = |inputB; //for reduction XOR

assign outputC = ^inputC; endmodule V d 4.50 ch ra Verilog testbench dng m phng module reduction trn module reduction_tb(); reg [3:0] inputA_reg, inputB_reg, inputC_reg; wire outputA_wire, outputB_wire, outputC_wire; integer i; initial begin for ( i = 0; i <16; i= i+1) begin inputA_reg = i; inputB_reg = i; inputC_reg = i; #10; end end // Instantiating your Design under Test here reduction DUT ( .inputA(inputA_reg),.inputB(inputB_reg),.inputC(in putC_reg),.outputA(outputA_wire),.outputB(outputB_ wire),.outputC(outputC_wire)); initial begin $monitor("inputA %h, inputB %h, inputC %h, outputA %b, outputB %b, outputC %b", inputA_reg, inputB_reg, inputC_reg, outputA_wire, outputB_wire, outputC_wire); end endmodule Di y l kt qu m phng bng ActiveHDL

4.8.11 : Ton t quan h ( Relational Operators) Ton t quan h ging vi ton t bng ngoi tr tr v gi tr so snh. Kt qu tr v t ton t ny c gi tr n bit. C 4 loi ton t bng khc nhau : Ln hn ( Greater than) c biu din bng k hiu ">", tr v gi tr "1" nu ton t em so snh ln hn mt ton t khc.Nu ton t A c gi tr 5; iu kin "A >3" s cho kt qu l "1" do ton hng A ln hn 3. Nh hn ( Less than) c biu din bng k hiu "<" vi ch gii ging nh i vi ton t ln hn tc l tr v gi tr "1" nu ton hng cn so snh c gi tr nh hn mt chun hay ton hng khc.

Ln hn hay bng ( Greater than or equal) : Ch gii ging nh trn v c k hiu l ">=" Nh hn hay bng ( Less than or equal) : c k hiu l "<=". V d 4.52 l m Verilog s dng ton t quan h module relational (inputA, inputB, inputC, inputD, outputA, outputB, outputC, outputD, outputE, outputF, outputG, outputH); input [1:0] inputA, inputB, inputC, inputD; output outputA, outputB, outputC, outputD, outputE, outputF, outputG, outputH; wire outputA, outputB, outputC, outputD, outputE, outputF, outputG, outputH; assign outputA = (inputA >1); assign outpuB = (inputB <2); assign outputC = (inputC >= 1); assign outputD = (inputD <= 2); assign outputE = (inputA > inputB); assign outputF = (inputB < inputC); assign outputG = (inputC >= inputD); assign outputH = (inputB <= inputD); endmodule M Testbench dng m phng hot ng ca mch trn module relational_tb(); reg [1:0] inputA, inputB, inputC, inputD; wire outputA, outputB, outputC, outputD, outputE, outputF, outputG, outputH; integer i,j; initial begin for(i=0;i<4;i=i+1)

begin inputA = i; inputB = (3 -i); for (j=0; j <4; j = j+1) begin inputC = j; inputD = (3-j); #10; end end end // Instantiating your DUT relational DUT (inputA, inputB, inputC, inputD, outputA, outputB, outputC, outputD, outputE, outputF, outputG, outputH); initial begin $monitor ("inputA %h,inputB %h,inputC %h,inputD %h,outputA %b, outputB %b, outputC %b, outputD %b, outputE %b, outputF %b, outputG %b, outputH %b",inputA, inputB, inputC, inputD,outputA, outputB, outputC, outputD, outputE, outputF, outputG, outputH); end endmodule Kt qu m phng bng ActiveHDL

Kt qu m phng nh th ca mch trn

4.9 : Latch Inference Khi vit m Verilog ngi thit k phi ht sc cn thn bo m rng khng c nhng con cht khng mong mun xut hin. iu kin dn n nhng con cht khng mong mun thng xy ra khi ngi thit k dng "if" hay "case" m khng hon chnh, tc l cha lit k ht tt c cc trng hp. V d 4.54 l m Verilog dng "if" to ra mch t hp tuy nhin do khng nh ngha ht tt c cc trng hp ca cu lnh if nn mt con cht khng mong mun b suy ra ( inferred). module latch_infer ( inputA, inputB, inputC, inputD, outputA); input inputA, inputB, inputC, inputD; output outputA; reg outputA; always @ ( inputA or inputC or inputB or inputD) begin

if ( inputA & inputB) // This is where inferred latch occurred begin if ( inputC | ~inputD) outputA = 1'b1; else outputA = 1'bz; end end endmodule Hnh 4.30 ch ra mch c tng hp

Trong hnh trn ta thy rng v trong cu lnh if ( inputA & inputB), nu hai ng vo inputA v inputB cng c gi tr 1 th ng ra s c c li bng gi tr 1 hay high-Z ty vo hai ng inputC v inputD. Tuy nhin iu g s xy ra khi c mt trong hai gi tr inputA hay inputB c gi tr khc 1. Vic ny buc, gi tr ng ra phi gi nguyn gi tr trc nn phi c mt con cht trc bo ton gi tr ny. sa li ny ta ch cn thm vo thit k trn nh sau : module latch_infer_modified ( inputA, inputB, inputC, inputD, outputA); input inputA, inputB, inputC, inputD;

output outputA; reg outputA; always @ ( inputA or inputC or inputB or inputD) begin if ( inputA & inputB) // This is where inferred latch occurred begin if ( inputC | ~inputD) outputA = 1'b1; else outputA = 1'bz; end else outputA = 1'b0; // This is modification end endmodule Mch tng hp loi b c cht

Ngoi cu lnh if, nhng cu lnh case cng c th dn n nhng con cht khng mong mun. Nu mt cu lnh case c s dng m khng khai bo tt c cc trng hp th cht cng s t ng c suy ra. V d 4.56 ch ra m Verilog trong mt con cht b suy ra khi trong cu lnh case khng khai bo ht cc trng hp. module case_infer ( inputA, inputB, select, outputA);

input inputA, inputB; input [1:0] select; output outputA; reg outputA; always @ ( inputA or inputB or select) begin case ( select) 2'b00 : outputA = inputA; 2'b01 : outputA = inputB; endcase end endmodule Hnh 4.32 ch ra s cho mch logic c tng hp cho m t trn. Lu mt con cht c to ra ng ra outputA.

Con cht ny c to ra do m Verilog ca cu lnh case khng xc nh gi tr ca tn hiu ng ra khi select c gi tr khc "00" hay "01". iu ny lm cho gi tr trc ca outputA c gia li khi select khng phi l "00" hay "01". Mt phng cch n gin loi b con cht ny l thm iu kin mc nh (default) trong cu lnh case. Chnh iu kin ny lm cho ng ra outputA c li n mc logic 0 khi select khng phi l "00" hay "01". module case_infer ( inputA, inputB, select, outputA); input inputA, inputB; input [1:0] select; output outputA; reg outputA; always @ ( inputA or inputB or select) begin case ( select) 2'b00 : outputA = inputA; 2'b01 : outputA = inputB; default : outputA = 1'b0; // This is the modification endcase end endmodule Kt qu tng hp sau khi chnh thm vo iu kin mc nh loi b cht

Ngoi cch dng iu kin mc nh nh ch ra trong m Verilog ca module trn, s suy ra cht cng c th trnh c nu ta xc nh tt c cc kh nng trong select nh sau : module case_uninfer ( inputA, inputB, select, outputA); input inputA, inputB; input [1:0] select; output outputA; reg outputA; always @ ( inputA or inputB or select) begin case ( select) 2'b00 : outputA = inputA; 2'b01 : outputA = inputB; 2'b10 : outputA = 1'b0; 2'b11 : outputA = 1'b0; endcase end endmodule

Trong nhng v d trc ta dng cu lnh case m phng chc nng ca mt mch dn knh ( Multiplexer) trong khi always. Ngoi cch ny ra ta c th dng cu lnh iu kin m t chc nng ny. module case_uninfer_assign ( inputA, inputB, select, outputA); input inputA, inputB; input [1:0] select; output outputA; wire outputA; assign outputA = select[1] ? 1'b0 : select[0] ? inputB : inputA; endmodule 4.10 : Mng nh ( Memory Array) Khi vit m Verilog tng hp i khi ngi thit k mun m t mt mng nh. Vic m ha ny thng thy theo phng php vit m t hnh vi ( behavioral) nhng khi chuyn qua tng hp th c nhng gii hn nht nh v kich thc. Trong tng hp, khi mt cell nh 1 bit c m ha sau khi tng hp s thnh mt mch dn knh v mt flip flop. Vic biu din ny gy tn ti nguyn silicon.Tuy nhin, d kch thc ca mt cell nh l tng i ln, vic thit k nhng mng nh vn thng thy trong qu trnh thit k vi mch. Mt v d in hnh l ngi thit k cn thit k mt dy nhng thanh ghi lu tr mt gi tr no hay ngi thit k c th m ha mt mng nh dnh cho tp thanh ghi trong khi thit k vi iu khin hay vi x l. Hnh 4.34 ch ra mch tng hp c ca 1 cell nh. Tng hp nhng mng nh ln rt tn km v din tch chip tuy nhin vic lm ny li tng i d dng trong Verilog.

V d 4.60 trnh by m Verilog cho 1 KByte b nh c th tng hp c.Tuy nhin ngi thit k nn lu l, vic m t mt mng nh trong Verilog tng i n gin nhng cng vic tng hp nhng mng nh c kch thc ln thng mt nhiu hn vi pht so vi vic tng hp nhng m khc. module memory ( addr, data_in, data_out, write, read, clock, reset); // 1Kbyte memory module -- 128 address * 8 bits input [6:0] addr; input [7:0] data_in; input write, read, clock, reset; output [7:0] data_out; reg [7:0] data_out; reg [7:0] memory [127:0]; integer i; // asynchronous reset always @ (posedge clock or posedge reset)

begin if( reset) begin data_out = 0; // to initializing all memory to zero for(i =0 ; i <128; i=i+1) memory [i] <= 0; end else begin if(read) data_out <= memory [addr]; else if (write) begin data_out <= 0; memory [addr] <= data_in; end end end endmodule V d 4.61 ch ra m Verilog testbench dng kim tra tnh chnh xc ca module memory trn module memory_tb(); reg [6:0] address, addr; reg [7:0] data, data_in; reg write, read, clock, reset; parameter cycle = 20; // initializing and clock generation initial begin addr = 0; reset = 0; read = 0; write = 0;

data_in = 0; clock = 0; forever #cycle clock = ~clock; end initial begin // for reset reset = 0; #cycle; reset = 1; #cycle; reset = 0; #cycle; for ( i = 10; i<15; i=i+1) begin address = i; data = i; memory_write ( address,data); #cycle; end for ( i = 14; i>=10; i = i-1) begin address = i; memory_read (address); #cycle; end $stop; end task memory_write; input [7:0] data; input [6:0] address; begin addr = address;

data_in = data; write = 0; #cycle; write = 1; repeat (2) #cycle; write = 0; $display ( "Completed writing data %h at address %h", data_in,addr); end endtask task memory_read; input [6:0] address; begin read = 0; addr = address; data_in = 0; #cycle; read =1; repeat (2) #cycle; read = 0; #cycle; $display("Completed reading memory at address %h.Data is %h", addr,data_out); end endtask memory DUT ( addr, data_in,data_out, write, read, clock,reset); endmodule

Kt qu m phng bng ActiveHDL

Gin nh th cho qu trnh c v ghi b nh trn