Double-Gate MOSFETs

Kavitha Ramasamy, Cristina Crespo Portland State University ECE 515 Winter 2003

Overview
Introduction General DGT Structure and Operation DGT Design Objectives Short-Channel Effects Advantages of DGT (Reduction of Ioff) DGT Design Challenges (VT Control and Device Fabrication) Different DGT Structures Challenges Ahead Conclusion

Introduction
Silicon CMOS has emerged as the predominant technology in the semiconductor industry. The concept of device scaling has consistently resulted in better device density and performance. In conventional MOSFETs , control of Ioff for scaled devices requires very thin gate dielectrics and high doping concentrations. The industry roadmap for CMOS technology suggests that we may be reaching some physical limitations as well as practical technological barriers to continuous scaling.

Introduction

[1]

We are expected to reach the limit value of 35nm for the gate length by 2010

Introduction
As the downscale of CMOS technology approaches physical limitations, the need arises for alternative device structures. Many novel structures have been proposed for the nanoscale regime. One such structure is the Double-Gate Transistor, proposed in the 1980s. Other possible solutions include SOI devices, strained-silicon FETs, carbon nanotube FETs, etc.

General DGT Structure

[2]

DGT is comprised of a conducting channel (usually undoped), surrounded by gate electrodes on either side. This ensures that no part of the channel is far away from a gate electrode.

General DGT Operation

The voltage applied on the gate terminals controls the electric field, determining the amount of current flow through the channel. The most common mode of operation is to switch both gates simultaneously. Another mode is to switch only one gate and apply a bias to the second gate (this is called ground plane (GP) or back-gate (BG))

[3]

DGT Design Objectives

Reduction of short channel effects (SCE)
Increased Ioff due to DIBL Decreased VT due to reduced channel depletion charge

Maintaining good electrical characteristics

High I on /I off ratio Sharp I-V slope

Keeping fabrication process simple

Addition of steps to existing processes

Short Channel Effects

For small channel lengths, potential barrier at the drain is lowered as Vds increases, allowing more electrons to flow into the drain.

[4]

This effectively lowers VT, causing a larger I off .

[4]

Advantages of DGTs
Main advantage: Reduction of Ioff. Undoped channel eliminates intrinsic parameter fluctuations and minimizes impurity scattering. Double gate allows for higher current drive capability Better control of short channel effects.

Reduction of Ioff
Ioff is defined as the drain current at Vgs = 0 V and Vds = Vdd . Ideally, I off = 0 Sources of I off:
Thermionic emission (main) Quantum Mechanical Tunneling Band-to-Band Tunneling (abrupt doping profile)
[5]

Ioff increases as we move the body further away from the control of the gate.

Reduction of Ioff
By placing a second gate on the opposite side of the device, the gate capacitance of the channel is doubled and the channel potential is better controlled by the gate electrode, thus limiting I off

[2]

Reduction of Ioff
Reducing the body thickness further decreases I off. Reducing body thickness has the tradeoff of increasing series resistance (R = rL/A ). Rseries can be minimized by using a raised source/drain type of structure.

[5]

DGT Design Challenges

Main challenge: Control of VT. VT is defined as the value of Vgs needed to cause surface inversion, creating a conducting channel. Due to scaling of Vdd , we want to have low (~0.2 V) and symmetrical (VTn = -VTp ) threshold voltages for both transistor types. For DGTs, V T is primarily controlled by f gate . With a single midgap material for both NMOS and PMOS, symmetrical VTs can be achieved, but the value is too large (~0.8 V).

VT Control
A possible solution would be the use of two different values of _gate near the middle of Eg Si. (~0.45 eV for NMOS and ~0.49 eV for PMOS for VTn = - VTp = 0.2 V). Difficulty: Need two materials that are compatible and can coexist on the same wafer. A dual-metal gate process has been proposed, but turned out too complex. Other solutions proposed: tunable f gate by altering the chemistry of the material, metal interdiffusion, and use of small bandgap semiconductor.

VT Control

[6]

Another proposed solution to this problem is the use of asymmetrical devices, where a n+ and a p+ gate are used. Main problem with this structure is fabrication, since it requires alignment of the two gates.

VT Control
Previously, reduction of body thickness was proposed as a means to control Ioff . Another tradeoff is that reducing body thickness increases the value of VT.

[5]

Fabrication Issues
Fabrication of the DG-FET is difficult. Alignment of both gates is hard to achieve, but it is required for good device performance. Misaligned gates result in extra capacitance and loss of current drive. Several different structures have been proposed to deal with fabrication issues, including planar and quasi-planar structures.

DGT Structures: Planar

[7]

Advantages:
Better uniformity of Silicon channel thickness Can take advantage of existing fabrication processes

Disadvantages:
Fabrication of back gate and gate dielectric underneath the Silicon channel is difficult Accessing bottom gate for device wiring is not easy (may impact device density)

DGT Structures: Non-planar

[7]

Advantages:
Easier formation and access of both gates (wraparound gate) Increases device density

Disadvantages:
Channel thickness defined by lithography (poorer uniformity) Front and back gates cannot be independently biased Major departure from conventional fabrication processes

Challenges ahead
Even though simulations have shown improved performance of DGTs versus conventional MOSFETs, many challenges remain. Standard fabrication process still to be developed. Ability to set multiple threshold voltages on a single chip not yet addressed successfully. Thin Silicon channel introducing series resistance is of particular concern. Maintaining a thin, uniform Silicon channel thickness remains a major manufacturing obstacle.

Conclusion
Scaling trend in CMOS approaching physical limits prompts the need for alternative device structures, such as DGT. DGT is more robust to SCE, such as Ioff. Major design challenge consists of achieving good V T control, while keeping low Rseries . Several structures have been proposed: planar, vertical, and FinFET FinFET structure is so far the most promising. Still major challenges remain ahead, specially issues related to fabrication.

References
[1] http://www.intel.com/research/silicon/Marcyk_tri_gate_0902.pdf [2] A. R. Brown et al., A 3-D Atomistic Study of Archetypal Double Gate MOSFET Structures, Structures, J. Comp. Elec., vol. 1, pp. 165-169, 2002 [3] H.-S. P. Wong, Beyond the Conventional Transistor, Transistor, IBM J. Res. & Dev., vol. 46 No. 2/3, March/May 2002 [4] http://www.ifm.liu.se/courses/tffy34/Tutorial3.pdf [5] L. Chang et al., Gate Length Scaling and Threshold Voltage Control of Double-Gate MOSFETs, MOSFETs, IEDM pp. 719-722, 2000 [6] J.G. Fossum et al., Extraordinarily high drive current in asymmetrical double-gate MOSFETs, MOSFETs, Superlattices and Microstructures., vol. 28 No. 5/6, 2000 [7] L. Geppert, Geppert, The Amazing Vanishing Transistor Act, Act, IEEE Spectrum, October 2002 [8] K. Keunwoo et al., Double-Gate CMOS: Symmetrical- versus Asymmetrical-Gate Devices, Devices, IEEE Trans. Elec. Dev., vol. 48 No. 2, February 2001 [9] F. Assad et al., Performance limits of Silicon MOSFETs, MOSFETs, IEDM,1999