VME Data Acquisition System:

Fundamentals and Beyond

Abhinav Kumar Bhabha Atomic Research Centre, Mumbai March 2011

Presentation Outline
Chapter 1 -------------------------------Introduction to VME Chapter 2 -------------------------------VME Architecture Chapter 3 -------------------------------Data Acquisition Setup under VME Chapter 4 -------------------------------Data Acquisition with VME Modules using LAMPS

Introduction to VME
VME stands for VERSA-Module Euro card introduced in 1981 for industrial, commercial and military applications. Electrical and mechanical specifications are defined by the standard. VME bus is a master-slave computer architecture. The signaling scheme is asynchronous, meaning that the transfer is not tied to the timing of a bus clock. VITA (VME International Trade Association) is the organisation whose purpose is to promote and develop the VME

Extension of VME for Physics Application

Unlike NIM and CAMAC, the VME was created for the industry and not for physics applications However, the North American, European and Japanese physics communities have joined to work with the VITA and found the VME International Physics Association (VIPA) Two standards have been created: VME/V430 (1990) and VME64xP (1998)

VME Components
VME master VME slave VME Crate

power supply

backplane Optical Link

smart fan units

VME Modules supported by LAMPS

V785 ADC V830 Scaler

Single Width 6 U Module having 32 Peak Sensing Analog to Digital conversion channel. High channel density 12-bit resolution 5.7 s / 32 channel conversion time Zero and overflow suppression for each channel 32 event buffer memory

Single Width 6 U Module 32 Channel Latching Scaler The counters values can be read on the fly from VME without interfering on data acquisition process.

Besides these, as of date, LAMPS provides support for V862 32 Channel Multi event Individual Gate QDC; support for V775 32 Channel Multievent TDC and MesyTec High resolution(11 to 13 bit) ADCs MADC-32

Advantages of VME over CAMAC Standard

As the VME is an asynchronous bus, the bandwidth indicated is a theoretical limit. For VME64, It works to around 80 MB/s of Theoretical maximum bandwidth ; usually the actual transfer rate is less than 50% of the bandwidth High Readout Speeds High Density Modules can provide up to 640 Channels (1 controller + 20 Digitizers) in a single VME crate with 21 slots. Usage of high bandwidth optical interconnect link makes sure that the interconnect technology doesnt become a bottleneck while transferring data.

Chapter 2 --------------------------------

VME Architecture and Protocols

/AS ADDRESS /DS0, /DS1 /DTACK DATA

VME Architecture
MASTER BACKPLANE INTERFACE LOGIC
BG[3..0]OUT*

SLAVE

BG[3..0]IN*

IRQ[7..1]*

IRQ[7..1]*

LW ORD*

LW ORD*

SYSRESET*

BR[3..0]*

DTACK*

AM[5..0]

DTACK*

AM[5..0]

W RITE*

W RITE*

BERR* D[31..0]

D[31..0]

A[31..1]

Electrical Properties All lines use TTL levels ; Low = 0 .. 0.6 V; High = 2.4 .. 5 V Address, Address Modifier and data lines are active high; Protocol lines are active low.

A[31..1]

SYSRESET*

BERR*

ACFAIL*

BCLR*

BBSY*

SYSCLK

IACK*

IACK*

DS0*

DS1*

DS0*

DS1*

AS*

AS*

DATA TRANSFER BUS (DTB) DTB ARBITRATION BUS PRIORITY INTERRUPT BUS UTILITY BUS

* Active low signals

VME Addressing Modes

Addressing modes - A16, A24, A32, A40, A64 The addressing mode and the access type are defined by the Address Modifier bus AM[5:0]
AM Code 0x3B 0x39 0x2F 0x29 0x20 0x0B 0x09 0x08 Functions A24 block transfer A24 single cycle CR/CSR space access A16 single cycle 2eVME and 2eSST transfers (+ extended AM) A32 block transfer (BLT) A32 single cycle A32 64-bit block transfer (MBLT)

VME Address Space

Address=BaseAddress + Offset The maximum VME address space is made of 264 bytes (although in most cases only 232 are used, since the A64 mode is very infrequent) Each slave occupies a portion of this space, depending on its internal addressing capability There are 3 ways to allocate the address space of the slaves: 1. by the Base Address of the slaves which is set at hardware level by means of jumpers or rotary switches 2. by the position of the slave in the crate (Geographical Address) 3. by the content of some registers of the slave programmed by the software (Address Relocation) modes 2 and 3 are available in the VME64x only

VME Data Readout

Data readout is possible in following modes Single cycle
Reads a word from the slave FIFO

BLT/MBLT (Block Transfer/Multiplexed Block Transfer)

Reads a number of events limited to 256 words from any slave module In MBLT two 32 bit words are multiplexed to read as a single 64-bit word in VME64 standard

CBLT (Chained Block Transfer)

Most pertinent mode for nuclear physics applications allowing for eventby-event data acquisition. Reads the data belonging to the same physical event from several contiguous boards in a crate limited to 256 words per CBLT cycle

Chained Block Transfer

The Chained Block Transfer has been introduced for sparse data readout across multiple modules. It consists in reading the data belonging to the same physical event from several contiguous boards in a crate. It uses the IACKIN-IACKOUT daisy chain line already present in any VME backplane to propagate the readout token. No additional hardware nor external connections are required. The CBLT is handled by the slaves and is transparent to the master The use of the Bus Error to terminate the cycle is mandatory.

Multi Cast Write

The Multi Cast Write (MCST) is a single write cycle that involves several slaves in the crate. The MCST uses the same propagation mechanism as the CBLT The master initiates the cycle like a normal single write The slaves get the data in sequence and the last one asserts the DTACK

FIFO Memories
Many VME acquisition boards use FIFO memories to store the data. This is particularly suitable for physics applications in which the events occur randomly in time and are readout sequentially A read access to any address within that range causes the non repeatable extraction of one word from the FIFO. CAEN ADC modules are endowed with 32 Events Buffer.

Interrupts in VME
The VME features a 7 level prioritized interrupt architecture; the request lines IRQ[7:1] are shared between all the slots The interrupt is initiated by the interrupter (this can be any board in any slot) that asserts one IRQ. The interrupt handlers (usually the board in slot 1) monitor the IRQ lines and generate an interrupt acknowledge cycle in response to the request The interrupt handler reads the STATUS/ID of the interrupter from the data bus If more interrupters had asserted the same IRQ line, the IACKINIACKOUT daisy chain allows the uppermost left to respond first (priority given by the position)

Chapter 3 --------------------------------

Setting up a VME acquisition system

C. A. E. N.

Bus Adapter Feature

It makes possible to control the VME bus remotely from a standard PC through a high speed link The acquisition program (DAQ) runs on the remote PC The VME board is just hardware (no software runs on it) Computing power (processors, memories, disks, etc ) is on the PC Unlike the ethernet port of a SBC, the communication link of the bus adapter must be able to sustain high data transfer rates VME-PCI/PCIe: usually communicates through an optical link, requires a card inside the PC

Advantages of Bus Adapter over SBC

HW and SW upgrade on PC side: you can buy a new one at any time Easy getting started: just install a driver in the PC Ready at power-up (no boot required) Lower total cost of ownership Multi-crate interconnection and control
Bus Adapter Slaves

computing power is here!

this is just hardware

access to the bus through the adapter

USB Link Optical

C. A. E. N.

used for data transfer

VME Controller V2718

Max throughput rate: 70MB/s VME64/VME64X (no 2eSST) PCI 32bit, 33MHz Optical Link: 1.25 Gb/s Max distance: 300m
V2718
~ 70 MB/s max 300m

FPGA

VMEbus

A2818 FPGA
PCI-int
RAM buffer Optical Link RAM buffer

CONET

Optical Link

PCI bus

VME Base Address ( Hardware Setting)

A32 mode
31 24 23 16 15 0

C 2
B CD E B CD E B CD E F01 F01 F01

4
2 2
3 45 6 3 45 6

8
B CD E F01

OFFSET

Address Space: 16 Kbytes from 0xC2480000 to 0xC248FFFF OFFSET: which register inside the board

2
3 45 6

2
3 45 6

BASE ADDRESS: which board inside the crate

A24 mode
31 24 23 16 15 0

unused
B CD E F01

4
2
3 45 6

8
B CD E F01

7 89

7 89
2
3 45 6

7 89

7 89

7 89

7 89

OFFSET

Address Space: 16 Kbytes from 0x480000 to 0x48FFFF

Operational Aspects
Controller should be inserted in slot 1 of the VME Crate. While setting up the CBLT Chain, the modules forming the chain should be contiguous; last module should be terminated with a 50 Ohm resistance. Scalars can be inserted in any empty slot. MesyTec ADCs, if used along with CAEN Modules, should be inserted first in the chain.

Chapter 4 --------------------------------

Data Acquisition using VME Modules through LAMPS software

Hardware/Software layers
DAQ Software (LAMPS)

CAENVME Library Digitizer Modules

A2818 Driver

Digitizer Modules

VME Bus

V2818 Controller

PCI Bus

Digitizer Modules A218 PCI CONET Controller

CONET

Software Installation
Installation of A2818 (PCI CONET Controller) driver
- CAEN A2818 PCI CARD - Linux kernel Rel. 2.4 or 2.6 with gnu C/C++ compiler PCI CONET Controller

Installation of CAENVMELib Library

Set of functions for the control and the use of CAEN VME Bridges. Typically, it provides function calls to
PCI Slot Open (Init) and Close the communication and the devices Make single Read/Write cycles Make Block Transfer Read/Write cycles Wait for an interrupt and make a IACK cycle

Installation of LAMPS
No changes in the LAMPS installation procedure.

Checking for Basic Connectivity

Post hardware setup and software installation, basic connectivity with the Bus Adapter can be checked using the Test Feature of the LAMPS software. Indication of an error at this stage implies an incorrect hardware/software setup.

Setup Configuration under LAMPS

Bus Adapter needs no Base Address configuration. For other modules, setting up of Base Address in software is compulsory.

Setting up Special Properties

QDC special settings

TDC special settings

Configuring SCALERS under LAMPS

Blue Rectangular region VME Controller ; Green Rectangular Region- CBLT Chain ; Purple rectangular region - Scaler

Master Gate Blocking

Master Gate blocking is essential to have any meaningful acquisition with VME, failing which a good number of events could be corrupt depending on the data rate. Concept: No master gate should reach VME modules until the current event has been completely digitized and read out. This statement may look incomplete because it doesnt talk of the 32-event buffer in VME modules. But the solution (see below) is based on BUSY status of VME modules, hence it covers this complication. Solution: Chain the BUSY output from all the modules in use using short Lemo cables and Lemo T connectors and veto the master gate of the experiment with this before input to VME modules. LAMPS automatically displays the dead time when the blocked and unblocked master gates are provided on two inputs of CAEN V830 VME scaler module.

Conclusion
The VME DAQ in the current form provides us with a powerful system because of the large number of parameters which can be acquired simultaneously and high event rates. The zero suppressed readout option along with the availability of variety of digitizers with higher channel density presents a very good system in front of users, before we eventually migrate to digital DAQ.