147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

Department of ECE

Pa e 1

147451 Electronic Circuits II & Simulation Lab CIRCUIT DIAGRAM: CURRENT- SERIES FEEDBACK AMPLIFIER: Without feedback: Without feedback:

II Yr / IV sem

12Vdc

R1 51K

RC 2.4K C2

C1 0.1uF Vin = 20mV f = 20 H ! 20KH

Q1

0.1uF

BC107A

RL 4.7K R2 9K RE 600

+
CRO

CE 5.3uF

Department of ECE

Pa e 2

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

1. CURRENT SERIES FEEDBACK AMPLIFIER

AIM:
1. To design a Current Series feedback amplifier for the following specifications. Vcc=12 V !c=2m" V#$=%.&V hfe=2%%. 2. To plot the fre'uenc( response graph for the amplifier with and without feedback. ). To calculate the following parameters with and without feedback a* Voltage gain b* #andwidth

EQUIPMENTS REQUIRED:
0"/1$ $+,!-.$/T -ower suppl( C05 8unction generator 3%4)%*V 3%42%*.67 3%41*.67 +,"/T!T2 1 1 1

COMPONENTS REQUIRED:
C5.-5/$/T #9T 0esistors Capacitors #C1%: +,"/T!T2 1

DESIGN:
Given Specific !i"n# $e Vcc=12 V !c=2m" V#$=%.&V hfe=2%%. R%&e "f T'%():

!C ; !$ re=2&mV<!$ re=2&=1%4)<2=1%4) = 1) > hie=hfe re=2.& ?> Department of ECE Pa e )

147451 Electronic Circuits II & Simulation Lab CURRENT- SERIES FEEDBACK AMPLIFIER: With Feedback:

II Yr / IV sem

12Vdc

R1 51K

RC 2.4K C2

C1 0.1uF Vin = 20mV f = 20H ! 20KH R2 9K

Q1

0.1uF

BC107

RL 4.7K RE 600 CRO

Department of ECE

Pa e @

147451 Electronic Circuits II & Simulation Lab T" fin* RE:

II Yr / IV sem

T" fin* RC:

T" fin* )i #in+ $e#i#!"$# R1 n* R,: Current through 02A

"ppl(ing Voltage diBider rule

Department of ECE

Pa e C

147451 Electronic Circuits II & Simulation Lab MODEL GRAP-: Frequency Response of Current Series Feedback Amplifier

II Yr / IV sem

Bandwidth without feedback = f) D f2. #andwidth with feedback = f@ D f1.

Department of ECE

Pa e &

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

b( solBing 31* E 32* we get

T" fin* CE:

Fet the smallest fre'uenc( f . /00 -1

T" fin* CC:

rin=hie=2.&?> GCC=).2?> CC=1< 32HfGcc*

Department of ECE

Pa e :

147451 Electronic Circuits II & Simulation Lab TABULATION: Iithout 8eedbackA 8re'uenc( Vo Volts 1ain = Vo<Vs

II Yr / IV sem

Vin = 1ain 3d#* = 2%log3Vo<Vs*

Iith feedbackA 8re'uenc( Vo Volts 1ain = Vo<Vs Vin = 1ain 3d#* = 2%log3Vo<Vs*

Department of ECE

Pa e J

147451 Electronic Circuits II & Simulation Lab PROCEDURE:

II Yr / IV sem

1. Connect the circuit as per the circuit diagram 2. Set Vs = C%mV using the signal generator ). ?eeping the input Boltage constant Bar( the fre'uenc( from 2%67 to 2% ?67 in regular steps and note down the corresponding output Boltage. @. -lot the graphA gain 3d#* Bs. fre'uenc(. C. 8ind the input and output impedances. &. Calculate the bandwidth from the graph. :. /ote the phase angle bandwidth input and output impedance. J. 0emoBe emitter resistance 30$* i.e. feedback loop and follow the same procedure 31 to :*.

RESULT: Thus the Current4series feedback amplifier was designed for the giBen specifications and the fre'uenc( response graph was plotted for the circuit with and without feedback. The results are summari7ed as followsA4 Current Series Iith Iithout 8eedback 8eedback #andwidth Voltage 1ain

Department of ECE

Pa e K

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

CIRCUIT DIAGRAM: 2OLTAGE-S-UNT FEEDBACK AMPLIFIER: Without feedback:

12Vdc

R1 51K

0C
2.4K C2

C1 0.1uF Vin = 2%mB f = 2%67 D 2%?67

Q1

0.1uF

BC107A

RL 4.7K R2 9K RE 600 CRO

CE 5.3uF

Department of ECE

Pa e 1%

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

,. 2OLTAGE S-UNT FEEDBACK AMPLIFIER

AIM:
1. To design a Voltage Shunt feedback amplifier for the following specifications. Vcc=12 V !c=2m" V#$=%.&V hfe=2%%. 2. To plot the fre'uenc( response graph for the amplifier with and without feedback. ). To calculate the following parameters with and without feedback a. Voltage gain b. #andwidth

EQUIPMENTS REQUIRED:
$+,!-.$/T -ower suppl( C05 8unction generator 0"/1$ 3%4)%*V 3%42%*.67 3%41*.67 +,"/T!T2 1 1 1

COMPONENTS REQUIRED: C5.-5/$/T #9T 0esistors Capacitors 0"/1$ #C1%: +,"/T!T2 1

DESIGN:
Given Specific !i"n# $e Vcc=12 V !c=2m" V#$=%.&V hfe=2%%. R%&e "f T'%():

!C ; !$ re=2&mV<!$ re=2&=1%4)<2=1%4) = 1) > hie=hfe re=2.& ?> Department of ECE Pa e 11

147451 Electronic Circuits II & Simulation Lab 2OLTAGE-S-UNT FEEDBACK AMPLIFIER: With Feedback:

II Yr / IV sem

12Vdc

R1 51K 1 R5 2.2K C1 0.1uF VA#$L = 20mV f=20H "20KH V2 C4 0.1uF Q1

R3 2.4K C2 0.1uF

BC107A

RL 4.7K R2 9K 9K R4 600 CRO

C3 5.3uF

T" fin* RE: Department of ECE Pa e 12

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

T" fin* RC:

T" fin* )i #in+ $e#i#!"$# R1 n* R,: Current through 02A

"ppl(ing Voltage diBider rule

MODEL GRAP-: Department of ECE Pa e 1)

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

Frequency Response of Voltage-shunt Feedback Amplifier

Bandwidth without feedback = f) D f2. #andwidth with feedback = f@ D f1.

Department of ECE

Pa e 1@

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

b( solBing 31* E 32* we get

T" fin* CE:

Fet the smallest fre'uenc( f . /00 -1

T" fin* CC:

%in=&i'=2.6K( )CC=3.2K( CC=1* +2,f)cc-

Department of ECE

Pa e 1C

147451 Electronic Circuits II & Simulation Lab TABULATION: Iith 8eedbackA 8re'uenc( Vo Volts 1ain = Vo<Vs

II Yr / IV sem

Vin = 444444 V 1ain 3d#* = 2%log3Vo<Vs*

Iithout feedbackA 8re'uenc( Vo Volts 1ain = Vo<Vs Vin = LL V 1ain 3d#* = 2%log3Vo<Vs*

Department of ECE

Pa e 1&

147451 Electronic Circuits II & Simulation Lab PROCEDURE:

II Yr / IV sem

1. Connect the circuit as per the circuit diagram 2. Set Vs = C%mV using the signal generator ). ?eeping the input Boltage constant Bar( the fre'uenc( from 2%67 to 2% ?67 in regular steps and note down the corresponding output Boltage. @. -lot the graphA gain 3d#* Bs. fre'uenc(. C. 8ind the input and output impedances. &. Calculate the bandwidth from the graph. :. /ote the phase angle bandwidth input and output impedance. J. Connect the feedback resistor 30f* between the base and the collector to form the feedback loop and follow the same procedure 31 to :*. RESULT: Thus the Voltage4shunt feedback amplifier was designed for the giBen specifications and the fre'uenc( response graph was plotted for the circuit with and without feedback. The results are summari7ed as followsA4 Voltage4shunt Iith Iithout 8eedback 8eedback #andwidth Voltage 1ain

SERIES AND S-UNT FEEDBACK AMPLIFIER Sample viva questions:

1. ,. 3' ! $e !'e *v n! +e# "f ne+ !ive Fee*) c4 (p&ifie$ 5'en c"(p $e 5i!' (p&ifie$6 7. 3' ! 5i&& ' ppen !" !'e B n*5i*!'8 + in8 "%!p%! n* inp%! $e#i#! nce "f v"&! +e #e$ie# fee*) c4 (p&ifie$ )ec %#e "f fee*) c46 9. Define ne+ !ive fee*) c4. /. 3' ! i# !'e !:pe "f fee*) c4 e(p&":e* in fee*) c4 (p&ifie$6 ;. C"(p $e O#ci&& !"$ n* A(p&ifie$. <. Define De#en#i!ivi!: n* Sen#i!ivi!: f c!"$. =. 3'en fee*) c4 (p&ifie$ i# # i* !" )e #! )&e6 K. A c"(("n > e(i!!e$ ci$c%i! 5i!'"%! B:-p ## c p ci!"$ i# c &&e* ne+ !ive c%$$en! fee*) c4 ci$c%i! 5':6 10. C%$$en! #e$ie# (p&ifie$ i# T$ n#c"n*%c! nce (p&ifie$: ?%#!if:6 11. 2"&! +e S'%n! (p&ifie$ i# T$ n#$e#i#! nce (p&ifie$: ?%#!if:6 1,. A c"(("n > c"&&ec!"$ (p&ifie$ ci$c%i! i# n e@ (p&e "f 5'ic' ne+ !ive fee*) c4 ci$c%i!6 CIRCUIT DIAGRAM: Department of ECE Pa e 1:

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

RC P-ASE S-IFT OSCILLATOR:

Department of ECE

Pa e 1J

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

7. DESIGN OF RC P-ASE S-IFT OSCILLATOR AIM:

1. To design and construct a 0C -hase shift oscillator for the following specifications. Vcc = 12V !c = 2m" V#$ = %.&V hfe = 2%% f = 2 ?67 C = %.%1M8 2. To plot the output sine waBeform graph for the 5scillator.

EQUIPMENTS REQUIRED:
$+,!-.$/T -ower suppl( C05 0"/1$ 3%4)%*V 3%42%*.67 +,"/T!T2 1 1

COMPONENTS REQUIRED: C5.-5/$/T #9T 0esistors Capacitors 0"/1$ #C1%: +,"/T!T2 1

DESIGN:
Given Specific !i"n# $e Vcc = 12V !c = 2m" V#$ = %.&V hfe = 2%% f = 2 ?67 C = %.%1M8 R%&e "f T'%():

!C ; !$ re=2&mV<!$ re=2&=1%4)<2=1%4) = 1) > hie=hfe re=2.& ?>

Department of ECE

Pa e 1K

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

MODEL GRAP-:

Department of ECE

Pa e 2%

147451 Electronic Circuits II & Simulation Lab T" fin* RE:

II Yr / IV sem

T" fin* RC:

T" fin* )i #in+ $e#i#!"$# R1 n* R,: Current through 02A

"ppl(ing Voltage diBider rule

Department of ECE

Pa e 21

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

TABULATION:

A(p&i!%*e A2"&!#B

Ti(e Pe$i"* T ASec"n*#B

F$eC%enc: f AK-1B

Department of ECE

Pa e 22

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

b( solBing 31* E 32* we get

T" fin* CE:

Fet the smallest fre'uenc( f . /00 -1

T" fin* CC:

rin=hie=2.&?> GCC=).2?> CC=1< 32HfGcc* Department of ECE Pa e 2)

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

T" fin* !'e fee*) c4 c p ci!"$ C: 1iBen f = 2 ?67 C = %.%1M8

C = 1 < 32H f 0N&* = %.%1M8

Department of ECE

Pa e 2@

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

T" fin* 0O 0O = 04 0i = 2.2 ? > 4 301 PP 02 PP hie* = 2.2 ? > D 3:.&C? > PP 2.&? >* = 2.2 ? > D 1.K@? > 0O = 2&% > PROCEDURE: 1. Connect the circuit as per the circuit diagram. 2. Switch on the power suppl( and obserBe the output on the C05 3Sine waBe*. ). /ote down the practical fre'uenc( and compare it with the theoretical fre'uenc(. RESULT: Thus the 0C phase shift oscillator was designed for the giBen fre'uenc( and the output sine waBeform was plotted. Theoretical fre'uenc( of the oscillator -ractical fre'uenc( of the oscillator = = 2 ?67.

Department of ECE

Pa e 2C

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

CIRCUIT DIAGRAM: -ARTLED OSCILLATOR:

Department of ECE

Pa e 2&

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

9. DESIGN OF -ARTLED OSCILLATOR AIM:

1. To design and construct a 6artle( oscillator for the following specifications. Vcc = 12V !c = 2m" V#$ = %.&V hfe = 2%% f = 1%%?67 F1 = 1m6 2. To plot the output sine waBeform graph for the 5scillator.

EQUIPMENTS REQUIRED:
$+,!-.$/T -ower suppl( C05 0"/1$ 3%4)%*V 3%42%*.67 +,"/T!T2 1 1

COMPONENTS REQUIRED: C5.-5/$/T #9T 0esistors Capacitors 0"/1$ #C1%: +,"/T!T2 1

De#i+n:
Given Specific !i"n# $e Vcc = 12V !c = 2m" V#$ = %.&V hfe = 2%% f = 1%%?67 F1 = 1m6 R%&e "f T'%():

!C ; !$ re=2&mV<!$ Department of ECE Pa e 2:

147451 Electronic Circuits II & Simulation Lab re=2&=1%4)<2=1%4) = 1) > hie=hfe re=2.& ?>

II Yr / IV sem

MODEL GRAP-:

Department of ECE

Pa e 2J

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

T" fin* RE:

T" fin* RC:

T" fin* )i #in+ $e#i#!"$# R1 n* R,: Current through 02A

"ppl(ing Voltage diBider rule

Department of ECE

Pa e 2K

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

TABULATION:

A(p&i!%*e A2"&!#B

Ti(e Pe$i"* T ASec"n*#B

F$eC%enc: f AK-1B

Department of ECE

Pa e )%

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

b( solBing 31* E 32* we get

T" fin* CE:

Fet the smallest fre'uenc( f . /00 -1

T" fin* CC:

rin=hie=2.&?> GCC=).2?> CC=1< 32HfGcc*

Department of ECE

Pa e )1

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

T" fin* !'e fee*) c4 c p ci!"$ C: 1iBen f = 1%% ?67 F1 = %.1 m6 F2 = 2.@m6

Department of ECE

Pa e )2

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

PROCEDURE: 1. Connect the circuit as per the circuit diagram. 2. Switch on the power suppl( and obserBe the output on the C05 3Sine waBe*. ). /ote down the practical fre'uenc( and compare it with the theoretical fre'uenc(. RESULT: Thus the 6artle( oscillator was designed for the giBen fre'uenc( and the output sine waBeform was plotted. Theoretical fre'uenc( of the oscillator -ractical fre'uenc( of the oscillator = = 1%% ?67.

Department of ECE

Pa e ))

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

CIRCUIT DIAGRAM: COLPITTS OSCILLATOR:

12Vdc

R1 51K

Rc 2.4K Cc

Cc 0.1uF

Q1

0.1uF

BC107A

R2 9K

CRO R4 600 CE 5.3uF

0
L 0.2mH

Department of ECE

C1 0.1uF

C2 0.01uF

Pa e )@

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

/. DESIGN OF COLPITTS OSCILLATOR AIM:

1. To design and construct a Colpitts oscillator for the following specifications. Vcc = 12V !c = 2m" V#$ = %.&V hfe = 2%% f = 1%%?67 C1 = %.1M8 2. To plot the output sine waBeform graph for the 5scillator.

EQUIPMENTS REQUIRED:
$+,!-.$/T -ower suppl( C05 Components 0e'uiredA C5.-5/$/T #9T 0esistors Capacitors 0"/1$ #C1%: +,"/T!T2 1 0"/1$ 3%4)%*V 3%42%*.67 +,"/T!T2 1 1

DESIGN:
Given Specific !i"n# $e Vcc = 12V !c = 2m" V#$ = %.&V hfe = 2%% f = 1%%?67 C1 = %.1M8 R%&e "f T'%(): Department of ECE Pa e )C

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

!C ; !$ re=2&mV<!$ re=2&=1%4)<2=1%4) = 1) > hie=hfe re=2.& ?>

TABULATION:

A(p&i!%*e A2"&!#B

Ti(e Pe$i"* T ASec"n*#B

F$eC%enc: f AK-1B

Department of ECE

Pa e )&

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

T" fin* RE:

T" fin* RC:

Department of ECE

Pa e ):

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

T" fin* )i #in+ $e#i#!"$# R1 n* R,: Current through 02 A

"ppl(ing Voltage diBider rule

MODEL GRAP-:

Department of ECE

Pa e )J

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

b( solBing 31* E 32* we get

T" fin* CE:

Fet the smallest fre'uenc( f . /00 -1

Department of ECE

Pa e )K

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

T" fin* CC:

rin=hie=2.&?> GCC=).2?> CC=1< 32HfGcc*

T" fin* !'e fee*) c4 c p ci!"$ C,: 1iBen f = 1%% ?67 F = %.2m6. Fet C1 = %.1Q8.

Department of ECE

Pa e @%

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

PROCEDURE: 1. Connect the circuit as per the circuit diagram. 2. Switch on the power suppl( and obserBe the output on the C05 3Sine waBe*. ). /ote down the practical fre'uenc( and compare it with the theoretical fre'uenc(.

RESULT: Thus the Colpitts oscillator was designed for the giBen fre'uenc( and the output sine waBeform was plotted. Theoretical fre'uenc( of the oscillator -ractical fre'uenc( of the oscillator = = 1%% ?67.

Department of ECE

Pa e @1

147451 Electronic Circuits II & Simulation Lab OSCILLATORS Sample Viva Questions:

II Yr / IV sem

1. Ihat t(pe of feedback is preferred in oscillatorsR 2. 6ow does oscillation start in oscillatorsR ). Fist out the applications of oscillators @. Ihich oscillator is Ber( suitable for audio range applicationsR C. Ihich oscillator is suitable for 08 range applicationsR &. Ihich oscillator is suitable for low fre'uenc( applicationsR :. "mplifier circuit is necessar( in an oscillator wh(R J. Three 0C sections are used in 0C -hase Shift oscillators wh(R K. 1enerall( negatiBe feedback is emplo(ed in amplifiers whereas positiBe feedback is emplo(ed in oscillators wh(R 1%. 8or low fre'uenc( applications we appl( 0C oscillators and not FC oscillators wh(R

CIRCUIT DIAGRAM:

Department of ECE

Pa e @2

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

12Vdc

0.01uF

0.2mH

C3 1uF

C1 1uF

Q1

BC107

VA#$L = 1V FREQ = 100KH

R1 15K

CRO

;. TUNED CLASS C AMPLIFIER

AIM: To design a Tuned Class C amplifier for the following specifications. Vcc = 12V f = 1%%?67 To plot the fre'uenc( response graph for the amplifier. To calculate the following parameters with and without feedback Department of ECE Pa e @)

147451 Electronic Circuits II & Simulation Lab c* Voltage gain d* #andwidth EQUIPMENTS REQUIRED: $+,!-.$/T -ower suppl( C05 8unction generator 0"/1$ 3%4)%*V 3%42%*.67 3%41*.67

II Yr / IV sem

+,"/T!T2 1 1 1 +,"/T!T2 1

COMPONENTS REQUIRED: C5.-5/$/T 0"/1$ #9T #C1%: 0esistors Capacitors PROCEDURE:

1. Connect the circuit as per the circuit diagram 2. Set Vs=C%mV3sa(* using the signal generator. ). ?eeping the input Boltage constant Bar( the fre'uenc( from %67 to 1 .67 in regular steps and note down the corresponding output Boltage. @. -lot the graphA 1ain3d#* Vs fre'uenc(.

MODEL GRAP-:

Department of ECE

Pa e @@

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

TABULATION: 8re'uenc( Vo Volts 1ain = Vo<Vs Vin = 1ain 3d#* = 2%log3Vo<Vs*

DESIGN: The giBen specification is Vcc = 12V f = 1%%?67

Department of ECE

Pa e @C

147451 Electronic Circuits II & Simulation Lab Fet us assume The resonant fre'uenc( f

II Yr / IV sem

= 1 @H231%%2*k2%.%1Q

= %.2m6

Department of ECE

Pa e @&

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

Department of ECE

Pa e @:

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

RESULT: Thus the Tuned Class C amplifier was designed and constructed and the fre'uenc( response was plotted in the graph. The results are summari7ed as follows A The theoretical resonant fre'uenc( = 1%% ?67. The practical resonant fre'uenc( = The lower cut4off fre'uenc( = The upper cut4off fre'uenc( = #andwidth of the tuned amplifier =

Sample Viva Questions:

1. 2. ). @. C. &. :. Ihat do (ou mean b( tuned amplifierR Sefine Class C amplifier. Sefine + factor. Ih( + factor is kept as high as possible in tuned circuitR .ention the applications of Class C tuned amplifier. Ihat is meant b( loaded and unloaded + of tank circuitR Ihat is the need for neutrali7ation in tuned amplifierR

CIRCUIT DIAGRAM:

Department of ECE

Pa e @J

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

10Vdc

RB RC 4.9. C 620.

RB 620. C 1.162nF Q2

RC 4.9.

1.162nF Q1 BC107

BC107

<. DESIGN OF ASTABLE MULTI2IBRATOR

AIM: 1. To design and construct an astable multiBibrator for the following giBen specificationsA Department of ECE Pa e @K

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

2. To plot the collector Boltage and base Boltage waBeform of the two transistors. EQUIPMENTS REQUIRED: $+,!-.$/T -ower suppl( C05 8unction generator 0"/1$ 3%4)%*V 3%42%*.67 3%41*.67 +,"/T!T2 1 1 1

COMPONENTS REQUIRED: C5.-5/$/T #9T 0esistors Capacitors DESIGN: The giBen specifications are 0"/1$ #C1%: +,"/T!T2 1

To find 0CA4 "ppl( ?VF to collector circuit

To find resistance 01 and 02A4 "ppl( ?VF to the base

MODEL GRAP-:

Department of ECE

Pa e C%

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

TABULATION: "mplitude 3V* -arameters V#2 VC1 V#1 VC2 Time 3ms*

Department of ECE

Pa e C1

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

!# should be greater than !#3min*

To find Capacitance CA4 Time Constant T for astable multiBibrator is

PROCEDURE: 1. 2. ). @. Connect the circuit as per the circuit diagram. Switch on the power suppl(. 5bserBe the waBeform both at base and collector of +1 and +2. -lot the waBeform.

RESULT: Thus an astable multiBibrator was designed and constructed for the giBen specifications and its output waBeforms were obserBed.

Department of ECE

Pa e C2

147451 Electronic Circuits II & Simulation Lab CIRCUIT DIAGRAM: MONOSTABLE MULTI2IBRATOR:

II Yr / IV sem

=. DESIGN OF MONOSTABLE MULTI2IBRATOR

AIM: Department of ECE Pa e C)

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

1. To design and construct a monostable multiBibrator for the following giBen specificationsA 2. To plot the collector Boltage and base Boltage waBeform of the two transistors. EQUIPMENTS REQUIRED: $+,!-.$/T -ower suppl( C05 8unction generator 0"/1$ 3%4)%*V 3%42%*.67 3%41*.67 +,"/T!T2 1 1 1

COMPONENTS REQUIRED: C5.-5/$/T #9T 0esistors Capacitors DESIGN: The giBen specifications are 0"/1$ #C1%: +,"/T!T2 1

8or stable state assume transistor +1 is 588 and +2 is 5/.

.Sue to

s(mmetr( 0c2 = 0c1 =0c

=1%M" Select hence take !#2 = 2.C !#2 3min* Time Constant

MODEL GRAP-:

Department of ECE

Pa e C@

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

TABULATION: "mplitude 3V* -arameters V#2 VC1 V#1 VC2 Trigger !nput Time 3ms*

Department of ECE

Pa e CC

147451 Electronic Circuits II & Simulation Lab "s

II Yr / IV sem

Ihen +1 is 588 Fet us take

% = 4201 + 01 + 02

%.202 01 + 02

4201 + %.202 =% %.202 = 201 02 = 201< %.2 "ssume 01 = 1%k> 02 = 1%%k>

"ssume CommutatiBe capacitor C1 = 1%%p8.

PROCEDURE: 1. Connect the circuit as per the circuit diagram. 2. Switch on the power suppl( and obserBe the output waBeform at the collector of +1 and +2. ). Sketch the waBeform. @. Trigger the monostable multiBibrator with a pulse and obserBe the change in waBeform. C. Sketch the waBeform and obserBe the changes before and after triggering the input to the circuit. RESULT: Thus the monostable multiBibrator was designed and constructed for the giBen specifications and its output waBeforms were obserBed.

CIRCUIT DIAGRAM: Department of ECE Pa e C&

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

BISTABLE MULTI2IBRATOR

E. DESIGN OF BISTABLE MULTI2IBRATOR

AIM: Department of ECE Pa e C:

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

1. To design and construct a monostable multiBibrator for the following giBen specificationsA ). To plot the collector Boltage and base Boltage waBeform of the two transistors. EQUIPMENTS REQUIRED: $+,!-.$/T -ower suppl( C05 8unction generator 0"/1$ 3%4)%*V 3%42%*.67 3%41*.67 +,"/T!T2 1 1 1

COMPONENTS REQUIRED: C5.-5/$/T #9T 0esistors Capacitors 0"/1$ #C1%: +,"/T!T2 1

DESIGN: The giBen specifications are

"ssume +1 is at cut4off and +2 is at saturation.

+1 is at cut4off so V#1 should be at negatiBe potential.

"ssume 01 = 1%?T

MODEL GRAP-:

Department of ECE

Pa e CJ

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

Department of ECE

Pa e CK

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

#( s(mmetr( 0C1 = 0C2= 0c

!f !#2 U !#2 3min* then +2 is in saturation.

"s !#2 U !#2 3min* +2 is in saturation. The resolution time is 2V where V = 0C.

TABULATION: Department of ECE Pa e &%

147451 Electronic Circuits II & Simulation Lab "mplitude 3V* -arameters V#2 VC1 V#1 VC2 Trigger !nput Time 3ms*

II Yr / IV sem

Department of ECE

Pa e &1

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

PROCEDURE: 1. Connect the circuit as per the circuit diagram. 2. Switch on the power suppl( and obserBe the output waBeform at the collector of +1 and +2. ). Sketch the waBeform. @. "ppl( a threshold Boltage VT3pulse Boltage* and obserBe the change of states +1 and +2. C. Sketch the waBeform. RESULT: Thus the monostable multiBibrator was designed and constructed for the giBen specifications and its output waBeforms were obserBed.

MULTI2IBRATORS Sample Viva Questions:

1. 2. ). @. C. &. :. J. Ihat is the multiBibratorR Fist the applications of monostable multiBibrator. Ihich mutiBibrator would function as a time dela( unitR Ih(R 6ow a Schmitt trigger is different from a multiBibratorR .ention the applications of astable multiBibrator. Sefine commutating capacitor. Ihat are the other names for bistable multiBibratorR Ihich multiBibrator would be useful for each of the following purposeR a. time4dela( unit b. memor( deBice c. fre'uenc( diBision d. adWustable pulse width generator e. reference clock to s(nchroni7e timings in digital s(stems.

CIRCUIT DIAGRAM:

Department of ECE

Pa e &2

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

TABULATION: DIFFERENTIATOR: 2i . ,2 pp8 f . 1 K-1 Re#i#! nce R A"'(#B 1K 10 K 100 K INTEGRATOR: 2i . ,2pp 8 f . 100 K-1 Re#i#! nce R A"'(#B ,< 10 K 100 K A(p&i!%*e A2"&!#B Ti(e A(#B A(p&i!%*e A2"&!#B Ti(e A(#B

10. DESIGN OF DIFFERENTIATOR AND INTEGRATOR

AIM: Department of ECE Pa e &)

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

1. To design a high pass 0C circuit and obserBe its response for the giBen s'uare waBeform for TXX0C T=0C and TUU0C. 2. To design a low pass 0C circuit and obserBe its response for the giBen s'uare waBeform for TXX0C T=0C and TUU0C. EQUIPMENTS REQUIRED: $+,!-.$/T C05 8unction generator 0"/1$ 3%42%*.67 3%41*.67 +,"/T!T2 1 1

COMPONENTS REQUIRED: C5.-5/$/T 0esistors Capacitors 0"/1$ +,"/T!T2

PROCEDURE:
Time constant of the circuit 0C= %.%1KJ ms 1. "ppl( a s'uare waBe of 2B p4p amplitude as input. 2. "dWust the time period of the waBeform so that TUU0C T=0C TXX0C and obserBe the output in each case. ).Sraw the input and output waBe forms for different cases.

MODEL GRAP-:
Department of ECE Pa e &@

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

LO3 PASS RC CIRCUIT:

Department of ECE

Pa e &C

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

-IG- PASS RC CIRCUIT:

Department of ECE

Pa e &&

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

Department of ECE

Pa e &:

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

RESULT:
Thus the integrator and differentiator circuits are designed and their output response for Barious time constants are obtained

CIRCUIT DIAGRAM:
Department of ECE Pa e &J

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

CLIPPERS:

11. CLIPPERS AND CLAMPERS

Department of ECE

Pa e &K

147451 Electronic Circuits II & Simulation Lab AIM:

II Yr / IV sem

To obtain the output response for Barious non linear waBe shaping circuits D Clippers and Clampers. EQUIPMENTS REQUIRED: $+,!-.$/T -ower suppl( C05 8unction generator 0"/1$ 3%4)%*V 3%42%*.67 3%41*.67 +,"/T!T2 1 1 1

COMPONENTS REQUIRED: C5.-5/$/T S!5S$ 0esistors Capacitors 0"/1$ !/@%%1 +,"/T!T2 1

T-EORD:
CLIPPERS: The basic action of a clipper circuit is to remoBe certain portions of the waBeform aboBe or below certain leBels as per the re'uirements. Thus the circuits which are used to clip off unwanted portion of the waBeform without distorting the remaining part of the waBeform are called clipper circuits or Clippers. The half waBe rectifier is the best and simplest t(pe of clipper circuit which clips off the positiBe<negatiBe portion of the input signal. The clipper circuits are also called limiters or slicers. CLAMPERS: The clamping network is one that will clamp an input signal to a different SC leBel. The network consists of a capacitor a diode and a resistance but it can also haBe an independent SC suppl( to introduce an additional SC shift. The magnitude of 0 and C must be chosen such that the time constant V = 0C is large enough to ensure that the Boltage across the capacitor does not discharge significantl( during the interBal when the diode is non4conducting.

CLAMPERS:
/egatiBe peak clamped at positiBe reference leBelA Department of ECE Pa e :%

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

-ositiBe peak clamped at negatiBe reference leBelA

DESIGN: CLAMPER : 8or proper clamping V U1%%T Department of ECE Pa e :1

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

where T is the time period of input waBeform !f fre'uenc( is 1 k67 with peak4peak input Boltage of 1%V T=1ms V = 0F.C=1%%=T = 1%%ms Fet C=1Qf 0F= 1%%?T Select C =1Q8 and 0F =1%% k>

T-EORETICAL CALCULATIONS: P"#i!ive pe 4 c&ippe$: Vr=2B VY=%.&B Ihen the diode is forward biased Vo =Vr+ VY =2B+%.&B = 2.&B Ihen the diode is reBerse biased the Vo=Vi P"#i!ive ) #e c&ippe$: Vr=2B VY=%.&B Ihen the diode is forward biased Vo=Vr DVY = 2B4%.&B = 1.@B Ihen the diode is reBerse biased Vo=Vi . Ne+ !ive ) #e c&ippe$: Vr=2B VY=%.&B Ihen the diode is forward biased Vo = 4Vr+ VY = 42B+%.&B = 41.@B Ihen the diode is reBerse biased Vo=Vi . Ne+ !ive pe 4 c&ippe$: Vr=2B VY=%.&B Ihen the diode is forward biased Vo= 43Vr+ VY* = 432+%.&*B =42.&B Ihen the diode is reBerse biased Vo=Vi .

PROCEDURE:
1. Connect the circuit as per circuit diagram shown in 8ig.1 2. 5btain a sine waBe of constant amplitude J V p4p from function generator and appl( as input to the circuit. ).5bserBe the output waBeform and note down the amplitude at which clipping occurs @. Sraw the obserBed output waBeforms.

MODEL GRAP-:

Department of ECE

Pa e :2

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

Department of ECE

Pa e :)

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

Department of ECE

Pa e :@

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

/egatiBe peak clamped at positiBe reference leBelA

-ositiBe peak clamped at negatiBe reference leBelA

Department of ECE

Pa e :C

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

RESULT:
Thus the performance of Barious clipping and clamping circuits were obserBed.

Department of ECE

Pa e :&

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

CIRCUIT DIAGRAM: CMOS IN2ERTER:

0
V # # 1 0 . V $ 1 d c

/ % ' 0

V 1 V 2 2 3 2 R 2 F $ 4 $ E R

= = = =

= =

5 0

0 0

V VV

# #

2 . 1

0 0 . 5 m 5 = 1 0m 5

/ % ' 0

CMOS NAND + !e:

0
5 V d c V 2

% '

0 .

V 1 V 2 2 3 2 R 2 F $ 4 $ E R

= = = =

= =

5 0

V 0 0 V 1

/ % '

0 .

0 0 . 5 m 5 = 1 0m 5

V 1 V 2 2 3 2 R 2 F $ 4 $ E R

= = = = = =

5 V 0 VV 3 0 0 0 0 . 5 m 5# = 1 0m 5

# / % '

5 0 . 1

# # / % '

6 0 . 1

Department of ECE

Pa e ::

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

1/. SIMULATION OF CMOS IN2ERTER8 NAND AND NOR GATES

AIM: To simulate the C.5S inBerter /"/S and /50 circuits. SOFT3ARE REQUIRED: -S-!C$ 5rcad famil( release K.2.

PROCEDURE:
1. 1o to start 5rcad capture /ew proWect. 2. Create a blank proWect then draw the circuit b( taking appropriate components and simulate the diagram. ). 5bserBe the output waBeforms. @. $bipolar D #C1%:" #reakout D mbreak- mbreak/ Source D Vdc Vpulse VS0C Vsin "nalog - D r c F

Department of ECE

Pa e :J

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

CMOS NOR + !e:

0
V 5 6 # V 1 V 2 2 3 2 R 2 F $ 4 $ E = = = = = R = 0 = 5 0 0 0 6V 3
V

4 d c 3 / % ' 0 . $

0 0. 5 m 5 1 m 5V V 2 2 2 $ $

# 1 2 3 R F 4 E = = = R = = = = 0 0 0 0 0 6V 2
V

/ % ' 0

0 0. 5 m 5 1 m 5
V

# # # # 2 . 1

1 . 1

/ % ' 0

/ % ' 0

Department of ECE

Pa e :K

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

RESULT: Thus the C.5S inBerter /"/S and /50 circuits were simulated and output waBeforms are Department of ECE Pa e J%

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

CMOS inve$!e$

C.5S /"/S

Department of ECE

Pa e J1

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

C.5S /50 1"T$

Department of ECE

Pa e J2

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

CIRCUIT DIAGRAM:

Department of ECE

Pa e J)

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

1;. SIMULATION OF DIFFERENTIAL AMPLIFIER

AIM: To simulate the differential amplifier circuit and obtain the output waBeform using -S-!C$. SOFT3ARE REQUIRED: -S-!C$ 5rcad famil( release K.2.

PROCEDURE:
1. 1o to start 5rcad capture /ew proWect. 2. Create a blank proWect then draw the circuit b( taking appropriate components and simulate the diagram. ). 5bserBe the output waBeforms.

RESULT:
Thus the simulation of differential amplifier was done using -S-!C$.

Department of ECE

Pa e J@

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

CIRCUIT DIAGRAM:
R 1

3 C = A C = 2 R A 1

4 . V 1 0 6 V 0 = 0 R 2

0
V 3 7 8 2 7 4

3 C = A C = 2 R A 1

V 22 . 0 6 V 0 = 0

1 5 65 9 : 2 7 : 6 1 5 5 6 6 2 1 1
V

0
R 3 C = A C = 2 R A 1 6 13 . 5 6 V 0 = 0 3

0
u

7 4

1 4

R 1 .

TABULATION : b % b1 b2 Theoritical Value -ractical Value

Sigital to analog

Department of ECE

V"

"

V8

9 9

Pa e JC

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

1<. SIMULATION OF DIGITAL TO ANALOG CON2ERTER

AIM: To simulate the digital to analog conBerter using -S-!C$. SOFT3ARE REQUIRED: -S-!C$ 5rcad famil( release K.2. T-EORD: #inar( weighed resistor S"C makes use of a summing amplifier using op4 amp. Ihen there are n4bits in the digital codes there is a re'uirement of n number of binar( weighed resistors from 0 to 0 < 2n41.

V% = 40f Z bo< 0o + b1<01 + b2<02[ PROCEDURE:

1. 1o to start 5rcad capture /ew proWect. 2. Create a blank proWect then draw the circuit b( taking appropriate components and simulate the diagram. ). 5bserBe the output waBeforms.

Department of ECE

Pa e J&

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

RESULT:
Thus the simulation of digital to analog conBerter was done using -S-!C$.

CIRCUIT DIAGRAM:

Department of ECE

Pa e J:

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

1=. DESIGN AND SIMULATION OF II ORDER LO3-PASS BUTTER3ORT- FILTER

AIM: 1. To design a second order #utterworth low4pass filter for the following giBen specifications 2. ,se -S-!C$ to plot the fre'uenc( response of the output Boltage of the filter designed from 1%67 to 1% ?67. SOFT3ARE REQUIRED: -S-!C$ 5rcad famil( release K.2. DESIGN: " second order filter e\hibits a stop band roll off of 4@% d#<decade. The general form the second4order low4pass filter is giBen b(

where ? is the dc gain. The #utterworth response re'uires that of The transfer function

Department of ECE

Pa e JJ

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

the sallen4ke( circuit giBes to achieBe a #utterworth response with sallen ke( topolog(. Therefore we must reduce the gain b( 1<?. 1iBen specifications are Fet us consider the design of the !! order F-8 from that we can design the #utterworth !! order F-8. !! 50S$0 F5I4-"SS 8!FT$0 S$S!1/A The cut4off fre'uenc( fo is giBen b(

Department of ECE

Pa e JK

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

Therefore

Choose C less than or e'ual to 1Q8. Fet C = %.%1Q8

1ain of the amplifier is

!! 50S$0 #,TT$0I50T6 F5I4-"SS 8!FT$0 S$S!1/A The transfer function of sallen ke( circuit giBes The transfer function of #utterworth filter giBes

Department of ECE

Pa e K%

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

To achieBe the #utterworth response reduce gain b( 1<?. The gain reduction can be achieBed b( adding a Boltage4diBider network consisting of 0a and 0b. The Balues of 0a and 0b must be such that 0in = 02 and the Boltage across 0b is Vi<?. i.e.

Voltage across 0b

SolBing these two e'uations for 0a and 0b

6ere ?=@

#utter worth low pass

Department of ECE

Pa e K1

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

PROCEDURE: 1. 2. ). @. C. &. :. 1o to start ] all ] programs ] capture. Select file in the menu bar ] new proWect. Choose location CA programfiles<orcad<LL Create a blank proWect. Sraw the circuit diagram in the schematic editor. Create new simulation profile from -spice menu. !n simulation settings select ac sweep and logarithmic scale. Choose the fre'uenc( range from 1%67 to 1% ?67. J. SaBe the proWect and click run and obserBe the output waBeform.

Department of ECE

Pa e K2

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

RESULT: Thus the #utterworth low pass filter of second order was designed and simulated using -S-!C$.

CIRCUIT DIAGRAM:

Department of ECE

Pa e K)

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

1E. DESIGN AND SIMULATION OF II ORDER -IG--PASS BUTTER3ORT- FILTER

AIM: 1. To design a second order #utterworth low4pass filter for the following giBen specifications P63W^* P= 1 fo = 1 ?67 + = %.:%: Vcc = 1CV. 2. ,se -S-!C$ to plot the fre'uenc( response of the output Boltage of the filter designed from 1%67 to 1% ?67. SOFT3ARE REQUIRED: -S-!C$ 5rcad famil( release K.2. DESIGN: !! 50S$0 #,TT$0I50T6 6!164-"SS 8!FT$0 S$S!1/A The transfer function of sallen ke( circuit giBes The transfer function of #utterworth filter giBes To achieBe the #utterworth response reduce gain b( 1<?. The gain reduction can be achieBed b( adding a Boltage4diBider network consisting of Ca and Cb. The Balues of Ca and Cb must be such that Cin = C2 and the Boltage across Cb is Vi<?. i.e. Department of ECE Pa e K@

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

C a + Cb = C 2 Then Ca < 3Ca +Cb* = 1<? Ca = C2<? C2 = %.%1 = 1%4& < 1.CJ& = &.)%C n8. Cb = C2 D &.)%Cn8 = ).K&C n8.

PROCEDURE: 1. Sraw the circuit diagram in the schematic editor. 2. Create new simulation profile from -spice menu. ). !n simulation settings select ac sweep and logarithmic scale. Choose the fre'uenc( range from 1%67 to 1% ?67. @. SaBe the proWect and click run and obserBe the output waBeform.

Department of ECE

Pa e KC

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

RESULT: Thus the butterworth high pass filter of second order was designed and simulated using -S-!C$.

2I2A QUESTIONS: 1. Ihat is difference between linear and non4linear waBe shaping circuits. 2. Ihat is meant b( lower )4db fre'uenc( of high4pass circuitR ). Ihat is meant b( fractional tiltR @. Ih( response of amplifier does not remain flat at all fre'uencies. C. $\plain condition of 0C circuit to work as differentiation. &. Ih( 0C circuits are preferred oBer 0F circuits for large time constant applications. :. Ihat do (ou mean b( a linear networkR J. Ihat do (ou mean b( Finear IaBe ShapingR Department of ECE Pa e K&

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

K. 8or a long time constant 0C high pass circuit with a s(mmetrical s'uare waBe input find the tilt. 1%. !ntegrators are preferred oBer the differentiators. Ih(R 11. Ih( 0C circuits are commonl( used as compared to 0F circuitsR 12. Ih( does comparator differ from clipperR 1). Ihat is drawback of haBing diode as series element in clipperR 1@. Ihat is drawback of haBing diode as shunt element in clipperR 1C. Ihat is the difference between regeneratiBe and non4regeneratiBe comparator. 1&. Ihat is difference between output from clipping and clamping circuitR 1:. Sefine an ideal differential amplifier. 1J. Sefine common4mode reWection ratio.

CIRCUIT DIAGRAM

V 3 1 2 V R 4 5 . 9 CK 1 Q B
V 1

C R 5 5 . 9 K

2 0 0 $ 0 K R 6 1 0 7 A F

C 1 1 0 0 $ R 1 3 0 K Q 2

0
V 1 V 2 2 3 2 R 2 F $ 4 $ E = =

R 1 9 1 . 6

7 K

R 2 9 1 . 6

B C 7 K

0 7 A

1 2V V 1 " 1 2 6 V = 0 = 0 = 0 = 0 0. 5 # : R = 1V m 1 5 = 1 2 V 2 = " 1 2 3 = 0 2 R = 0 2 F = 0 $ 4 = 0 $ E R =

V V 2 2 6 V

0. 5 #
1 m

Department of ECE

Pa e K:

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

,0. SIMULATION OF BISTABLE MULTI2IBRATOR

AIM: To simulate the bistable multiBibrator circuit and obtain the output waBeform using -S-!C$. SOFT3ARE REQUIRED: -S-!C$ 5rcad famil( release K.2.

PROCEDURE:
1. 1o to start 5rcad capture /ew proWect. 2. Create a blank proWect then draw the circuit b( taking appropriate components and simulate the diagram. ). 5bserBe the output waBeforms.

Department of ECE

Pa e KJ

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

RESULT: Thus the bistable multiBibrator was designed and simulated using -S-!C$.

CIRCUIT DIAGRAM:

Department of ECE

Pa e KK

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

,1.SIMULATION OF ASTABLE MULTI2IBRATOR

AIM: To simulate the astable multiBibrator circuit and obtain the output waBeform using -S-!C$. SOFT3ARE REQUIRED: -S-!C$ 5rcad famil( release K.2.

Department of ECE

Pa e 1%%

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

PROCEDURE:
1. 1o to start 5rcad capture /ew proWect. 2. Create a blank proWect then draw the circuit b( taking appropriate components and simulate the diagram. ). 5bserBe the output waBeforms.

MODEL GRAP-:

Department of ECE

Pa e 1%1

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

Department of ECE

Pa e 1%2

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

RESULT: Thus the astable multiBibrator was designed and simulated using -S-!C$.

Department of ECE

Pa e 1%)

147451 Electronic Circuits II & Simulation Lab CIRCUIT DIAGRAM

II Yr / IV sem

,,. SIMULATION OF MONOSTABLE MULTI2IBRATOR

Department of ECE

Pa e 1%@

147451 Electronic Circuits II & Simulation Lab AIM:

II Yr / IV sem

To simulate the monostable multiBibrator circuit and obtain the output waBeform using -S-!C$. SOFT3ARE REQUIRED: -S-!C$ 5rcad famil( release K.2.

PROCEDURE:
1. 1o to start 5rcad capture /ew proWect. 2. Create a blank proWect then draw the circuit b( taking appropriate components and simulate the diagram. ). 5bserBe the output waBeforms.

MODEL GRAP-:

Department of ECE

Pa e 1%C

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

Department of ECE

Pa e 1%&

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

RESULT: Thus the monostable multiBibrator was designed and simulated using -S-!C$.

SPECIFICATIONS: Department of ECE Pa e 1%:

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

BC 10< > NPN GENERAL PURPOSE TRANSISTOR

FEATURES: 4 Fow Current 3ma\. 1%%m"* 4 Fow Voltage 3ma\. @C V*

8or !C = 2m" VC$ = CV hfe3min* = 11% hfe3ma\* = @C% Vbe3min* = CC%mV Vbe3t(p* = &2%mV Vbe3ma\* = :%%mV

Department of ECE

Pa e 1%J

147451 Electronic Circuits II & Simulation Lab

II Yr / IV sem

Department of ECE

Pa e 1%K