TUNNELING DEVICES

Interband tunneling in Si end-of-roadmap devices

Multiemitter tunneling HBT - good peformance with enhanced logic - ULSI-compatible (in principle) - no predictive (tunneling) device model

Lateral interband tunneling diode on SOI - FET geometry with VG control of current - no inversion channel, different scaling - testbed for interband tunneling theory

Motivation: MOSFET scaling will end

ideal long-channel ID(VG) makes MOSFET a perfect switch

subthreshold slope S > 2.3kT/q ~ 60 mV/decade MOSFET degraded by short-channel effects: degraded S, DIBL

Downscaling difficulties
ultimate scaled planar transistors [Doris et al, 2002]

ID
(A/m)

V D = 1.2 V
EOT= 1.2 nm LG = 6 nm tSi = 48 nm

V D = 0.05 V

VG (V)

short channel effects, degraded subthreshold slope S reduced current drive due to series resistance

Can tunneling help?

annoyance in standard MOSFETs
gate leakage

S/D leakage

BUT

not apriori constrained by S = 60 mV/decade can provide highly nonlinear characteristics

log J

FET

TT (tunneling transistor)

VG

INTERBAND TUNNELING DEVICES

Esaki tunnel diode (heavily-doped pn junction) [Esaki, 1958]

p+

n+

reverse bias

forward bias

current ITUN ~ strong (exponential) function of electric eld F note the same tunneling mechanism in reverse bias no rigorous expression for ITUN in indirect materials (e.g. Si)

INDIRECT TUNNELING
direct tunneling conserves energy E and momentum k analytically tractable for a known barrier shape U(z)

U(z) E

T( E ) ~ e

2 # [2m*(U(z)E)/h2]1/2 dz

E k k E EC EV Indirect material (like Si !!) means !k " 0

simulators (e.g. Silvaco) use empirical expressions quantitatively unreliable !! Can interband tunneling be useful in end of roadmap devices?

MULTIEMITTER TUNNELING HBT Proposed [Gribnikov & Luryi, 1994] first demonstration [Zaslavsky, Luryi et al., 1997]
E1
BACKWARD DIODE EMITTER-BASE JUNCTIONS

E2
n -Si p -SiGe base

n-Si

C
n -Si collector

two (or more) emitter contacts, no base contact required for operation control current due to interband emitter-base tunneling under reverse bias enhanced logic due to emitter contact symmetry (xor and ornand functions in a single device) easier fabrication, high current gain, ultra-narrow HBT base, VLSI compatibility

MULTIEMITTER BIASING
VE2 VC
IC IE IB

forward bias injection

reverse bias tunneling

note that tunneling base current is indirect (Si/SiGe) so no quantitative evaluation is possible

GAIN AND TRANSCONDUCTANCE

VE2 VC
IC
VE2

IE

IB

IC = IE

- !IB

output current level for a given emitter V E2 (with VE1 = 0, grounded)

IB

forward turn-on voltage schematic backward diode I(VEB )

VEB

VE2 splits between forward and reverse bias on EB junctions small tunneling current IB controls IE1 ~ IC = $IB output current gain $ depends on emitter-base parameters (large b in HBTs) transconductance IC(VE2) depends on emitter-base I(VEB) if VE1 = VE2 no current ows (oating base transistor)

FIRST IMPLEMENTATION
Emitter-base I(VEB)

n-Si ~ 3x1018 p-SiGe ~ 4x1019

floating base Transistor characteristics

IB = 010 A
$ ~ 400 floating second emitter

multiemitter biasing indistinguishable from standard HBT

DEVICE OPTIMIZATION

(a)

Heavier E-B doping

IC(IB,VC) curves IB = 05 A $ ~ 1300

IC(VE2,VC) curves VE2 = 0.61 V

ADDED LOGIC FUNCTIONALITY

VE1 VE2
1 0 1 0 4.31 mA 4.23 mA

(a)

XOR (2 emitters) low = 0 high = 0.9 V

0

IC

(mA)
2

0.14 A

TIME

1 VE1 0

(b)

ORNAND (3 emitters) low = 0 high = 0.9 V

VE2 VE3

1 0 1 0 6.42 6 5.22 5.65

IC 4 (mA)
2 0 <10 nA

2.24

2.90

2.36 0

TIME

reasonable emitter symmetry good on/off logic ratio (> 60 dB at room temperature)

VLSI COMPATIBILITY

collector

p-SiGe base

BiCMOS industry process (Agere Systems) with selective SiGe base epitaxy Comparable multiemitter HBT process

collector

KEY PROBLEM: no predictive device model for circuit designer

IDEAL TUNNELING DIODE STRUCTURE

surface-controlled avalanche transistor [Schockley, 1964] lateral interband tunneling transistor on thin SOI [Zaslavsky and Luryi, 1999]

VG n++-Si BOX p+-Si

VD

thin Si channel (< 50 nm, low CSD); ultra-short gate (low CG) different scaling rules (no channel!) implications unknown complicated electrostatic problem for F(VG, VD) in reverse bias (no minority carrier injection, low capacitance) high-speed analog applications

COMPETING MOSFET-BASED STRUCTURE

n-MOSFET with p-type drain [Koga and Toriumi, 1996-99]

VG n p ninv

VG control of ID reported in forward bias to maintain negative differential resistance (NDR) channel not needed, but requires area and adds CG

FIRST DEVICE RUN (LETI-Grenoble)

simplest possible process, no additional masks

VG1 n++(p+)-Si p+-Si VG2

junction obtains by counterdoping, with the drain protected by a shifted active area mask

gate much wider than the junction depletion region gate overlaps junction, source and drain

 shifted lithography

counterdoping of n-Si source, P = 8 keV, 5x1014 cm-2 deposited gate oxide, tox = 4.6 nm, followed by in-situ doped poly-Si gate, standard subsequent processing

TRANSISTOR CHARACTERISTICS

T = 300 K LG = 0.35 m

reverse bias tunneling ID shows VG control (either VG polarity, VG > 0 more effective) soft reverse bias ID turn-on (insufcient junction doping!) no dependence on gate length LG (as expected)

REVERSE-BIAS TUNNELING ID(VD) vs. VG

heaviest doping (np 1020:6x1019)
1.0
TUNNELING ID (m A)

5V4.8V 4.6V 4.4V 4.2V 4V 3.5V VG = 0 0.0 0.4 0.8 1.2 1.6 2.0
REVERSE BIAS VD (V)

0.8 0.6 0.4 0.2 0.0

0.25
TUNNELING ID (m A)

0.20 0.15 0.10 0.05 0.00 0.0 0.4 0.8 1.2

-5V -4.8V -4.6V -4.4V -4V VG = -3.5 V 1.6 2.0

REVERSE BIAS VD (V)

VG control of ID exists, but requires large VG

SIMULATIONS FOR ABRUPT pn JUNCTION

5.0x106

!MAX (V/cm)

ideal ab rup t 4x1019 p n junction in 10 nm Si channel

4.0x106 3.0x106
real doub le-imp lanted p n junction

2.0x106

-4

-2

VG (V)

taking empirical ITUN(VD,VG) at face value:

Q. Zhang et al, IEEE EDL 27, 297 (2006)

subthreshold S < 60 mV/decade for low VD

MULTIEMITTER TUNNELING HBT - works well, enhanced logic - requires BiCMOS process

GATED INTERBAND TUNNELING DIODE - works in principle - becoming !popular! in industry Inneon is publishing counterdoped FET designs

INTERBAND TUNNELING MODEL ***key issue - better modeling/simulation needed