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Code No: 3220203

Set No. 1

II B.Tech II Semester Regular Examinations, April/May 2009 LINEAR AND DIGITAL IC APPLICATIONS ( Common to Electrical & Electronic Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Explain how the input o set voltage compensated for Op-amp. [6+6+4]

(b) How fast can the output of an Op-amp change by 10V, if its slew rate is 1V/s? (c) Dene thermal drift. 2. (a) With the help of neat block diagram, explain the operation of a xed voltage regulator. (b) Describe the operation of an IC based negative voltage regulator. Give few applications. (c) Describe the principle of operation of a peak detector with wave forms.[6+6+4] 3. Write short notes on: (a) Frequency of oscillation of a square wave generator. (b) Triangular wave generator using a square wave generator. 4. (a) Explain the operation of Astable multivibrator using 555 timer. (b) Design a Monostable multivibrator using 555 timer to produce a pulse width of 200 ms. [10+6] 5. (a) With an example explain the functional diagram of successive approximation ADC. (b) Draw the schematic circuit diagram of a Servo A/D converter and explain the operations of this system. (c) Compare Servo A/D with other types of A/D converters. [7+6+3] [8+8]

6. (a) Draw the circuit of two input NAND gate with totem-pole output and do the static analysis when output is HIGH & Output is low. (b) Dene the following terms: i. ii. iii. iv. Fan-in. Fan-out. Standard load. Noise-Margin.

[8+8]

7. (a) Implement the following Boolean function using 8:1 multiplexer F (ABCD) = ABD + ACD + BCD + ACD 1 of 2

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Code No: 3220203

Set No. 1

(b) Design a 32 to 1 multiplexer using four 74151 multiplexers and 74139 decoder? [8+8] 8. (a) Design 4 bit left shift register with serial in and parallel out facility. Show the output waveform of each ip op output. (b) Explain the functional behavior of Static RAM cell? Show the internal structure of 84 static RAM? [8+8]

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Code No: 3220203

Set No. 2

II B.Tech II Semester Regular Examinations, April/May 2009 LINEAR AND DIGITAL IC APPLICATIONS ( Common to Electrical & Electronic Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) List out the AC characteristics of an Op-amp and discuss about them.[10+6] (b) A 741 Op-amp is used as an inverting amplier with a gain of 50. The voltage gain Vs frequency curve of 741 is at up to 20 KHz. What is the maximum peak to peak input signal that can be applied with out distorting the output. 2. (a) Discuss the operation of a log amplier and derive the expression for output voltage. (b) Design a current to voltage converter using Op-amp and explain how it can be used to measure the output of a photocell. [8+8] 3. (a) Explain the frequency responses of all lters. (b) Figure 3 shows the rst order Butterworth LPF that uses RC network, calculate the gain if the lter is a function of frequency. Give gain magnitude and phase angle equations. [8+8]

Figure 3 4. (a) Draw the circuit of Schmitt trigger using 555 timer and explain its operation. (b) How is an Astable multivibrator using 555 timer connected in to a pulse position modulator? [8+8] 5. (a) Compare weighted resistor D/A converter and R-2R D/A converter. (b) Why successive approximation A/D converter is preferable than parallel comparator A/D converter. Explain. (c) Draw the schematic block diagram of Dual-slope A/D converter and explain its operation. Derive expression for its output voltage Vo. [2+4+10] 1 of 2

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Code No: 3220203

Set No. 2

6. (a) Draw the circuit of two input NAND gate with totem-pole output and do the static analysis when output is HIGH & Output is low. (b) Explain why two totem pole outputs cant be tied together. (c) With neat circuit explain the concept of open collector O/P with pull-up. resistor. [6+6+4] 7. (a) Implement the following Boolean function using 8:1 multiplexer F (ABCD) = ABD + ACD + BCD + ACD (b) Design a 32 to 1 multiplexer using four 74151 multiplexers and 74139 decoder? [8+8] 8. (a) Design a modulo-100 counter using two 74163 binary counters? (b) Design an 8-bit parallel-in and serial-out shift register? Explain the operation of the above shift register with the help of timing waveforms? [8+8]

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Code No: 3220203

Set No. 3

II B.Tech II Semester Regular Examinations, April/May 2009 LINEAR AND DIGITAL IC APPLICATIONS ( Common to Electrical & Electronic Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) Give the design procedure of a compensating network for an Op-amp which uses 10V supply voltages. Assume necessary data. (b) In the circuit of gure 1, R1 =100 , RF = 4.7K , CMRR=90 db. If the amplitude of the induced 60-Hz noise at the output is 5mV (rms). Calculate the amplitude of the common-mode input voltage Vcm . [8+8]

Figure 1 2. (a) Draw the basic circuit diagram of an Op-amp dierentiator and explain its operation and stability. (b) Design a monostable multivibrator with trigger pulse shaping which will drive a LED on for 0.5 sec each time it is pulsed. [8+8] 3. (a) Dene Bessel, Butterworth and Chebysher lters, and compare their frequency response. (b) Sketch the block diagram of I/II order band elimination lter and design a I order wide band- reject having fH =200 Hz and fL =1 kHz, having the passband gain of 2 each. Assume necessary data. [6+10] 4. (a) Give the functional block diagram of NE 565 PLL and for the given component values. C1 = 390PF, C2 = 680PF and R1 = 10k,Vcc = 6V. Find i. The free running frequency. ii. The lock range and capture range. Where C1 is the capacitor connected between pin number 9 and - VCC , C2 is the capacitor connected between + VCC and output pin 7, and R1 is connected between pin number 8 and + VCC .

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Code No: 3220203

Set No. 3

(b) Give the functional block diagram of VCO NE566 and explain its working and necessary expression for free running or center frequency. [16] 5. (a) Explain the operation of a multiplying DAC and mention its applications. (b) A 12-bit D to A converter has a full-scale range of 15 volts. Its maximum dierential linearity error is 1/2 LSB. i. What is the percentage resolution? ii. What are the minimum and maximum possible values of the increment in its output voltage? [8+8] 6. (a) What are the desirable features of CMOS gates? (b) Sketch the circuit of CMOS NAND gate and verify that it satises the Boolean NAND equation. (c) Dene the following terms: i. ii. iii. iv. v. Fan-in Fan-out Standard load Current sink Current source.

[5+6+5]

7. (a) Write short notes on priority encoder? (b) Design full adder using NOR gates only? [8+8]

8. (a) Explain with an example why asynchronous inputs are required in ip ops. (b) Explain the operation of edge triggered T ip- op. [8+8]

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Code No: 3220203

Set No. 4

II B.Tech II Semester Regular Examinations, April/May 2009 LINEAR AND DIGITAL IC APPLICATIONS ( Common to Electrical & Electronic Engineering and Instrumentation & Control Engineering) Time: 3 hours Max Marks: 80 Answer any FIVE Questions All Questions carry equal marks 1. (a) What are the three factors that aect the electrical parameters of an Op-amp. (b) Derive the expression for CMRR for the rst stage dierential amplier. [8+8] 2. (a) What is Gyrator circuit? Explain its operation with a neat circuit diagram. (b) What is a sample and hold circuit? Why is it needed? With neat circuit diagram, describe the operation of an Op-amp based sample and hold circuit. [6+10] 3. (a) A fourth order Butterworth polynomial is given as (S2 +0.765S+1) (S2 + 1.848S+1). Design the fourth order Butterworth lter having upper cuto frequency 2 KHz. Assume suitable data. Draw the circuit diagram with suitable values. (b) What are the gain constraints imposed on higher order lters? Explain.[10+6] 4. (a) Design an astable multivibrator using 555 timer to produce a square wave of 2 KHz frequency and 70% duty cycle. Draw the circuit with all component values. (b) Explain how a PLL is used as a frequency multiplier. [8+8]

5. (a) With a neat circuit diagram explain the functioning of an inverted R-2R ladder type Digital to Analog converter. (b) The LSB of a 10-bit DAC is 20 mVolts. i. What is its percentage resolution? ii. What is its full-scale range? iii. What is the output voltage for an input, 10110 01101? 6. (a) Give the classication of MOS logic. (b) Explain the switching action of MOS logic. (c) What are the advantages of MOS logic families over others? [6+6+4]

[8+8]

7. (a) What is multiplexer? Draw the logic diagram of 4 to 1 line multiplexer? (b) Design half adder using NAND gates only? [8+8]

8. (a) Discuss in detail ROM access mechanism with the help of timing waveforms? 1 of 2

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Code No: 3220203 (b) Write short notes on Clocked T ip op.

Set No. 4
[8+8]

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