TIMER/COUNTER

I. Gii thiu
Trong cc ng dng ca vi iu khin (VDK), vic nh thi (to mt khong thi gian
gia hai s kin) gia cc thao tc ng vai tr rt quan trng. thc hin vic ny, ta
c hai cch thng dng : ta tr bng hm delay hoc dng chc nng timer ca vi iu
khin. Nhng hm delay ch l mt chui nhng cu lnh v ngha m khi thc hin,
VDK khng th thc hin thm mt tc v no khc. Trong khi , dng timer, VDK
thc hin song song gia vic m timer v cc lnh trong chng trnh chnh v vy s
dng timer nh thi s tt hn.
Vi iu khin PIC 16F887 cung cp cho ngi dng ba b Timer : Timer0, Timer 1 v
Timer 2. Trong bi ny chng ta s ch nghin cu v Timer 0. Timer 1 v Timer 2 s
c nghin cu c th cc phn sau v cc b hai Timer ny c nhiu ng dng phc
tp hn.
Trong bi ny, ti s nhc s b v mt khi nim l ngt (interrupt) ca VDK v phn
timer/counter v phn interrupt lin quan mt thit vi nhau. Phn nghin cu y v
Interrupt s c cp n cc bi sau. y chng ta ch nghin cu Interrupt ng
dng trong b Timer0.
II. Timer 0
II.1. Cu to
II.1.1. Tng quan
Timer 0 c ng dng rng ri trong thc hnh. Rt t chng trnh khng s dng n
trong mt vi trng hp. Timer0 rt thun tin v d dng trong vic vit cc chng
trnh hay cc chng trnh con to cc xung c rng ty , tnh ton thi gian hay
m xung ngoi.
B Timer 0 l b timer 8-bit vi cc c im sau:
B timer/counter 8-bit: b Timer 0 c hai chc nng l timer v counter. Gi tr
m hin ti ca b Timer 0 s c cha trong thanh ghi 8 bit l TMR0.
B chia tn (prescaler) 8 bit s dng chung vi b Watchdog timer (WDT).
C th c lp trnh s dng ngun xung dao dng ni (internal clock source)
hoc ngun xung dao ng ngoi (external clock source).
nh ngha xung clock ni v xung clock ngoi cho timer khc hon ton so vi
chip.
i vi chip xung ni ngha l xung c to ra t b dao dng RC c tch hp
sn c trong chip. Xung ngoi l ngun xung c cung cp t bn ngoi chip c
th l xung t thch anh hoc mt b dao ng RC khc bn ngoi chip, c th l
ngun xung t mt chip khc.
i vi b Timer 0, xung ni internal l xung ly t ngun xung m VDK ang
hot ng bt k xung l xung ca b RC ni hay l xung ngoi ca ngoi vi
khc. Xung ngoi external l ngun xung c a vo bng chn T0CKI trng
vi chn RA4. Xung c a vo chn ny mi c gi l external clock.
B Timer 0 cng c th c lp trnh chn cnh ngt ln hoc ngt xung ca
external clock lm xung m cho timer 0. Chn ngt ln (cnh ngt l cnh ln)
l khi c mt xung chn T0CKI chuyn t mc thp ln mc cao th thanh ghi
TMR0 s m ln 1 n v. Ngc li, chn ngt xung (cnh ngt l cnh xung)
l khi c mt xung chuyn t mc cao xung mc thp thanh ghi TMR0 s m
ln 1 n v.



Timer 0 cho php thc hin ngt (interrupt) khi xy ra trn.

II.1.2. Nguyn l hot ng
B nh thi Timer 0 l b nh thi 8-bit hot ng hai ch l timer v counter. V
bn cht, timer v counter l mt. Nhng s khc nhau y l: chn timer ta s dng
xung ni (internal clock) b timer0 hot ng cn chn counter ta s dng xung ngoi
(external clock). Bit T0CS s quy nh b timer0 s hot ng ch no.
T0CS = 0, timer 0 lm vic ch timer v hot ng vi ngun xung internal
clock v xung ny bng xung m VDK ang dng chia cho 4 ( FOCS/4).
T0CS = 1, timer 0 lm vic ch counter. y, s c thm mt bit T0SE quy
nh vic chn ngt ln hay ngt xung.

Hnh 1. S minh ha cu to ca b Timer 0
Sau khi cu hnh c bit T0CS ta c c ngun xung clock cn thit. Tip theo, ta
s gp mt bit l PSA. PSA quy nh b chia tn prescaler s c s dng cho b timer0
hay WDT. Nu dng b chia tn cho timer0 th ta cho PSA = 0 ( y ta ch quan tm
n b timer0, cn b WDT s c xt n sau). Trong trng hp khng dng b
prescaler, bit PSA = 1 v xung clock ca ta s i trc tip n thanh ghi TRM0 thc
hin m. Ngc li, xung clock ca ta s c a qua b chia tn v to ra mt xung
clock mi. B chia tn ny l b chia tn 8 bit vi 4 gi tr chia tn. Cc gi tr chia tn
c quy nh bi 3 bit l PS0, PS1 v PS2. B chia tn ny c chc nng t xung clock
ban u (internal clock hay external clock) s to ra xung mi c tn s nh hn tc l
chu k di hn. Xung mi s thc hin m thanh ghi TMR0, sau mt chu k ca xung,
TMR0 s nhy ln mt n v.
TMR0 l mt thanh ghi 8 bit cha gi tr m hin ti ca timer0. TMR0 s c ngi
s dng t gi tr ban u (gi s l s p) th p c gi tr trong khong 0x00 n 0xFF.
TMR0 s bt u m t gi tr p ny, c sau mt chu k ca xung clock TMR0 m ln
1 n v cho n khi c s trn xy ra tc l khi gi tr ca TMR0 m n 0xFF, mt c
ngt s c bt ln bit rng thanh ghi ny trn ng thi TMR0 s t ng xa v
0x00. C ngt ny l bit T0IF (Timer0 Interrupt Flag). Bit T0IF ny c set ln mc 1
bi phn cng tc l khi TMR0 trn th c ngt s c t ng set ln bi phn cng,
nhng c ny khng c t ng xa i bi phn cng v vy trong khi lp trnh, trong
code chng ta phi thc hin lnh xa c ngt trnh nhng li khi lp trnh.
II.1.3. Cc thanh ghi lin quan
Cc chc nng ca timer0 s c quy nh bi cc thanh ghi: TMR0, OPTION_REG v
INTCON. Ty theo mc ch m ngi lp trnh s set gi tr ca cc thanh ghi khc
nhau.
II.1.3.1. Thanh ghi TRM0
a ch 01h.
TMR0 l thanh ghi cha gi tr m hin ti ca timer0.
II.1.3.2. Thanh ghi OPTION_REG
a ch 81h.
OPTION_REG : OPTION REGISTER

T0CS (bit 5) : TMR0 Clock Source Select bit
0 = Timer0 lm vic ch timer.
1 = Timer0 lm vic ch counter.
T0SE (bit 4) : TMR0 Source Edge Select bit
0 = chn ngt ln.
1 = chn ngt xung.
PSA (bit 3) : Prescaler Assignment bit
0 = b chia tn c s dng cho b timer0.
1 = b chia tn c s dng cho b WDT.
PS<2:0> (Bit 2-0) : Prescaler Rate Select bits
Cc bit ny quy nh gi tr chia tn cho b chia tn, c th hin bng 1.

Bng 1
II.1.3.3. Thanh ghi INTCON
a ch 0Bh.
INTCON: INTERRUPT CONTROL REGISTER

GIE (bit 7) : Global Interrupt Enable bit
0 = khng cho php thc hin tt c cc lnh ngt.
1 = cho php thc hin tt c cc lnh ngt c hot ng.
T0IE (bit5) : Timer0 Overflow Interrupt Enable bit
0 = khng cho php thc hin ngt i vi timer0.
1 = cho php thc hin ngt i vi timer0.
T0IF (bit 2) : Timer0 Overflow Interrupt Flag bit
0 = xc nhn thanh ghi TMR0 cha b trn.
1 = xc nhn thanh ghi TMR0 b trn.
II.2. Tnh ton trong timer0
Nh cp phn trn, thanh ghi TMR0 s m ln 1 n v sau mi chu k ca xung
clock a vo. Gi s chu k xung clock l T s th c sau T s th TMR0 li m ln 1 n
v, v TMR0 l thanh ghi 8 bit nn mt ti a 255T s th TMR0 s xy ra trn. Vy yu
cu t ra y l vi xung c tn s cho trc, gi tr b chia tn chn trc, ta phi t
gi tr ban u cho TMR0 l bao nhiu sau mt s ln trn timer0 s to ra cho ta mt
khong thi gian mong mun.
C th, khi hot ng ch timer, timer0 s ly ngun xung internal clock hot
ng.
t
c
=
N.4d
F
O5C
(2SS p) (*)
Trong :
FOSC : tn s dao ng ca internal clock.
p : gi tr t ban u ca thanh ghi TMR0.
N : s ln trn ca TMR0.
d : gi tr ca b chia tn.
tc : khong thi mong mun.
V d 1 : Cho tn s dao ng xung thch anh l 4MHz, chn b chia tn l 1:d = 1:4
(d=4), khong thi gian mong mun tc = 1s. Hy tnh gi tr t ban u p cho TMR0 v
s ln trn N thch hp.
T (*) ta c :
t , v p > 0 nn suy ra .
Vy y, . Ta chn x = 0.001s N =
t
c
x
=
1
0.0 0 1
= 1uuu, cui
cng ta tm c .

II.3. Ngt trong timer0
Vy ngt l g?
Ngt (interrupt) l mt s kin gin on trong qu trnh thc hin mt cng vic no .
V d : nh bn ang ngi hc m c chung in thoi reo ln, khi bn phi dng
vic hc li v nghe in thoi, sau khi nghe in thoi xong bn tr li hc bi. Qu
trnh ngt trong timer0 cng tng t nh vy. VDK ang thc hin chng trnh chnh,
khi TMR0 xy ra trn th c ngt pht ln (chung in thoi reo), sau c ngt c
xa (bi ngi lp trnh) VDK tm dng thc hin chng trnh chnh v nhy qua thc
hin chng trnh con phc v ngt, sau khi thc hin ngt xong VDK tr li thc hin
chng trnh chnh cho n khi c ngt li pht ln v VDK thc hin li qu trnh nh
trn.

II.4. Tm tt
s dng b timer0 mt cnh hiu qu v chnh xc, ta cn ch khi lp trnh:
Bc 1: Chn ch :
Vic chn ch trong timer0 c quy nh bi bit T0CS ca thanh ghi
OPTION_REG , (T0CS: 0=timer, 1=counter).
Chn t l chia tn ph hp vi cc bit PS2, PS1 v PS0.
Khi s dng interrupt timer0, cn ch n vic set cc bit GIE v T0IE ca thanh
ghi INTCON.
Bc 2: nh thi v m:
nh thi:
Xa thanh ghi TMR0 v set gi tr ban u ph hp cho TMR0.
Tnh ton chnh xc khong thi gian cn thit vi cc thng s ca phn cng
(tn s ca ngun xung, t l chia tn,).
Bit c ngt T0IF c t ng set ln mc cao khi xy ra trn thanh ghi TMR0.
Ngay lc ny, VDK s thc hin ngt nu c chng trnh con phc v ngt.
m xung:
Xung m c a vo bng chn RA4. Vic chn cch m (m cnh ln hay
m cnh xung) c quy inh bi bit T0SE ca thanh ghi OPTION_REG.
Thanh ghi TMR0 thc hin m xung. B chia tn v ngt hot ng tng t nh
chc nng timer.


III. p dng.

Bi 1. Cho mch nh hnh v. Dng b timer0, vit chng trnh hin th s t 0 n 59
ln 2 leg 7 on. Sau khi m n 59, 2 leg s tr gi tr v 0 v thc hin li chu trnh
nh trn. Khong thi gian mi ln nhy s l 1s.



Bi gii:
Vic tnh ton gi tr ban u cn set cho TMR0 v s ln lp N thc hin v d 1.
V y khong thi gian nhy 1s l tng i v VDK phi mt vi ms thc hin
cc cu lnh trong chng trnh ngt. V vy mun tnh ton tht s chnh xc 1s khng
phi l n gin. Khi nghin cu su hn, ta s thc hin c vic ny. Sau y l phn
code c th cho bi ton.



#include <htc.h>
#define _XTAL_FREQ 4000000
__CONFIG(FOSC_HS & WDTE_OFF & PWRTE_ON & MCLRE_ON & CP_OFF &
BOREN_OFF & IESO_OFF & FCMEN_OFF & LVP_OFF & DEBUG_OFF);
//__CONFIG(BOR4V_BOR21V);
int x,count;
unsigned char num[10] =
{0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90};
void hienthi(int x) //Chuong trinh con hien thi so tu nhien 2
chu so len leg 7-seg
{
unsigned int ch,dv;
ch=x/10;
dv=x-ch*10;
PORTC=num[ch];
PORTD=num[dv];
}
void interrupt ngat_timer0() /*Chuong trinh con phuc vu ngat
*/
{
TMR0IF=0; // xoa co ngat
GIE=0; // cam ngat toan cuc, de phong lai xay ra ngat khi dang
xu ly ngat
TMR0=5; // chon gia tri ban dau cho timer0
count++;
if (count==1000)
{
x++;
count=0;
}
if (x==60)
{
x=0;
count=0;
}
GIE=1;
}
void main()
{
TRISC=0x00;
TRISD=0x00;
count=0;
x=0;
TMR0=5;
GIE=1;
TMR0IE=1;


T0CS=0; // t0cs =0: TRM0 hoat dong o che do timer; =1:TMR0 hoat
dong o che do counter
PSA=0; // psa =0:chon bo chia tan cho timer0; =1 chon bo chia
tan cho WDT
PS2=0; PS1=0; PS0=1;
/* chon ti le chia tan
000 1:2
001 1:4
010 1:8
011 1:16
100 1:32
101 1:64
110 1:128
111 1:256 */
while(1)
{
hienthi(x);
}
}




Bi 2. Cho mch nh hnh v. Dng b timer0 m s ln nhn nt t nt nhn ni vi
chn RA4. S ln nhn hin th ln 2 leg 7 on. Khi s ln m ti a l 99, nu vt
qu kt qu hin th s tr li 00 v tip tc li nh trn.




y, vic nhn nt tng ng vi to mt xung. Nu ta cha nhn nt, mc in p
chn RA4 l 5V, nhng khi nhn nt, p ti chn RA4 l 0V. Vy vic nhn nt s to ra
xung v v l xung a vo chn RA4 nn l external clock, v vy ta s dng b timer
vi chc nng counter.
Phn code cho bi ton.

#include <htc.h>
#define _XTAL_FREQ 4000000
__CONFIG(FOSC_HS & WDTE_OFF & PWRTE_ON & MCLRE_ON & CP_OFF &
BOREN_OFF & IESO_OFF & FCMEN_OFF & LVP_OFF & DEBUG_OFF);
int i;
unsigned char num[10] =
{0xC0,0xF9,0xA4,0xB0,0x99,0x92,0x82,0xF8,0x80,0x90};
void hienthi(int x)
{
unsigned int ch,dv;
ch=x/10;
dv=x%10;
PORTC=num[ch];
PORTD=num[dv];
}


void interrupt ngat_ngoai()
{
T0IF=0; // xoa co ngat
GIE=0; /* cam ngat toan cuc, de phong lai xay ra ngat khi dang
xu ly ngat*/
TMR0=255;
if (i<=98)
{
i++;
hienthi(i);
}
else
{
i=0;
hienthi(i);
}
GIE=1;
}
void main()
{
RA4=1;
TRISC=0x00;
TRISD=0x00;
PORTC=num[0];
PORTD=num[0];
i=0;
TMR0=255;
T0IE=1;
T0CS=1;
GIE=1;
T0SE=0; //Chon ngat len

while(1)
{
}
}




Ti liu tham kho

1. http://www.mikroe.com/chapters/view/5/chapter-4-timers/

2. PIC16F882/883/884/886/887 Data Sheet, Microchip.

3. Ti liu v Timer0 ca cu lc b Pay It Forward trng i hc Bch Khoa thnh ph
H Ch Minh.