ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland

A 1.2 V Bandgap Reference Based on Transimpedance Amplifier

Yueming Jiang and Edward K.F. Lee Dept. of Electrical and Computer Engineering, Iowa State University, Ames, Iowa, USA 50011 Tel.: 515-294-7686 Fax.: 515-294-3780 email: jym@iastate.edu leekfe@iastate.edu
Abstract For practical implementation of a typical bandgap reference, the minimum supply voltage is usually over 1.8 V mainly due to the limited input common mode range of the opamp used in the bandgap reference. In this paper, a low voltage bandgap reference using transimpedance amplifier that does not have this limitation is proposed. Based on this technique, a 1.2 V bandgap reference was implemented in a 1.2 m CMOS process (VTN 0.53 V and VTP 0.91 V) with bipolar option. The variations of the output voltage over temperature (0 o C T 100 oC) were measured to be less than 1 % without resistor trimming. I. Introduction Recently, battery-powered portable devices and systems are of increasing interests. These demands require both analog and digital circuits to be operated at a supply voltage lower than 1.5 V. In addition, advances in CMOS processes also demand the reduction in supply voltage down to the same level due to reliability issues. Since the threshold voltages of the devices in these processes do not reduce at the same rate as the supply voltages, it presents a great challenge in designing analog circuits such as amplifiers, filters, data converters, etc. Another important analog building block is the voltage reference, which is usually required for many analog and mixed signal systems such as data acquisition systems, sensors, and also for some digital systems such as DRAMs. To design a precise voltage reference for low supply voltages, different techniques have been proposed with a main emphasis on reducing the reference output voltage value, which is designed to be equal to or proportional to the material bandgap voltage. These techniques include using a fraction of the voltage across the diodes by resistive subdivision [1] [2] and the use of dynamic threshold MOS transistor (DTMOS), which is based on lowering the material bandgap by electrostatic field [3]. However, as discussed in the literature [1] and in this paper, the supply voltage of most bandgap references are in fact limited by the input common mode range of the opamp, which is required to produce a PTAT voltage or current. In this paper, a technique that does not have this limitation is
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proposed. Based on this technique, a low voltage bandgap reference with all the MOSFETs operated in saturation region was demonstrated. II. Supply Voltage Requirement A typical CMOS implementation of a conventional bandgap reference is shown in Fig. 1. As documented in the literature, the output reference voltage of this bandgap circuit Vref can be written as

Vref = VEB2 +

R 2 kT A 1 ln( ) R1 q A2

(1)

where A1 and A2 are the emitter areas of Q1 and Q2, respectively. The second term in (1) is proportional to the absolute temperature (PTAT), which is used for canceling the negative temperature coefficient of VEB. The output voltage Vref is usually about 1.25 V, and the theoretical minimum supply voltage of this topology is given as min{V DD } = Vref + VSDsat3 (2) Since VSDsat3 is about 0.1 V to 0.3 V, the theoretical min{VDD} is about 1.4 V. A further reduction on this theoretical limit can be achieved if Vref is obtained by resistive subdivision techniques [1] [2]. However, as Vref reduces, min{VDD} will be limited by the input common mode voltage range of the opamp. This is due to the fact that one of the opamp inputs must be connected to one of the bipolar transistors so that a

M4

M3 Vref R2

R1 Q1

Q2

Figure 1: Typical CMOS bandgap reference circuit

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PTAT voltage or current can be produced. If NMOS differential input stage is used in the opamp, the minimum input common mode voltage is equal to VTN + 2VDSsat, which will be higher than VEB for VTN > 0.4 V since VEB can be as low as 0.45 V at very high temperature. As a result, a PMOS differential input stage is usually used and hence, the minimum supply voltage for a practical CMOS bandgap reference can be written as

A and B have the same potential equal to VEB2. Since voltage across R1 is equal to VEB2 VEB1, I1 can be expressed as

I1 =

1 kT A 1 ln( ) R1 q A2

(4)

and the current flow through the two R2s, I2, is equal to (VEB2 Vb)/R2. Since ID3 is equal to ID1, which is equal to I1 + I2, the value of Vref can be written as

min{V DD } = VEB2 + V TP + 2VSDsat

(3)

where the term |VTP| + 2VSDsat is the minimum required voltage for the PMOS differential pair to have proper operation. For most CMOS processes, the threshold voltage of PMOS is about 0.7 V or above. Furthermore, the value of VEB can change above 0.8 V over temperature. Therefore, a practical min{VDD} will be about 1.8 V or above. As a result, it is clear that the input stage of the opamp is the major limiting factor in the design of a low voltage bandgap reference even though the theoretical limit of the bandgap reference can be reduced down below 1 V [1]. Although opamps with rail-to-rail input common mode voltage using complementary differential pairs have been developed, the minimum supply voltage for this type of opamps is equal to VTN + |VTP| + 2VDSsat + 2VSDsat, which will still be over 1.5 V. To achieve a suitable common mode voltage range for the bandgap reference at low supply voltage, multi VT processes [4], CMOS processes with depletion device option [5], bulk driven techniques [6], or using DTMOSTs [3] can be applied. However, the first two techniques require enhancement on a standard CMOS process, which increases the overall cost. Although the last two techniques do not require any enhancements on a standard CMOS process, operating the MOSFETs in these fashions may not be modeled accurately by SPICE. Another possibility is to remove the opamp input common mode voltage constraint as discussed in the following session. III. Proposed Bandgap Reference The main idea of the proposed bandgap reference is to remove the input differential stage of the opamp and use resistors at the inputs to obtain a PTAT current. This current is then added with a current, which is proportional to VEB, to produce the final reference voltage. The proposed technique is based on the use of a transimpedance amplifier (TIA). Fig. 2 shows the simplified schematic diagram of the proposed bandgap reference. The TIA is assumed to have a very large transimpedance gain and a very low input impedance with a fixed potential equal to Vb at both inputs. Similar to the conventional bandgap reference, a PTAT voltage across R1 will be produced by applying feedback, which makes nodes

Vref = R 3 [

V V 1 kT A 1 ln( ) + EB2 b ] R1 q A2 R2 R2

(5) if I3 is neglected. Equation (5) is very similar to the output voltage of the conventional bandgap reference shown in (1) except for the Vb term and the scaling factor R3/R2. If the Vb term is neglected, Vref is in first order independent of temperature by selecting an appropriate ratio between R1 and R2. Furthermore, the value of Vref can be freely changed from the conventional value of 1.25 V (within ground and VDD VSDsat3) by choosing different values of R1, R2 and R3. This result is very similar to the result based on the resistive division techniques [1] [2]. To eliminate the Vb term in (5), I3 is introduced as shown in Fig. 2. Node C is a low impedance node. The impedance is approximately equal to 1/gm4gm6rds8 and the voltage at this node is equal to Vbn VTN6. If Vb is equal to this voltage, then the current flow through R4 and hence, the value of I3 will be equal to Vb/R2. After adding the value of I3, the Vb term in (5) will be cancelled out. To ensure Vb equal to Vbn VTN6, the input stage of the TIA can be realized based on the same structure as the one that produces I3. Fig. 3 shows the design of the TIA. The difference in input currents are first converted into voltages at nodes X and Y. Two intermediate gain stages are then followed to ensure that the overall transimpedance gain is sufficiently large. The output stage is a common source amplifier with resistor load. Using this type of loads, the minimum output voltage can swing close to ground in order to produce a low enough voltage for driving the PMOSs (M1, M2 and M3 in Fig. 2). Compensation capacitors C1 and C2 are added to ensure the stability of the circuit after feedback is applied. The minimum supply voltage of the bandgap reference can be found to be equal to max{VSDsat2 + max{VEB2}, |VTP| + VDSsat + VSDsat}. The first term is the theoretical limit of the proposed bandgap reference, and the second term is the minimum supply voltage of the TIA. Similar to conventional Bandgap references, input offset current and offset voltage of the TIA will affect the accuracy of Vref and lead to a higher temperature coefficient. To minimize this effect, good matching between the NMOS cascode

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R2

M1 I2 A

M2

M3 Vref

M9 Vbp1 M8

B R2 R1 I1 Q1 Q2 R3

I3

Vbn M7 M5

M6 C M4 R4=R2

Figure 2: Proposed bandgap reference

Vbp1 Vbp2 Vbn Vb In+ X Y

Vbp1 Vbn Vbp2 C1 C2 Vout

Vbn

In

Intermediate gain stage Intermediate gain stage Figure 3: Transimpedance amplifier design
transistors that are connected to node C in Fig. 2 and the inputs of the TIA is required. By doing this, it will reduce the voltage difference between these nodes and hence, the effects of offset voltage. Besides, input offset current of the TIA can also be minimized by having good matching on the current mirrors and the current sources of the TIA input stage. In addition, good matching between M4 and M5 as well as M8 and M9 in Fig. 2 will produce a better cancellation of the Vb term in (5) due to the reduction of offset current produced from this block. IV. Implementation and Experimental Results The proposed bandgap reference was implemented in a 1.2 m CMOS process with VTN 0.53 V and VTP 0.91 V. Although substrate PNP transistors could be used in the proposed circuit, NPN transistors that were also available in this process were chosen for implementation due to the availability of SPICE model. All the resistors were implemented using poly. Since the threshold voltage of the PMOS was relatively high, a supply voltage of 1.2 V was chosen. For a CMOS process with |VTP| < 0.7 V, the minimum supply voltage can be lower than 1 V with a value approximately equal to the theoretical limit of the proposed bandgap reference. The reference output voltage Vref was selected to be about 1 V by choosing the appropriate resistor values. The die photo of the proposed bandgap reference is shown in Fig. 4. The active area is about 1 mm2 without layout optimization. As shown in Fig. 5, the untrimmed accuracy with a 1.2 V supply was measured to be within 1 % for a temperature range between 0 oC and 100 oC. If R1 can be trimmed, the variations on the reference output for the same range of temperatures will be less than 0.3 % as indicated

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from SPICE simulations. The Vref-to-noise ratio over the frequency band from 20 Hz to 20 kHz was measured to be 67 dB. The PSRR and the power dissipation were measured to be approximately 20 dB at 1 kHz and 0.6 mW, respectively. V. Conclusion In this paper, the limitations on the minimum supply voltage of bandgap references are discussed. For most bandgap references, the minimum supply voltage is limited by the input common mode range of the opamp. To obtain a low voltage bandgap reference in a conventional CMOS process with all the MOSFETs operated in saturation region, a bandgap reference based on transimpedance amplifier is proposed. In this case, the constraint due to opamp input common mode voltage is removed. Based on this technique, a 1.2 V bandgap reference is demonstrated in a 1.2 m CMOS process with VTN 0.53 V and VTP 0.91 V. An untrimmed accuracy of 1 % over a temperature range from 0 oC to 100 o C can be achieved. The minimum supply voltage is mainly limited by the relatively high value of |VTP|. For more advanced CMOS processes with |VT| < 0.7 V, a bandgap reference with a supply voltage reaching the theoretical limit of VEB + VDSsat (< 1 V) can be obtained. An accuracy of 0.3 % within 0 oC to 100 oC can be achieved after resistor trimming. Reference [1] H. Neuteboom, B. M. J. Kup, M. Janssens, A DSP-based hearing instrument IC, IEEE J. Solid-State Circuits, vol. 32, pp.1791-1793., Nov. 1997. [2] H. Banda, H. Shiga, A. Umezawa, T. Miyaba, T. Tanzawa, S. Atsumi, K. Sakui, A CMOS Bandgap References with Sub-1-V Operation, IEEE J. Solid-State Circuits, vol. 34, pp.670673, May 1999.

[3] Anne-Johan Annema, Low Power Bandgap References Featuring DTMOSTs, IEEE J. Solid-State Circuits, vol. 34, pp.949-955, Jul. 1999. [4] Y. Matsuya and J. Yamada, 1 V Power Supply, 384 kS/s 10b A/D and D/A Converters with Swing-Suppression Noise Shaping, 1994 IEEE ISSCC Dig. of Tech. Papers, pp. 192 193, Feb. 1994. [5] R. Griffith, R. Vyne, R. Dotson and T. Petty, A 1-V BiCMOS Rail-to-Rail Amplifier with nChannel Depletion Mode Input Stage, IEEE J. Solid-State Circuits, vol. 32, pp. 2012-2022, 1997. [6] B. Blalock, P. Allen and G. Rincon-Mora, Designing 1-V Op Amps Using Standard Digital CMOS Technology, IEEE Trans. on Circuits & Systems II: Analog and Digital Signal Processing, vol. 45, pp.769-780, 1998.

Figure 4: Die photo

1.06 1.05 Vref (V) 1.04 1.03 1.02 1.01 0 20 40 60 T (oC) 80 100

Figure 5: Measured Vref characteristics without trimming over temperature

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