VALLIAMMAI ENGINEERING COLLEGE

SRM NAGAR, KATTANKULATHUR

DEPARTMENT OF ELECTRICAL & ELECTRONICS ENGINEERING

LAB MANUAL
NAME : REGISTER NUMBER : CLASS : SEMESTER : IV SEM SUBJECT CODE : EE 2258 SUBJECT : LINEAR AND DIGITAL INTEGRATED CIRCUITS LAB

SYLLABUS
EE 2258 LINEAR AND DIGITAL INTEGRATED CIRCUITS LABORATORY AIM: To study various digital & linear integrated circuits used in simple system configuration. LIST OF !" #IM $TS: 1. Study of %asic &igital I'(s. )erification of trut* ta+le for A$&, O#, !O#, $OT, $O#, $A$&, -. FF, #S FF, & FF/ 0. Implementation of %oolean Functions, Adder1 Su+tractor circuits. 2.a/. 'ode converters, "arity generator and parity c*ec3ing, 4cess 2, 0s 'omplement, %inary to gray code using suita+le I'(s . +/ ncoders and &ecoders: &ecimal and Implementation of 56+it s*ift registers in SISO,SI"O,"ISO,"I"O modes using suita+le I'(s.

5. 'ounters: &esign and implementation of 56+it modulo counters as sync*ronous and async*ronous types using FF I'(s and specific counter I'. 7. S*ift #egisters: &esign and implementation of 56+it s*ift registers in SISO, SI"O,"ISO, "I"O modes using suita+le I'(s. 8. Multiple41 &e6multiple4 : Study of 5:19 ::1 multiple4er and Study of 1:59 1:: demultiple4er ;. Timer I' application. Study of $ 1S 777 timer in Asta+le, Monosta+le operation. :. Application of Op6Amp6I Sle< rate verifications, inverting and non6inverting amplifier, Adder, comparator,Integrator and &ifferentiator. =. Study of Analog to &igital 'onverter and &igital to Analog 'onverter: )erification of A1& conversion using dedicated I'(s. 1>. Study of )'O and "LL I's i. )oltage to fre?uency c*aracteristics of $ 1 S 788 I'. ii. Fre?uency multiplication using $ 1S 787 "LL I'. " @ 57 Total @ 57 0

LIST OF EXPERIMENTAL SETUP I CYCLE: 1. Study of Logic Aates 0. &esign an implementation of adder1su+tractor 2. a/Four +it parity generator +/ 'ode converter 5. ncoders & &ecoders

7. &esign and implementation of Multiple4er and &e6Multiple4er

II CYCLE: 8. &esign and implementation of 56+it S*ift #egisters ;. &esign and implementation of Sync*ronous and Async*ronous 'ounter :. Study and verification of A1& converter and &1A converter =. &esign and implementation of Asta+le and Monosta+le 1>. Inverting and $on6Inverting amplifier, Adder, 'omparator, Integrator and &ifferentiator. 11. Study of )'O and "LL I's a/ )oltage to fre?uency c*aracteristics of $ 1 S 788 I'. +/ Fre?uency multiplication using $ 1S 787 "LL I'. 10. &esign And Test t*e &c "o<er Supply Bsing Lm 21; and Lm ;02.

CONTENTS
Sl.No Dat Na! o" t# E$% &'! (t Pa) No. Ma&*+ A,a&- - ./01

Average Mar3s

4. $o: 5

&ate: STUDY OF BASIC DIGITAL ICS AIM: To verify t*e trut* ta+le of +asic digital I's of A$&, O#, $OT, $A$&, $O#, !6O# gates. APPARATUS RE2UIRED: S.$o 1. 0. 2. 5. 7. 8. ;. :. $ame of t*e Apparatus &igital I' trainer 3it A$& gate O# gate $OT gate $A$& gate $O# gate !6O# gate 'onnecting <ires I' ;5>: I' ;520 I' ;5>5 I' ;5>> I' ;5>0 I' ;5:8 As re?uired #ange Cuantity 1 1 1 1 1 1 1

T3EORY: a. A$& gate: An A$& gate is t*e p*ysical realiDation of logical multiplication operation. It is an electronic circuit <*ic* generates an output signal of E1( only if all t*e input signals are E1(. +. O# gate: An O# gate is t*e p*ysical realiDation of t*e logical addition operation. It is an electronic circuit <*ic* generates an output signal of E1( if any of t*e input signal is E1(. c. $OT gate: A $OT gate is t*e p*ysical realiDation of t*e complementation operation. It is an electronic circuit <*ic* generates an output signal <*ic* is t*e reverse of t*e input signal. A $OT gate is also 3no<n as an inverter +ecause it inverts t*e input.

d. $A$& gate: 7

A $A$& gate is a complemented A$& gate. T*e output of t*e $A$& gate <ill +e E>( if all t*e input signals are E1( and <ill +e E1( if any one of t*e input signal is E>(. e. $O# gate: A $O# gate is a complemented O# gate. T*e output of t*e O# gate <ill +e E1( if all t*e inputs are E>( and <ill +e E>( if any one of t*e input signal is E1(. f. !6O# gate: An 46O# gate performs t*e follo<ing %oolean function, A % @ F A . %( / G F A( . % /

It is similar to O# gate +ut e4cludes t*e com+ination of +ot* A and % +eing e?ual to one. T*e e4clusive O# is a function t*at give an output signal E>( <*en t*e t<o input signals are e?ual eit*er E>( or E1(. PROCEDURE: 1. 'onnections are given as per t*e circuit diagram 1. For all t*e I's ;t* pin is grounded and 15t* pin is given G7 ) supply. 0. Apply t*e inputs and verify t*e trut* ta+le for all gates. A$& AAT LOAI' &IAA#AM:

"I$ &IAA#AM OF I' ;5>::

'I#'BIT &IAA#AM:

T#BTH TA%L : S.$o 1. 0. 2. 5. I$"BT A > > 1 1 % > 1 > 1 OBT"BT I@A.% > > > 1 O# AAT LOAI' &IAA#AM:

"I$ &IAA#AM OF I' ;520 :

'I#'BIT &IAA#AM: ;

T#BTH TA%L : I$"BT A > > 1 1 % > 1 > 1 OBT"BT I@AG% > 1 1 1 $OT AAT LOAI' &IAA#AM:

S.$o 1. 0. 2. 5.

"I$ &IAA#AM OF I' ;5>5 :

'I#'BIT &IAA#AM: :

T#BTH TA%L : S.$o 1. 0. I$"BT A > 1 OBT"BT I @ A( 1 >

$A$& AAT LOAI' &IAA#AM:

"I$ &IAA#AM OF I' ;5>> :

'I#'BIT &IA#AM:

T#BTH TA%L : I$"BT A > > 1 1 % > 1 > 1 OBT"BT I @ FA. %/( 1 1 1 > $O# AAT

S.$o 1. 0. 2. 5. LOAI' &IAA#AM:

"I$ &IAA#AM OF I' ;5>0 :

1>

'I#'BIT &IAA#AM:

T#BTH TA%L : I$"BT A > > 1 1 % > 1 > 1 OBT"BT I @ FA G %/( 1 > > > !6O# AAT LOAI' &IAA#AM

S.$o 1. 0. 2. 5.

"I$ &IAA#AM OF I' ;5:8:

'I#'BIT &IAA#AM: 11

T#BTH TA%L : S.$o 1. 0. 2. 5. I$"BT A > > 1 1 % > 1 > 1 OBT"BT I@A % > 1 1 >

DISCUSSION 2UESTIONS: 1. J*at is Integrated 'ircuitK 0. J*at is a Logic gateK 2. J*at are t*e +asic digital logic gatesK 5. J*at are t*e gates called universal gatesK 7. J*y $A$& and $O# gates are called universal gatesK 8. J*at are t*e properties of !6$O# gateK

# SBLT: T*e trut* ta+les of all t*e +asic digital I's <ere verified. 4. $o: 10

&ate: DESIGN AND IMPLEMENTATION OF ADDER4SUBTRACTOR AIM: To design and construct *alf adder, full adder, *alf su+tractor and full su+tractor circuits and verify t*e trut* ta+le using logic gates. APPARATUS RE2UIRED: S. No 1. 0. 2. I' &igital I' Trainer .it "atc* c*ords Na! S% 5'"'5at'o( ;520, ;5>:, ;5:8, ;5:2 26a(t't7 1 1 6

T3EORY: T*e most +asic arit*metic operation is t*e addition of t<o +inary digits. T*ere are four possi+le elementary operations, namely, >G>@> >G1@1 1G>@1 1 G 1 @ 1>0 T*e first t*ree operations produce a sum of <*ose lengt* is one digit, +ut <*en t*e last operation is performed t*e sum is t<o digits. T*e *ig*er significant +it of t*is result is called a carry and lo<er significant +it is called t*e sum. HALF A&& #: A com+inational circuit <*ic* performs t*e addition of t<o +its is called *alf adder. T*e input varia+les designate t*e augend and t*e addend +it, <*ereas t*e output varia+les produce t*e sum and carry +its. FBLL A&& #: A com+inational circuit <*ic* performs t*e arit*metic sum of t*ree input +its is called full adder. T*e t*ree input +its include t<o significant +its and a previous carry +it. A full adder circuit can +e implemented <it* t<o *alf adders and one O# gate.

HALF A&& # 12

T#BTH TA%L : S.$o 1. 0. 2. 5. & SIA$: From t*e trut* ta+le t*e e4pression for sum and carry +its of t*e output can +e o+tained as, Sum, S @ A % 9 'arry, ' @ A . % CIRCUIT DIAGRAM: I$"BT A > > 1 1 % > 1 > 1 S > 1 1 > OBT"BT ' > > > 1

FBLL A&& # T#BTH TA%L : S.$o 1. 0. 2. 5. 7. 8. ;. :. & SIA$: 15 I$"BT % > > 1 1 > > 1 1 OBT"BT SBM 'A##I > > 1 > 1 > > 1 1 > > 1 > 1 1 1

A > > > > 1 1 1 1

' > 1 > 1 > 1 > 1

From t*e trut* ta+le t*e e4pression for sum and carry +its of t*e output can +e o+tained as,SBM @ A(%(' G A(%'( G A%('( G A%'9'A##I @ A(%' G A%(' G A%'( GA%' Bsing .arnaug* maps t*e reduced e4pression for t*e output +its can +e o+tained as, SBM

SBM @ A(%(' G A(%'( G A%('( G A%' @ A 'A##I

'

'A##I @ A% G A' G %' CIRCUIT DIAGRAM:

HALF SB%T#A'TO#: 17

A com+inational circuit <*ic* performs t*e su+traction of t<o +its is called *alf su+tractor. T*e input varia+les designate t*e minuend and t*e su+tra*end +it, <*ereas t*e output varia+les produce t*e difference and +orro< +its. FBLL SB%T#A'TO#: A com+inational circuit <*ic* performs t*e su+traction of t*ree input +its is called full su+tractor. T*e t*ree input +its include t<o significant +its and a previous +orro< +it. A full su+tractor circuit can +e implemented <it* t<o *alf su+tractors and one O# gate. HALF SB%T#A'TO# T#BTH TA%L : S.$o 1. 0. 2. 5. & SIA$: From t*e trut* ta+le t*e e4pression for difference and +orro< +its of t*e output can +e o+tained as, &ifference, &IFF @ A %9 %orro<, %O## @ A( . % CIRCUIT DIAGRAM: I$"BT A > > 1 1 % > 1 > 1 OBT"BT &IFF %O## > > 1 1 1 > > >

FBLL SB%T#A'TO# 18

T#BTH TA%L : S.$o 1. 0. 2. 5. 7. 8. ;. :. & SIA$: From t*e trut* ta+le t*e e4pression for difference and +orro< +its of t*e output can +e o+tained as, &ifference, &IFF@ A(%(' G A(%'( G A%('( G A%' %orro<, %O## @ A(%' G A%(' G A%'( GA%' Bsing .arnaug* maps t*e reduced e4pression for t*e output +its can +e o+tained as, &IFF # $' I$"BT % > > 1 1 > > 1 1 OBT"BT &IFF %O## > > 1 1 1 1 > 1 1 > > > > > 1 1

A > > > > 1 1 1 1

' > 1 > 1 > 1 > 1

&IFF @ A(%(' G A(%'( G A%('( G A%' @ A %O##OJ

'

%O## @ A(% G A(' G %' CIRCUIT DIAGRAM: 1;

PROCEDURE: T*e connections are given as per t*e circuit diagram. T<o 5 L +it num+ers added or su+tracted depend upon t*e control input and t*e output is o+tained. Apply t*e inputs and verify t*e trut* ta+le for t*e*alf adder or s su+tractor and full adder or su+tractor circuits. DISCUSSION 2UESTIONS: 1. 0. 2. 5. 7. J*at is com+inational circuitK J*at is different +et<een com+inational and se?uential circuitK J*at are t*e gates involved for +inary adderK List t*e properties of 46$or gateK J*at is e4pression for sum and carryK

RESULT: T*us t*e *alf adder, full adder, *alf su+tractor and full su+tractor circuits <ere designed and t*eir trut* ta+le <ere verified.

1:

4. $o: &ate: PARITY GENERATOR 8 C3EC9ER AIM: To design and verify t*e trut* ta+le of a t*ree +it Odd "arity generator and c*ec3er & ven "arity Aenerator And '*ec3er. APPARATUS RE2UIRED: S.$o 1. 0. 2. 5. $ame of t*e Apparatus &igital I' trainer 3it !6O# gate $OT gate 'onnecting <ires #ange I' ;5:8 I' ;5>5 As re?uired Cuantity 1

T3EORY: A parity +it is used for t*e purpose of detecting errors during transmission of +inary information. A parity +it is an e4tra +it included <it* a +inary message to ma3e t*e num+er of 1(s eit*er odd or even. T*e message including t*e parity +it is transmitted and t*en c*ec3ed at t*e receiving end for errors. An error is detected if t*e c*ec3ed parity does not correspond <it* t*e one transmitted. T*e circuit t*at generates t*e parity +it in t*e transmitter is called a parity generator and t*e circuit t*at c*ec3s t*e parity in t*e receiver is called a parity c*ec3er. In even parity t*e added parity +it <ill ma3e t*e total num+er of 1(s an even amount and in odd parity t*e added parity +it <ill ma3e t*e total num+er of 1(s an odd amount. In a t*ree +it odd parity generator t*e t*ree +its in t*e message toget*er <it* t*e parity +it are transmitted to t*eir destination, <*ere t*ey are applied to t*e parity c*ec3er circuit. T*e parity c*ec3er circuit c*ec3s for possi+le errors in t*e transmission. Since t*e information <as transmitted <it* odd parity t*e four +its received must *ave an odd num+er of 1(s. An error occurs during t*e transmission if t*e four +its received *ave an even num+er of 1(s, indicating t*at one +it *as c*anged during transmission. T*e output of t*e parity c*ec3er is denoted +y " ' Fparity error c*ec3/ and it <ill +e e?ual to 1 if an error occurs, i.e., if t*e four +its received *as an even num+er of 1(s.

1=

"A#ITI A $ #ATO# T#BTH TA%L : I$"BT F T*ree +it message/ A > > > > 1 1 1 1 % > > 1 1 > > 1 1 ' > 1 > 1 > 1 > 1 OBT"BT F Odd "arity +it/ " 1 > > 1 > 1 1 > OBT"BT F ven "arity +it/ " > 1 1 > 1 > > 1

S.$o 1. 0. 2. 5. 7. 8. ;. :.

From t*e trut* ta+le t*e e4pression for t*e output parity +it is,"F A, %, '/ @ M F>, 2, 7, 8/ Also <ritten as, " @ A(%('( G A(%' G A%(' G A%'( @ FA % '/ E CIRCUIT DIAGRAM: O&& "A#ITI A $ #ATO#

CIRCUIT DIAGRAM: ) $ "A#ITI A $ #ATO#

0>

"A#ITI 'H '. #

PROCEDURE: 1. 'onnections are given as per t*e circuit diagrams. 0. For all t*e I's ;t* pin is grounded and 15t* pin is given G7 ) supply. 2. Apply t*e inputs and verify t*e trut* ta+le for t*e "arity generator and c*ec3er. DISCUSSION 2UESTIONS: 1. 0. 2. 5. 7. J*at is parity +itK J*y parity +it is added to messageK J*at is parity c*ec3erK J*at is odd parity and even parityK J*at are t*e gates involved for parity generatorK

RESULT: T*e design of t*e t*ree +it odd "arity generator and c*ec3er& ven "arity Aenerator and '*ec3er circuits <as done and t*eir trut* ta+les <ere verified. 01

4. $o: &ate:

CODE CONVERTER
AIM: To construct and verify t*e performance of +inary to gray and gray to +inary. APPARATUS RE2UIRED:

S. No 1. 0. 2. I'

Na!

S% 5'"'5at'o( ;5>5, ;5:8

26a(t't7 1 1 6

&igital I' Trainer .it "atc* c*ords

T3EORY: %I$A#I TO A#AI: T*e MS% of t*e +inary code alone remains unc*anged in t*e Aray code. T*e remaining +its in t*e gray are o+tained +y !6O# ing t*e corresponding gray code +it and previous +it in t*e +inary code. T*e gray code is often used in digital systems +ecause it *as t*e advantage t*at only one +it in t*e numerical representation c*anges +et<een successive num+ers. A#AI TO %I$A#I: T*e MS% of t*e Aray code remains unc*anged in t*e +inary code t*e remaining +its are o+tained +y ! L O# ing t*e corresponding gray code +it and t*e previous output +inary +it. PROCEDURE: 'onnections are given as per t*e logic diagram. T*e given trut* ta+les are verified.

00

%I$A#I TO A#AI:

A#AI TO %I$A#I

02

TRUT3 TABLE &ecimal > 1 0 2 5 7 8 ; : = 1> 11 10 12 15 17 D > > > > > > > > 1 1 1 1 1 1 1 1 %inary code ' % A > > > > > 1 > 1 > > 1 1 1 > > 1 > 1 1 1 > 1 1 1 > > > > > 1 > 1 > > 1 1 1 > > 1 > 1 1 1 > 1 1 1 Aray code A0 A1 > > > > > 1 > 1 1 1 1 1 1 > 1 > 1 > 1 > 1 1 1 1 > 1 > 1 > > > >

A2 > > > > > > > > 1 1 1 1 1 1 1 1

AO > 1 1 > > 1 1 > > 1 1 > > 1 1 >

DISCUSSION 2UESTIONS: 1. 0. 2. 5. 7. List t*e procedures to convert gray code into +inaryK J*y <eig*ted code is called as reflective codesK J*at is a se?uential codeK J*at is error deducting codeK J*at is AS'II codeK

RESULT: T*e design of t*e t*ree +it %inary to Aray code converter & Aray to %inary code converter circuits <as done and its trut* ta+le <as verified. 05

4. $o: &ate:

/1 ENCODER
AIM: To design and implement encoder using I' ;515: F:62 encoder/ APPARATUS RE2UIRED: S. No 1. 0. 2. I' &igital I' Trainer .it "atc* c*ords Na! S% 5'"'5at'o( ;515: 26a(t't7 1 1 6

T3EORY: An encoder is digital circuit t*at *as 0n input lines and n output lines. T*e output lines generate a +inary code corresponding to t*e input values : L 2 encoder circuit *as : inputs, one for eac* of t*e octal digits and t*ree outputs t*at generate t*e corresponding +inary num+er. na+le inputs
1

s*ould +e connected to ground and

s*ould +e connected to )''

PROCEDURE: 'onnections are given as per t*e logic diagram. T*e trut* ta+le is verified +y varying t*e inputs.

PIN DIAGRAM
/ 2N I N P 2 U 2
N N

/ T
: /

2 N

N O

07

TRUTH TABLE
1

> > > > > > > > 1

A> > 1 1 1 1 1 1 1 1

A1 1 > 1 1 1 1 1 1 1

A0 1 1 > 1 1 1 1 1 1

I$"BTS A2 A5 1 1 1 1 1 1 > 1 1 > 1 1 1 1 1 1 1 1

A7 1 1 1 1 1 > 1 1 1

A8 1 1 1 1 1 1 > 1 1

A; 1 1 1 1 1 1 1 > 1

OBT"BTS &0 &1 > > > > > 1 > 1 1 > 1 > 1 1 1 1 1 1

&> > 1 > 1 > 1 > 1 1

2) DECODER
AIM: To design and implement decoder using I' ;5177 F26: decoder/. APPARATUS RE2UIRED:

S. No 1. 0. 2.

Na! I' &igital I' Trainer .it "atc* c*ords

S% 5'"'5at'o( ;5177

26a(t't7 1 1 6

08

T3EORY: A decoder is a com+inational circuit t*at converts +inary information from n input lines to 0n uni?ue output lines. In 26: line decoder t*e t*ree inputs are decoded into rig*t outputs in <*ic* eac* output representing one of t*e minterm of 2 input varia+les. I' ;5177 can +e connected as a dual 0N5 decoder or a single 2N: decoder desired input in '1 and '0 must +e connected toget*er and used as t*e ' input. A1 and A0 s*ould +e connected and used as t*e A Fena+le/ input. A is t*e ena+le input and must +e e?ual to > for proper operation. PROCEDURE: 'onnections are given as per t*e logic diagram. T*e trut* ta+le is verified +y varying t*e inputs. CIRCUIT DIAGRAM:
/ N I N P2 U N T /

2 2N 2N

N O
: /

0;

TRUT3 TABLE I$"BTS ' % ! ! > > > > > 1 > 1 1 > 1 > 1 1 1 1 OBT"BTS 0I2 1I> 1 1 1 1 1 1 1 1 > 1 1 > 1 1 1 1 1 1

A 1 > > > > > > > >

A ! > 1 > 1 > 1 > 1

0I> 1 > 1 1 1 1 1 1 1

0I1 1 1 > 1 1 1 1 1 1

0I0 1 1 1 > 1 1 1 1 1

1I1 1 1 1 1 1 1 > 1 1

1I0 1 1 1 1 1 1 1 > 1

1I2 1 1 1 1 1 1 1 1 >

DISCUSSION 2UESTIONS: 1. 0. 2. 5. 7. 8. ;. :. =. Ho< t*e output line <ill +e activated in decoder circuitK J*at are t*e necessary steps for implementing *ig*er order decodersK J*at is t*e use of code convertersK Ho< to convert %'& to &ecimal decoderK J*at is seven segment displaysK J*at is t*e ot*er name of encoderK J*at is encodingK J*at are t*e applications of encoderK J*at is %'& encoderK

RESULT: T*us t*e encoder and decoder circuits <ere designed and implemented.

0:

4. $o: &ate: MULTIPLEXER 8 DEMULTIPLEXER AIM: To design and verify t*e trut* ta+le of a 5!1 Multiple4er & 1!5 &emultiple4er. APPARATUS RE2UIRED: S.$o 1. 0. 2. 5. 7. $ame of t*e Apparatus &igital I' trainer 3it O# gate $OT gate A$& gate F t*ree input / 'onnecting <ires #ange I' ;520 I' ;5>5 I' ;511 As re?uired Cuantity 1

T3EORY: Multiple4er is a digital s<itc* <*ic* allo<s digital information from several sources to +e routed onto a single output line. T*e +asic multiple4er *as several data input lines and a single output line. T*e selection of a particular input line is controlled +y a set of selection lines. $ormally, t*ere are 0n input lines and n selector lines <*ose +it com+inations determine <*ic* input is selected. T*erefore, multiple4er is Emany into one( and it provides t*e digital e?uivalent of an analog selector s<itc*. A &emultiple4er is a circuit t*at receives information on a single line and transmits t*is information on one of 0n possi+le output lines. T*e selection of specific output line is controlled +y t*e values of n selection lines. & SIA$: 5 ! 1 MBLTI"L ! # LOAI' SIM%OL:

0=

T#BTH TA%L : S.$o 1. 0. 2. 5. S L 'TIO$ I$"BT S1 S0 > > > 1 1 > 1 1 OBT"BT I I> I1 I0 I2

"I$ &IAA#AM OF I' ;511:

'I#'BIT &IAA#AM:

2>

1!5 & MBLTI"L ! # LOAI' SIM%OL:

T#BTH TA%L :

S.$o S1 1. 0. 2. 5. 7. 8. ;. :. > > > > 1 1 1 1

I$"BT S0 > > 1 1 > > 1 1 &in > 1 > 1 > 1 > 1 I> > 1 > > > > > >

OBT"BT I1 > > > 1 > > > > I0 > > > > > 1 > > I2 > > > > > > > 1

21

CIRCUIT DIAGRAM:

PROCEDURE: 1. 'onnections are given as per t*e circuit diagrams. 0. For all t*e I's ;t* pin is grounded and 15t* pin is given G7 ) supply. 2. Apply t*e inputs and verify t*e trut* ta+le for t*e multiple4er & demultiple4er. DISCUSSION 2UESTIONS: 1. 0. 2. 5. 7. 8. ;. :. J*at is t*e ot*er name of de6multiple4erK 'ompare MB! and & 6MB!K Ho< many select lines needed for four outputs of & 6MB!K J*at is ot*er name of multiple4erK J*at is serial to parallel converterK J*at is t*e use of select linesK Ho< to ena+le t*e multiple4erK J*at are t*e applications of multiple4erK

RESULT: T*e design of t*e 541 Multiple4er and 145 &emultiple4er circuits <as done and t*eir trut* ta+les <ere verified. 20

4. $o: &ate: S3IFT REGISTERS AIM: To implement t*e follo<ing s*ift register using flip flop Fi/ Fii/ Fiii/ Fiv/ SI"O SISO "ISO "I"O

APPARATUS RE2UIRED: S. No 1. 0. I' &igital I' Trainer .it Na! S% 5'"'5at'o( ;5;5 26a(t't7 1 1 6

2. "atc* c*ords T3EORY:

A register is used to move digital data. A s*ift register is a memory in <*ic* information is s*ifted from one position in to anot*er position at a line <*en one cloc3 pulse is applied. T*e data can +e s*ifted eit*er left or rig*t direction to<ards rig*t or to<ards left. A s*ift register can +e used in four <ays depending upon t*e input in <*ic* t*e data are entered in to and ta3es out of it. T*e four configuration are given as Serial input L Serial output "arallel input L Serial output Serial input L "arallel output "arallel input L "arallel output #S or -. flip flop are used to construct s*ift register *ave & flip flop is used for constructing s*ift register. PROCEDURE: Aive t*e connections as per t*e circuit Set or #eset at t*e pin 0 <*ic* it(s t*e MS% of serial data. Apply a single cloc3 Set or #eset second digital input at pin 0. #epeat step 0 until all 56+it data are ta3en a<ay. 22

S3IFT REGISTER:
>
=5 V C
C

L2

R D

9 P

2R

/ <

/ ?

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<
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L/ R

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I P LO E

I F

=5 V C 2 / 0 A / 2 I C / ? ; < ; < / / / 5
2

2 < 2

2 A / 0 / 2

< 5 2

I N

I C

;
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<

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I C
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<
/ /

<

I C
/

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=5 V C

I P RO I G

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25

S
D
O U

I S
T

= 5 CV

/ A I C /

0 / 2 ; < ; ? / / < 5

<

/ 0

/ 2

< 5 2

I N

I C
/

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<

I C
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= 5 CV

PIPO
22 2/ 20

22

SISO &ata input @ 11>> 'loc3 > 5 : 10 18 Serial input > 1 1 > > Serial output > 1 1 > >

27

PIPO 'loc3 > 1 A > 1 "arallel input % > 1 ' > > & > 1 CA > 1 "arallel output C% > 1 C' > > C& > 1

SIPO L "t +#'"t $o of cl3 pulse > 1 0 2 5 7 8 ; : Serial input &in > 1 1 > 1 > > > > "arallel output C2 C0 C1 > > > > > > > > 1 > 1 1 1 1 > 1 > 1 > 1 > 1 > > > > >

C> > 1 1 > 1 > > > >

R')#t S#'"t $o of cloc3 pulse > 1 0 2 5 7 8 ; : 28 Serial input &in > 1 1 > 1 > > > > "arallel output C2 C0 C1 C> > > > > 1 > > > > 1 > > 1 > 1 > 1 1 > 1 > 1 1 > > > 1 1 > > > 1 > 0 > >

DISCUSSION 2UESTIONS: 1. 0. 2. 5. 7. 8. ;. J*at is registerK J*at are t*e modes of s*ift registerK Ho< ring counter is implemented using s*ift registersK 'ompare parallel and serial su+ registersK &efine se?uence generatorK J*at are t*e types of s*ift registerK &efine s*ift registers.

RESULT: T*us t*e SISO, SI"O, "ISO, "I"O s*ift registers <ere designed and implemented. 2;

4. $o: &ate: ASYNC3RONOUS COUNTER AIM: To implement and verify t*e trut* ta+le of an async*ronous decade counter. APPARATUS RE2UIRED: S.$o 1. 0. 5. 7. $ame of t*e Apparatus &igital I' trainer 3it -. Flip Flop $A$& gate 'onnecting <ires #ange I' ;5;2 I' ;5>> Cuantity 1 0 1 As re?uired

T3EORY: Async*ronous decade counter is also called as ripple counter. In a ripple counter t*e flip flop output transition serves as a source for triggering ot*er flip flops. In ot*er <ords t*e cloc3 pulse inputs of all t*e flip flops are triggered not +y t*e incoming pulses +ut rat*er +y t*e transition t*at occurs in ot*er flip flops. T*e term async*ronous refers to t*e events t*at do not occur at t*e same time. Jit* respect to t*e counter operation, async*ronous means t*at t*e flip flop <it*in t*e counter are not made to c*ange states at e4actly t*e same time, t*ey do not +ecause t*e cloc3 pulses are not connected directly to t*e cloc3 input of eac* flip flop in t*e counter. "I$ &IAA#AM OF I' ;5;2:

2:

'I#'BIT &IAA#AM:

T#BTH TA%L : S.$o 1 0 2 5 7 8 ; : = 1> 11 PROCEDURE: 1. 'onnections are given as per t*e circuit diagrams. 0. Apply t*e input and verify t*e trut* ta+le of t*e counter. 'LO'. "BLS 6 1 0 2 5 7 8 ; : = 1> OBT"BT &FMS%/ > > > > > > > > 1 1 > ' > > > > 1 1 1 1 > > > % > > 1 1 > > 1 1 > 1 > AFLS%/ > 1 > 1 > 1 > 1 > > >

DISCUSSION 2UESTIONS: 2=

1. 0. 2. 5. 7. 8. ;. :.

'ompare sync*ronous and async*ronous se?uential circuitsK J*at is ripple counterK J*at is propagation delay in ripple counterK &efine MO& counterK J*at are t*e applications of countersK State t*e types of counterK &efine +it, +yte and <ord. &efine address of a memory.

RESULT: T*e trut* ta+le of t*e Async*ronous counter <as *ence verified 4. $o: 5>

&ate: TIMER IC APPLICATIONS : I .ASTABLE MULTIVIBRATOR1 AIM: To design an asta+le multivi+rator circuit for t*e given specifications using 777 Timer I'. APPARATUS RE2UIRED: S. $o 1. 0. 2. 5. 7. 8. ;. :. $ame of t*e Apparatus Function Aenerator '#O &ual #"S Timer I' %read %oard #esistors 'apacitors 'onnecting <ires and pro+es #ange 2 MHD 2> MHD > L 2> ) I' 777 Cuantity 1 1 1 1 1

As re?uired

T3EORY: An asta+le multivi+rator, often called a free6running multivi+rator, is a rectangular6<ave6 generating circuit. T*is circuit do not re?uire an e4ternal trigger to c*ange t*e state of t*e output. T*e time during <*ic* t*e output is eit*er *ig* or lo< is determined +y t<o resistors and a capacitor, <*ic* are connected e4ternally to t*e 777 timer. T*e time during <*ic* t*e capacitor c*arges from 112 )cc to 012 )cc is e?ual to t*e time t*e output is *ig* and is given +y, tc @ >.8= F#1 G #0/ ' Similarly t*e time during <*ic* t*e capacitor disc*arges from 012 )cc to 112 )cc is e?ual to t*e time t*e output is lo< and is given +y, td @ >.8= F#0/ ' T*us t*e total time period of t*e output <aveform is, T @ tc G td @ >.8= F#1 G 0 #0/ ' T*e term duty cycle is often used in conOunction <it* t*e asta+le multivi+rator. T*e duty cycle is t*e ratio of t*e time tc during <*ic* t*e output is *ig* to t*e total time period T. It is generally e4pressed in percentage. In e?uation form, P duty cycle @ QF#1 G #0/ 1 F#1 G 0 #0/R 4 1>>

"I$ &IAA#AM: 51

CIRCUIT DIAGRAM OF ASTABLE MULTIVIBRATOR:

& SIA$: 50

Aiven f@ 5 .HD, T*erefore, Total time period, T @ 11f @ SSSSSSSSSSSS Je 3no<, duty cycle @ tc 1 T T*erefore, tc @ 666666666666666666666666 and td @ SSSSSSSSSSSS Je also 3no< for an asta+le multivi+rator td @ >.8= F#0/ ' T*erefore, #0 @ SSSSSSSSSSSSS tc @ >.8= F#1 G #0/ ' T*erefore, #1 @ SSSSSSSSSSSSS PROCEDURE: 1. 'onnections are given as per t*e circuit diagram. 0. G 7) supply is given to t*e G )cc terminal of t*e timer I'. 2. At pin 2 t*e output <aveform is o+served <it* t*e *elp of a '#O 5. At pin 8 t*e capacitor voltage is o+tained in t*e '#O and t*e ) > and )c voltage <aveforms are plotted in a grap* s*eet. OBSERVATIONS: Amplitude F $o. of div 4 )olts per div / Time period F $o. of div 4 Time per div / tc 1. 0. Output )oltage , )o 'apacitor voltage , )c td

S.$o

Javeforms

MODEL GRAP3: 52

O1p voltage

)cc

T Fms/
012 )cc

'apacito r voltage

112 )cc TO$ TOFF

DISCUSSION 2UESTIONS:
1. 0. 2. 5. 7. 8. ;.

&efine Offset voltage. &efine duty cycle. Mention t*e applications of I'777. Aive t*e met*ods for o+taining symmetrical s?uare <ave. J*at is t*e ot*er name for monosta+le multivi+ratorK 4plain t*e operation of I'777 in asta+le mode.. J*y negative pulse is used as triggerK

RESULT: T*e design of t*e Asta+le multivi+rator circuit <as done and t*e output voltage and capacitor voltage <aveforms <ere o+tained. 4. $o: &ate: 55

TIMER IC APPLICATIONS BII .MONOSTABLE MULTIVIBRATOR1 AIM: To design a monosta+le multivi+rator for t*e given specifications using 777 Timer I'. APPARATUS RE2UIRED: S.$o 1. 0. 2. 5. 7. 8. ;. :. $ame of t*e Apparatus Function Aenerator '#O &ual #"S Timer I' %read %oard #esistors 'apacitors 'onnecting <ires and pro+es #ange 2 MHD, Analog 2> MHD > L 2> ) I' 777 Cuantity 1 1 1 1 1

As re?uired

T3EORY: A monosta+le multivi+rator often called a one6s*ot multivi+rator is a pulse generating circuit in <*ic* t*e duration of t*e pulse is determined +y t*e #' net<or3 connected e4ternally to t*e 777 timer. In a sta+le or stand6+y state t*e output of t*e circuit is appro4imately Dero or at logic lo< level. J*en an e4ternal trigger pulse is applied, t*e output is forced to go *ig* Fappro4. )cc/. T*e time during <*ic* t*e output remains *ig* is given +y, tp @ 1.1 #1 ' At t*e end of t*e timing interval, t*e output automatically reverts +ac3 to its logic lo< state. T*e output stays lo< until a trigger pulse is applied again. T*en t*e cycle repeats. T*us t*e monosta+le state *as only one sta+le state *ence t*e name monosta+le. "I$ &IAA#AM:

CIRCUIT DIAGRAM OF MONOSTABLE MULTIVIBRATOR: 57

& SIA$: Aiven tp @ >.818 ms @ 1.1 #1 ' T*erefore, #1 @ SSSSSSSSSSSSS PROCEDURE: 1. 0. 2. 5. 7. 'onnections are given as per t*e circuit diagram. G 7) supply is given to t*e G )cc terminal of t*e timer I'. A negative trigger pulse of 7), 0 .HD is applied to pin 0 of t*e 777 I' At pin 2 t*e output <aveform is o+served <it* t*e *elp of a '#O At pin 8 t*e capacitor voltage is o+tained in t*e '#O and t*e ) > and )c voltage <aveforms are plotted in a grap* s*eet.

OBSERVATIONS: Amplitude F $o. of div 4 )olts per div / Time period F $o. of div 4 Time per div / ton 1. 0. 2. Trigger input Output )oltage , )o 'apacitor voltage , )c toff

S.$o

MODEL GRAP3: 58

DISCUSSION 2UESTIONS: 1. 4plain t*e operation of I'777 in monosta+le mode. 0. J*at is t*e c*arging time for capacitor in monosta+le modeK 2. J*at are t*e modes of operation of 777 timersK 5. Give the comparison between combinational circuits and sequential circuits. 5. What do you mean by present state !. Give the applications o" 555 timers #$.

RESULT: T*e design of t*e Monosta+le multivi+rator circuit <as done and t*e input and output <aveforms <ere o+tained. 4. $o: &ate: 5;

APPLICATIONS OF OP:AMP : I .INVERTING AND NON B INVERTING AMPLIFIER1 a. INVERTING AMPLIFIER AIM: To design an Inverting Amplifier for t*e given specifications using Op6Amp I' ;51. APPARATUS RE2UIRED: S.$o 1. 0. 2. 5. 7. 8. ;. $ame of t*e Apparatus Function Aenerator '#O &ual #"S Op6Amp %read %oard #esistors 'onnecting <ires and pro+es #ange 2 MHD 2> MHD > L 2> ) I' ;51 As re?uired As re?uired Cuantity 1 1 1 1 1

T3EORY: T*e input signal )i is applied to t*e inverting input terminal t*roug* #1 and t*e non6 inverting input terminal of t*e op6amp is grounded. T*e output voltage )o is fed +ac3 to t*e inverting input terminal t*roug* t*e #f 6 #1 net<or3, <*ere #f is t*e feed+ac3 resistor. T*e output voltage is given as, )o @ 6 A'L )i Here t*e negative sign indicates t*at t*e output voltage is 1:>> out of p*ase <it* t*e input signal. PRECAUTIONS: 1. Output voltage <ill +e saturated if it e4ceeds T 17). PROCEDURE: 1. 'onnections are given as per t*e circuit diagram. 0. G )cc and 6 )cc supply is given to t*e po<er supply terminal of t*e Op6Amp I'. 2. %y adOusting t*e amplitude and fre?uency 3no+s of t*e function generator, appropriate input voltage is applied to t*e inverting input terminal of t*e Op6Amp. 5. T*e output voltage is o+tained in t*e '#O and t*e input and output voltage <aveforms are plotted in a grap* s*eet. "I$ &IAA#AM:

5:

CIRCUIT DIAGRAM OF INVERTING AMPLIFIER:

& SIA$: Je 3no< for an inverting Amplifier A'L @ #F 1 #1 Assume #1 Fappro4. 1> .U/ and find #f Hence )O Ft*eoretical/ @ 6 A'L )I OBSERVATIONS: S.$o. Input Output ODEL GRAP3: 5= Amplitude F $o. of div 4 )olts per div / T*eoretical 6 "ractical 6 Time period F $o. of div 4 Time per div /

I$) #TI$A AM"LIFI #: INPUT SIGNAL:

Amplitude

Time "eriod

OUTPUT SIGNAL:

RESULT: T*e design and testing of t*e inverting amplifier is done and t*e input and output <aveforms <ere dra<n. C. NON : INVERTING AMPLIFIER 7>

Amplitude

AIM: To design a $on6Inverting Amplifier for t*e given specifications using Op6Amp I' ;51. APPARATUS RE2UIRED: S.$o 1. 0. 2. 5. 7. 8. ;. $ame of t*e Apparatus Function Aenerator '#O &ual #"S Op6Amp %read %oard #esistors 'onnecting <ires and pro+es #ange 2 MHD 2> MHD > L 2> ) I' ;51 As re?uired As re?uired Cuantity 1 1 1 1 1

T3EORY: T*e input signal )i is applied to t*e non 6 inverting input terminal of t*e op6amp. T*is circuit amplifies t*e signal <it*out inverting t*e input signal. It is also called negative feed+ac3 system since t*e output is feed+ac3 to t*e inverting input terminals. T*e differential voltage )d at t*e inverting input terminal of t*e op6amp is Dero ideally and t*e output voltage is given as, )o @ A'L )i Here t*e output voltage is in p*ase <it* t*e input signal. PRECAUTIONS: 1. Output voltage <ill +e saturated if it e4ceeds T 17). PROCEDURE: 1. 'onnections are given as per t*e circuit diagram. 0. G )cc and 6 )cc supply is given to t*e po<er supply terminal of t*e Op6Amp I'. 2. %y adOusting t*e amplitude and fre?uency 3no+s of t*e function generator, appropriate input voltage is applied to t*e non 6 inverting input terminal of t*e Op6Amp. 5. T*e output voltage is o+tained in t*e '#O and t*e input and output voltage <aveforms are plotted in a grap* s*eet.

"I$ &IAA#AM: 71

CIRCUIT DIAGRAM OF NON INVERITNG AMPLIFIER:

& SIA$: Je 3no< for a $on6inverting Amplifier A'L @ 1 G F#F 1 #1/ Assume #1 F appro4. 1> .U / and find #f Hence )o @ A'L )i

OBSERVATIONS: 70

S.$o. Input Output

Amplitude F $o. of div 4 )olts per div / T*eoretical 6 "ractical 6

Time period F $o. of div 4 Time per div /

MODEL GRAP3: $O$ 6 I$) #TI$A AM"LIFI #: INPUT SIGNAL:

Amplitude

Time "eriod

OUTPUT SIGNAL:

Amplitude

DISCUSSION 2UESTIONS: 1. J*at do you mean +y linear circuitsK 0. &efine an I'K 2. J*at is an inverting amplifierK 5. J*at is t*e type of feed+ac3 employed in t*e inverting op6amp 7. J*at is a voltage follo<erK 8. &efine a non6inverting amplifierK ;. Aive t*e closed loop gain of an inverting amplifierK :. J*at is t*e gain of a non6inverting amplifierK

Tim

72

RESULT: T*e design and testing of t*e $on6inverting amplifier is done and t*e input and output <aveforms <ere dra<n. 4. $o: 75

&ate:

APPLICATIONS OF OP:AMP : II .DIFFERENTIATOR AND INTEGRATOR1 0. a. &IFF # $TIATO#

AIM: To design a &ifferentiator circuit for t*e given specifications using Op6Amp I' ;51. APPARATUS RE2UIRED: S.$o 1. 0. 2. 5. 7. 8. ;. :. $ame of t*e Apparatus Function Aenerator '#O &ual #"S Op6Amp %read %oard #esistors 'apacitors 'onnecting <ires and pro+es #ange 2 MHD 2> MHD > L 2> ) I' ;51 Cuantity 1 1 1 1 1

As re?uired

T3EORY: T*e differentiator circuit performs t*e mat*ematical operation of differentiation9 t*at is, t*e output <aveform is t*e derivative of t*e input <aveform. T*e differentiator may +e constructed from a +asic inverting amplifier if an input resistor #1 is replaced +y a capacitor '1. T*e e4pression for t*e output voltage is given as, )o @ 6 #f '1 Fd)i 1dt/ Here t*e negative sign indicates t*at t*e output voltage is 1:> > out of p*ase <it* t*e input signal. A resistor #comp @ #f is normally connected to t*e non6inverting input terminal of t*e op6amp to compensate for t*e input +ias current. A <or3a+le differentiator can +e designed +y implementing t*e follo<ing steps: 1. Select fa e?ual to t*e *ig*est fre?uency of t*e input signal to +e differentiated. T*en, assuming a value of '1 V 1 WF, calculate t*e value of #f. 0. '*oose f+ @ 0> fa and calculate t*e values of #1 and 'f so t*at #1'1 @ #f 'f. 2. T*e differentiator is most commonly used in <aves*aping circuits to detect *ig* fre?uency components in an input signal and also as a rateLofLc*ange detector in FM modulators. "I$ &IAA#AM:

CIRCUIT DIAGRAM OF DIFFERENTIATOR: 77

& SIA$: Aiven fa @ 666666666666666 Je 3no< t*e fre?uency at <*ic* t*e gain is > d%, fa @ 1 1 F0X #f '1/ Let us assume '1 @ >.1 WF9 t*en #f @ SSSSSSSSS Since f+ @ 0> fa, f+ @ 666666666666666 Je 3no< t*at t*e gain limiting fre?uency f+ @ 1 1 F0X #1 '1/ Hence #1 @ SSSSSSSSS Also since #1'1 @ #f 'f 9 'f @ SSSSSSSSS PROCEDURE: 1. 'onnections are given as per t*e circuit diagram. 0. G )cc and 6 )cc supply is given to t*e po<er supply terminal of t*e Op6Amp I'. 2. %y adOusting t*e amplitude and fre?uency 3no+s of t*e function generator, appropriate input voltage is applied to t*e inverting input terminal of t*e Op6Amp. 5. T*e output voltage is o+tained in t*e '#O and t*e input and output voltage <aveforms are plotted in a grap* s*eet. OBSERVATIONS: Input 6 Sine <ave S.$o. Amplitude F $o. of div 4 )olts per div / Input Output Input L S?uare <ave S.$o. Amplitude F $o. of div 4 )olts per div / Input Output

Time period F $o. of div 4 Time per div /

Time period F $o. of div 4 Time per div /

MODEL GRAP3: 78

&IFF # $TIATO#: INPUT SIGNAL:

Amplitude

Time "eriod

OUTPUT SIGNAL:

Amplitude

Time "eriod

RESULT: T*e design of t*e &ifferentiator circuit <as done and t*e input and output <aveforms <ere o+tained. 0. +. I$T A#ATO# 7;

AIM: To design an Integrator circuit for t*e given specifications using Op6Amp I' ;51. APPARATUS RE2UIRED: S.$o $ame of t*e Apparatus 1. Function Aenerator 0. '#O 2. &ual #"S 5. Op6Amp 7. %read %oard 8. #esistors ;. 'apacitors :. 'onnecting <ires and pro+es #ange 2 MHD 2> MHD > L 2> ) I' ;51 Cuantity 1 1 1 1 1

As re?uired

T3EORY: A circuit in <*ic* t*e output voltage <aveform is t*e integral of t*e input voltage <aveform is t*e integrator. Suc* a circuit is o+tained +y using a +asic inverting amplifier configuration if t*e feed+ac3 resistor #f is replaced +y a capacitor 'f . T*e e4pression for t*e output voltage is given as, )o @ 6 F11#f '1/ Y )i dt Here t*e negative sign indicates t*at t*e output voltage is 1:> > out of p*ase <it* t*e input signal. $ormally +et<een fa and f+ t*e circuit acts as an integrator. Aenerally, t*e value of fa V f+ . T*e input signal <ill +e integrated properly if t*e Time period T of t*e signal is larger t*an or e?ual to #f 'f. T*at is, T Z #f 'f T*e integrator is most commonly used in analog computers and A&' and signal6<ave s*aping circuits. "I$ &IAA#AM:

CIRCUIT DIAGRAM OF INTEGRATOR: 7:

& SIA$: Je 3no< t*e fre?uency at <*ic* t*e gain is > d%, f+ @ 1 1 F0X #1 'f/ T*erefore f+ @ SSSSS Since f+ @ 1> fa, and also t*e gain limiting fre?uency fa @ 1 1 F0X #f 'f/ Je get, #f @ SSSSSSS and *ence #1 @ SSSSSSSSSS PROCEDURE: 1. 'onnections are given as per t*e circuit diagram. 0. G )cc and 6 )cc supply is given to t*e po<er supply terminal of t*e Op6Amp I'. 2. %y adOusting t*e amplitude and fre?uency 3no+s of t*e function generator, appropriate input voltage is applied to t*e inverting input terminal of t*e Op6Amp. 5. T*e output voltage is o+tained in t*e '#O and t*e input and output voltage <aveforms are plotted in a grap* s*eet. OBSERVATIONS: S.$o. Input Output Amplitude F $o. of div 4 )olts per div / Time period F $o. of div 4 Time per div /

7=

MO& L A#A"H: I$T A#ATO#: INPUT SIGNAL:

Amplitude

Time "eriod

OUTPUT SIGNAL:

DISCUSSION 2UESTIONS: 1. J*at is integratorK 0. Jrite t*e disadvantages of ideal integratorK 2. Jrite t*e application of integratorK 5. J*y compensation resistance is needed in integrator and *o< <ill you find it valuesK 7. J*at is differentiatorK 8>

Amplitude

8. Jrite t*e disadvantages of ideal differentiator. ;. Jrite t*e application of differentiatorK :. J*y compensation resistance is needed in differentiator and *o< <ill you find it valuesK =. J*y integrators are preferred over differentiators in analog comparatorsK

RESULT: T*e design of t*e Integrator circuit <as done and t*e input and output <aveforms <ere o+tained. 4. $o: &ate: STUDY OF FLIP FLOPS 81

AIM: To verify t*e c*aracteristic ta+le of #S, &, -., and T Flip flops . APPARATUS RE2UIRED: S.$o 1. 0. 2. 5. 7. 8. $ame of t*e Apparatus &igital I' trainer 3it $O# gate $OT gate A$& gate F t*ree input / $A$& gate 'onnecting <ires #ange I' ;5>0 I' ;5>5 I' ;511 I' ;5>> As re?uired Cuantity 1

T3EORY: A Flip Flop is a se?uential device t*at samples its input signals and c*anges its output states only at times determined +y cloc3ing signal. Flip Flops may vary in t*e num+er of inputs t*ey possess and t*e manner in <*ic* t*e inputs affect t*e +inary states. #S FLI" FLO": T*e cloc3ed #S flip flop consists of $A$& gates and t*e output c*anges its state <it* respect to t*e input on application of cloc3 pulse. J*en t*e cloc3 pulse is *ig* t*e S and # inputs reac* t*e second level $A$& gates in t*eir complementary form. T*e Flip Flop is reset <*en t*e # input *ig* and S input is lo<. T*e Flip Flop is set <*en t*e S input is *ig* and # input is lo<. J*en +ot* t*e inputs are *ig* t*e output is in an indeterminate state. & FLI" FLO": To eliminate t*e undesira+le condition of indeterminate state in t*e S# Flip Flop <*en +ot* inputs are *ig* at t*e same time, in t*e & Flip Flop t*e inputs are never made e?ual at t*e same time. T*is is o+tained +y ma3ing t*e t<o inputs complement of eac* ot*er. -. FLI" FLO": T*e indeterminate state in t*e S# Flip6Flop is defined in t*e -. Flip Flop. -. inputs +e*ave li3e S and # inputs to set and reset t*e Flip Flop. T*e output C is A$&ed <it* . input and t*e cloc3 pulse, similarly t*e output C( is A$&ed <it* - input and t*e 'loc3 pulse. J*en t*e cloc3 pulse is Dero +ot* t*e A$& gates are disa+led and t*e C and C( output retain t*eir previous values. J*en t*e cloc3 pulse is *ig*, t*e - and . inputs reac* t*e $O# gates. J*en +ot* t*e inputs are *ig* t*e output toggles continuously. T*is is called #ace around condition and t*is must +e avoided. T FLI" FLO":

80

T*is is a modification of -. Flip Flop, o+tained +y connecting +ot* inputs - and . inputs toget*er. T Flip Flop is also called Toggle Flip Flop. #S FLI" FLO" LOAI' SIM%OL:

CIRCUIT DIAGRAM:

C3ARACTERISTIC TABLE: 'LO'. "BLS 1 0 2 5 7 8 ; : I$"BT S > > > > 1 1 1 1 # > > 1 1 > > 1 1 "# S $T STAT FC/ > 1 > 1 > 1 > 1 & FLI" FLO" $ !T STAT FCG1/ > 1 > > 1 1 ! ! STATBS

LOAI' SIM%OL: 82

CIRCUIT DIAGRAM:

C3ARACTERISTIC TABLE: 'LO'. "BLS 1 0 2 5 I$"BT & > > 1 1 "# S $T STAT FC/ > 1 > 1 $ !T STAT FCG1/ > > 1 1 STATBS

-. FLI" FLO" LOAI' SIM%OL:

85

CIRCUIT DIAGRAM:

C3ARACTERISTIC TABLE: 'LO'. "BLS 1 0 2 5 7 8 ; : I$"BT > > > > 1 1 1 1 . > > 1 1 > > 1 1 "# S $T STAT FC/ > 1 > 1 > 1 > 1 T FLI" FLO" $ !T STAT FCG1/ > 1 > > 1 1 1 > STATBS

87

LOAI' SIM%OL:

CIRCUIT DIAGRAM:

C3ARACTERISTIC TABLE: 'LO'. I$"BT "BLS T 1 > 0 > 2 1 5 1 PROCEDURE: "# S $T STAT FC/ > 1 > 1 $ !T STAT FCG1/ > > 1 > STATBS

1. 'onnections are given as per t*e circuit diagrams. 88

0. For all t*e I's ;t* pin is grounded and 15t* pin is given G7 ) supply. 2. Apply t*e inputs and o+serve t*e status of all t*e flip flops. DISCUSSION 2UESTIONS: 1. 0. 2. 5. 7. 8. ;. :. &efine flip6flop J*at is race around conditionK 4plain t*e flip6flop e4citation ta+les for & flip6flop 4plain t*e flip6flop e4citation ta+les for -. flip6flop J*at is a master6slave flip6flopK J*at is edge6triggered flip6flopK J*at is t*e operation of & flip6flopK J*at are t*e different types of flip6flopK

RESULT: T*e '*aracteristic ta+les of #S, &, -., T flip flops <ere verified. 4. $o: &ate: DC PODER SUPPLY USING LM ?/; AND LM ;2?

8;

AIM: To design and test t*e &' po<er supply using LM;02 and LM21; APPARATUS RE2UIRED: S. NO 1 0 2 5 7 8 ; : NAME OF T3E APPARATUS LM21; LM;02 #esistor #esistor 'apacitor &#% '#O %read +oard SPECIFICATION 6 6 1.5., 1.,,1.8. 1>. >.1WF,1>>pF,22> WF,00 WF 6 6 6 2UANTITY 1 1 1 0 1 1 1 6

PROCEDURE: LM;2?: i/ ii/ iii/ iv/ LM ?/;: i/ ii/ iii/ 'onnections are made as per t*e circuit diagram To vary t*e unregulated po<er supply from F>62)/ and note do<n t*e corresponding output voltage at across t*e load resistance #LFpin no:1>/ "lot t*e grap* +et<een resistance )in and )o 'onnections are made as per t*e circuit diagram Set up t*e input voltage as 7),8) and 1>) )ary t*e resistance #0 Fdesigning value/ t*e corresponding output voltage are noted do<n "lot t*e grap* +et<een resistance #0 and t*e o+served output voltage

CIRCUIT DIAGRAM: LM;2?: 8:

LM?/;:

LM?/;:

LM;2?:

TABULATION:

8=

LM;2?: #esistance in o*ms )in:SSSSSSSSS Output voltage )o

LM?/;: V'( Vo6t

MODEL GRAP3: LM;2?:

LM?/;:

DISCUSSION 2UESTIONS: ;>

1. 0. 2. 5. 7.

J*at are t*e main advantages of voltage regulatorK &efine line regulator or source regulator1 Ho< is t*e I' ;02 protected from s*ort circuitK &efine ripple reOection <it* respect to t*e voltage regulatorK J*at is meant +y drop out voltageK

RESULT: To design and test t*e &' po<er supply using LM;02 and LM21;<as done and <ave forms <ere o+tained.

;1