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IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO. 4, NOVEMBER 1996

proved PS

el for Simulation yristor C ircuits in DC

across it for a minimum time t,, which is greater than its specified turn-off time, toff. If a forward voltage is reapplied before t,, commutation failure occurs. This phenomenon, which is vital for the commutation circuit design and analysis, has not been taken into account in the dc thyristor model in [4] where the thyristor has been represented by a voltage-controlled switch and a series diode. The object of the present paper is to report the development of an improved dc thyristor model for use with PSpice where the following additional features o f thyristor behavior during turn off, as detailed in [SI, have been taken into account. 4) When forced commutation is used to turn off a conducting thyristor, the anode current decreases to the reverse peak current (Ir,) and the thyristor becomes reverse blocking. The reverse current begins to decrease exponentially. 5 ) The thyristor becomes forward blocking only when the reverse current decreases to a very small value Ioff at the end of toff. The relation between the turn-off time (toff)and the peak forward current ( I F )can be expressed as [8]

Bobba Sudhakar and Ajit K. Chattopadhyay, Fellow, IEEE

Abstract- An accurate model of a thyristor in dc chopper commutation circuits is described using the available elements in the PSpice program library. The improved model, which takes into account the reverse recovery time during turn off, is used to simulate voltage and current commutated dc choppers. Simulation results, which include a study of commutation failure, agree with theoretical and experimental results. The model developed is useful for computer aided analysis and design of dc thyristor choppers including the commutation circuits.

I. INTRODUCTION
SPICE is a PC-based version of the SPICE circuit simulation program available for general purpose circuit analysis [ 11. Recently, attempts have been made to include thyristor and other power electronic device models that can be used with this program [2]-[5],as well as with other versions like SPICE 2 [6], [7]. While in the early thyristor SPICE model [2] the thyristor was represented by the two complementary bipolar transistor configuration, in the latter models [31, [4] it has been represented by a voltage-controlled switch and a polynomial current source. This model, known as the ac thyristor model, lias been used for the simulation of ac line commutated power electronic circuits in which the thyristor current falls to zero by itself [3] or is diverted to another incoming thyristor [4]. This model incorporates the minimum requirements of the thyristor characteristics as follows. 1j It is normally reverse and forward blocking. With a gate pulse applied, it turns ON regeneratively when the anode is positive. to cathode voltage (VAK) 2 ) It remains in the ON state as long as anode current flows: the gate pulse has no effect on the conducting thyristor. 3) It switches to the OFF state when the anode current goes through zero toward the opposite polarity. For thyristors operated from a dc supply an additional requirement to turn off the thyristor is that the anode current must be reduced to zero with a reverse voltage or reverse current pulse applied (via a commutation circuit)
Manuscript received June 27, 1994; revised May 6, 1996. B. Sudhakar was with the Department of Electrical Engineering, India Institute of Technology, Kharagpur 721 302, India. He is now with the Department of Electrical and Computer Engineering, University of Illinois, Urbana-Champaign, IL 61801 USA. A. K. Chattopadhyay was with the Department of Electrical Engineering, Indian Institute of Technology, Kharagpur 721 302, India. He is now with the Department of Electrical Engineering, Bengal Engineering College, Howrah 71 1 103, India. Publisher Item Identifier S 0018-9359(96)08930-3.

where Iho = holding current, r, = reverse recovery time constant. The PSpice model obtained by adding these features during turn off to that of [31 is found to be suitable for simulation and analysis of the thyristor commutation circuits of dc choppers-both voltage and current commutated [9]-with R and R L loads. The results of simulation for commutation circuits of both types of choppers with this model are presented here together with experimental results. It may be mentioned that the SCR model obtained in [7] for SPICE 2 does have a turn-off block, but it has limitations for application in dc chopper circuits, particularly in current commutated ones, as in [6], where it was assumed that: 1) when a reverse voltage is applied, the device becomes reverse blocking and the current falls from the peak value instantaneously; 2 ) the reverse voltage must be constant for the reverse current to decrease exponentially.

0018-9359/96$05.00 0 1996 IEEE

SUDHAKAR AND CHATTOPADHYAY:IMPROVED PSPICE MODEL FOR SIMULATION AND ANALYSIS OF THYRISTOR

541

Q
Main # 1

l+

I 2

# 2

# 3

#4

.subckt scrm I 2 3 vas I 5 0 . 0 ~ svl 5 6 7 0 smainl dl 6 2 dmain sw2 6 2 12 0 srevl frev 2 5 vrev 1.0 rgate 3 2 50.0 fl o 7 poly(1) vas -O.OOI 1.0 gl 0 7 3 2 1.0 g2 0 7 9 0 2 . 0 rl 7 0 10.0 cl 7 0 luf ic = 0 . 0 ~ has 8 0 vas 0.01 dcap 8 9 dnaub crev 9 0 2.5uf ic = 0.0 sw3 9 10 0 12 srev2 rrev 10 I 1.0 vrev 11 0 0 . 0 ~ f2 0 12 vas 10.0 c2 12 0 lOnf ic = 0.0 r2 12 0 10.0 .model smainl vsuitch(ron=0.015 roff=lE+6 von=l.O voff=0.5) .model screvl vswitch(ron=0.0001 roff=lE+6 von=l.O voffe0.0) .model srev2 vswitch(ron=0.0001 roff=lE+6 von=0.0 voff=-l.O) .model dmain d(n=O.Ol) .ends.
Fig. 1. Thyristor model: (a) circuit and (b) PSpice program.

These assumptions are not strictly valid for voltage- and current-commutated choppers. The model developed here gives a more correct representation and is a generalized model that can be used in ac circuit applications also by removing the additional blocks representing turn off by the commutation circuit.
11. THYRISTOR MODEL

during turn-off. The PSpice program that describes this circuit is given along with the thyristor model. The turn-on and turn-off mechanisms of the proposed model are described as follows.

A. Turn On
The turn-on process of the thyristor as modeled here involves closing of two voltage controlled switches SW, and SW2 (Fig. l), which are controlled by V(7) and V(12), respectively. When a positive gate pulse is applied at node

Fig. 1 shows the dc thyristor model developed by modifying that of [3] considering the reverse recovery characteristics

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IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO. 4, NOVEMBER 1996

Voltage commutated dc chopper.(RL vinput 1 0 30v rload 2 7 60.0 lload 7 0 80 mH ic=O.O dfvd 0 2 dmain XI 1 2 3 scrm x2 4 2 5 scr q ccom 4 1 0.4uf ic=O.O lres 6 2 O.lmh ic=O.O dres 6 4 dckt vgatel 3 2 pulse ( 0 3 Ims Ins Ins vgate2 5 2 pulse (0 3 Oms Ins Ins

load)

; Subcircuit defined earlier ; AC thyristor model ; Commutating capacitance

O.lms 2ms) O.lms 2ms)

.subckt scr 1 2 3 vas I 6 0 . 0 ~ dio 6 4 dmain sw 4 2 5 0 dmain rgate 3 2 50.0 fsense 0 5 vas 1.0 gsense 0 5 3 2 1.0 rl 5 0 5.0 cl 5 0 iOuf ic=O.O .ends .model smain vswitch (ron=0.015 roff=lE+6 von=0.4 voff=0.0) model dmain d (n=O.01) .model dckt d(n=O.Ol rs=l)

.nodeset v(xi.7)=0.0

v(xi.12)=0.9

v(x2.25)=0.0

.tran .25ms 1Oms 5ms .options acct it15=0 .probe .end

(b) Fig. 2. Voltage commutated chopper: (a) circuit and (b) PSpice program.

3, a voltage-controlled current source G1 starts charging the RlCl combination connected across nodes 7 and 0. With the increase of control voltage V(7), the SW1 resistance decreases and a forward current starts flowing through VAS and this is

reflected in F1 and F2 (both controlled current sources). As Fl assists G1 in increasing V(7), the SW1 resistance is further reduced. F2 has similar effect on S W . . This positive feedback mechanism thus created continues until SW, and SW2 tum

SUDHAKAR AND CHATTOPADHYAY:IMPROVED PSPICE MODEL FOR SIMULATION AND ANALYSIS OF THYRISTOR

543

V o l t a g e Commutated dc chopper (R.60 load) Date/Time r u n : 05/26/94 18:59:03Temp 27 0

V o l t a g e Commutated dc chopper ( R . 1 0

L=80mh)

D a t e / T i m e run

05/26/94

18 55 57Temp 27 0

"LOAD

'c(C0M)

B- 10

r r

-?- '1

--

TW 0.RTE- 0.5..

I--

r7

V~~~~

*-- RTB- 0 . 5 ~ -;---y---

b 10

TB-

0.5"

'c

(COM)

'c (COM)

(b)

(b)

Voltage commutated chopper with R load: (a) simulated and (b) experimental. Frequency = 500-Hz, duty ratio = 0.5, and R = 60
Fig. 3.

a.

Fig. 4. Voltage-commutated chopper with E L load: (a) simulated and (b) experimental. Frequency = 500 Ha, duty ratio = 0.5, R = 60 0, andL

= 80mH.

on completely. Once the switches are ON, the gate pulse has no effect and the switches remain ON until V(7) decreases to zero. The components RI and C1 of the control circuit can be adjusted to give the turn ON delay.

The parameters of the thyristor model can be obtained from the data given in the manufacturer's data sheet specifications of the device. # RGATEcan be obtained from the gate

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IEEE TRANSACTIONS ON EDUCATION, VOL. 39, NO. 4, NOVEMBER 1996

V o l t Comm ( b e f o r e comm f a i l u r e ) C = O 5 u f Date/Time r u n 05/27/94 20 05 44 Temp 27 0

# The control voltage VON is taken to be 1 V and TONand

VOFF are computed using the following expressions: I(G1) * t o n = c 1 * VON I(G1) * t d =C1 * VOFF(5) (6)

In the model proposed here, the junction capacitances of the thyristor have been neglected. B. Turn Off In order to turn off a conducting thyristor, the anode curfent must be reduced below the holding current level. This is achieved by the forced commutation circuit used. The turnoff process as modeled here involves opening of the switches SW1 and SW, (Fig. 1) under this condition. As the anode current tends to go negative toward peak reverse recovery current, F2 and hence V(12) decreases. As V(l2) decreases to zero, SW2 switches off making the thyristor reverse blocking. However, the device can block forward voltage only after the reverse recovery current has died down. This is modeled by the control block #3. As soon as SW2 turns off, SW, turns on. The capacitor CEEV, which was charged to a voltage numerically equal to the peak forward current by the currentcontrolled voltage source HAS and the diode DCAP during the ON period of the thyristor, discharges through RREV.This discharge current is reflected by FREV in the main circuit block as an exponentially decaying reverse recovery current. FI and F2 are modeled such that SWI opens only when the reverse recovery current has decreased to a very small value l o f f after time toff.The relation (1) is taken care of by suitably selecting CREV and RREV. The peak reverse current is obtained from the data sheet specifications and is used in the computation of K, the scaling factor used with HAS K = -I F
1 T m

Volt Comm ( a f t e r comm failure)C=O 4uf Date/Time r u n 05/27/94 20 18 42Temp 27 0

(7)

and
-4ov+-----------------~-----------------~ 1 95ms 2 OOms 2 05ms 0 v(1,2) Time

log

is calculated using K and holding current Iho

(b)
Fig 5 (a) I , and VAKwaveforms before commutation failure (simulated) commutating capacitance 1 0 5 p F and (b) I , and VAlc waveforms after commutation failure (simulated) commutating capacitance = 0 4 ~ L F

Ih o IOE= -. K Since the voltage across capacitor CREVreflects the is taken to be 1. # reverse recovery current, RREV CREVis computed using the expression
CREV = -

,
(k). ITm

RREV* In

(9)

characteristics

VGT RGATE = --. IGT

#

The ac thyristor model can be obtained by omitting SW2 and FREVof main block, G2 of control block # 2 4 .
111. VOLTAGE-COMMUTATED CHOPPER

Roncan be obtained from the ON state characteristics

~

VTM RON= ITM and ROFF from the OFF state characteristics

(3)

VRRM ROFF= -. IDRM

(4)

Here, a charged capacitor is switched across the conducting thyristor and the reverse voltage is applied for a minimum time t, to turn off the conducting thyristor. Fig. 2 shows the voltage commutated chopper circuit and its associated PSpice program. The auxiliary thyristor is represented by the ac thyristor model [31 because the current naturally comes to zero. The simulation and experimental results for R and RL loads are shown in

SUDHAKAR AND CHATTOPADHYAY: IMPROVED PSPICE MODEL FOR SIMULATION AND ANALYSIS OF THYRISTOR

545

Current Commutated dc chopper vinput 1 0 30V rload 2 7 60.0 lload 7 0 80mh ic=O.O dfwd 0 2 dckt xl 1 2 3 scrm x2 1 5 6 scr Ccom 1 4 4Uf ic=30.0 lres 4 79 ;0.12mh ic=0.35 rpar 79 5 0.002 dres 5 2 dckt daccr 2 1 dckt vgatel 3 2 pulse ( 0 3 Oms Ius vgate2 6 5 pulse ( 0 3 Ims lus

(R=60 Ohms L=80mH)

; Subcircuit defined earlier

lus O.Ims 2ms) ius O.lms 2ms)

.subckt scr 1 2 3 vas 1 4 0 . 0 ~ sw 4 2 5 0 smain rgate 3 2 5 0 . 0 fsense 0 5 vas I.0 gsense 0 5 3 2 1.0 rl 5 0 5.0 cl 5 0 ;iouf ic = 0 . 0 .ends .model smain vswitch(ron=0.015 roff=lE+6 von=O.4 voff=O.O) .model dckt d(tt-0.lns cjo=2pf) .nodeset v(xl.7)eO.O v(xI.l2)=0.0 v(x2.5)=0.0 .tran .25ms IOms 5ms .options acct it15=0 reltol=imv vntol=lmv abstol=lua .probe .end
(b) Fig. 6. Current commutated chopper: (a) circuit and (b) PSpice progrdm.

Figs. 3 and 4. The simulated waveforms of I A and VAKwith different values of capacitors before and after commutation

failure are shown in Fig. 5. The commutating capacitance value was decreased to 0.4 /-IF to simulate commutation failure.

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I I
I I

! I
I I I

(b)

Fig. 7. Current commutated chopper with Hz, and duty ratio = 0 5

R and R L loads: (a) simulated and

(b) experimental. R = 60

and L = 80-mH, frequency = 500

IV. CURRENT-COMMUTATED CHOPPER

A current pulse is made to flow in the reverse direction through the conducting thyristor. When the current through the thyristor comes to zero, it turns off. The current commutated chopper [9] and its PSpice program description are given in Fig. 6. The simulation and experimental results with R and R L loads are shown in Fig. I .
V. CONCLUSIONS

are also grateful to D. Kastha of the Department of Electrical Engineering, India Institute of Technology, Kharagpur, for his help during the revision of the manuscript.

REFERENCES
[I] P. W. Tuinenga, SPICE-A Guide to Circuit Simulation and Analysis Using PSpice. Englewood Cliffs, NJ: Prentice-Hall, 1988. [2] L. J. Giacoletto, SCR modeling for SPICE computer program, Dept. of Elect. Eng., Internal memo, Michigan State Univ., Jan. 1978. [3] ~, Simple SCR and TRIAC PSPICE computer models, IEEE Trans. Ind. Elec., vol. 36, no. 3, pp. 4 5 1 4 5 5 , Aug. 1989. [4] M. H. Rashid, SPICEfor Power Electronics and Electric Power. Englewood Cliffs, NJ: Prentice-Hall, 1993. [5] D. W. Hart, Circuit simulation as an aid in teaching the principles of Power Electronics, IEEE Trans. Educ., vol. 36, no. 1, pp. 10-16, Feb. 1993. [6] F. J. Gracia. F. Arizti, and F. J. Aranceta, A nonideal macromodel of thyristor for transient analysis in power electronic systems, IEEE Trans. h d . Electron., vol. 37, no. 6, pp. 514-520, Dec. 1990. [7] S . B. Taib, L. N. Hulley, Z. Wu, and W. Shepherd, Thyristor switch model for power electronic circuit simulation in modified SPICE 2, IEEE Trans. Power Electron., vol. 7, no. 3, July 1992. [S] Kubat, Power Semiconductors. New York Springer-Verlag, 1984, p. 208. [9] P. C. Sen, Thyristor DC Drives. New York: Wiley, 1981.

An improved PSpice model for a thyristor is formulated including the reverse recovery behavior for analysis of dc chopper commutation circuits. An excellent correlation was found between the theoretical and simulated results as well as experimental results in a few cases. The model developed is shown to be of use in studying the design and performance of dc thyristor commutation circuits.
ACKNOWLEDGMENT

The authors would like to thank the anonymous reviewers for their valuable comments on improving the paper. They

SUDHAKAR AND CHATTOPADHYAY:IMPROVED PSPICE MODEL FOR SIMULATION AND ANALYSIS OF THYRISTOR

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Bobba Sudhakar received the B.Tech. (Hons.) degree in electrical engineering from the Indian Institute of Technology (IIT), Kharagpur, India in 1994. He is currently working toward the Ph.D. degree at University of Illinois, Urbana-Champaign, USA. His current research interests include VLSI design for low power and reliability.

Ajit K. Chattopadhyay (SM83-F91) received the B.E. degree in electrical engineering from University of Calcutta (B.E. College), the M.Tech. degree in electrical machines from the Indian Institute of Technology (IIT), Kharagpur, and the Ph.D. degree from the University of Manchester (UMIST), England in 1958, 1963, and 1971, respectively. After working for more than one year in Guest Keen, Williams Ltd., Howrah and for some time in the Indian Standards Institution, New Delhi, he joined the Electrical Engineering Department of IIT in 1960, where he became a Professor in 1976 and Head of the Department during 1992-1995. During 1969 -1971, he was engaged in research work in the field of ac drives at UMIST, Manchester, as a Colombo Plan Study Fellow. During 1980-1981, he was a Visiting Professor at the University of Technology, Baghdad, Iraq. In 1972, he established Power Electronics and Drive Laboratories at IIT, Kharagpur, and initiated research activities and Postgraduate course work in this area. He has authored more than 85 research papers in international journals and conference records and guided a number of Ph.D. degree candidates in the area of electrical machines, power electronics, and microprocessor-control of dc and ac drives. He has acted as a consultant-in-charge of a few industrial research projects and was the coordinator of the first National Workshop on Power Electronics held at IIT, Kharagpur, in May 1988. Dr. Chattopadhyay is a Fellow of Indian National Academy of Engineering, a Life Fellow of IE (India), and a Fellow of IETE (India). He was elected IEEE Fellow in 1991 for his leadership in the development of power electronics research and educational programs in India. He received the Bimal Bose Award in 1986 from IETE (India), Bharatia Cutler Hammer Prize in 1986, and the Tata Rao Prize (1993-1994) from IE (India). He has served on program committees of many international conferences and chaired many technical sessions in India and abroad. He visited and delivered invited seminar talks in a number of research establishments/universities in the U.K., US., Canada, Japan, Germany, and Romania. He is listed in several international biographies, including the Znternational Register of Projles and Internal Leaders in Achievement. He has been recently awarded an AICTE Emeritus Fellowship for two years to work at Bengal Engineering College (D.U.), Howrah, India.