experiment 7

Goal of the experiment

The goal of this experiment is to make you aware of the functionality of the Phase Lock Loop commonly referred to as PLL which is primarily used for a frequency synthesizer in high frequency stable clock generators. From a crystal of some kHz range, it is possible to generate waveform of GHz frequency range using a PLL.

7.1 Brief theory and motivation

KVCO in experiment number 5 if we replace the In the loop of self-tuned filter studied Vi Voltage Control Filter (VCF) with Voltage Control Oscillator (VCO) (discussed in KVCO d~ Vref Kwill VCO experiment 6) then it becomes PLL as K shown in Figure 7.1. The reader benefit Design a PLL to get locked to frequency of 1 kHz. d~ dV c VCO K pd # r # A0 # KVCO from viewing the recorded lecture at [22]. d~ dVc U4 2 d~ VF3 K VCO Vc dVc ~ = Vc C2 R4 ~ =dVc U 4 4 V RC $ r C 2 d ~ + V c C1 R4 VF3 4 V RC ~ The sensitivity of the PLL is given by K and is , VCO r $V c equal to VG1 d~ ~ dVc , where = 4V= =4 r $ RCVc V r $ RC + Vc d~ dVc VV C1 c r $ RC d~ dd~ V c ~= V ~ =V c VG1 = c = U3 4Vr $ RC dV cr $ RC , which is nothing but frequency of oscillation of VCO. Hence dV c~ V R5 RC r $c$RC dVc dVc VrVV R1 d~ Vc ~ V c U3 R5 ~ K VCO = ~ Vc = V $ RC Vc4Vr $ RC ~= R 1 dV r c + ~ Vc KVCO ~ Vc = V2 ~ Q 0 + d V ~ K V ~ c c VCO = ~ Vc U1 + dVc = Vr $ RC ~0Q VCQ (7.1) V2 ~ KVCO V ~ 0Q K c = VCO = ~ Vc ~ Vc VCQ V0 VCQ U1 ~0Q VCO = ~ Vc ~0Q K V 0 V i V0 VCQ ~0Q Voltage Vc Control Vi Vref V i V0 V CQ V CQ Vref (Output) Vref Vi R K pd # r # A0 # KVCO VO V 0 2 V0 VCO K pd # r # A0 # KVCO r K A0 # KVCO Vref 2 # V i pd # 2
ref VI Input Frequency r ref K pd # 2 W(Input)

Vc Vc V dVc ~= d~ dVc ~ = Vc c 4Vr $ RC 4Vr $ RC 4 V $ RC r RC V V $ dV c r c V ~= d V ~ c ~ = 4V $ cRC d~ Vc 4Vr $ RC Vc ~ ~ dV c r = dVc = Vr $ RC dVc = Vr $ RC dVc Vr $ RC d~ Vc d~ Vc KVCO Vc ~$ RC Vc Vc ~ Vc ~ Vc ~ = dVc = V r ~= dVc = Vr $ RC 4Vr $ RC ~0Q ~ Vc KVCO = ~ Vc KVCO = no ~ Vc ~ c Vc system oscillates VCO = ~ the When voltage is applied to the K system, atVthe free d~ Vinput c = V ~ CQ Q 0 K VCO = ~ Vc ~ 0Q V RC $ dV K r c VCO c =~ V ~ Q 0 with corresponding control voltage of running frequency of the VCO, given by Vc ~ VCQ to the system ~0applied KVCO V0V Q V CQ . If the input is ~ Q 0 with the same frequency as , the PLL CQ K VCO continue = ~ Vc to run Vi V V0 free running VCQ at the d~frequency will and the phase difference V 0 VCQ between 0 dVc ~ 0Q two signals V the 5 i as 90 since Vref is 0 (already explained in Experiment 0 and V V i V0 Vi Vc ~ =4 of Chapter 6 ). As the frequency of input signal voltage will Vref CQ r is changed, the control V Vref Vi V RC $ V r i KV # 2 # A0 # KVCO pdref change correspondingly, so as the output frequency. d~ Vc frequency to the input V0 rto lock Vref r V = ref r K A K # # # pd VCO 0 K pd a A0 # KVCO is a change # result, # V RC $ dV r c K A K # # # pd VCO 0 As there of phase difference between the two signals away 2 2 Vi 2 r r K pd # A0 # KVCO ~ Vc for which output frequenciesK # A K pd # locked from 90. The range of input frequencies gets 2 2 # 0 # VCO Vref KVCO Vc ~ system. to the input is called the lock range of= the The lock range is defined as K pd # r # A0 # KVCO on either side of ~0Q . 2 VCQ V0
~ = KVCO

7.2 Specifications

V1
+
+ V1

VF2

VF2

R2

R2
+

U2

U2 R3 R3

VF1

VF1

Vi V

K pd # r # A0 # KVCO 2

10.00

Vref=0 KVCO # A0 #

5.00

Output

K pd #

A K 2 # 0 # VCO

0.00

-5.00

-10.00 0.00 10.00m Time (s) 20.00m 30.00m

Figure 7.1: Phase Locked Loop (PLL) and its characteristics page 44

Figure 7.2: Sample output waveform for the Phase Locked Loop (PLL) Experiment

Analog System Lab Kit PRO

1 2

Measure the lock range of the system and measure the change in the phase of the output signal as input frequency is varied within the lock range. Vary the input frequency and obtain the change in the control voltage and plot the output. A sample output characteristic of the PLL is shown in Figure 7.2.

Design a Frequency Synthesizer to generate a waveform of 1MHz frequency from a 100kHz crystal as shown in Figure 7.3.

7.4 What you should submit

1 2 3 4
Simulate the circuits and obtain the characteristics of the system. Take the plots of characteristics from oscilloscope and compare it with simulation results. Measure the change in the phase of the output signal as input frequency is varied within the lock range. Vary the input frequency and obtain the change in the control voltage. Use Table 7.2 to record your readings. Figure 7.3: Block Diagram of Frequency Optimizer

Notes on Experiment 7:

S.No. 1 2 3 4

Input Frequency

Output Phase

Table 7.2: Control Voltage as a function of Input Frequency S.No. 1 2 3 4 Table 7.1: Output Phase as a function of Input Frequency Input Frequency Control Voltage

Analog System Lab Kit PRO

page 45

experiment 7

7.3 Measurements to be taken

7.5 Exercise Set 7