INTEGRATED PASSIVE COMPONENT TECHNOLOGY

IEEE Press
445 Hoes Lane Piscataway, NJ 08854 IEEE Press Editorial Board Stamatios V. Kartalopoulos, Editor in Chief M. Akay J. B. Anderson R. J. Baker J. E. Brewer M. E. El-Hawary R. J. Herrick D. Kirk R. Leonardi M. S. Newman M. Padgett W. D. Reeve S. Tewksbury G. Zobrist

Kenneth Moore, Director of IEEE Press Catherine Faduska, Senior Acquisitions Editor John Griffin, Acquisitions Editor Anthony VenGraitis, Project Editor IEEE Components, Packaging & Manufacturing Technology Society, Sponsor CPMT Liaison to IEEE Press, Joe E. Brewer

INTEGRATED PASSIVE COMPONENT TECHNOLOGY

Edited by

RICHARD K. ULRICH LEONARD W. SCHAPER

University of Arkansas

IEEE Components, Packaging & Manufacturing Technology Society, Sponsor

IEEE PRESS

A JOHN WILEY & SONS, INC., PUBLICATION

Copyright 2003 by the Institute of Electrical and Electronics Engineers, Inc. All rights reserved. Published simultaneously in Canada. No part of this publication may be reproduced, stored in a retrieval system or transmitted in any form or by any means, electronic, mechanical, photocopying, recording, scanning or otherwise, except as permitted under Section 107 or 108 of the 1976 United States Copyright Act, without either the prior written permission of the Publisher, or authorization through payment of the appropriate per-copy fee to the Copyright Clearance Center, Inc., 222 Rosewood Drive, Danvers, MA 01923, (978) 750-8400, fax (978) 750-4744, or on the web at www.copyright.com. Requests to the Publisher for permission should be addressed to the Permissions Department, John Wiley & Sons, Inc., 111 River Street, Hoboken, NJ 07030, (201) 748-6011, fax (201) 748-6008, e-mail: permreq@wiley.com. Limit of Liability/Disclaimer of Warranty: While the publisher and author have used their best efforts in preparing this book, they make no representation or warranties with respect to the accuracy or completeness of the contents of this book and specifically disclaim any implied warranties of merchantability or fitness for a particular purpose. No warranty may be created or extended by sales representatives or written sales materials. The advice and strategies contained herein may not be suitable for your situation. You should consult with a professional where appropriate. Neither the publisher nor author shall be liable for any loss of profit or any other commercial damages, including but not limited to special, incidental, consequential, or other damages. For general information on our other products and services please contact our Customer Care Department within the U.S. at 877-762-2974, outside the U.S. at 317-572-3993 or fax 317-572-4002. Wiley also publishes its books in a variety of electronic formats. Some content that appears in print, however, may not be available in electronic format.

Library of Congress Cataloging-in-Publication Data: Integrated passive component technology / edited by Richard K. Ulrich, Leonard W. Schaper. p. cm. Includes bibliographical references and index. ISBN 0-471-24431-7 (cloth) 1. Passive components. 2. Integrated circuitsDesign and construction. 3. Printed circuitsDesign and construction. I. Ulrich, Richard K., Ph.D. II. Schaper, Leonard W. TK7874.147145 2003 621.3815dc21 Printed in the United States of America. 10 9 8 7 6 5 4 3 2 1

2003041102

To Dan and Joy Ulrich, the best teachers I ever had and To the late Len Schaper Sr., who taught me that it was OK to get my hands dirty

CONTENTS

Contributors Preface 1 Introduction Richard K. Ulrich 1.1 1.2 1.3 1.4 Status and Trends in Discrete Passive Components Definitions and Configurations of Integrated Passives Comparison to Integrated Active Devices Substrates and Interconnect Systems for Integrated Passives 1.4.1 Organic Substrates 1.4.2 Inorganic Substrates 1.5 Fabrication of Integrated Passives 1.6 Reasons for Integrating Passive Devices 1.7 Problems with Integrating Passive Devices 1.7.1 Cost Modeling 1.8 Applications for Integrated Passives 1.8.1 Replacing Surface Mount Discretes with Arrays and Networks 1.8.2 Decoupling 1.8.3 DC/DC Conversion 1.8.4 Passive Replacement in FR4 1.8.5 Passive Replacement in HDI 1.9 The Past and Future of Integrated Passives 1.10 Organization of this Book References Characteristics and Performance of Planar Resistors Richard K. Ulrich 2.1 Performance Parameters 2.1.1 Resistance of Planar Resistors 2.1.2 Resistivity of Materials

xv xvii 1 2 7 10 11 12 14 14 17 20 22 23 23 24 26 27 27 27 29 30 33 33 33 35
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CONTENTS

2.1.3 Temperature Effects 2.1.4 Value Stability 2.2 Resistance in Electronic Materials 2.2.1 Resistivity and Charge Carriers 2.2.2 Semiconducting Oxides 2.2.3 Tunneling 2.2.4 Temperature, Composition, and Morphology Effects 2.3 Sizing Integrated Resistors 2.3.1 Thermal Issues 2.3.2 Parasitic Capacitance between Meanders 2.3.3 Parasitic Capacitance to Ground 2.3.4 Lumped Versus Distributed Performance 2.4 Trimming References 3 Integrated Resistor Materials and Processes Richard K. Ulrich Single-Component Metals Metal Alloys and MetalNonmetal Compounds 3.2.1 Tantalum Nitride 3.2.2 Titanium Oxy-Nitride 3.2.3 Nickel Phosphide 3.3 Semiconductors 3.3.1 Silicon 3.3.2 Semiconducting Oxides 3.4 Cermets 3.5 Polymer Thick Film 3.6 Ink Jet Deposition 3.7 Commercialized Processes 3.7.1 Ohmega-Ply 3.7.2 Dupont Interra 3.7.3 MacDermid M-Pass 3.7.4 Polymer Thick Film 3.7.5 Shipley Insite 3.8 Summary References 4 Dielectric Materials for Integrated Capacitors Richard K. Ulrich 4.1 4.2 4.3 4.4 Polarizability and Capacitance Capacitance Density Temperature Effects Frequency and Voltage Effects 3.1 3.2

37 38 40 40 41 43 43 45 46 49 51 52 52 53 55 56 58 59 60 60 61 61 61 61 63 65 66 66 66 68 70 70 70 73 75 76 79 82 83

CONTENTS

ix

4.5 4.6 4.7 4.8 4.9 4.10

Aging Effects Composition and Morphology Effects Leakage and Breakdown Dissipation Factor Comparison to EIA Dielectric Classifications Matching Dielectric Materials to Applications 4.10.1 Decoupling and Energy Storage 4.10.2 Analog Functions 4.10.3 Termination of Transmission Lines References 5 Size and Configuration of Integrated Capacitors Richard K. Ulrich 5.1 Comparison of Integrated and Discrete Areas 5.2 Layout Options 5.3 Tolerance 5.4 Mixed Dielectric Strategies 5.5 CV Product 5.6 Maximum Capacitance Density and Breakdown Voltage References 6 Processing Integrated Capacitors Richard K. Ulrich 6.1 6.2 6.3 Sputtering CVD, PECVD and MOCVD Anodization 6.3.1 Benefits of Anodization for Capacitor Dialectics 6.3.2 Film Formation During Anodization 6.3.3 Ta Anodization 6.3.4 Dielectrics from Anodized Ta 6.3.5 Patterning Ta and Ta2O5 6.3.6 Ferroelectrics by Anodization 6.4 Sol-Gel and Hydrothermal Ferroelectrics 6.5 Thin- and Thick-Film Polymers 6.6 Thick-Film Dielectrics 6.6.1 Ferroelectric Powder Dispersed in Polymer 6.7 Interlayer Insulation 6.8 Interdigitated Capacitors 6.9 Capacitor Plate Materials 6.10 Trimming Integrated Capacitors 6.11 Commercialized Integrated Capacitor Technologies 6.11.1 DuPont Interra 6.11.2 3-M C-Ply

84 85 86 89 91 93 96 96 96 97 101 101 105 106 107 108 109 111 113 114 116 117 118 118 120 121 123 124 124 126 127 127 129 130 131 131 132 132 133

CONTENTS

6.11.3 Dupont HK4 6.11.4 Motorolas Mezzanine Capacitor 6.11.5 Sanmina BC2000 6.11.6 nChip 6.12 Summary References 7 Defects and Yield Issues Richard K. Ulrich 7.1 7.2 7.3 Causes of Fatal Defects in Integrated Capacitors Measurement of Defect Density Defect Density and System Yield 7.3.1 Predicting Yield from Defect Density 7.4 Yield Enhancement Techniques for Capacitors 7.5 Conclusions References 8 Electrical Performance of Integrated Capacitors Richard K. Ulrich and Leonard W. Schaper Modeling Ideal Passives Modeling Real Capacitors Electrical Performance of Discrete and Integrated Capacitors 8.3.1 Inductance of the Capacitor Alone 8.3.2 Inductance of the Capacitors Leads and Contacts 8.3.3 Equivalent Series Resistance 8.3.4 Capacitors as Distributed Devices 8.4 Dissipation Factor of Real Capacitors 8.5 Measurement of Capacitor Properties 8.5.1 ESR and ESL Measurement with an Impedance Analyzer 8.5.2 ESR and ESL Measurement with a Network Analyzer 8.6 Summary References 9 Decoupling Leonard W. Schaper 9.1 Power Distribution 9.2 Decoupling with Discrete Capacitors 9.3 Decoupling with Integrated Capacitors 9.4 Dielectrics and Configurations for Integrated Decoupling 9.5 Integrated Decoupling as an Entry Application References 8.1 8.2 8.3

133 135 135 135 135 138 145 145 146 147 148 149 150 151 153 154 154 158 158 164 165 165 166 166 167 170 174 175 177 177 181 183 185 187 189

CONTENTS

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10 Integrated Inductors Geert J. Carchon and Walter De Raedt 10.1 Introduction 10.2 Inductor Behavior and Performance Parameters 10.2.1 Inductor Layouts and Values 10.2.2 Inductor Operating Principles 10.2.3 Equivalent Circuit 10.2.4 Extraction of the Equivalent Circuit Parameters 10.2.5 Figure of Merits: QL, QLC, FOML 10.2.6 Spiral Inductor Layouts 10.2.7 Improving QL by Technology and Layout Parameters 10.3 Inductor Performance Prediction 10.3.1 Transmission Line Inductor 10.3.2 Spiral Inductors 10.4 Integrated Inductor Examples 10.4.1 Inductors Integrated on 1020 -cm Si Substrates 10.4.2 GaAs MMIC Inductors 10.4.3 MCM-D Inductors 10.4.4 LTCC 10.4.5 Integration of On-Chip Si Inductors through Wafer-Level Packaging Techniques 10.5 Use of Inductors in Circuits: Examples 10.5.1 Filters 10.5.2 Voltage-Controlled Oscillators 10.5.3 Size-Reduction Techniques 10.5.4 Coupled Spiral Inductors 10.6 Conclusions Acknowledgments References 11 Modeling of Integrated Inductors and Resistors for Microwave Applications Zhenwen Wang, M. Jamal Deen, and A. H. Rahal 11.1 Introduction 11.1.1 Miniature Hybrid Microwave Integrated Circuit (MHMIC) 11.1.2 Goals of this Chapter 11.2 Modeling of Spiral Inductors 11.2.1 Geometry of the Spiral Inductor 11.2.2 Inductor Circuit Model 11.2.3 Calculation of Inductance 11.2.4 Ground Plane Effect on Inductance 11.2.5 Series Resistance 11.2.6 Parasitic Capacitance

191 191 192 192 194 196 198 200 206 208 216 217 217 224 224 224 226 230 231 232 233 235 235 237 238 238 238 247

247 248 248 249 249 250 250 252 253 254

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CONTENTS

Summary of Spiral Inductor Model Quality Factor of a Spiral Inductor Inductor Synthesis Design and De-Embedding of Inductor Test Structure Measurement Setup and Calibration Specifications Experimental Verification Low-Pass Filter Extension of the Model to Spiral Inductors on Silicon Substrates 11.3 Modeling of Thin-Film Resistors 11.3.1 Step Discontinuity in Microstrip Width 11.3.2 High Sheet Resistance Microstrip Model 11.3.3 Experimental Verification 11.3.4 S-parameter Measurement Setup 11.3.5 Measurement Calibration 11.4 Conclusions References Appendix: Characteristics of Microscript Lines A.1 Chareristic Impedance ZL and Effective Dielectric Constant eff under Static TEM Approximation A.2 Dispersion Models of Effective Dielectric Contant eff and Characteristic Impedance ZL A.3 Lumped-Element Model of a Microstrip Line A.4 Microstrip Losses 12 Other Applications and Integration Technologies Elizabeth Logan, Geert J. Carchon, Walter De Raedt, Richard K. Ulrich, and Leonard W. Schaper 12.1 Demonstration Devices Fabricated with Integrated Passives 12.1.1 RC Terminators 12.1.2 Voltage Dividers 12.1.3 Reliability Test Structures 12.1.4 Filters and RF Devices 12.1.5 Functional Modules and Subsystems 12.2 Commercialized Thin-Film Build-Up Integrated Passives 12.2.1 Capacitor Arrays 12.2.2 Termination 12.2.3 Intarsia 12.2.4 SyChip 12.2.5 Telephus 12.3 Other Integrated Passive Technologies 12.4 Summary Acknowledgments References

11.2.7 11.2.8 11.2.9 11.2.10 11.2.11 11.2.12 11.2.13 11.2.14

257 257 258 259 261 261 263 265 271 273 274 278 278 278 282 282 284 234 286 288 288 293

294 294 297 298 299 305 313 314 315 316 318 320 320 322 323 323

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13 The Economics of Embedded Passives Peter A. Sandborn 13.1 Introduction 13.2 Modeling Embedded Passive Economics 13.3 Key Aspects of Modeling Embedded Passive Costs 13.3.1 Board Size and Routing Calculations 13.3.2 Recurring Cost Analysis 13.3.3 Throughput 13.3.4 Trimming Embedded Resistors 13.3.5 Yield and Test 13.3.6 Life Cycle Costs 13.4 Example Case Studies 13.4.1 Picocell Board Application 13.4.2 NEMI Hand-Held Product Sector Emulator 13.4.3 Fiber Channel Card 13.5 Summary Acknowledgments References 14 The Future of Integrated Passives Richard K. Ulrich 14.1 Status of Passive Integration 14.2 Issues for Implementation on Organic Substrates 14.2.1 Electrical Design Issues 14.2.2 Board Design Issues 14.2.3 Fabrication and Manufacturing Issues 14.3 Progress on Board-Level Implementation 14.3.1 Advanced Embedded Passives Technology Consortium (AEPT) 14.3.2 National Electronics Manufacturing Initiative (NEMI) 14.3.3 The Embedded Capacitance Project 14.4 Three Ways In for Organic Boards 14.4.1 Decoupling 14.4.2 Replacement on FR4 14.4.3 High Density Interconnect 14.5 Conclusion Index About the Editors

327 327 329 332 332 336 338 341 343 345 347 348 352 354 356 357 357 361 361 362 362 363 364 365 366 366 367 367 367 369 369 369 373 381

CONTRIBUTORS

GEERT J. CARCHON, IMECMCP Division, Belgium, geert.carchon@imec.be JAMAL DEEN, Electrical and Computer Engineering Department, McMaster University, Hamilton, Ontario, Canada, jamal@mcmaster.ca ELIZABETH LOGAN, Consultant, Danville, California, drlizl@aol.com WALTER DE RAEDT, IMECMCP Division, Belgium, walter.deraedt@imec.be A. H. RAHAL, Nanowave Technologies Inc., Etobicoke, Ontario, Canada PETER A. SANDBORN, Department of Mechanical Engineering, University of Maryland, College Park, Maryland, sandborn@eng.umd.edu LEONARD W. SCHAPER, Department of Electrical Engineering, University of Arkansas, Fayetteville, Arkansas, schaper@uark.edu RICHARD K. ULRICH, Department of Chemical Engineering, University of Arkansas, Fayetteville, Arkansas, rulrich@uark.edu ZHENWEN WANG, Electrical and Computer Engineering Department, McMaster University, Hamilton, Ontario, Canada

xv

PREFACE

The purpose of this book is to provide an overview of the technology, potential applications, motivations and problems associated with integrating passive components such as resistors, capacitors, and inductors into circuit boards instead of mounting them as discrete components on the surface. It was written primarily for the engineer or scientist in industry who wants to determine if passive integration is a viable option for a particular product. Thus, when explaining the various aspects of integrated passives throughout this book, we have sought to address a basic set of questions concerning the tradeoffs between discrete and integrated approaches such as: What are the advantages and disadvantages of integrated passives? What sort of processing would be required? Is this processing compatible with existing substrates? Can integrated passives be made with conventional PWB fabrication equipment? What are the performance and/or form factor advantages of integration? How do the electrical characteristics of integrated passives differ from discretes? Can existing equipment and materials be used? Can all of the passive components be integrated? How are integrated passives designed? What are the tolerance and repeatability limits? To what extent is yield an issue? Is reworkability possible? What must be considered in the economic analysis?

Because passives have been integrated into ceramic substrates for decades, the focus of this book is on the organic substrate and buildup materials more closely associated with the consumer sector, such as FR-4 and flex. Passive integration is
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PREFACE

only beginning for these materials and, at present, there is very little established methodology. The lessons learned from integrated passives in ceramics were combined with contemporary work on consumer-level substrates in order to project what is possible and practical for organic boards. We are aware of no other book dedicated to integrated passives so we pulled together information from many sources and locations outside of our own work at the University of Arkansas. Although we wrote most of this book, outside experts have been used wherever we could find them for both contributions and reviews to help ensure adequate coverage of important topics. We assume that the reader is familiar with the basics of board-level fabrication, specifically with regard to conductor definition, via formation, surface-mount assembly, thin- and thick-film processing, photolithography, and etching. An elementary knowledge of the electrical aspects of resistance, capacitance, and inductance will also be required to appreciate the performance advantages of passive integration. Both materials science and electrical engineering issues are presented in clearly delineated sections throughout the book so readers can pick those parts that are most beneficial to them. Chapter 1 sets forth the important issues that will be covered individually in detail in subsequent chapters. After reading this chapter, the reader should be able to select chapters of interest and read them as stand-alone works with a minimum of referencing previous chapters for background information. Whether to organize individual chapters around materials or around processes turned out to be a fundamental question. They are intimately connected, but it is impossible to discuss separately all the permutations of deposition methods, patterning techniques, and materials. The best choice seemed to group materials under the various processes. For instance, there is a section on sputtering that includes how to deposit TaNx rather than a section on TaNx that discusses sputtering. This approach seems better, since most existing manufacturers are more likely to be organized around various types of processes than around various types of materials. A board shop looking to get into passive integration has to begin manufacturing components that it previously purchased ready-to-use. Therefore, it must have a fundamental understanding of the relationship between the materials in passives and their electrical performance. The electrical properties of materials are reviewed in context with the various passive devices and their manufacturing processes in order to help the uninitiated make this connection. Again, the purpose of this book is to disseminate the state of the art in passive integration to help the practicing engineer evaluate the possibility of using this technology in their products. Since this technology is rapidly developing, the next edition of this book should contain fewer fundamentals and more commercially implemented processes. It is our hope that we are promoting that evolution. The editors are grateful to many people for helping to make this book possible including Julia Busch, Louise Schaper, David Nelms, Tim Lenihan, Matt Leftwich, Errol Porter, Kaoru Maner, and all the graduate students who have worked on integrated passive projects at the University of Arkansas. Thanks to colleagues Bill Brown, Simon Ang, Hameed Naseem, and others associated with the High Density

PREFACE

xix

Electronics Center at the University of Arkansas, as well as to the departments of Chemical Engineering and Electrical Engineering for providing some of the time and support necessary for such a large undertaking. Thanks to Erik Brandon and other researchers at JPL for their support through the years. Also, we benefited from review work on various chapters by many people including Istvan Novak, Bill Borland, David McGregor, Thomas Lantzer, Joel Peiffer, Robert Croswell, and Kim Fjeldsted. RICHARD K. ULRICH LEONARD W. SCHAPER
Fayetteville, Arkansas April 2003

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 1

INTRODUCTION
RICHARD K. ULRICH

Integrating passive components directly into the circuit board is a well-established idea but an immature practice. To put this into perspective, compare two technologies familiar today: the laser and color TV. The laser came about comparatively suddenly in the early 1960s, taking much of the technological community by surprise. It was an unanticipated invention, to most, whose utility became obvious when the technology was revealed. In contrast, color TV was anticipated for decades. Its potential benefits and anticipated implementation problems were well established long before its common usage in the industry. Debate ensued for years over the most effective and economical solutions to the numerous interrelated technical issues. It was an engineered system, not an invention, developed to augment a well-established technology, and it was not clear how much of that old technology it would displace. Integrated passives are like color TV. Those in the electronics business have a firm idea of the benefits integrated passives can bring as well as the problems of implementing them into one of the largest and most established industries in the world. There are a large number of candidate materials and processes but little agreement as of yet over which, if any, are superior to the rest. The purpose of this book is to identify these potential payoffs and problems and to provide an overview of the current technologies available in order to help the engineer choose the best options for integrating passive components in a given application. This first chapter will provide a summary of the state of surface-mount passives, an introduction to the concept, benefits, and problems of integrated passives, and some coverage of the fabrication and materials technologies involved. As many relevant references as possible are included to help the reader follow up on a topic of interest. The organization of this book is such that the introduction provides a general overview for readers of just about any level of familiarity with the subject and the rest of the chapters are more specific to individual topics. The reader should at least skim this first chapter, and then choose subsequent chapters of special interest for further study.
1

INTRODUCTION

1.1 STATUS AND TRENDS IN DISCRETE PASSIVE COMPONENTS Tremendous progress has been made in the past four decades in miniaturizing and integrating transistors and capacitors for logic applications onto silicon. By comparison, passive components (resistors, capacitors, and inductors) at the circuit-board level have made only incremental advances in size and density. Consequently, passive components occupy an increasingly larger area and mass fraction of electronic systems and are a major hurdle to the miniaturization of many electronic systems. This is particularly true for analog and mixed-signal applications that use a larger number of passives than typical digital systems. Almost no through-hole, axialleaded resistors and disk capacitors are used anymore; they have been replaced with smaller, rectangular surface-mount components with solder joints at both ends. The size of these modern discretes is described by a number such as 0603, which indicates a size of 60 30 mils (1.5 0.75 mm). The 0402 (1.0 0.5 mm) size is commonly used, and the smallest discrete passives today are 0201 (0.50 0.25 mm), which represents a considerable challenge in handling, attachment, and inspection. Figure 1.1 shows a cell phone RF section that utilizes 0402 resistors and capacitors surrounding a 6 x 6 mm packaged integrated circuit. About a trillion passive devices were placed in electronic systems in 2000, with the vast majority utilizing surface-mount technology. Today, each mounted passive costs about half a U.S. cent to purchase, and about 1.3 cents for conversion (assembly, testing, inspection, and rework), for a total installed cost of around 1.8 cents [1]. The present total market for passive devices is around $18 billion annually. In terms of numbers, there are more passive devices than active devices in just about any application. An Ericsson CF388 PCS 1900 cell phone has 380 components, including 322 passives and 15 ICs, for a passive-to-active ratio of 21:1. Digi-

Figure 1.1

Cell phone RF section utilizing surface-mount passives.

1.1

STATUS AND TRENDS IN DISCRETE PASSIVE COMPONENTS

tal systems, such as desktop and laptop computers, have somewhat lower ratios: between 5 and 15 passives for every IC (see Table 1.1) [2]. An Apple G4 has 230 capacitors, 218 resistors, 9 inductors, and 8 diodes [3] mounted on the motherboard, together with 42 integrated circuits. In terms of area, an individual surface-mount passive is almost always smaller than any packaged IC and usually has only two connections, so the relative total footprints and total number of device-to-board connections are closer to equal. Figure 1.2 shows part of a board from a Nokia 6161 cell phone with the location and footprint of surface-mount discrete passives marked in white. Typical passive component density in hand-held wireless applications is about 20/inch2, which, at 2 cents/component, amounts to $0.40/inch2 for passives alone [5]. A breakdown of the 405 individual passive components by number and value for this same phone is shown in Table 1.2 [6]. Additionally, there are 15 ICs and 40 miscellaneous surface-mount devices such as power transistors and diodes for ESD protection, all mounted onto 6.2 square inches of board area for an average passive density of 85/inch2.

Table 1.1 System

Passive and IC count for portable consumer products [4] Total Passives Cellular Phones 359 243 283 432 389 373 993 492 Consumer Portable 437 489 1226 1329 Other Communication 142 585 101 PDA 538 Computers 184 457 Total ICs 25 14 11 21 27 29 45 30 15 17 14 43 3 24 8 74 24 42 Ratio 14:1 17:1 25:1 20:1 14:1 13:1 22:1 16:1 29:1 29:1 33:1 31:1 47:1 24:1 13:1 7:1 8:1 11:1

Ericsson DH338 Digital Ericsson E237 Analog Philips PR93 Analog Nokia 2110 Digital Motorola Md 1.8 GHz Casio PH-250 Motorola StarTAC Matsushita NTT DOCOMO I Motorola Tango Pager Casio QV1O Digital Camera 1990 Sony Camcorder Sony Handy Cam DCR-PC7 Motorola Pen Pager Infotac Radio Modem Data Race Fax-Modem Sony Magic Link Apple Portable Logic Board Apple G4

INTRODUCTION

Figure 1.2 Cell phone board showing the footprints of surface mount passive components marked in white.

The number of discrete passives in a model series of desktop computers over the years is given in Table 1.3 [7, 8]. Some trends are clear: a rapid increase in the total number of passives utilized, a total switch from leaded to SMT components, and the initiation of the use of passive arraysmultiple passives in one package. Mobile wireless, including cell phones, will account for the largest share of the increase in passive usage in coming years but other significant new markets include Bluetooth and automotive applications. The 2000 National Electronic Manufacturing Initiative (NEMI) roadmap predicts that cell phone sales will reach one billion units annually by 2004, which will require replacing half the cell phones in use today, and there should be two billion Bluetooth devices operating by 2005. Telecommunications has replaced computers as the top user of printed wiring boards. An analysis of two cell phones, one GPS receiver, and two two-way radios produced the resistor and capacitor distributions shown in Figures 1.3, 1.4, and 1.5 [9]. The required values extend over many orders of magnitude for resistors and capacitors. Inductors range in value from about 1 to 50 nH, but there are usually far fewer inductors than capacitors and resistors in most consumer microelectronic products. It has been observed that 40% of capacitors in a cell phone are under 1 nF [2] and 80% of inductors in hand-held products are less than 200 nH [5].

Table 1.2 Distribution of sizes and values for surface-mount passive components in a Nokia 6161 cell phone Size 0402 0402 0402 0603 0603 0805 0805 1206 1310 electrolytic Values Capacitors <100 pF 1 nF 15 nF 30 nF 100 nF 250 nF 1 F 2 F 9 F 10 F Resistors 110 M 120 M 122 M 122 M 122 M Inductors 1100 nH 2500 nH <220 H Total Passive Components: 405 Quantity 100 37 20 22 29 2 12 2 2 6 Total: 232 109 18 16 4 2 Total: 149 16 3 5 Total: 24

0402 0402 dual-array 0603 0805 1206

0603 0805 1206

Table 1.3

Number and type of passive components in personal computers 486 Pentium 120 Pentium 200 0 151 0 1 0 7 0 0 0 146 0 64 369 0 190 32 0 0 32 3 0 0 188 0 148 593 Pentium II 0 300 140 0 37 11 0 4 0 635 10 336 1,473 Pentium III 0 600 200 0 80 15 0 0 0 1000 0 300 2,195 5

Leaded MLC SMT MLC Cap Arrays (4) Leaded Tantalum SMT Tantalum Aluminum Feedthrough Disks Leaded Resistors SMT Resistors Resistor Arrays (2) Resistor Arrays (4) Total Passives

58 0 0 15 0 0 0 0 92 0 0 0 165

Figure 1.3

Distribution of resistor values in portable consumer equipment.

Figure 1.4

Distribution of capacitor values in portable consumer equipment.

Figure 1.5 6

Distribution spectrum of capacitors by product type, 1996 [5].

1.2 DEFINITIONS AND CONFIGURATIONS OF INTEGRATED PASSIVES

In summary, all types of electronic systems are becoming more complex while pressure is simultaneously mounting to make them smaller and lighter. The numbers of passives are steadily increasing and the required range of values is very wide. Manufacture and placement of 0201 discretes may represent the size and density limit for SMT devices.

1.2 DEFINITIONS AND CONFIGURATIONS OF INTEGRATED PASSIVES Passives usually refer to resistors, capacitors, and inductors, but could also include thermistors, varistors, transformers, temperature sensors, and almost any nonswitching analog device. The concept of integrated, integral, embedded, arrayed, or networked passives involves manufacturing them as a group in or on a common substrate instead of in their own individual packages. The following lexicology will be used in this book: Discrete Passive ComponentThis is a single passive element in its own leaded or surface-mount-technology (SMT) package. An example would be a single resistor, capacitor, or inductor in an 0402 package, as shown in Figure 1.1. This will typically have two contacts to be soldered to the board. Presently, the vast majority of passives are utilized in this manner. Integrated Passive ComponentThis is a general term for multiple passive components that share a substrate and packaging. They may be housed inside the layers of the primary interconnect substrate, which would give them the subdesignation of an embedded passive component, or they may be on the surface of a separate substrate that is then placed in an enclosure and surface mounted on the primary interconnect substrate, in which case they would be called passive arrays or passive networks (see below). Embedded Passive ComponentOne that is formed or otherwise inserted inside the primary interconnect substrate as opposed to being on the surface. (See Figure 1.6.) Passive ArrayMultiple passive components of like function are formed on the surface of a separate substrate and packaged in a single SMT case. This case is then mounted on the primary interconnect substrate of the system. (See Figure 1.7.) Examples include an array of capacitors or an array of resistors. The number of leads will typically be twice the number of internal components in the array but more leads may be provided to reduce the total inductance in capacitor arrays, or fewer leads may be present if some of the components are connected internally, such as for voltage dividers. Inductors are not normally arrayed since their separate electromagnetic fields would interfere with one another in close proximity. The passive array does not always reduce the number of leads that must be attached, but does increase the efficiency of their attachment since more connections are

INTRODUCTION

Figure 1.6

Embedded passive components in the primary interconnect substrate.

made with one alignment and mounting. This is the lowest level of passive integration and may involve the same manufacturing techniques used for discretes. Integrated Passive NetworksMultiple passive components of more than one function are formed on the surface of a separate substrate and packaged in a single SMT case. This case is then mounted on the primary interconnect substrate of the system. (See Figure 1.8.) These typically have some internal connections to form simple functions such as terminators or filters. The number of leads can vary with functionality and the number of internal elements. This approach generally does reduce the number of leads to be connected since some passive-to-passive connections are made within the package. (See Figure 1.9.)

Figure 1.7

Integrated passive arrays.

1.2 DEFINITIONS AND CONFIGURATIONS OF INTEGRATED PASSIVES

Figure 1.8

Integrated passive network.

Both passive arrays and networks of various types are available from several manufacturers and are in common use in all types of electronic systems as surface-mount components as small as 0402. They are particularly useful in digital systems in which parallel data buses require RC termination or pull-up/pull-down resistors for many lines in a small footprint. Their commercial penetration is probably less than 5% at this time but is expected to increase. Integrated Passive SubsystemsThese are similar to but more complex than passive networks and may include some active devices to form a functional subsystem module that can be surface mounted onto the primary interconnect board. Figure 1.10 shows a voltage-controlled oscillator from Intarsia that consists of integrated passives featuring several visible square-format integrated inductors and planar capacitors, along with three wire-bonded actives. The solder balls enable the network to be flipped and mounted onto a primary interconnect substrate, made possible by the low profile of the integrated passives. It may be feasible to provide subsystems as complex as GPS or Bluetooth this way, so that a manufacturer could add them as desired to a primary interconnect board of another product.

Figure 1.9

Hierarchy of integrated passive components.

10

INTRODUCTION

Figure 1.10

An integrated passive device that includes active components.

1.3 COMPARISON TO INTEGRATED ACTIVE DEVICES To understand the potential benefits and issues of integrated passives, the obvious parallel is the integration of active devices. In the 1950s, the term interconnect problem referred to the dilemma that engineers could design digital electronic systems that were much more complex than could be manufactured at the time, since all individual active devices had to be individually manufactured, packaged separately, manually placed, and hand-soldered onto a circuit board. Although transistors were mass-produced at low price, the price of an electronic system was dominated by the cost of interconnecting these individually packaged components at the circuit-board level. In addition to the high cost of manual interconnection, problems existed due to the resulting system size and complexity, along with low reliability brought about by the large number of solder joints. The invention of the integrated circuit in 1958 greatly reduced these problems by employing chemical means instead of mechanical means to fabricate transistors and interconnects all at once on a common substrate. As a result, the cost of producing one gate on a chip is the same as the cost of producing millions of the same size or, in other words, the incremental cost of one more transistor is zero. The first transistor on a Pentium 4 might cost $300, but the next 41,999,999 are free. Soldered con-

1.4 SUBSTRATES AND INTERCONNECT SYSTEMS FOR INTEGRATED PASSIVES

11

nections were eliminated and changes in layout could be made by simply changing artwork. Initially, there was some concern that large-scale integration could never be realized because of yield issues; absolutely every gate must work for the system to function since there is no possibility of rework. For instance, to obtain a chip yield of at least 80% for an IC with 10 million transistors, the number of defective individual transistors must average no more than about one in 44 million. However, the status of present-day thin film formation, photolithography, and etching routinely achieve these numbers and better. Although chip size is somewhat constrained by yield concerns, the density of active devices on a chip is not; that is more a function of the ability to expose and etch fine features. Since the invention of the integrated circuit, continuous improvements in yield and gate density have resulted in a steady increase in the functionality of a single chip. The result, as described by Moores law, is that on-chip logic density has doubled about every 18 months for decades and will do so for at least another one. The resulting orders-of-magnitude increases in function per unit cost, volume, and mass are well known, and, in fact, still drive a large portion of our economy. The status of passive components today is similar to that of active devices almost half a century ago. Many of the same well-known motivations and concerns relate to passive integration; the task is to determine which of these apply to this new scenario and what they mean to the rate of acceptance, ultimate configurations, and degree of replacement of discrete components. There are several differences in the two situations; the most important is that passive components cannot be scaled down in size to the extent that active devices can be. Since logic devices such as transistor-based gates and memory cells can, in principle, operate with individual electrical quanta; they can be scaled down to the submicron dimensions that are ubiquitous today. However, the signals processed in analog systems or digital signals at the board level cannot be reduced in amplitude arbitrarily. They may be RF signals going to an antenna, the input for A/D conversion, or bursts of hundreds of watts of power to a single chip during a clock cycle. As a result, increases in integrated passive component density can only come about when the passive is made smaller while maintaining the same value of Ohms, Farads or Henrys (Figure 1.11). As will be frequently pointed out in this book, the need for higher values of resistance and capacitance per unit area is a limiting factor in the implementation of integrated passives, underscoring the importance of fundamental materials research in this area.

1.4 SUBSTRATES AND INTERCONNECT SYSTEMS FOR INTEGRATED PASSIVES There is a vast array of materials, processing methods, and configurations in use as interconnect substrates, from resin-impregnated paper with printed conductors on the low end to single-crystal silicon with photolithographic thin-film built-up layers on the high end. In between there are FR4, ceramic, polymer film, and rigid inorganics,

12

INTRODUCTION

Figure 1.11

The second generation of integration.

each of which can be composed of a multitude of specific materials and processed in dozens of ways [10, 11]. The number of possible interconnect substrates times the number of processes used to achieve them times the number of materials and processes for integrated passives equals an impossible number to describe individually. In order to make this manageable, the types of substrates must be grouped. The first natural division is into organic and inorganic designations. Organic means that there is a polymer material, either thermoset or thermoplastic, in the board, even if it makes up a small fraction by mass. This will limit the maximum temperature for any processing to around 200300C and possibly lower for some steps. For instance, polyimide can withstand temperatures well over 250C without decomposing, but mil-thick sheets may be permanently distorted if the temperature during sputtering exceeds about 100C [12]. Inorganic substrates can withstand well over 7001000C and are usually limited by the softening point of the metals. 1.4.1 Organic Substrates 1.4.1.1 FR4. This is the ubiquitous green rigid circuit board material found in almost every consumer system. The polymeric component is at least one, and usually more, layers of glass-fiber-reinforced epoxy about 0.51.5 mm (2060 mils) thick with 17 or 34 micron Cu ( oz or 1 oz Cu) patterned as the conductor. Multiple layers are laminated with heat and pressure. 1.4.1.2 Flex. These are laminated stacks of polyimide (Kapton), polyester, liquid crystal, or layers of any other free-standing polymer films, each from 15 mils thick. These can be obtained with Cu already laminated on one or both sides for

1.4 SUBSTRATES AND INTERCONNECT SYSTEMS FOR INTEGRATED PASSIVES

13

subtractive patterning, or processing can be through sputtering, plating, and photolithographic techniques. Higher interconnect density than with FR4 is achievable due to thinner insulating films, which enable smaller vias, and through the use of thin-film processes, but at higher cost per square inch of the resulting board. 1.4.1.3 Build-Up. A rigid material such as glass, silicon, or plastic is used as a base, and alternating layers of conducting and insulating layers are deposited and etched one at a time in the same manner as fabrication for the interconnect layers for an IC. These are similar to thin-film techniques and, in most technologies, no mechanical lamination is performed, although vacuum processing is used extensively. The organic portion is either the insulating dielectric, which is either spin-on or cast coatings of BCB, polyimide or some other liquid-state precursor that is then thermally cured, or the rigid material that forms the base for the build-up. Metals are sputtered or plated, then etched photolithographically. Vias are made by plasma etching, laser drilling, or photodefinition. This provides the highest interconnect density of the three organic approaches because there is generally no lamination, allowing via catchpads to be smaller. Removing half the vias from a board will not have as much beneficial effect on wiring density as reducing the diameter of these catchpads by half [10]. FR4 is by far the most mature and utilized organic substrate, representing 85% of the resin systems used to produce copper-clad laminate [1]. At present (mid 2002), there are perhaps four or five commercial technologies for integrated resistors and capacitors spread between about that many vendors, but more are in development and should appear soon. As will be described below, there are more factors to overcome in integrated passive implementation than just process development, including design, standardization, testing, reliability, and understanding the economic tradeoffs. However, all of these issues are being addressed in academia, industry, and consortia so that it is expected that integrated passives will become common in FR4 over the coming years. Most of the papers from microelectronic journals and proceedings since about 1995 involve various flex substrates, microvia methods on thin laminates, and build-up processes. These have the possibility to achieve high-density interconnection, perhaps reflecting the feeling that integrated passives would be more economically feasible on a more expensive and higher-performance platform or else that it might be easier to introduce integrated passives into an interconnect technology that is itself under development. As HDI flex increases its share of the total market, integrated passives will probably be present in some fraction. Buildup processing with organic dielectrics on substrates like silicon, alumina, and glass was known as MCM-D a decade ago but, as is the nature of the electronics business, the same thing has a different name today: system-in-apackage (SIP). Intarsia (now defunct) built a variety of integrated passive networks on glass using thin-film BCB interlayer insulation. IMEC, the Belgian development organization, builds a similar technology and cooperates with European partners. Today, even taken together, embedded passives on organic substrates/layers make up an insignificant portion of the total sales of passives, but that is expected to change soon.

14

INTRODUCTION

1.4.2 Inorganic Substrates/Layers 1.4.2.1 Cofired Ceramic. Layers of greentape uncured ceramic with screenprinted metallization paste and metal-filled punched vias are collimated, stacked and fired, typically at 7001100C, to form an interconnect board. This is a very mature technology, dating back to the early 1960s. The materials used then were alumina ceramic and tungsten or molybdenum metal, which had to be fired at very high temperature. Today, low-temperature cofired ceramic (LTCC) is used with copper, silver, or gold metallization. Other pastes are used to form resistors and capacitor dielectrics. Ceramic substrate technology accounts for only about 10% of the boards produced worldwide [1]. Established methodology for integrated passives is widely available from the design phase through reliability assessment. The infrastructure for ceramics is so entrenched that a new company need only contact the vendors to establish a process. However, integrated passives in ceramic substrates cannot be controlled to tight tolerances and cannot be easily trimmed. 1.4.2.2 Front-End Silicon. These are standard IC manufacturing techniques on silicon that utilize either sputtered TiNx, CrSi, or doped Si resistors along with SiOx or SiNx capacitors. There are no active devices fabricated. The insulation layers are SiO2 and the metal is Al, which limits processing temperature to about 500C. n-Chip (now Flextronics) employed an anodized alumina decoupling capacitor built into a silicon substrate that was used as an MCM-D substrate. Integrated passive sales are currently around 3% of the total and almost all of that comes from the inorganic category in the form of passive arrays and networks. These are manufactured either by using extensions of the fired ceramic and thinfilm technologies used to make discrete passives or else by the front-end silicon process described above.

1.5 FABRICATION OF INTEGRATED PASSIVES The overall situation is that neither the optimal materials nor methods for fabricating integrated passives on organic substrates have been established, which limits their use in the most common substrates. Integrated passives are well established on inorganic substrates, but problems exist with regard to tolerance for those in cofired ceramics and with value range on silicon. Due to the planar nature of integrated passives, the formation and patterning of films are central to this technology. There are three broad classes of films required: conductive, resistive, and dielectric. Conductive films are those that are needed for carrying current with a minimum of voltage loss, such as the top and bottom plates of capacitors and the spiral windings of a planar inductor. There is no advantage to having parasitic resistance in this type of film; that would only degrade the performance of the capacitor or inductor. Therefore, these would normally be metals or else very conductive metal-filled polymer thick films with resistances less than

1.5

FABRICATION OF INTEGRATED PASSIVES

15

about 0.1 /square. Narrow tolerance and repeatability is not a major issue as long as the overall resistance is low enough for the application. Of course, it would be desirable for integrated passives to utilize the same metal used as the interconnect on the substrate. Resistive films would be used in making integrated resistors only, and would be specified on the basis of providing predictable, reproducible values of resistance in a sufficiently small footprint. A wide variety of materials could be used for this, ranging from resistive alloys (NiCr, CrSi, TaNx, TiNxOy) to ceramicmetal nanocomposites (cermets) to carbon-filled polymers. Resistivities of 100 to 10,000 /square are required. Dielectric films would be used to form integrated capacitors, and a vast array of materials with a wide range of dielectric constants are feasible, from simple unfilled polymers for small-valued capacitors (k = 25) to amorphous metal oxides (k = 950) to highly ordered mixed oxides for the highest possible dielectric constants (k > 1000). There are essentially no fabrication issues for inductors; they are simply shaped conductors made from the interconnect metallization already present in the boards. These three types of films can be formed subtractively or additively by sputtering, CVD, evaporation, anodization, dry oxidation, solgel, spin-on, doctor-blade coating, chemical conversion, and many other techniques. Etching options include liquids and a variety of reactive and unreactive, directed or nondirected plasmas. They can be modified by annealing, exposure to chemicals, or an array of surface treatments. A classification scheme of films based on manufacturing methods is shown in Table 1.4. Integrated passives are not a new idea; they have been used for decades in ceramic and some organic substrates under the name hybrids. Thick-film pastes of conductors and dielectrics are used to form resistors, capacitor dielectrics, and spiral inductors that are fired simultaneously with the green tape of the insulating layers. However, the firing requirements mean that this technology is not transferable to heat-sensitive organic substrates. Glass has been used for integrated passive substrates by Intarsia, and silicon had a brief period of use as an MCM substrate; Bell Labs and nChip utilized an integrated decoupling capacitor as part of the build-up over a silicon substrate for their MCM designs. Organic substrates make up the vast majority of interconnect boards due to their low cost, and it is here that integrated passive efforts are most important. Because organic boards cannot tolerate temperatures much above about 250C, many processing options are not possible, including all involving fired ceramic thick films. Also, vacuum processing is not available in many board shops. Whatever methods and materials are chosen must be compatible with the boards conductors and insulation layers already in place, integrated passives already in place, and any subsequent fabrication. A search of the literature reveals that most papers for integrated resistors and capacitors on organic boards involve a demonstration of a specific film technology (often sputtered) on a specific substrate, generally leading to either a test structure to measure film properties or to a simple system such as a filter or a terminator, possibly with an inductor thrown in to complete the device. Integrated inductors pose little fabrication and material challenges, so most papers on them concentrate on

16

INTRODUCTION

Table 1.4 Thin Film

Comparison of electronic film technologies Polymer Thick Film Ceramic Thick Film Cast, screen print, or stencil glass paste, functional filler, and organic binder, then fire to remove binder 6001000C Additive processing Thickness = few microns to mils Filled glasses, oxides Medium capacitance as they are thick, but has high k Widths and spaces down to mils Less controllable tolerance Stable values with time and humidity

Sputtering, CVD, evaporation. Spin-on, cast, screen print, Similar to IC technology. or stencil polymer materials Requires vacuum with functional filler, then cure polymer 100250C Subtractive processing Thickness < few microns Metals, oxides, but rarely polymers Higher capacitance as they are thin Capable of smaller width and spaces down to microns Better dimensional tolerance Most have stable values with time and humidity 100250C Usually additive processing Thickness = few microns to mils Filled polymers Lower capacitance as they are thick Widths and spaces down to mils Less controllable tolerance Reliability and stability a limiting concern for many, and a major area of R&D on these materials Least expensive

Most expensive

In between

their design. Few papers have addressed the full integration of resistance, capacitance, and inductance (R, C, and L) on one substrate. Although an exact count of the papers has not been performed, some generalizations can be made. Most of the reported efforts that involve organic substrates employ sputtering of the resistor material or capacitor dielectric. TaNx is the clear favorite among sputtered resistor materials due to its advantageous combination of properties that were well known before integrated passives became an issue: appropriate material resistance, ease of processing, and stability with time and temperature. TaNx, together with CrSi, NiCr, and a few other sputtered alloys, cover the range of resistance up to a few hundred /square. A higher range is necessary for resistors up to a M, requiring perhaps as much as 10,000 /square. Much less integrated resistor development has occurred there, but sputtered cermets such as CrSiO or TiNxOy seem to be the most feasible. For capacitor dielectrics, the situation is much less clear. Almost any dielectric that can be formed has been investigated, so many that their discussion will be left to three chapters later in this book. The materials and fabrication of capacitor dielectrics is the major hurdle in the development of fully integrated passives on organic substrates.

1.6

REASONS FOR INTEGRATING PASSIVE DEVICES

17

1.6 REASONS FOR INTEGRATING PASSIVE DEVICES Although it is tempting for engineers to look only at the technical aspects, these issues should only serve as inputs to business models to determine the ultimate worth of changing technologies. Deciding which engineering option will provide a higher return on each dollar invested cannot be based solely on the goal of lowering the cost to make the same product; the implications are much more nebulous and include concepts such as increased functionality, added product value, higher consumer appeal, and the ability to make products that cannot be realized with the older technology. Some of these issues are difficult to quantify; for instance, what is the added dollar value to a cell phone that is made 20% smaller? There is a real worth to this type of improvement, but it is a function of consumer psychology, which is notoriously hard to enumerate. The merely technical issues often can be quantified fairly accurately. For integrated passives, the reasons in favor of integration can be broken down into these motivations: 1. Reduced system mass, volume and footprint. Individual packages are eliminated and passives can go underground, leaving more room on the surface for ICs. 2. Improved electrical performance. Integrated passives can have lower parasitics, particularly, much lower inductance in capacitors. 3. Increased design flexibility. The components resistance, capacitance, or inductance can be sized to any desired value within the technologys range. 4. Improved reliability. Solder joints are eliminated. 5. Reduced unit cost. Integrated passives can be formed simultaneously and with very low incremental cost. Also, they are inherently lead-free. These issues will be introduced briefly below, and then examined at length individually later in this book. Not all integrated passives have smaller footprints than the surface mount devices they might replace. In fact, the higher values of integrated capacitors and inductors would occupy a much larger area. For example, a 100 nF integrated capacitor formed by sputtering 3000 of Al2O3 onto a circuit board would require almost 4 cm2 of area, compared to only 0.01 cm2 for an 0402 surface mount capacitor plus its associated keep-away distance [13]. Similarly, a 50 nH planar spiral inductor could be made from five turns of 5 mil conductor, but would have an outer diameter of 3.3 mm. Furthermore, this inductor would require a keep-away distance on all layers of the substrate, not just one like a capacitor or a resistor, about equal to its radius to avoid interference from other metal with its electromagnetic field, which would reduce its effective value. Its total area would be 0.34 cm2 and would be effectively multiplied times the number of layers in the substrate that must be kept clear. Integrated resistors and small-valued capacitors are much closer to, or even smaller than, their surface-mount size. The reduction in system form factor with integrated passive technology would come from the fact that integrated passives, re-

18

INTRODUCTION

gardless of their footprint, can be fabricated under the surface of the board, which frees up top-surface area that was formerly occupied by surface-mount passives. Since many wireless and mixed-signal systems have something like half of the board surface occupied by passives, the footprint reduction can be significant. Additionally, system mass may be reduced by stripping an integrated resistor, capacitor, or inductor down to only its electrically active portions, leaving less than a milligram of metal and/or dielectric. The integrated passive would depend on the substrate for mechanical support and the layers above and below it for environmental protection, eliminating the mass and volume of the individual package. The price paid for this is that additional board layers may be required to accommodate these passives in their integrated form, adding cost and complexity to the manufacturing process, which can offset some of the benefits of freeing up surface area and reducing volume or mass. This is an important trade-off in passive integration and will be a major driving force in the economic viability of any integrated approach. It is not clear that more layers will always be required for integrated passives; savings in wiring and, especially, vias required to route all passive connections to the surface may be significant if the passives can be placed on any desired layer. As previously mentioned, active logic devices can be scaled down to nanometer scales, principally by improvements in processing technology, since they can operate with arbitrarily few electrical quanta. But passives may have to maintain values of resistance, capacitance, and inductance regardless of their size, and footprint reduction can come about only be improvements in materials to give higher specific values per unit area. This is particularly problematic for integrated capacitors. Due to their simplified structure and lack of leads and contacts, integrated capacitors and resistors tend to have considerably less parasitic inductance than their surface-mount counterparts. Also, short leads to the integrated capacitor or inductor can result in less parasitic resistance. As a result, integrated passives tend to be purer components with less undesired properties to be taken into account in the design phase. Lower parasitic inductance is particularly important for capacitors in high-frequency applications such as decoupling and RF filtering since, above the self-resonance frequency, the inductive properties of the capacitor dominate the components behavior, making it act completely like an inductor. Integrated capacitors can be fabricated that have far higher self-resonant frequencies and, therefore, a larger usable frequency range, than is possible with any discrete capacitor, no matter how much the latter is optimized for low inductance. This is a major motivation for integrating capacitors, as will be discussed in the section of this book dealing with decoupling applications. An additional electrical advantage comes about because the value of integrated passives can be specified exactly (Figure 1.12). If an 18.2 nF capacitor, a 2360 resistor, and a 14.6 nH inductor are needed for a design, the integrated passives can be sized to give those values (within tolerance limits); it is not necessary to choose the next closest value from a catalog of discrete passives or to have to create the values by stringing together discretes in series and/or parallel. Using multiple discretes may take up a large amount of board space, require a large number of leadattach steps, and exacerbates problems associated with parasitics.

1.6

REASONS FOR INTEGRATING PASSIVE DEVICES

19

Figure 1.12 Integrated low-pass filter made with custom-sized components by Integral Wave Technologies for NASAs Langley Research Center.

With regard to reliability, the use of integral passives does eliminate two solder joints per passive, which are a major failure point for systems with discrete components. However, the use of new materials and fabrication methods necessary for integration may bring with them new failure modes that have not been fully revealed. There is much research to be done to validate the conjecture that integrated passives enhance system reliability. The standard environmental and thermal stress tests will still apply but, whereas discrete components may be tested on their own to identify failure modes not associated with the solder joints, integrated passives must always be tested in the systems that they will occupy, since the interconnect substrate forms their packaging. Of particular concern is the result of mechanical stresses on largearea capacitors and long resistors brought about by CTE mismatch, layer-to-layer slippage during fabrication, and flexure.

20

INTRODUCTION

Issues regarding lower unit cost were briefly addressed in the previous section. Because integrated passives can be formed simultaneously, the incremental cost of producing just one more is nearly zero. This characteristic is attractive for systems requiring dense placement of passives, which is the direction most systems are heading in. A major issue in business models for integrated passives is whether all of them can be integrated or only some. If they can all be integrated, then there is no need for any pick-and-place equipment for surface-mount passives, just for the ICs, and the cost model needs to consider only one technology set for passives: integration. However, if only most of them can be integrated, then it would seem more difficult to be cost-competitive since the manufacturing facility must support both technologies at once. Some passives, such as large-value capacitors and inductors, may be very challenging to integrate due to their large footprints, even in buried layers, and may be best left as surface mounts. On the plus side, integrated passives are inherently lead-free. At present, economic analysis to determine the feasibility of integrated passives is specific to both the application and the integrated passive technology.

1.7 PROBLEMS WITH INTEGRATING PASSIVE DEVICES The problems with implementing integrated passives on organic boards are as well understood as their potential benefits. These include: 1. Indecision on materials and processes. Research continues on many resistor materials and capacitor dielectrics. 2. Lack of design tools, for both component sizing and system layout. 3. Requires vertical integration. The same company must manufacture both substrates and passives. 4. Yield issues. One bad component can lead to scrapping the entire board. 5. Tolerance issues. Integrated passives cannot be presorted prior to inclusion on the board. 6. Lack of standardization. The various segments of the integrated passive industry arent speaking the same language [14]. 7. Surface-mount technology is improvingmoving towards 01005. 8. Lack of costing models. It is not easy to tell when integrated passives might be more cost effective. It is not that it cannot be done; scores of research projects have shown that the full required range of R, C, and L values are achievable on just about any substrate. The problem is that the optimal materials and processes have not been identified, if they exist for a given substrate, and that the infrastructure does not yet exist in the industry for their design and manufacture. The vast number of material and process choices was the major reason for writing this book. The physical integration of passive components into circuit boards necessitates the integration of the correspond-

1.7 PROBLEMS WITH INTEGRATING PASSIVE DEVICES

21

ing business units. For example, a manufacturer that previously made only boards but now expands into integrated passives finds itself in the business of making passive components instead of simply buying them from a catalog. That means having to understand issues of passive performance, fabrication, sizing, tolerance, parasitics, and reliability, which were previously taken care of by a separate entity. There are two main aspects to the design issue: designing the individual components and designing the components into a system. Taking the narrower one first, designing individual integrated resistors and capacitors is easy but dependent on the materials used, since this will influence the value density of the structure, such as the number of nF/cm2 for an integrated capacitor. If the ohms/square of the resistor film or the nF/cm2 of the dielectric film are known, then it is a simple matter to size the component for a required overall value. Therefore, the components material and processing technology have to be established before components can be sized. For inductors, the design situation is much more complex. Accurate sizing of a spiral inductor from first principles requires solving Maxwells equations for a spiral shape on a Cartesian geometry with various other conductors from the eventual system layout present to distort the magnetic field. Although there are some excellent approximate design tools for isolated spirals, described later in this book, the presence of other conductive materials nearby means that the design of the integrated inductor usually cant be done as a stand-alone component. Trial and error with physical prototypes will sometimes be required. With regard to overall layout, only a few programs are capable of taking integrated passives into consideration by incorporating them from SPICE-like electrical models and autorouting around them or optimizing their placement on and among layers. Doing all of these by hand is possible but can be quite tedious, and very few designers are experienced with integrated passives to the point of knowing the pertinent layout issues necessary for taking advantage of their unique electrical and size characteristics. However, progress is being made in this area by design and layout software vendors, and there is no major technological hurdle to enabling these programs to utilize integrated passives effectively and with the same ease of operation as they do for surface mount boards. Again, the processes must be established first. On the assembly side, attachment of surface-mount discretes is one of the last steps to be performed on a circuit board prior to its inclusion in the overall system. All of the layers and conductors are fully formed and tested before the passives go on. The only concession made by the board designers to the eventual presence of the surface-mount passives, and ICs for that matter, is that proper attachment metallurgy be available and that the board be able to withstand the temperatures associated with the attachment process. The attachment process is typically reflowed or wave soldering, requiring about 250C for up to a few minutes; or conductive epoxies, which usually have even milder thermal requirements. However, if integrated passives are utilized, they will be fabricated as part of the boards manufacturing flow and the portions of the board already formed will have to be able to withstand not only the thermal stresses that a particular integrated passive technology requires, but also any chemical and mechanical exposures that are involved. Subse-

22

INTRODUCTION

quent interconnect/insulator processing must not degrade any integrated passives that are already in place and any integrated passive processing must not degrade the board layers already in place. Not only are the passives integrated into the board, their processing requirements are mixed in as well. The same yield problem exists for integrated passives that is well known for integrated circuits: one bad component out of many can cause the entire board to be scrapped. The problem might not be apparent until the substrate is completed, so a considerable amount of fabrication may be wasted if the bad component is formed early on. Rework might be possible but few procedures for this have been developed or reported in the literature. This same problem was identified and solved for active integration, enabling tens of millions of components to be formed on silicon with IC yields routinely over 75%. The same issue impacts tolerance; discrete passives may be presorted by value, whereas the values for planar integrated passives will be ruled by sizing tolerances associated with film patterning or printing. In the case of integrated capacitors, because they are area-ruled, the resulting variation in value will be higher than the variation in one-dimensional sizing. Attempting to make smaller integrated passives will result in less exact values. Trimming technology for integrated passives requires further development. The use of singulated and embedded passives might help alleviate these problems by enabling sorting for yield and tolerance. Meanwhile, surface-mount technology continues to improve. On the average, surface-mount passives have decreased by about one case size every four years [1]. Sizes as small as 0201 (0.50 0.25 mm) are in use and, although it is hard to imagine them becoming much smaller, there is work in progress for 01005 components. With a 10 mil keep-away distance, the theoretical density for 0402s is 107 components/cm2 and for 0201s its 270/cm2. However, in some instances, integrated passives may be the only way to make the product possible. This situation is rapidly approaching in the case of decoupling upcoming generations of microprocessors that will draw very high bursts of current from the boards power and ground planes. Surface-mount capacitors may exhibit too much inductance to do the job and integrated capacitors may be the only way to enable these chips to function. 1.7.1 Cost Modeling The greater the detail necessary to accurately model a system, the less general and more application-specific are the results [2, 15]. This is the situation with integrated passives on organic boards. Because the specific processes and materials have not yet been reduced to a manageable number, it is not currently possible to say when passive integration is and is not economically feasible. No generalized models exist to aid the manufacturer. This sounds like a chicken-and-egg problem, but it can be solved by first assuming a specific and feasible material and process set for the existing manufacturing infrastructure and for the potential product, and then performing the costing based on that [1619]. What is the impact of passive integration on an existing board design that utilizes surface mounts? Of primary importance is that the number of layers will probably

1.8 APPLICATIONS FOR INTEGRATED PASSIVES

23

increase due to the need to accommodate subsurface passives. Also, if reduced board form factor is desired, this will also add pressure to increase the number of layers simply to accommodate the interconnects. PWB cost increases about linearly with the number of layers. Adding another signal layer to a controlled-impedance board actually requires the addition of two layers since a ground or power layer has to be added as well between the signal planes [20]. The decrease in board area will result in a more compact product, but the benefit of this is harder to put into terms of dollars than is the cost. It does have the advantage of increasing throughput since there can be more boards per panel, but board yield will probably decrease, for reasons discussed earlier in this section. There may be some decrease in wiring and, particularly, via density due to the reduced need to route to specific areas on the surface to accommodate surface-mount units. Instead, it may be possible to put the passive in any given layer and position where they are needed. Overall, each design needs to be considered on a case-by-case basis, at least until a lot more experience with these designs has been accumulated.

1.8 APPLICATIONS FOR INTEGRATED PASSIVES In principle, integrated passives can replace discretes in any application, but in what forms will they find widespread use? Except for decoupling, the circuit schematic will not generally change if integrated passives are used instead of discretes, except that slightly fewer integrated passives may be used if exact component values can be made in one unit instead of having to string discretes together in series or parallel to achieve a specific value. Therefore, replacement of resistors and most capacitors will be one-to-one. This section will discuss some of the most likely initial applications and describe what factors will motivate the switch from surface mount to integration. 1.8.1 Replacing Surface Mount Discretes with Arrays and Networks Individual surface mount discrete passives can be replaced with a smaller number of passive arrays or networks, resulting in significant conversion cost savings with a minimum of design and process changes. Arrays will have the same number of total contacts but are achieved with fewer component placements. Passive networks contain internal connections that result in fewer mounted components and contacts. Not only are there fewer components to mount, but each one is bigger than the individual units it replaces, and therefore easier to handle, with a smaller total footprint on the board than the group it replaces. Since this brings almost all of the advantages of passive integration with few of the problems, both listed above, this trend is well underway and represents the majority of integrated passive usage today, especially for units mounted on organic boards. The reason this approach has gained rapid acceptance is that it maintains the separation between passive integration issues and substrate issues. The only concession for the board is that pads be moved to accommodate the layout of the integrated surface-mount units. The board maker does not

24

INTRODUCTION

have to be in the passive manufacturing business and the integrated units can be presorted and tested to avoid yield and tolerance problems. Numerous configurations of R + C networks are available in quantity from reputable vendors and custom arrangements are possible. Integrated inductors are also available. Off-the-shelf versions include filters, terminators, and low-inductance decouplers. With diodes and transistors added to silicon substrates, networks can include ESD protection, oscillators, and amplifiers. RC termination is a popular application for passive networks since densely packed groups of resistors and capacitors are required to terminate wide bus lines. Integrated RC termination networks can be formed in single packages with footprints to match the physical bus width on the board and will require only half the number of pads since there are internal RC connections within the unit. There is much more to be squeezed out of this approach as the passive networks become merged with active devices to form what NEMI refers to as functional modules, which could include, for instance, Bluetooth or GPS subsystems mounted as surface units on the primary interconnect board. There is tremendous potential flexibility with little downside. For example, a cell phone maker could include a GPS receiver in the form of a surface-mount module that would include integrated passives, integrated antennas, as well as integrated transistors on one piece of silicon in a single chip-scale package. They would not have to worry about going into the business of manufacturing GPS systems and could also upgrade or switch vendors when required, possibly with the same surface-pad layout. At this point, the distinction between which is the primary interconnect substrate and which is the add-on module becomes blurred. In the limit, the main board may have no passives at all and simply provide interconnection among various functional modules. 1.8.2 Decoupling High-frequency operation of digital logic circuitry places severe demands on power distribution systems to supply stable, noise-free power during the clock-driven simultaneous switching of millions of transistor gates. Decoupling capacitors are necessary to supply these large current surges, ramping as fast as 500 A/ns, to highpower microprocessor and logic ICs during the switching portions of the clock cycles. The purpose of this is to ensure that unacceptable drops in logic voltage levels do not occur due to the high current demands on a power supply that may be located many inches away down narrow conductor paths. Between cycles of current demand, the power distribution system recharges these capacitors in preparation for the next switching cycle. It is not too simplistic to think of the capacitors as actually providing the power to run the chips with the power supply merely acting as a battery charger during low-demand periods. In other words, the impedance of the power supply is too high to prevent voltage drop during high-demand periods, so the capacitors must provide low-impedance power to the chip. Figure 1.13 shows a large group of surface-mount decoupling capacitors on the opposite side of an FR4 board from a PowerPC microprocessor. The two main requirements for these capacitors are that they provide sufficient charge to run the

1.8 APPLICATIONS FOR INTEGRATED PASSIVES

25

Figure 1.13 Surface-mount decoupling capacitors competing with escape conductors on the opposite side of the board from a microprocessor.

chip for one clock cycle and that they provide that power at low impedance to prevent excessive voltage drop during moments of high current draw by the chip. Of these two criteria, the low-impedance issue is the more challenging to surfacemount capacitors. The inherent parasitic inductance of surface mounts requires that many separate capacitors be arranged in parallel in order to lower the overall inductance, resulting in a large number of small capacitors instead of a few large-valued units. That means using more board area near the microprocessor, where space is at a premium anyway, and more solder joints. Also, the temperature extremes are higher near the chip, which can cause a variety of reliability problems, including failure of those solder joints. The much lower parasitic inductance of integrated capacitors, the ability to bury them beneath the surface of the board, and the lack of solder joints makes them very attractive for replacing surface-mount capacitors in decoupling. It is an important enough application to warrant an entire chapter in this book. Because of their inherently low inductance, there is no need to use multiple capacitors in parallel; a single large integrated capacitor will suffice. The inductance is so low that, when using integrated capacitors, the designer must consider the inductance of the vias and inter-

26

INTRODUCTION

connects from the power/ground planes to the capacitor, whereas these contributions are usually negligible compared to the inductance of surface-mount capacitors. The major unknown in replacing surface-mount decoupling capacitors is how much capacitance is needed. With surface mounting, an excess of capacitance is usually present because of all the units placed in parallel to lower the total inductance, but with integrated capacitors, probably much less will suffice. Exactly how much less is not fully understood and can only be determined with a combination of modeling and power/ground voltage measurements with a variety of integrated capacitor values. 1.8.3 DC/DC Conversion One application of integrated capacitors, either on a substrate or on the ICs themselves, is as charge storage elements in DC-to-DC converters. An example made by the University of Arkansas for NASAs Jet Propulsion Laboratory is shown in Figure 1.14. For example, charging capacitors in series and discharging them in parallel achieves a step-down function. If the switching frequency is high enough, rela-

Figure 1.14 Integrated capacitors over the passivation layer of an integrated circuit chip to form a DC/DC converter [21].

1.9

THE PAST AND FUTURE OF INTEGRATED PASSIVES

27

tively small capacitors can be used for small (~1 W) converters. Localized power conversion of this type becomes more and more important as IC supply voltages decrease and large currents must be supplied. 1.8.4 Passive Replacement in FR4 Developing passive integration for commodity FR4 will open up a huge market. Because it is such a large target, there is a concerted effort to solve the problems associated with integration onto this platform. In October 1998, NIST funded the Advanced Embedded Passives Technology Consortium (AEPT) to develop the materials, design, and processing technology for embedding passive devices into circuit board substrates. This combination of industrial partners and associations are tackling the parallel issues of processing, materials, design software, cost modeling, standardization, testing, and reliability for FR4. They made this task manageable by selecting a small number of integration technologies (materials and processes) and building the modeling, reliability, and costing efforts around those. As their results and products come onto the market over the next few years, many of the obstacles will be solved or made manageable, enabling integration to penetrate this market. 1.8.5 Passive Replacement in HDI The various forms of HDI interconnect will employ processing steps not common in the FR4 domain, such as sputtering, build-up, spin-on, dry etching, and more. A wider spectrum of metals and dielectrics will also be used. This provides the opportunity to employ a variety of possible integrated passive processes and materials into this maturing technology. If these are all developed in parallel, integrated passives will arrive as part of the infrastructure instead of as add-ons.

1.9 THE PAST AND FUTURE OF INTEGRATED PASSIVES Integrated RC networks on ceramic substrates consisting of barium titanate overlaid by a resistive conductor date back as far as the late 1940s. The first volume application was in the IBM 360, which utilized integrated resistors and RC terminators, also on ceramic substrates [22]. From there, development of integrated passives in ceramic substrates grew along with advances in interconnect technology to the present day. One of the most important pioneers was Robert Berry of Bell Labs, who described in the February 1963 issue of the Bell Laboratories Record the idea of using Ta simultaneously as the basis of the interconnect metal, resistors, and capacitor dielectrics of a single system [23]. He recognized the unique combination of physical, chemical, and electrical properties of Ta for integrated passives, such as its chemical stability, ability to be anodized into an excellent capacitor dielectric, and suitability as an integrated resistor when combined with nitrogen, and noted that Ta-based resistors could be trimmed to close tolerances through anodization. He reported on prototypes of modem boards containing 10 resistors from 65 to 5000

28

INTRODUCTION

and two capacitors of 20 nF each, and clock boards with 88 resistors and 14 capacitors using this technology. His 34-year-old book on thin-film processing is excellent reading even today [24]. Few articles on integrated passives outside of ceramic substrates appear before the mid 1990s. Of the over one trillion passive devices mounted on organic boards in 2003, less than 3% will be surface-mounted passive arrays and passive networks, and almost none will be fully integrated into the primary interconnect substrate. Although the share of passive integration is increasing and will continue to grow, the technology is too new to project trends accurately very far into the future. However, the factors influencing the rate of growth are easily identified and are mainly technical in nature. The broad application of integrated passives will be possible only when there are established materials and fabrication methodology for all three components. For inductors, this is not an issue. For resistors, several technologies are available for components under about 10 k and are under development for higher values. But capacitors have a long way to go, principally because of the difficulty in finding dielectric materials that are easy to process on organic substrates and provide sufficient specific capacitance to make the component footprints small enough for economical layout without excessive numbers of layers. (See Table 1.5.)

Table 1.5 Design Issues Resistors Easy if /square is known

Issues and status of integrated components Fabrication Issues Several thin-film and PTF materials available for FR4 and flex Long-established on ceramic substrates Current Status Small amount of market penetration, increasing steadily PTF promising and inexpensive, but reliability problems remain Higher values needed for thin film processes

Capacitors

Easy if nF/cm2 is known

Lack of established Little usage at this time on materials and fabrication organics due to fabrication procedure limits usage issues on organic boards Unfilled and filled polymer Long-established on can only replace low ceramic substrates values due to low specific capacitance Very Easy Requires no new technology to implement In use

Inductors

Difficult Requires solution of magnetic field in an environment of interfering conductors

1.10

ORGANIZATION OF THIS BOOK

29

The vital first step is to decide on a materials and processing technology for a given substrate. After that is done, detailed design and cost modeling can be accomplished, enabling a determination of when passive integration is worthwhile for a given product. This was accomplished decades ago for ceramic substrates, but they may have reached their limit in terms of values and tolerance. Also, ceramics make up only a very small fraction of total board sales. For organic substrates, the large number of potential materials and processes have yet to be reduced to a manageable list of realistic candidates. This is farther along for FR4 than for other organic boards, and significant market penetration is expected in coming years. As integrated passives begin to work their way into accepted practice, there will initially be minimal changes to existing board materials and procedures. Integrated passives will be perceived as something added to the kinds of circuit boards that have been manufactured for many years. As they gain acceptance, hopefully by showing their worth in terms of performance, form factor, and the associated financial benefits, board fabrication and materials will be altered to enable more latitude in integrated passive implementation in order to further take advantage of their unique characteristics. Probably the best way to foresee what these concessions may be is to gain a thorough understanding of the technologies required for passive integration and see how these fit in with current interconnect substrate practices. With the advent of new substrate materials, such as various flex films, and the development of high-density interconnect line and via sizes, there is an opportunity to dovetail with other process modifications such as passive integration.

1.10 ORGANIZATION OF THIS BOOK The purpose of this introductory chapter has been to describe some of the advantages and challenges of integrated passives in one place. Various researchers have identified almost all the important issues of design, fabrication, and utilization over the past few years, so the challenges are clear. The rest of this book will concentrate on addressing these issues individually and in depth in order to assist in their solution, leading to more widespread use of integrated passive components. When attempting to describe a developing technology area in electronics, there is a fundamental decision to be made between basing the writing on materials or on processes. The authors have organized around materials and placed the candidate processes in context around them. This is a less limiting approach in case new processes become available to create the materials described. There are probably fewer unknown materials to be discovered than processes. For the individual passive componentsresistors, capacitors, and inductors the treatment will start with a description of how the various performance parameters of the components are quantified, such as value (ohms, farads, henrys) and the effects of various operating parameters on value (temperature, frequency, voltage, etc.). The purpose of doing so is to provide a language for discussing the relationships among materials, integrated passive configuration, and resulting electrical performance. This is followed by component-level design rules that relate the

30

INTRODUCTION

shape, size, and footprint of integrated passives to these performance parameters. Then, for resistors and capacitors, there is a brief theoretical treatment of the resistance and dielectric properties of films that are pertinent to integrated passives. After that, the candidate materials are listed with a discussion of the composition and morphology effects on component performance and the processing options for making integrated passives from them. Chapters are provided on two important topics relating to integrated capacitors: yield issues and electrical performance. Because integrated capacitors will be largearea film structures, they are particularly susceptible to defects that can result in the loss of the entire board, so a detailed treatment of these problems is appropriate. Integrated capacitors enjoy a considerable inductance advantage over surface-mount discretes to the point that it can be difficult to actually measure quantitatively. This is followed by chapters on electrical measurement techniques and models, a survey of current integrated passive applications, and a cost analysis.

REFERENCES
1. National Electronic Manufacturing Initiative Roadmap, 2000 edition, Chapter 22, Passive Components, p. 1, 2000. 2. J. Rector, Economic and Technical Viability of Integral Passives, In Proceedings of the 48th Electronics Components and Technology Conference, Seattle, WA, p. 218, May 1998. 3. Passive Component Industry Magazine, p. 8, May/June 2001. 4. R. Ladew and A. Makl, Integrating Passive Components, In ISHM 95 Proceedings, p. 59, 1995. 5. J. Rector et al., Integrated and Integral Passive Components: A Technology Roadmap, In Proceedings of the 47th ECTC Conference, p. 713, 1997. 6. M. Leftwich, Between the LayersA Case Study of PWB Design Options from Current Surface Mount Component Technology to Embedded and Integral Component Technologies. Masters thesis, University of Arkansas, p. 9, 2001. 7. D. Liu et al., Integrated Thin Film Capacitor Arrays, In Proceedings of the International Conference and Exhibition on High Density Packaging and MCMs, IMAPS, p. 431, 1999. 8. J. Dougherty et al., The NEMI Roadmap Perspective on Integrated Passives, Advanced Embedded Passives Technology Website: aept.ncms.org/papers.htm, 2001. 9. H. Kapadia et al., Evaluating the Need for Integrated Passive Substrates, Advancing Microelectronics, 26, 1, 12, Jan/Feb 1999. 10. C. Coombs (ed.), Printed Circuits Handbook, 5th ed., McGraw-Hill, p. 1.17, 2001. 11. W. Brown (ed.), Advanced Electronic Packaging, IEEE Press, 1999. 12. M. Nielsen et al., Demonstration of Integral Passives on Double Sided Polyimide Flex, In Proceedings of the 2000 International Conference on High-Density Interconnect and Systems Packaging, p. 351, 2000. 13. M. Thakre, Integral Planar Inductors. MS thesis, Dept. of Chemical Engineering, University of Arkansas, December 2000.

REFERENCES

31

14. D. McGregor, Standard Development Efforts for Embedded Passive Materials, Advanced Embedded Passives Technology Website: aept.ncms.org/papers.htm, 2001. 15. P. Sandborn, B. Etienne, and D. Becker, Analysis of the Cost of Embedded Passives in Printed Circuit Boards, Advanced Embedded Passives Technology Website: aept.ncms.org/papers.htm, 2001. 16. B. Etienne and P. Sandborn, Application-Specific Economic Analysis of Integral Passives, In Proceeding of the IMAPS Advanced Packaging Materials Processes, Properties and Interfaces Symposium, Braselton, GA, pp. 399404, March 2001. 17. M. Realff and C. Power, Technical Cost Modeling for Decisions in Integrated vs. Surface Mount Passives, In Proceedings of IMAPS 3rd Advanced Technology Workshop on Integrated Passives Technology, Denver, CO, April 1998. 18. D. Brown, The Economics of Integrated Passive Component TechnologiesAn Ongoing Exploration of a Life Cycle Cost Analysis, Advancing Microelectronics, 25, 3, 55, 1998. 19. M. Scheffler et al., Assessing the Cost-Effectiveness of Integral Passives, Microelectronics International, 17, 3, 11, 2000. 20. C. Coombs (ed.), Printed Circuits Handbook, 5th ed., McGraw-Hill, New York, p. 1.21, 2001. 21. M. Wasef, Fabrication of Anodized Tantalum Oxide Integrated Capacitors on Singulated Chips with Active Devices. Ph.D. dissertation, Dept of Chemical Engineering, University of Arkansas, May 2001. 22. R. Cote, Back to the FutureIntegrated Passive Devices, Advancing Microelectronics, p. 20, Jan/Feb 1999. 23. R. Berry, Tantalum Thin-Film Circuitry and Components, Bell Laboratories Record, Feb. 1963. 24. R. Berry, P. Hall and M. Harris, Thin Film Technology, Van Nostrand, New York, 1968.

Additional References
The following are overview articles on integrated passives. S. Bhattacharya and R. Tummala, Next Generation Integral Passives: Materials, Processes and Integration of Resistors and Capacitors on PWB Substrates, Journal of Materials Science: Materials in Electronics, 11, 253, 2000. R. Frye, Integrated Passive Components: Technologies, Materials and Design, International Journal of Microcircuits and Electronic Packaging, 20, 4, 578, 1997. R. Frye, Passive Components in Electronic Applications: Requirements and Prospects for Integration, International Journal of Microcircuits and Electronic Packaging, 19, 4, 483, 1996. E. Logan et al., Advanced Packaging of Integrated Passive Devices for RF Applications, In Proceedings RAWCON 98, 1998 IEEE Radio and Wireless Conference, IEEE, p. 289, 1998. K. Paik, Studies on Thin Film Integral Passive Components for Mixed Mode Multichip Module (MCM) Applications, In Proceedings of 1995 Japan International Electronic Manufacturing Technology, 1995 Japan IEMT Symposium, p. 365, 1996. C. Power, M. Realff, and S. Battacharya, A Decision Tool for Design of Manufacturing

32

INTRODUCTION

Systems for Integrated Passive Substrates, In Proceedings of IMAPS 4th Advanced Technology Workshop on Integrated Passives Technology, Denver, CO, April 1999. J. Rector, Jr. et al., Future Trend Towards Integral Passives, In 17th Capacitor and Resistor Technology Symposium, CARTS 97, p. 1, 1997. R. Tummala et al., SOP Microelectronics for the 21st Century with Integral Passive Integration, Advancing Microelectronics, 27, 1, 13, 2000.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 2

CHARACTERISTICS AND PERFORMANCE OF PLANAR RESISTORS

RICHARD K. ULRICH

The treatment of integrated resistor technology is split into two chapters. This one is a discussion of issues common to all such components including layout patterns of planar resistors, the metrics used to describe the resistivity of materials, the effects of temperature, time and film morphology, a brief treatment of electrical conduction in resistive materials, and issues important in sizing integrated resistors, such as heat dissipation, tolerance, and parasitic capacitance. Chapter 3 uses this general information to analyze the performance characteristics that can be expected from the various candidate integrated resistor materials and describes the process options for making them. It concludes with a listing of the commercialized technologies for integrated resistors.

2.1 PERFORMANCE PARAMETERS 2.1.1 Resistance of Planar Resistors Integrated resistors are fabricated either by depositing and patterning a layer of resistive material or by printing resistive paste in series with an interconnect line on an insulating substrate. In keeping with the concept of a planar, stacked assembly, the resistor will be a film of material, probably between a few hundred angstroms and a few microns thick (Figure 2.1). Assuming that all of the resistance is in the resistor material and not in the interconnects, the resistance of the structure is

L R= Wt
33

34

CHARACTERISTICS AND PERFORMANCE OF PLANAR RESISTORS

Figure 2.1

Layout for a simple integrated resistor.

where: R = resistance, = resistivity of the material, -cm L = length of the strip, cm W = width of the strip, cm t = thickness of the strip, cm The resistivity of a material is an intrinsic property and is a function of composition and microstructure. For thin films, the resistivity can be somewhat different from that of bulk materials, and is generally higher. The reciprocal of resistivity is conductivity in (-cm)1, sometimes referred to as Siemens. Sheet resistance is defined by

R= t
where: Rs = /t = sheet resistance, /square Ns = L/W = the number of squares L = length of the strip, cm

=RN W L
s

The sheet resistance is the resistance of a square of material (L = W) when the electrical contacts cover opposite edges completely, as in the second part of Figure 2.2. The size of the square is irrelevant as long as length equals width and the contacts completely cover two opposing sides. When long, narrow materials are used, the resistor is thought of as squares in series. Resistors consisting of many squares are usually formed in a serpentine pattern to fit into an allocated substrate area with corner squares counted as somewhat less than a full square (0.556 squares) since the current does not have to traverse the entire side-to-opposite-side distance. Thus, a material with a resistivity of 1 m-cm that is 1 m thick would have a sheet resistance of 10 /square and this

2.1

PERFORMANCE PARAMETERS

35

Figure 2.2

Resistor geometries expressed as numbers of squares.

number, multiplied by the number of squares, would give the value of the resistor in ohms. The benefit of expressing films of resistor materials in /square is that it doesnt matter what the resistivity or the thickness is as long as it gives the desired sheet resistance. For example, in sputtering TaNx resistors, the sputtering conditions such as vacuum level, temperature, power, gas composition, etc. may be varied to affect both the materials film thickness and resistivity. It may be impossible to change conditions so that only resistivity or film thickness is adjusted to desired values due to the inevitable cross-dependencies of processing conditions. However, if the sheet resistance is the target variable, processing conditions can be optimized to give the desired value of /square without having to measure or specify both the thickness and resistivity. Also, the sheet resistance is a quantity easily measured with standard four-point probes or from simple test structures such as those in Figure 2.3, again without having to measure either of its two constituent variables. 2.1.2 Resistivity of Materials Required resistor values in common electronic systems span a large range: from less than 10 to well over 1 M. Its practical to build a serpentine integrated resistor with between about 0.1 and perhaps a hundred squares; resistor patterns with more squares may require excessive footprints, are more prone to yield and tolerance problems, and tend to show greater parasitic capacitance at high frequencies

36

CHARACTERISTICS AND PERFORMANCE OF PLANAR RESISTORS

Figure 2.3

Serpentine thin film sputtered CrSi resistor test structures on flex.

due to coupling between the meandering strips. Taking these as the boundaries of the design envelope, a 10 resistor fabricated from 0.1 squares would require a material with 100 /square, whereas a 1 M resistor with 100 squares would require 10,000 /square. It would be possible to cover this range with integrated resistors if they could be made with two different materials: 1. Resistor material with about 100 /square for values from 1010,000 2. Resistor material with about 10,000 /square for values from 10,0001 M If these two materials are utilized, then resistances from 10 to 1 M can be covered with 0.1 to 100 squares. For resistances outside of this range, integrated resistors may not make sense. In fact, depending on the application and the number of extreme-value resistors required, it may only make sense to use one material, and to use SMT discretes for the rest. It should also be noted that its possible to make very-low-valued resistors from the interconnect metallization. For example, 2 microns of Cu gives about 10 m/square, so 100 squares would give only 1 . Subohm values are often used for current sensing. It is presumed that the integrated resistors will be in the form of thick or thin films since it is desired to embed them between layers of substrate insulating layers. To achieve 100 and 10,000 /square with 1 micron films would require 0.01 and 1.0 -cm materials, whereas with 100 films, would require 104 and 102 -cm. It then seems that, for integrated resistors, the range of interest in resistivity is between about 104 and 1 -cm. Figure 2.4 shows various materials arranged according to their resistivities along with this approximate range of interest for integrated resistors. This provides a first cut of the possible materials for integrated resistors. Although many materials fall into this range of acceptable values, some of them are difficult to deposit or etch, or have resistivities that are insufficiently stable with respect to temperature or time to be utilized in a practical manner.

2.1

PERFORMANCE PARAMETERS

37

Figure 2.4

Electrical resistivities of various materials.

2.1.3 Temperature Effects The temperature coefficient of resistivity (TCR) is defined as the temperature derivative of dimensionless resistivity and is usually expressed in ppm/C: 1 R 1 RT2 RT1 TCR = = RT1 T2 T1 R T For resistor materials instead of the resistors themselves, the values of R may be replaced by the materials resistivity in -cm [1]. For most applications, the ideal values of TCR would be zero so that the value of the resistor is constant under any operating temperature. As a general guideline, the percent variation in resistance over the standard military operating range of 55 to +125C is the TCR in ppm/C times 0.018, assuming that the TCR is constant. Therefore, if a resistor has a TCR of 100 ppm/C, it will increase by 1.8% over this range or, with a TCR of 300 ppm/C, it would decrease by 5.4%. In some applications, such as thermistors used to measure temperature, the TCR is made purposefully large and reproducible. Also, in RC networks where the capacitors have a slightly positive temperature coefficient of ca-

38

CHARACTERISTICS AND PERFORMANCE OF PLANAR RESISTORS

pacitance (TCC), a correspondingly negative TCR is sometimes used to maintain a constant RC time constant. For example, the coefficient for a Ta2O5 capacitor is about +200 ppm/C, so the coefficient for TaNx resistors can be set to 200 ppm/C by optimization of the sputtering conditions. Some materials, such as pure metals, cannot be made to have a negative TCR and could not be used as a temperaturecompensating resistor against a capacitor with a positive TCC. The voltage coefficient of resistance (VCR) is similarly defined: 1 RV2 RV1 1 R VCR = = R V RV1 V2 V1 V2 = 50 V and V1 = 5 V are commonly used [2]. Significant levels of VCR are only observed when the voltage drop over the resistor is large, and even then it is usually less than about 5 ppm/volt. The noise index is a measure of the voltage fluctuations over a resistor that is being driven by a purely DC voltage and is expressed in dB:
2 V no ise Noise Index = 20 log VDC

where the noise voltage is measured in microvolts. By this measure, an rms noise of 1 V at 1 V DC would give 0 dB of noise. Noise indices under 30 db are typical. Smoother substrates and resistor materials result in less noise. 2.1.4 Value Stability The stability of a resistor refers to how its resistance changes with time under conditions of temperature, humidity, current, etc. These changes may be due to recrystallization, hydration, oxidation, and other chemical alterations of the resistor material as well as effects at the conductorresistor interface. The value can drift up or down, depending on the mechanisms involved. For instance, it would increase with time if a metal alloy resistor were oxidized, even just on the surface, due to contact with humidity and temperature, or it might drop if high operating temperatures caused recrystallization of the metal lattice resulting in a more regular structure. Figure 2.5 shows the upward value drift with temperature for plated NiP resistors intended for use in FR4. TaNx is a popular material for resistors in part because the high melting point of Ta (2996C) implies that the TaNx microstructure will be more resistant to crystal change at slightly elevated temperatures than metal compound resistors made from metals that melt at lower temperatures. Metals with high melting points and low reactivities, especially to oxidation, are preferred components for integrated resistors. Oxidation of interconnect/resistor interfaces would result in increased values, which is a major concern with the use of carbon-filled polymer thick-film resistors that make contact with Cu or Al metallization. Although the tendencies of the various resistor materials to be chemically changed with time, temperature, and humidity can be ranked, it is not possible to

2.1

PERFORMANCE PARAMETERS

39

Figure 2.5

Resistor drift with time and temperature for Ohmega-Ply-plated NiP on FR4.

use that information to predict quantitatively how the value will change for a resistor that has been integrated, due to the influences of the resistors resulting thermal and packaging environment. This is much easier for discrete resistors that are packaged in the same type of enclosure every time. Since it is also not usually practical to wait for years to evaluate their behavior in field usage conditions, standard accelerated testing procedures may be used to give some indication of the amount of drift expected. Typical accelerated tests for integrated resistors should include the same ones used for reliability testing, such as 1000 hrs at 150C and 1000 hrs of 85C + 85% relative humidity. The acceleration factors, the ratio of corresponding field usage time to accelerated testing time, are notoriously hard to quantify, but it is agreed that they are exponential in temperature in accordance with the Arrhenius rate expression. The acceptable amount of value drift from these tests depends on the tolerance required by the application. Heat treatments can accelerate this aging process and provide much better subsequent stability. Resistor values are sometimes purposely set below the desired values at manufacture and then raised to a more stable value through a short temperature treatment; 5 hours at 250C is typical [3]. This treatment might be on the high end of what some organic boards could withstand. There are no reports found in the literature of rapid thermal aging using halogen lamps or lasers, but this should be investigated due to possible advantages of low thermal stress on the parts and high throughput. Various passivation schemes are often used with discrete resistors such as overcoats of SiO2, SiN, or polymer, and these should be effective on integrated resistors as well. Some materials, such as TaNx, may be surface oxidized on purpose to prevent further changes. Integrated resistors may not require a pas-

40

CHARACTERISTICS AND PERFORMANCE OF PLANAR RESISTORS

sivation layer if they are buried deep enough in the substrate so that the board itself provides protection. Other factors such as film stress and adhesion are important to yield and stability, particularly for thin-film resistors. If the resistive material is much thinner than the interconnect material, the resistor must go down onto the substrate first to avoid having to step over a large ledge with a thin material. Resistor thicknesses of under 1000 are typical, in comparison with 20,000 of sputtered conductor or even more for plated metals. This usually means that the conductor metal will have to be etched after the resistor material is patterned and, as a result, the thin film of resistor material must be unaffected by the metal etch to maintain tolerance. Tensile stresses can lead to resistor cracking, especially if a thin, low-CTE resistor material such as a metal alloy (CrSi, TaNx) is deposited on a thick, high-CTE substrate such as a polymer and exposed to elevated operating temperatures.

2.2 RESISTANCE IN ELECTRONIC MATERIALS 2.2.1 Resistivity and Charge Carriers This section will present a brief explanation of conduction theory in order to help the reader qualitatively understand the effects of composition, microstructure, and temperature on the integrated resistors behavior. This is a rich and well-developed area of materials science, and there should be no trouble finding deeper treatments in both the cited literature and in a variety of books on electronic materials science of whatever specific topics are of interest [4]. The conductivity of a material is the sum of the conductivities of all mobile charge carriers: 1 = = (1.60 1019) (|zi|Cii) where: = conductivity, 1/-cm = resistivity of the material, -cm zi = absolute value of the charge on charge carrier i Ci = concentration of charge carrier i, charges/cm3 i = mobility of charge carrier i, (cm/sec)/(volt/cm) Except for optical transparency, there may be no intrinsic material property that varies over such a wide range as electrical resistivity. Not even counting superconductors, the span between silver, aluminum, copper, and gold at around 106 -cm and fluorocarbon polymers, silicon nitride and NaCl at around 1018 -cm is 24 orders of magnitude, as shown in Figure 2.4. In resistive materials, the charge carriers are typically electrons, metal cations, and nonmetal anions, in order of decreasing mobility. Free electron mobilities are many orders of magnitude higher than the dif-

2.2 RESISTANCE IN ELECTRONIC MATERIALS

41

fusive hopping mobilities of the much larger and more massive cations and anions. As a result, even a small concentration of electrons will dominate the conduction mechanism; electrons are the only charge carriers that must be considered when attempting to explain the resistive behavior of the material. At one extreme of this trend are metals and their alloys, in which each atom in the material contributes at least one, and maybe as many as five, electrons to the conduction band, resulting in the lowest resistivities of any room temperature solid. In the middle, an ionic oxide such as TiO2 has a potential charge carrier in every Ti+4 and every O2, but the vast majority of conduction comes from a much smaller concentration of free electrons, maybe only one per millions of TiO2 molecules. Since TiO2 has a much lower free electron concentration than metals, its resistivity is much higher. At the other end are the purely ionically conducting solids, such as NaCl, which have almost no free electrons and utilize only Na+ and Cl ions as charge carriers. These are some of the most resistive materials known. Materials that rely exclusively on ionic conduction are far too resistive to be used as integrated resistors, so electrons are the only charge carriers that need be considered when evaluating candidate materials. At the other extreme, all pure metals and almost all metal alloys are too conductive to be used as integrated resistors. It should be noted that the conductivity of oxides varies over almost the entire span in Figure 2.4, from tens of m-cm for cadmium oxide to over 1015 -cm for aluminum oxide, whereas polymers, pure semiconductors and metals cover a much smaller range. This is due to the wide range of electron concentrations for the various oxide materials. Simple conduction by free electrons moving under the influence of an electric field requires no further explanation, but there are a couple of variations on this that are more complex but germane to integrated resistors. 2.2.2 Semiconducting Oxides When free electrons are present, the fraction of current carried by ions is usually negligible by comparisonless than about 1/1000 for NiO and CuO. These types of conductors fall into two categories: metal-excess semiconductors and metal-deficient semiconductors. As an example, consider the metal-excess semiconductor ZnO shown in Figure 2.6. Stoichiometric ZnO would achieve charge balance by having exactly one Zn+2 for every O2 but if there is an excess of Zn+2, there will have to be free electrons to balance the extra cations. This material would be considerably more conductive than stoichiometric ZnO, with electrons carrying almost all the current. Other examples of this type are Ta2O5, TiO2, WO3, and SnO2. The addition of small amounts of cations with other valances can produce large changes in the resistivity of these kinds of materials. For instance, the addition of 1 mole percent of Al2O3 to the ZnO example shown above will increase its conductivity considerably, whereas addition of Li2O will lower it. The reason lies in the semiconducting nature of the compounds and follows the same logic as doping for semiconductors. If Li2O is added to ZnO, Li+, which has a lower positive charge than Zn+2, will replace a Zn ion somewhere but will require one less electron for charge balance (Figure 2.7).

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CHARACTERISTICS AND PERFORMANCE OF PLANAR RESISTORS

Figure 2.6

ZnO, a metal-excess semiconductor.

As a result, the number of free conduction electrons is decreased, moving the material closer to a purely ionic conductor with higher resistivity. Adding elements of higher valances, such as Al+3, works in the opposite manner, requiring extra free electrons for charge balance, thus decreasing the resistivity. The same principles can be extended to metal-deficient semiconducting oxides, such as NiO, Cu2O, and Ag2O, except that the dopant ions work in the opposite direction. For these materials, adding ions with lower valances, such as Li2O, would decrease the resistivity, whereas Al+3 would increase the resistivity [5]. Since these are almost completely extrinsic semiconductors (all charge carriers are due to doping), the conductivity is not nearly as large a function of temperature as it is in intrinsic semiconductors like pure undoped Si. Metal-excess and metal-deficient semiconduction are sometimes referred to as Wagner mechanisms, conduction that is predominately cationic or anionic are called Frenkel mechanisms, and roughly equal cationic and anionic contributions are called Schottky mechanisms. The above explanation is a very brief summary of a broad and interesting field of physical science. One immediate application to integrated capacitor dielectrics would be to add small amounts of cations to thin metal-

Figure 2.7 Li2O.

The number of free electrons in ZnO is decreased by adding small amounts of

2.2 RESISTANCE IN ELECTRONIC MATERIALS

43

excess or metal-deficient dielectrics in order to decrease their leakage. This appears to have been investigated when the Lanthanide rare earth Dy+2 was added to TiO2 in order to decrease the leakage current of this dielectric without significant change to its dielectric constant [6]. 2.2.3 Tunneling Resistor materials known as cermets consist of metallic particles, as small as 50 , embedded in a matrix of insulating material such as SiO2. As long as the particles are separated, conduction through this type of matrix will be controlled by tunneling through the insulator between the particles. In this case, the identity of the metal has little effect on the resistivity of the material, but the percent of filler has a major influence because it sets the insulator thickness between the particles. Very high resistivities along with low temperature dependencies can be achieved this way. 2.2.4 Temperature, Composition, and Morphology Effects Increased temperature decreases the mobility of electrons by creating a higher concentration of lattice vibrations (phonons) to interact with them, causing more frequent scattering. If the number of charge carriers remains constant with temperature, then the TCR will be positive for this reason. For conduction through a pure metal with a perfect lattice, resistivity is caused primarily by interactions of the electrons with lattice vibrations and, based on the Debye theory of phonon frequency distribution, the resistance near room temperature would be directly proportional to the absolute temperature. If that were the case, then the TCR would be: 1 1 TCR for pure perfect metals = = T T At room temperature, 1/T is about 3400 ppm/C, in close agreement with the measured values of 4200 for Cu, 3700 for Al, and 3900 for Au. If higher temperatures lead to increased numbers of charge carriers, then their concentration may rise faster than their mobility decreases, resulting in a negative TCR. The extreme case of this would be undoped semiconductors which, because of the exponential dependency of n and p concentrations on temperature, exhibit very highly negative TCRs, such as 73,000 ppm/C for Si. Two other mechanisms can increase the resistivity of a material in ways applicable to materials suitable for resistor integration. The addition of impurities and the inclusion of defects in the lattice will both result in increased electron scattering and higher resistance. Actually, both of these are similar in action since they each change the crystal structure from the regular ideal periodic arrangement. Adding a metal to another pure metal to produce an alloy normally results in a more resistive material than either pure component since the added metal is seen

44

CHARACTERISTICS AND PERFORMANCE OF PLANAR RESISTORS

as an impurity that modifies the original crystal lattice. For instance, the resistivity of Ag is 1.47 -cm and Au is 2.44 -cm, but as Au is added to Ag, the resistivity increases smoothly to a maximum of about 11 -cm at a 5050 atomic mixture, then decreases smoothly back to the resistivity of pure Au. The other effect, increased resistivity due to structural defects, may be brought about by making the film polycrystalline or by introducing vacancies, interstitials, and dislocations. There is an important advantage to decreasing the conductivity of a material in this way for use as a resistor. Pure metals are generally too conductive to be used as integrated resistors but mixing them with nonmetallic elements such as N or Si increases their resistance by decreasing the number of free electrons and has the added advantage of decreasing the TCR, sometimes to near zero. The reason that this happens is that the total resistance can be considered to be a combination of different electron scattering phenomena: thermal, compositional, and structural. If the scattering mechanism is completely thermal, as it is for pure metals with perfect lattices, the TCR will be very high but if the resistance is instead dominated by nonthermal mechanisms so that the vast majority of electron-scattering collisions are with lattice defects whose concentration is not a function of temperature, this mechanism will dominate and the resulting resistivity will be only a weak function of temperature. As a result, several metal-based compounds exist with sufficiently high resistivity and low TCR to be useful in integrated resistors, including CrSi, TaNx, and NiCr. Purposely depositing resistor films with a high concentration of crystalline defects will lead to high resistivity but at the risk of poor time stability. Large amounts of defects are thermodynamically out of equilibrium with a perfect lattice and, with time, can precipitate out to phase boundaries, resulting in lowered resistance with time. Thermal annealing steps following resistor formation can accelerate this process and stabilize the films against further changes during field usage. The mean free path of electrons in common electronic metals at room temperature is about 200400 and when film thicknesses approach these values, resistivities can significantly exceed bulk values due to scattering of conduction electrons off the top and bottom film surfaces. Figure 2.8 shows the effect of both this and surface roughness on the resistivity of various thicknesses of TiNx. Utilizing this effect to increase the value of an integrated resistor can be difficult to control due to the strong dependency of sheet resistance on thickness in this regime. To convert the data in Figure 2.8 into sheet resistance, the resistivities needs to be divided by the thickness, adding even more sensitivity. Very thin films, less than a few 10s of , can have even higher resistivities due to the lack of a continuous film structure. These films are deposited, typically sputtered or evaporated, only until the nucleation islands are on the verge of agglomerating into a continuous film. TCR values for these types of resistors are very low since the metal islands have a positive TCR and electron transfer between islands has a negative TCR. However, these films are difficult to make within a few percent of the desired resistance values and also tend to be unstable, exhibiting falling values since the islands tend to conglomerate with heat and time.

2.3

SIZING INTEGRATED RESISTORS

45

Figure 2.8 Variation of tantalum nitride film resistivity with film thickness and surface roughness [7].

2.3 SIZING INTEGRATED RESISTORS Once a resistor material and process is selected, it is a simple matter to determine the length/width ratio to give any required value of resistance from the ohms/square of the material. However, to separate these two measures out of the ratio and establish the actual footprint of the resistor, other factors must be considered such as: Heat Dissipation. Integrated resistors must be designed so that the temperature rise during use will not heat them to the point where their value drifts significantly or failure mechanisms are accelerated to the point of affecting their reliability. Large-area resistors are favored regardless of their number of squares. Tolerance. Tolerance and precision improve for larger areas. Parasitic Capacitance. Long serpentine resistors will exhibit characteristics of capacitors at high frequencies due to coupling between adjacent strips, resulting in a drop in resistor impedance. Small numbers of squares and large strip spacing are favored regardless of the total area. Standing Waves and Internal Reflections. The resistor will act as a lumped rather than a distributed component only if its length is shorter than about 1/5 the wavelength, which can considerably simplify its modeling [8]. Small

46

CHARACTERISTICS AND PERFORMANCE OF PLANAR RESISTORS

numbers of squares or narrow widths, either of which can result in short lengths, are favored. Reflections at the Resistor/Interconnect Interface. The resistor width should match the interconnect width to decrease the effects of size discontinuities that would lead to reflections of high-frequency signals [8]. Heat dissipation and tolerance are usually the most important considerations, and the resistor will be sized to be just large enough to satisfy the more critical of the two. 2.3.1 Thermal Issues The following will usually be known when sizing an integrated resistor: The required value of the resistor, R The sheet resistance of the resistive material, Rs /square The required heat dissipated from the resistor, P = (V)2/R = I2R watts The maximum allowable heat flux from the resistor, P/A = q watts/cm2

Depending on the application, the designer will know either the current through the resistor or the voltage drop required. In either case, these may be conveniently expressed as the power in watts to be dissipated by the component. The maximum allowable heat flux, by convention, is expressed as the flux as if the heat were emerging from only one surface of the planar resistor. In reality, the actual distribution of heat from each of the two sides may be just about anything, depending on the proximity of each surface to the outside of the substrate and the effects of interconnect metal and other nearby heat-producing devices. Various rules of thumb exist for resistors on the surface of interconnect substrates; 1030 W/cm2 are typical. To put these heat fluxes into perspective, maximum sunlight is about 0.10 W/cm2 and the surface of a 100 W light bulb is about 1 W/cm2, so resistor-level fluxes can result in a considerable temperature rise. Moreover, integrated resistors will be buried beneath the surface of a substrate that consists of materials that are typically considered to be thermal insulators. Materials that are poor conductors of electricity are also poor conductors of heat for the same reason: lack of free electrons that can efficiently transport both electric current and heat. Assuming for the moment that the maximum power dissipation from the resistor material is established (q W/cm2), the length and width may be separated as follows: W= cm qR PRs

R L = W = NsW cm Rs

2.3

SIZING INTEGRATED RESISTORS

47

As an example, consider a 1000 resistor using TaNx with a sheet resistance of 100 /square, which will dissipate a total of 0.025 W with an upper heat flux limit of 10 W/cm2. Applying the above equations shows that the 10-square resistor should have the minimum dimensions of 0.16 mm wide and 1.6 mm long (6.2 62.0 mils). These dimensions are far larger than the lower limit of thin films photolithographic patterning, and achievable for thick-film by screen printing. The total area is slightly smaller than a surface mount 0402. Of course, it is not the heat flux thats important, but the temperature [9]. The preceding analysis was appropriate when the resistor was at or near the surface, enabling the relationship between the flux and temperature to be straightforward. The situation of heat transfer from a solid surface to air, whether free or forced convection, is simple enough and has been studied sufficiently to allow accurate predictions of component temperature based on heat flux. However, the situation is far more complex for integrated resistors inside the substrate because of the variable distance from component to surface, the complex arrangement of insulating and conductive board materials, the presence of other heat-producing integrated resistors nearby, and the presence of heat-producing ICs on the surface on top of them. As a result, simple rules of thumb based on the heat flux will rarely apply to integrated passive systems, particularly when they are densely packed in order to be more economically viable. The same heat flux that gives an acceptable temperature rise on the surface may seriously overheat the component if it is buried, especially if other components are nearby, producing their own thermal fields. In systems dense enough to benefit from integrated passives, three-dimensional finite-element modeling of the temperature distribution will probably be necessary. Many software packages are available for this purpose. Figure 2.9 shows a finite element simulation of the two-dimensional width cross-sections of three integrated resistors in a flex circuit board. The board was 0.8 mm thick and the three resistors were 0.3 mm wide. Each resistor dissipated 250 mW, and two were placed 0.3 mm from the top surface, whereas one was placed 0.3 mm from the bottom surface. Board-level cooling was provided by a 3.5 m/s air flow initially at 20C both above and below the surfaces of the flex board. The air had a heat capacity of 29 W/kg K and a thermal conductivity of 2 W/m K. The air was assumed to have a laminar profile that rose to the maximum velocity through a distance of 1.5 mm. The figure was generated by solving and coupling the NavierStokes equations to heat transfer in FEMLAB; it shows the isotherms and the temperature profile through the circuit board. Even without a proper, detailed thermal analysis, some general trends can be noted. To give some idea of the amount of thermal resistance of common substrate materials, consider the 10 W/cm2 heat flux from the above example. Using thermal conductivity values from Table 2.1, the temperature drop required to push this heat flux through only 1 mil of the various materials would be 8.4C for typical FR4, 13C for BCB, and 17C for polyimide. Metal thermal conductivities are typically about 1000 times higher than those of polymeric board materials. Metal interconnects and, especially, power and ground planes will tend to spread heat more strongly in the lateral direction rather than in

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CHARACTERISTICS AND PERFORMANCE OF PLANAR RESISTORS

Figure 2.9

Thermal profile through a circuit board containing integrated resistors.

Table 2.1 Material

Thermal conductivities of various materials Thermal Conductivity (W/cm K) 0.0003 0.0015 0.0016 0.0020 0.0025 0.0020.004 0.0010.002 0.020 0.200.35 0.84 2.37 3.98

Air Polyimide (Kapton) Silicone BCB Teflon FR4 Epoxy, unfilled Epoxy, silver-filled Al2O3 Si Al Cu

2.3

SIZING INTEGRATED RESISTORS

49

the z axis, since there is much more continuous metal laterally than vertically. With high interconnect density and/or continuous planes, the metal layers may dominate the lateral heat transport to the point where the composition and thickness of the insulating layers is of little consequence to the lateral temperature distribution. The interconnects to the resistor can also carry away a significant amount of heat from the ends of the component. The effect will be to even out the thermal flux at the surface of the board, but there can still be high temperature gradients in the vicinity of the integrated resistor since it is surrounded by insulator. Figure 2.10 shows the temperature rise of an Ohmega-Ply resistor on one side of a circuit board with and without Cu cladding on the other, illustrating the large influence of heat spreading by the Cu plane. 2.3.2 Parasitic Capacitance between Meanders Adjacent segments of a serpentine integrated resistor can capacitivly couple, resulting in a drop in component impedance at high frequencies. The effect is like having a small capacitor in parallel with the resistor. Figure 2.11 shows the measured impedance of five CrSi integrated resistors with various numbers of meandering segments using line widths and spacings of about 5 mils [10]. The impedances of the larger resistors drop at high frequencies because of the larger number of nearby segments in the serpentine structure. The resistance of the component does not affect the amount of capacitive coupling, but it does influence the frequency at which it begins to show up on the components impedance. Straight resistors show much less capacitance, but it can be important at very high frequencies [11].

Figure 2.10

Temperature rise for 250 integrated resistors with and without Cu cladding.

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CHARACTERISTICS AND PERFORMANCE OF PLANAR RESISTORS

Figure 2.11 Measured impedance of CrSi integrated resistors with various numbers of meandering segments.

The frequency in Hz at which capacitive effects begin to cause a decrease in overall impedance is 1 f= 2RC where C is the capacitive coupling between segments in F. Values of 0.084 pF/mm for 4 mil lines separated by 4 mil spaces were measured in the authors laboratory. Figure 2.12 shows that the number of capacitors is equal to one less than the number of segments (N), in this case there are six segments and five capacitors.

Figure 2.12

Five capacitive couples for six meandering segments.

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SIZING INTEGRATED RESISTORS

51

The effective length of the coupled capacitor is N1 capacitive length = (resistor length) N As an example, consider a 20 k resistor to be fabricated from 5-mil-wide sputtered TaNx with a sheet resistance of 100 /square. The length of the resulting 200 squares would be 1000 mils (2.54 cm). If this is to be fit into a square footprint, the size is easily calculated from the total required area. The area of the resistor material itself is 5 1000 = 5000 mils2 and, using equal width and spacing, the area of the gaps between meanders will be the same for a total footprint area of 10,000 mils2. Taking the square root gives 100 mils to a side. Since the pitch is 10 mils, there will be 100/10 = 10 meander segments or, calculated another way, the total length of the resistor is 1000 mils divided into segments 100 mils long, which also gives 10 segments. The capacitive length is, then, (9/10)(1000 mils) = 900 mils or 23 mm. This is all somewhat approximate since the single squares that link the meanders have been ignored and since the top and bottom of the footprint will both have resistor material, not resistor material on top and a space on bottom (think of the red stripes of the American flag), but these are small effects when the number of squares is large. 23 mm at, say, 0.084 pF/mm gives a total capacitance of 1.9 pF. Based on this analysis, the impedance of this resistor would be expected to remain constant at 20 k until about 4.2 MHz, at which time it will drop due to current bypassing the resistor through the parasitic capacitor. 2.3.3 Parasitic Capacitance to Ground The previous section dealt with the issue of parasitic capacitance between adjacent serpentine resistor segments, but, for integrated resistors, there is another even more troubling parasitic: the parasitic capacitance from the resistor film to a nearby ground or power plane. Depending on the geometry of the resistor, the vertical spacing between the resistor and a ground or power plane, the dielectric constant of the board material, and the frequency of the signal across the resistor, this effect could be minor or serious. The parasitic capacitance in question can be determined from the usual parallel plate capacitor model (see Chapter 5) using the total area of the resistor and its terminals as the area of the plates, assuming a continuous ground or power plane. However, if the width of the resistor stripe is less than five times the distance between the resistor material and the ground plane, there will also be significant fringing capacitance and the parallel plate model will not give an accurate result. For example, a resistor 1 mm square, separated from a ground plane by a 50 m (the thickness of flex) dielectric with a dielectric constant of four, would have a parasitic capacitance to ground of 0.7 pF. For equivalent circuit purposes, this should be considered as a 0.35 pF capacitor from each terminal of the resistor to ground. In some applications, this would seriously affect circuit performance, and in others it would not matter at all. But the circuit designer must be aware of this effect when designing with integrated resistors.

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CHARACTERISTICS AND PERFORMANCE OF PLANAR RESISTORS

2.3.4 Lumped Versus Distributed Performance If the resistor length is less than about 1/5 the wavelength, then it will act as a lumped component, but when larger than this, it begins to act as a distributed set of R, C, and Ls, complicating its modeling. A 1 GHz signal propagating at half the speed of light through a board has a wavelength of 15 cm. One-fifth of this is 3 cm, which would be considered quite large for an integrated resistor. For most components in laminate boards, this will not be an issue, though certainly the designers of microwave hybrids deal with this problem all the time.

2.4 TRIMMING Integrated resistors can be trimmed in much the same way that they are in hybrid circuits or discretes, using simultaneous value measurement and laser cutting. This is especially important because they cannot be presorted for value nor can they be removed and replaced. A wide variety of thick and thin film materials can be trimmed, but care must be taken to avoid damage or even perforation of insulating materials below. Figure 2.13 shows a NiP resistor trimmed with an IR laser system manufactured by Electro Scientific Industries (ESI) and Figure 2.14 shows how the same process can convert a wide bell curve of resistor values into a much smaller range. Of course, laser trimming can only increase the resistance, so the units that were higher than the target remain at their original values. Table 2.2, from an article by Fjeldsted and Chase [12], gives the sources of error for some integrated resistor materials on FR4 showing how the various contributions add up to overall tolerances of around 10%. For thin-film sputtered and etched systems, the contribution from the interconnect geometry would probably be negligible, enabling tolerances close to 5% to be achieved without trimming

Figure 2.13

Laser-trimmed NiP integrated resistor.

REFERENCES

53

Figure 2.14

Value distributions of PTF resistors before and after laser trimming.

Table 2.2 Resistor Type PTF Metal thin film Thin film on foil Specific Resistivity 1% 1% 1%

Error sources for resistors on FR4 Thickness 5% 3% 1% Resistor Geometry 15% 15% 15% Cu Geometry 5% 5% 5% Total 1216% 1014% 812%

Some accommodations need to be made to facilitate trimming, namely the proper size and placement of test pads. The exact requirements will be specific to the trimming equipment but, in general, the pads should be in a systematic xy layout with a repeated pattern, close enough to the resistors to provide accurate values but far enough from the resistors to allow the laser unhindered access. Suggested pad size for ESI equipment is a minimum of 5 mils. Their laser spot is 27 mils across and the minimum recommended resistor size for trimming to high tolerance is 10 10 mils. Resistors below 200 may require four-point Kelvin probing for 1% accuracy. Laser trimming changes the value of integrated resistors from low to higher values but they can also be trimmed from high to lower values by using a process based on ink jet printer technology to deposit conductive polymer over the top of resistors in place. This has been demonstrated with a filled polyimide that is deposited over the resistor, forming a parallel conductive path. This approach can be used to repair resistors that were overtrimmed by laser methods [13].

REFERENCES
1. K. Coates et al., Highly Reliable Embedded Thin Film Resistors in Cu/PI MCM-Ds for Aerospace Applications, In Proceedings of the 49th ECTC Conference, p. 93, 1999.

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2. J. Sergent and C. Harper, Hybrid Microelectronics Handbook, McGraw-Hill, New York, pp. 374, 1995. 3. R. Berry, P. Hall, and M. Harris, Thin Film Technology, Van Nostrand, New York, p. 271, 1968. 4. J. Watkins, Modern Electronic Materials, Butterworths, London, p. 22, 1971. 5. O. Kubaschewski and B. Hopkins, Oxidation of Metals and Alloys, Butterworths, London, p. 26, 1953. 6. G. Alers et al., Advanced Amorphous Dielectrics for Embedded Capacitors, 1999 IEEE IEDM 99-797, p. 33.3.1, 1999. 7. R. Petrovic et al., Electrical and Structural Properties of Tantalum Nitride Thin Films Deposited by Sputtering, Thin Solid Films, 57, p. 333, 1978. 8. P. Chahal et al., Electroless Ni-P/Ni-W-P Thin-Film Resistors for MCM-L Based Technologies, In Proceedings of the 48th Electronic Components and Technology Conference, IEEE, p. 232, 1998. 9. D. Brandler, The Effect of Miniaturization on Embedded Resistors in High Density Interconnecting Substrates, In Proceedings of the 2001 IMAPS International Symposium on Microelectronics, p. 464, 2001. 10. T. Lenihan and L. Schaper, Integrated Passives Developments, In Proceedings of the 1996 ISHM Advanced Technology Workshop, 1996. 11. S. Demurie and G. Mey; Parasitic Capacitance Effects of Planar Resistors, IEEE Trans. Components, Hybrids. Manufacturing Tech., CHMT-12, p. 348, September 1989. 12. K. Fjeldsted and S. Chase, Embedded Passives: Laser Trimmed Resistors, CircuiTree, March 2002. 13. V. Shah and D. Hayes. Trimming and Printing of Embedded Resistors Using DemandMode Ink-Jet Technology and Conductive Polymer, In IPC Printed Circuit Expo 2002, p. 1, 2002.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 3

INTEGRATED RESISTOR MATERIALS AND PROCESSES

RICHARD K. ULRICH

The previous chapter covered the generalities of integrated resistor configuration, values, performance, and sizing. This chapter will describe the various resistor materials and processes that can be used to form those components. A resistors performance is at least a direct function of its composition, microsegregation of composition, crystal structure, film thickness, temperature, and voltage. These, in turn, are a function of processing conditions such as pressure, temperature, power, gas flow, etc. for sputtering, CVD, or evaporation of thin films and cure time and temperature for thick films. Subsequent anneals, which alter crystal structure and composition microsegregation, are often used to modify resistor properties. Some useful reviews of this topic are available [1, 2]. Much of the information in this chapter will be familiar to those in the business of manufacturing discrete resistors, but there are compelling reasons to make it available here. First, integrating the materials means manufacturing them in a new setting with different substrates and different connection methods. Second, the developing technology of integrated passives is inherently interdisciplinary, requiring knowledge of both the electrical engineering and materials engineering aspects to determine what combination of performance and processibility is optimal for a given application. Much of the information presented here is from the published results of many investigations into integrated resistors and indicates what materials those groups preferred and how they processed them. The intent is to combine the old and new information to help the engineer select a suitable technology for his specific application. The use of integrated resistors, and capacitors and inductors for that matter, requires that the design and process engineers work together to an extent that is not necessary when off-the-shelf discretes are used. The selection of an integrated resistor technology for a given application requires the simultaneous consideration of electrical performance issues (resistivity, temperature effects, stability), and com55

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INTEGRATED RESISTOR MATERIALS AND PROCESSES

patibility with the materials and processing of other parts of the substrate/interconnect/passive assembly. No resistor material should be considered that cannot be deposited, cured and/or patterned by techniques and chemicals that do not harm the preexisting substrate, interconnects, and other passive components in place. For these reasons, the integrated-passive engineer must understand the potential resistor film materials and processing methods, how those methods affect the composition and structure of the films, and how the resulting composition and structure affects the electrical properties. All of the materials and processes in this chapter are suitable for use on organic substrates. That is, the resistors can be processed at under about 250C and without using chemical steps that would harm polymer board materials or buildup layers. Of course, these same technologies could also be used on inorganic substrates such as glass, silicon, or ceramic since these are typically more thermally and chemically robust than polymer. There are two restrictions to transferring the technology from this chapter to ceramic substrates: the ceramic surface may be significantly rougher than organic surfaces, resulting in yield and tolerance problems with thin-film devices; and ceramic substrates are fired at temperatures usually exceeding 600C, which may not be tolerated by some of the materials described here.

3.1 SINGLE-COMPONENT METALS The resistance behavior of elemental metals is fairly predictable since it is not a function of composition and is a weaker function of crystal structure than for most compound materials. Every atom in the metal contributes integer numbers of conduction electronsgenerally 1, 2, or 3which are unbound and free to move throughout the material with high mobility. Ionic conduction is completely unimportant. Because the density of charge carriers is high, on the order of the atomic density (~1022 cm3), and because electrons are very mobile, metal conductivities are the highest of any materials at room temperature, ranging from about 1.7 cm for Cu and 2.7 for Al. The high end is represented by Ti at 43, Mn at 140, and beta-Ta at 180. First-order electron scattering theory indicates that metal resistivities should be inversely proportional to molecular weight and this is found to be roughly true in practice, which is one reason that Al is so conductive. Typical resistivities for thin metal films, or any other material, are somewhat higher than bulk values because of microstructure differences between thin films and bulk materials, roughness of the substrate, and columnar grain growth influenced by the two-dimensional surface structure of the underlying material. The concentration of charge carriers in single-component metals is not a strong function of temperature since each metal atom already contributes an integer number of electrons for conduction reflected by the valance states in the periodic table, and it would require much higher than room temperature to liberate more. Therefore, resistivity typically increases with temperature due to electron scattering off lattice vibrations, which are more numerous at higher temperatures, resulting in

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SINGLE-COMPONENT METALS

57

TCRs of typically a few 1000 ppm/C. Metal films may be sputtered as thin as a few 100 for applications as low-valued resistors for current-sensing applications, or plated to almost unlimited thickness for use as low-loss interconnects. 1000 films of pure metals would give sheet resistances of only 0.2 to 4 /square, which would not be practical for resistors above a few hundred ohms. Cu metallization gives about 10 m/square for 2 microns of sputtered material and around 1 m/ square for oz layers. Of the single-component metals studied for integrated resistor applications, Ta is a favorite due to its relatively high resistivity, stability with time, and the ability to anodically trim it to precise values. Ta has a high melting point (2996C) compared to other electronic metals, which implies that its crystal structure will not change much at slightly elevated temperatures, resulting in stable resistance values with time and temperature. A corollary to this is that annealing to stabilize the properties is usually unnecessary since Ta responds little to temperatures that organic substrates can withstand. It is, however, a reactive metal and pure Ta films can be hard to make consistently, due to easy contamination with gases during sputtering. It is too refractory for easy evaporation. Ta is a valve metal, which means it forms a tenacious protective oxide when heated in air or exposed to anodic voltage in a conductive aqueous solution. This oxide may be used to protect the resistor from further reaction with oxygen or nitrogen, stabilizing its value against exposure to these gases. Ta resistors may also be trimmed by anodizing, using a DC voltage to anodize the metal while simultaneously using an AC voltage to measure the resistance. Tolerances well under 1% can be achieved this way [3]. Of course, this procedure may be complicated for integrated resistors since the component might be electrically connected to other passives. In bulk form, Ta has a resistivity of 14 -cm and a TCR of 3800 ppm/C, typical of single-component metals. Sputtering can produce two forms. The alpha form is bcc, the same as the bulk structure, which, like most materials, has a resistivity slightly higher than bulk at 2040 -cm and a TCR slightly lower at 5001800. The beta form is easily sputtered under conditions that exclude contaminants. This is a tetragonal configuration with the same density as bcc but considerably higher resistivity180 -cm and an attractive TCR of 100 to +100. Beta Ta is not stable in bulk form [4]. There is also an unusual low-density form at 12 gm/cm3 compared to the bulk value of 16.6 that is formed by lowering the cathode voltage of the sputtering equipment from 5000 V to around 1500 V. It is also bcc but very porous, with numerous voids and channels between crystallites that are 2050 across, giving it a surface area estimated to be 15 times as high as a highdensity bcc film, a void volume of 27%, and a very high resistivity at about 4000 -cm. Its TCR is considerably lower than the bulk material and can approach zero under some processing conditions. Its appearance is not sudden; it comes on slowly with lowered voltage, enabling a variety of intermediate forms to be produced. The problem with low-density Ta as a resistor material is that it is very sensitive to oxidation due to very large surface area. Heating in air increases resistance somewhat but can drop TCR significantly; 2 hrs at 200C has been seen to change the TCR

58

INTEGRATED RESISTOR MATERIALS AND PROCESSES

from 0 to 300 ppm/C [5, 6].

3.2 METAL ALLOYS AND METALNONMETAL COMPOUNDS Mixtures of metals exhibit higher resistivities than single-component materials, some as high as 160 -cm, due to mutual distortion of the single-metal lattices. They also typically have lower TCR because of electron band overlap between the two elements that causes an increase in conduction electrons with increasing temperature, which somewhat offsets increased phonon scattering. But most metalmetal alloys, like elemental metals, have resistivities too low for use as integrated resistors. Many binary metal-containing compounds have been investigated that could serve at the low end of the required resistance range, and three seem the most practical: NiCr, TaNx, and CrSi. TaNx may be the best of the group due to its ease of processing, low TCR, and stability, but all three have been demonstrated as integrated resistors for organic substrates. A TCR of 40 ppm/C has been measured for sputtered CrSi films on polyimide, and postdeposition stabilization for 250 hrs at 125C resulted in the loss of only about 0.6% of its initial resistance value, after which it was stable at that temperature [7, 8] (Figure 3.1). Ni0.8Cr0.2 has a resistivity of around 100 -cm, depending on its microstructure, and a TCR of 55 to +100. 200 of this would give 50 /square and is useful into the k range without excessive numbers of squares. Various annealing treatments at hundreds of degrees are used to modify and stabilize NiCr resistor properties; 250C for 5 hrs is typical. NiCr is known to be sensitive to moisture conditions, and passivation layers may be used to stabilize its value against time and humidity. SiO2 and polymer coatings have been used for this purpose but, for integrated applications, being buried beneath layers of substrate material may suffice.

Figure 3.1

Integrated resistors made from 10-mil-wide CrSi on flex.

3.2

METAL ALLOYS AND METALNONMETAL COMPOUNDS

59

3.2.1 Tantalum Nitride TaNx, formed by reactive sputtering of Ta in a nitrogen-containing atmosphere, is one of the most practical integrated resistor materials. At zero nitrogen levels, the films are, of course, bcc Ta with a resistivity of about 1320 -cm (or beta with 180 -cm) and a positive TCR in the high hundreds or low thousands, typical of elemental metal thin films. As the nitrogen levels increase, the resistivity rises to a plateau at about 250 -cm and, simultaneously, the TCR falls to a plateau of around 75 ppm/C, as shown in Figure 3.2. In this region, conductivity is thought to be due to tunneling through nitrogen-rich grain boundaries, which would explain the low TCR. This wide plateau region is one of the features that make TaNx so attractive as a resistor; a wide range of processing conditions results in the same film behavior that, fortunately, has good values of resistivity and TCR. Typical deposition conditions are 1020 mTorr of 1020% N2, resulting in 1001000 -cm, 2000 films, and < 200 ppm/C. Multivariable studies of TaNx properties with respect to sputtering parameters have correlated film resistivity, TCR, and stress (buckling and cracking) [9]. TaNx is more immune to recrystallization with temperature and time than NiCr or CrSi. It can be surface anodized in a controlled fashion for trimming and passivation. Subsequent high-temperature annealing processes, both with and without oxygen, are used to stabilize these properties. 250C for 5 hours in air will increase the resistance by 0.52%. TaNx can be wet etched in a mixture of nitric and hydrofluoric acid or dry etched with CF4 in an RIE. Reactively sputtered films of oxygen-rich tantalum oxide offer sheet resistivities of 27 to 25,400 ohms/square and TCR values of 3 to 1280 ppm/C, which would be useful for high-valued resistors. However, the high-resistivity films were very unstable and exhibited large resistance increases with time and temperature+21% after 2 hrs at 300C [10].

Figure 3.2

Resistivity and TCR of sputtered TaNx as a function of nitrogen content.

60

INTEGRATED RESISTOR MATERIALS AND PROCESSES

3.2.2 Titanium Oxy-Nitride Various stoichiometries of titanium oxy-nitride (TiNxOy) can, like cermets, provide resistivity values near the top of the required range for integrated resistors. Sputtered TiNxOy films have exhibited 155,000 /square with TCR 100 ppm/C [11]. They were formed by the DC magnetron reactive sputtering of Ti in N2 + 0.5 ppm O2 at 110 mTorr and a substrate temperature of 150C over both Si and FR4 substrates. With identical sputtering conditions, the resulting values, as N2 partial pressure was varied, were 152,000 /square over Si and 305,000 /square over FR4, as shown in Figure 3.3. TCR values decreased with increasing N2 partial pressure, reaching zero for films around 2000 -cm. Material resistivity appeared to vary from 200 to 3000 -cm. Annealing at 685C for one hour raised the resistivity by only 4.5% for films on Si, and 1000 hrs at a heat flux of 80 W/cm2 resulted in a 5% increase, which might indicate good time/temperature stability at normal usage temperatures. Deposition repeatability was within 5% and the films may be wet etched with an aqueous solution of ammonia and hydrogen peroxide with good selectivity between TiNxOy and Cu. The resistor material can act as an adhesion layer between Cu and Si. 3.2.3 Nickel Phosphide Although most thin-film compounds demonstrated for integrated resistor applications are sputtered, it is also possible to electroplate various materials such as

Figure 3.3

Sheet resistivity for sputtered TiNxOy as a function of nitrogen pressure.

3.4

CERMETS

61

NiP and NiWP, which are both thoroughly reviewed by Chahal et al. [12]. These materials can be electrolytically or electrolessly plated to give up to 170 m-cm with a TCR of about 100 ppm/C for 1214% P in Ni, and up to 150 m-cm with a TCR of 5 to +60 ppm/C for NiWP. The resulting sheet resistances in this study ranged from 5 to 50 /square [13, 14]. Electroplated NiP is also used as the resistive material for Ohmega-Ply, one of the few mature commercialized integrated passive systems, providing up to 250 /square, and for MacDermids M-Pass, providing up to 100 /square. These are described in more detail later in this chapter. Ohmega-Ply is produced by a subtractive process in which the NiP is electrolytically plated and M-Pass is produced by an additive process that uses selective electroless plating over areas pretreated with a catalyst [15].

3.3 SEMICONDUCTORS 3.3.1 Silicon Undoped semiconductor materials, on the average, contribute only one charge carrier (electron or hole) per billions or trillions of atoms. As a result, resistivities are much higher than for metals; that of undoped Si is 250,000 -cm, almost a trillion times that of Cu. However, the concentration of charge carriers is a strong function of temperature and impurity levels, which makes many of these materials too variable for use. Since increasing temperature liberates charge carriers in exponential amounts, the TCR is strongly negative, about 73,000 ppm/C for pure Si at room temperature. Furthermore, their resistivity is a strong function of trace amounts of impurities, which is a key feature in making integrated circuits possible. Polycrystalline Si can be sputtered onto organic substrates, but its extreme TCR behavior would make it useful for thermistor applications only. 3.3.2 Semiconducting Oxides There are semiconductor oxides that are by virtue of their low TCR, such as ruthenium dioxide, which is widely used as a fired thick-film material on ceramic substrates. However, it can also be sputtered as a thin film from 32 to 500 -cm [16]. The sputtering conditions that give near zero TCR for RuO2 yields about 150 -cm. Tin oxide is a n-type semiconductor that can give a wide range of resistivities depending on how it is doped; antimony is routinely added to it to decrease both resistivity and TCR, whereas indium has the opposite effect. 200 /square is possible at 1000 .

3.4 CERMETS Most of the resistor materials described above are useful at only the lower end of the range required for common systems. High-value resistors, above about 100 k, made from reasonably small numbers of squares require films with sheet resis-

62

INTEGRATED RESISTOR MATERIALS AND PROCESSES

tances in excess of 1000 /square; this is not achievable with metalmetal or metalnonmetal alloys. Stable high-resistivity materials may be obtained by combining a metal and a ceramic insulator into a two-phase structure known as a cermet. These are nano-structured compounds, with metal being the distributed phase and ceramic the continuous phase. They are commonly used on ceramic substrates, where they are made by firing metalglass pastes, but they may also be sputtered at much lower temperatures. The most commonly used of these is Cr plus SiO, which can provide useful resistors with high values, low TCR, and good stability. 70% Cr in SiO gives 1100 -cm and TCR = 0, whereas 55% approaches 10,000 -cm, as shown in Figure 3.4. One disadvantage of the Cr system is that it is hard to dry etch; W-SiO is easier [17]. Because cermets are nano-structured compounds, the TCR of these materials is complex, but tends to go negative and stay there once the metal particles are fully coated, which seems to happen above about 4050% ceramic [18]. The microstructure of these films consists of grains of Cr, maybe with some dissolved Si, in a matrix of SiO. The conduction seems to be due tunneling between conductive grains through the insulating matrix. The metal grains are around 50 in diameter, depending on the temperature of the substrate during deposition. The low TCR is a result of the need to thermally activate electrons to cross insulating barriers. Cermets show two limiting regimes of behavior: 1. Low resistivity and positive TCR at high metal fractions. Although the metal still exists only in grains, there is a continuous metal network due to direct particleparticle contact. Conductivity is similar to that of metals. 2. High resistivity and negative TCR at low metal fractions. The metal grains are isolated in the ceramic matrix and conduction is by tunneling. This is the area of interest for high-value integrated resistors.

Figure 3.4

Resistivity of CrSiO cermet films sputtered at 200C [19].

3.5

POLYMER THICK FILM

63

Figure 3.5 Resistivity of cermet materials correlated with the volume percent of the insulating phase.

Attempting to raise the resistivity to very high values, near 1 -cm, by lowering the metal fraction to less than around 30% results in a high sensitivity of resistance and TCR to processing conditions, to the point that useful tolerance is difficult to achieve. The tunneling mechanism is supported by the fact that the resistivity of cermet materials has been found to correlate well when plotted against the volume percent of ceramic, independent of the identity of the metal addedabove about 40%, at which packing theory indicates that the metal grains would start to be separated by insulator. Figure 3.5 shows this relation for a resistivity range of over 14 orders of magnitude for a variety of metals combined with SiO or SiO2 [20]. 3.5 POLYMER THICK FILM Polymer thick film (PTF) materials are a very promising technology for integrated resistors due to their low cost of materials and processing, wide range of resulting resistance, and low-enough curing temperature for organic substrates; but there are significant problems with value drift and reliability to overcome before they can be widely used. Most PTF systems under development are epoxy-based polymers with micron-scale carbon or graphite fillers, and the conduction mechanism is contact

64

INTEGRATED RESISTOR MATERIALS AND PROCESSES

bridging between filler particles. They are provided as viscous liquids that may be screen printed or stenciled, then cured at temperatures generally below 200C. One available product cures in 45 minutes at 165C or may be snap cured with IR in only 5 minutes. The result is a film of several microns thickness with a practical width no smaller than about 35 mils due to limitations in screen printing or stenciling, although 1 mm is a more common lower limit due to heat removal considerations. Not only is the processing simple and suitable for FR4 and flex, but the achievable sheet resistances also cover a very wide range, from 1 to 107 /square. There is rarely a need to use more than 10 squares due to the wide range of resistivities supplied by the manufacturers, so resistor footprints can be quite compact. Figure 3.6 shows some typical screen printed resistors on FR4 from Parlin Industries. Advertised TCR values are around 200 ppm/C. As printed, their tolerance is no better than about 510%, but they can be laser trimmed. Solder will not wet them, due to the epoxy polymer binder, so they can be printed and cured before other surface-mount components are added without the need for solder masking. PTF is inherently solder-free, and is selectively added only where it is needed with no patterning and etching required. The films are generally 12 mils thick wet and about half that dry, and a single gram may cover 200400 cm2 with little waste. Several board shops offer PTF as an option, although generally only for non-critical applications in which some drift is not harmful, such as in rheostats. The problem with these materials is that the resistivity tends to increase with time both in the bulk of the material and at the metal/polymer interfaces, especially in humid environments. There are several reasons for this, including oxidation at the Cu/polymer interface, delamination from the contacts, swelling of the polymer material with moisture, cracking of the polymer material due to CTE mismatch, and possibly others [21, 22]. Better contact stability may be obtained by using larger

Figure 3.6

Screen printed PTF resistors on FR4.

3.6

INK JET DEPOSITION

65

contact areas, by using Au- or Ag-filled epoxy materials over the Cu termination as a transition material, or by applying proprietary oxidation inhibitors, all at additional cost [23]. Considerable research is being performed on this class of materials to solve these limitations. Most efforts are centered on various additives such as corrosion inhibitors and oxygen scavengers to prevent metal contact oxidation and to improve mechanical properties. Some manufacturers recommend using conductive silver-filled ink between the contact pad and the PTF resistor. Allowable heat fluxes are a bit lower than for thin-film resistors; a maximum of 58 W/cm2 are cited in manufacturing literature. Larger square size (lower heat dissipation) and higher cure temperatures give better value stability. Screen printing is more of an art than a science, and requires careful process control and skilled personnel for accurate tolerance and reproducibility. As supplied, the inks are in the range of tens of thousands of cP, but can be thinned with appropriate solvents to some degree. 200 mesh screen is recommended by some manufacturers. Similar technologies are under development such as low-resistance solder-free attach materials for surface-mount parts and printable interconnect inks with resistivities less than about 150 m/square [24]. Such films are filled with metal flakes, generally Ag, in order to maximize their conductivity, but they also suffer from value drift problems similar to those exhibited by PTF resistors. Some of these stability problems are solved by using a system of low-melting metals in a polymer matrix in which the metal particles are sintered together into a continuous but porous network. This eliminates the problems with unconnected particles moving relative to one another during temperature changes. The same strategy has been used to make conductive pastes used for mounting components. The main constituents of these materials are selenium, solder powder, and epoxy resin, and the resulting sheet resistance is from 1 to 2000 /square with TCRs around 300 ppm/C. Cures are typical of epoxiesaround 215C for 15 minutes [25]. Several companies offer PTF products and services, but value stability should be evaluated under the conditions of the intended use and not extrapolated from the companys test conditions. If issues related to long-term stability and reliability can be resolved, PTF should become a major player in integrated resistors [26, 27].

3.6 INK JET DEPOSITION This technology comes directly from ink jet printers, but is better described as material jetting since a wide variety of fluids can be deposited this way, including curable polymer resins and solder. There are two types of deposition: continuous droplets and droplets on demand. In continuous mode, droplets are produced at a constant rate and caught in a deflector when not wanted on the substrate. For droplets on demand, a small, rapid volume change is made to a fluid reservoir using a pulse of voltage to a piezoelectric material, a pulse of voltage through a resistor resulting in partial vaporization, or focused acoustic energy. This forces a single droplet as small as 10 m out of an orifice at rates as high as 20,000 drops/second.

66

INTEGRATED RESISTOR MATERIALS AND PROCESSES

Printed resistors have been made from conductive polymers that resulted in about 100 /square and geometries as small as 20 mils. The advantages of this method include the ability to change resistor values, shape, and placement in software, and the possibility of performing repairs. As described in the previous chapter, ink jetting can also be used to trim resistors from high to lower values, the opposite direction from laser trimming, by selectively coating the top of the existing resistor with a less conductive material until it is within specification [28, 29].

3.7 COMMERCIALIZED PROCESSES 3.7.1 Ohmega-Ply Ohmega-Ply is an integrated resistor technology, primarily for organic substrates or laminates, that consists of 0.1 to 0.4 m thick electroplated NiP on one side of Cu foil. It is laminated, resistor material down, to the substrate, followed by two mask steps and three etch steps to form both circuitry and resistors for that layer, as shown in Figure 3.7. It can be used on most resin systems including high-Tg epoxies, polyimides, BT blends, cyanate esters, PTFE (Teflon), and ceramic-filled resins. It is not applicable to LTCCs, MCM-Cs, or any cofired ceramics or ceramic hybrids. Once etched, the layer consists of either Cu with Ohmega under it where a conductor will be, or Ohmega with the Cu etched away from on top of it where a resistor will be. This provides both a variety of possible resistor values and arbitrary patterns of Cu interconnects on a rigid substrate, which can then be laminated into the stack just like any other material and connected to other layers with vias. Multiple layers of Cu/Ohmega can be used to place integrated resistors anywhere in the stack. This technology is advertised as being applicable for values up to 10,000 from sheet resistances of 25, 50, 100, and 250 /square with 1000 /square under development. The company claims that cost benefits begin if the resistor density is approximately 34 discrete resistors per square inch of board area [3032] (Table 3.1). 3.7.2 DuPont InterraTM DuPont is developing a lanthanum boride (LaB6) based material that is screen printed as a paste in the desired shapes on one side of Cu foil, fired at 900C to convert the paste into resistor material, then laminated onto the board with the resistors down. The Cu is then etched to form the interconnects, as shown in Figure 3.8 [3335]. Up to 10 k/square with 200 ppm/C can be achieved with thickness of approximately 1012 microns. The choice of this system was based on chemistry that would be resistant to the etching solutions used to make cores and boards. Also, LaB6 has been used as a resistor material on ceramic substrates for many years and is known to be highly reliable and stable. Scattered resistance due to etching of the conductive phase was experienced with other resistor systems that were evaluated.

3.7

COMMERCIALIZED PROCESSES

67

Figure 3.7

Ohmega-Ply integrated resistor processing flow.

Table 3.1 Sheet Resistance (/square) 25 50 100 250

Performance specifications for Ohmega-Ply integrated resistors TCR (ppm/C) 50 60 80 +100 after 1000 hrs at 70C 0.50% 0.75% 1.0% 1.0% Max Power Dissipation at 40C Ambient (W/cm2) 39 31 23 16

Tolerance 5% 5% 5% 10%

68

INTEGRATED RESISTOR MATERIALS AND PROCESSES

Figure 3.8

DuPonts InterraTM fired lanthanum boride integrated resistor processing flow.

The copper foil is first conditioned by printing and firing a thin layer of copper/glass paste over one side of its surface. This conditioning process has been found essential in developing good adhesion of both the resistor to the foil and the foil to the epoxy prepreg adhesive. A protective layer is applied to the resistors before being flipped on the prepreg that protects the board during laser trimming. The vacuum lamination to FR4 is done at 150C, so other parts of the boards never see high-temperature processing. 3.7.3 MacDermid M-Pass M-Pass employs a selective thin-film, electrolessly plated NiPx material to form integrated resistors of 25100 ohm/square. Processing is additive; the material is selectively plated only where it is needed through the use of a palladium catalyst and photoresist to define the plating areas. The process fits into traditional PWB fabrication equipment and procedures. The process is shown in Figure 3.9.

3.7

COMMERCIALIZED PROCESSES

69

Figure 3.9

M-Pass integrated resistor processing flow.

Resistivity of the deposit is controlled by plating time; longer times create a thicker deposit that is less resistive. The final films are less than a few hundred angstroms thick. Multiple masking and plating time variation allows multiple resistor values on the same layer. Solder mask or screened dielectric material is used to protect the final resistor to maintain the as trimmed value through subsequent handling and lamination. The resulting resistors have a lower-size limit of 250 m when oz Cu foil and conventional dry resist are used, an upper limit of 100 /square, and an untrimmed tolerance of about 10%. By successive imaging steps,

70

INTEGRATED RESISTOR MATERIALS AND PROCESSES

it would be possible to form resistors of values from 25 to 100 ohms/square on the same layer. Finished and passivated resistors show less than 2% value drift over 1000 hours at 85C and 85% RH or 500 cycles of 35 to +125C. MacDermids development goals for this product include increasing the as-plated precision to 5% and produce higher /square materials to enable higher-value resistors [15]. 3.7.4 Polymer Thick Film PTF materials for screen printing integrated resistors were described earlier in this chapter but are included briefly here since they are commercialized products. PTF ink vendors include Metech, Acheson Colloids, and Electra. Metech and several board shops offer this as a process option. Although the materials handling and curing steps are easy and inexpensive, the key to success lies in the screen printing process, which can be a complex and sensitive procedure. Also, company claims about value stability should only be taken as general guidelines; users should evaluate this under their own testing conditions. Motorola has demonstrated the printing of resistors from 18 to 10 M with the same family of PTF inks [23]. They have developed a proprietary material to go between the Cu termination and the PTF material that diminishes the tendency for pad oxidation to increase the resistance with time and temperature. 3.7.5 Shipley Insite Shipley is developing a resistor material they describe as consisting of thin-film doped platinum deposited directly on copper foil by combustion chemical vapor deposition (CCVD). This combination of material and process allows high values of sheet resistivity (up to 1000 /square) and a TCR value less than 100 ppm [36]. SEM photos show what appears to be a cermet-type structure consisting of 50 grains surrounded by another phase, possibly an insulator. Processing is much like Ohmega-Ply; it is deposited onto one side of Cu foil, flipped onto the board, and etched. As of the date of this writing, it has not been commercially released.

3.8 SUMMARY Table 3.2 gives an overview of the values of resistivity, reasonable film thickness, and resulting sheet resistances for a variety of materials useful for integrated resistors. Interconnect metals are shown for comparison. The resistivities given for elemental metals are bulk values; thin-film values will be somewhat greater and are given as ranges for alloys and metalnonmetal compounds since their specific values are dependent on their exact composition, processing, and annealing conditions. TCR values for metals are maximums for perfect crystals but, in practice, would not be much lower. Film thicknesses are set at 2 m for interconnect materials, which is practical for sputtered films, and 500 for the sputtered resistor materials, which is a practical lower limit. Resistors as thin as 200 have been

3.8

SUMMARY

71

Table 3.2 Resistance properties of materials useful for integrated resistors and interconnects Resistivity Range (-cm) 1.6 1.7 2.4 2.7 6.9 bcc: 13 beta: 180 13 42 100500 ~2000 Film Thickness 2 m 2 m 2 m 2 m 2 m 500 500 500 500 10004000 Sheet Resistance (/square) 0.0080 0.0085 0.0120 0.0135 0.0345 2.6 2.6 8.4 20100 Up to 250 1000 in development Up to 100 higher in development Up to 7000 500 Up to 1400 100 with process optimization 200 ~200 Close to zero or slightly negative 50 with process optimization 0100 6750 3800 3000 TCR (ppm/C) 4100 4330 4000

Material Ag Cu Au Al Ni Ta Cr Ti TaNx, CrSi, NiCr, TiNx, NiP NiP (Ohmega-Ply) NiP (MacDermid) TiNxOy

LaB6 (DuPont)

107

10 m 12 mil 1 m

10,000 10107 100108

PTF Very wide, (several vendors) depending on filler Cermets 1041010 depending on metal/glass ratio

used, giving sheet resistances 2.5 times higher than shown for thin-film resistor materials, but tolerance and yield become more difficult as the films become thinner. Commercialized technologies are shown with whatever thickness and performance data is known. As described in the previous chapter, most integrated passive resistor applications can be realized using two ranges of sheet resistanceabout 100 /square and about 10,000 /square. The lower range can be obtained using any one of several

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INTEGRATED RESISTOR MATERIALS AND PROCESSES

materials, including TaNx, CrSi, NiCr, and TiNx, and the high end of the resistance range can be covered by cermets or, perhaps, TiNxOy and LaB6. Polymer thick films can accommodate the entire range, but problems with value stability exist at this time. Table 3.3 shows the status of these materials on organic substrates. It should be remembered that these films, formed by any method, cannot subsequently be annealed at high temperature on organic substrates for the purposes of modifying their structure and properties.

Table 3.3 Processing limitations for various integrated resistor materials on organic and inorganic substrates Material Low- metals (Cu, Al, Au) Practical Range of Resistance Resistivity too low for almost any resistor applications, useful as interconnects and contact metal to resistors <100 Useful to around 100 k; TiNxOy may be higher with development Processing on Organic Substrate Sputtering to ~2 m Plating to >100 m Processing Issues Well-established

High- metals TaNx, CrSi, NiCr, TiNxOy

Sputtering to ~2 m Plating to >100 m Sputtered thin film

Well-established Well-established, may require passivation or thermal stabilization

Electrolytic NiP Useful to around 100 k

Electrolytically plated Commercialized as onto Cu foil, laminated Ohmega-Ply in the onto board, Cu and form of plated foil NiP etched to shape Dielectric surface is catalyzed for selective plating, fully additive Under development by MacDermid

Electroless NiP

Useful to around 100 k

LaB6

Useful over wide range

LaB6 paste printed to Under development shape on Cu foil, fired, by DuPont laminated onto board, Cu etched to shape Sputtered thin film Screen print or stencil epoxy-based paste, cure <250C Experimental Very attractive technology due to flexibility and low cost, once value drift and reliability problems are solved

cermets PTF

Useful for high range, up to M Very wide range

REFERENCES

73

REFERENCES
1. R. Kennedy, Materials for Thin Film Resistors, Advancing Microelectronics, p. 12, Sept/Oct 1999. 2. L. Maissel and R. Glang, Handbook of Thin Film Technology, McGraw-Hill, New York, 1970. 3. R. Berry, P. Hall, and M. Harris, Thin Film Technology, Van Nostrand, New York, p. 344, 1968. 4. P. Catania, R. Roy, and J. Cuomo, Phase Formation and Microstructure Changes in Tantalum Thin Films Induced by Bias Sputtering. Journal of Applied Physics,74, 2, 1008, 1993. 5. B. Vromen, Low-Density Tantalum, Bell Laboratories Record, p. 327, Nov. 1968. 6. H. Schuetze, H. Ehlbeck, and G. Doerbeck, Transactions of the 10th National Vacuum Symposium, p. 434, 1963. 7. T. Lenihan et al., Embedded Thin Film Resistors, Capacitors and Inductors in Flexible Polyimide Films, International Journal of Microcircuits and Electronic Packaging, 20, 4, 474, 1997. 8. K. Fairchild et al., Reliability of Flexible Thin-Film Embedded Resistors and Electrical Characterization of Thin-film Embedded Capacitors and Inductors, In Proceedings of the 1997 Electronic Components and Technology Conference, p. 730, 1997. 9. K. Coates et al, Development of Thin Film Resistors for Use in Multichip Modules, In 1998 International Conference on Multichip Modules and High Density Packaging, IEEE, p. 490, 1998. 10. R. Clark and C. Orr, Reactively Sputtered Tantalum Resistors and Capacitors for Silicon Networks, IEEE Trans. Parts, Materials Pack., PMP-1, 3144, June 1965. 11. A. Shibuya et al., Embedded TiNxOy Thin-Film Resistors in a Build-Up CSP for 10 Gbps Optical Transmitter and Receiver Modules, In Proceedings of the 51st Electronic Components and Technology Conference, IEEE, p. 847, 2001. 12. P. Chahal et al., Electroless Ni-P/Ni-W-P Thin-Film Resistors for MCM-L Based Technologies, In Proceedings of the 48th Electronic Components and Technology Conference, IEEE, p. 232, 1998. 13. S. Yamada, et al., Electroless Ni-P Resistors for Fusing Roll, IEEE Transactions on Components, Hybrids and Manufacturing Technology, 13, 3, 576, 1990. 14. M. Fernandez, J. Martinex-Duant, and J. Albella, Electrical Properties of Electroless NiP Thin Films, Electrochemica Acta, 31, 1, 55, 1986. 15. J. DAmbrisi, D. Fritz, and D. Sawoska, Plated Embedded Resistors for High Speed Circuit Applications, In IPC Fall Annual Meeting, Orlando, FL, Oct. 11, 2001. 16. Q. Jia et al., Development and Fabrication of RuO2 Thin Film Resistors, Materials Science and Engineering, B18, p. 220, 1993. 17. N. Kim et al., Development of Multi-Chip Modules with Integrated Thin Film Passive Elements, In Proceedings of the 1997 Interenational Symposium on Microelectronics, p. 157, 1997. 18. V. Fronz et al., Electrical and Structural Properties of Cr-SiO Thin Films, Thin Solid Films, 65, p. 33, 1980.

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19. L. Maissel and R. Glang, Handbook of Thin Film Technology, McGraw-Hill, New York, p. 13-3, 1970. 20. Neugebauer, Resistivity of Cermet Films Containing Oxides of Silicon, Thin Solid Films, 6, p. 443, 1970. 21. A. Xiao, Q. Tong, and A. Savoca, Polymer Thick Film Materials for Integral Resistors, In Proceedings of the 49th ECTC Conference, p. 88, 1999. 22. Xi, Xiaomei et al., Metal-Containing Polymer-Based Composites for Resistor and Thermistor Applications, In Proceedings of the International Symposium on Microelectronics, San Diego, CA, p. 453, Nov. 1998. 23. J. Savic et. al., Embedded Passives Technology Implementation in RF Applications, In Proceedings of the IPC Printed Circuit Expo, Long Beach, CA, March 2428, 2002. 24. P. Harrey, P. Evans, and D. Harrison, Integrated Capacitors for Conductive Lithographic Film Circuits, IEEE Transactions on Electronics Packaging Manufacturing, 24, 4, 333, 2001. 25. H. Hwang et al., Polymer Thick Film Resistor with a Dual Curing System, In Proceedings of the 1999 International Symposium on Microelectronics, p. 489, 1999. 26. D. Lu and C. P. Wong, Development of a Conductive Adhesives for Solder Replacement, IEEE Transactions on Components and Packaging Technologies, 23, 4, 620, 2000. 27. K. Gilleo, Polymer Thick Film, SMT Plus Inc., 1996. 28. V. Shah and D. Hayes, Trimming and Printing of Embedded Resistors Using DemandMode Ink-Jet Technology and Conductive Polymer, In Proceedings of the IPC Printed Circuits Expo 2002, Long Beach, CA, March 2428, 2002. 29. D. Hayes, W. Cox, and M. Grove, Micro-Jet Printing of Polymers and Solder for Electronics Manufacturing, Journal of Electronics Manufacturing, 8, 3 & 4, 209, 1998. 30. G. Walther, Tolerance Analysis of Ohmega-Ply Resistors in Multilayer OWB Design, CircuiTree, p. 64, March 2001. 31. Ohmega-Ply Cost Analysis, a white paper from Ohmega Technologies Inc., Culver City, CA, www.ohmega.com 32. D. Cullen et al., Effects of Surface Finish on High Frequency Signal Loss Using Various Substrate Materials, In Proceedings of the IPC Expo Conference, April 2001. 33. W. Borland and J. Felten, Thick Film Ceramic Capacitors and Resistors inside Printed Circuit Boards, In Proccedings of the 34th International Symposium on Microelectronics (IMAPS), Baltimore, MD, Oct. 911, 2001. 34. W. Borland and S. Ferguson, Embedded Passive Components in Printed Wiring Boards, CicuiTree, p. 24, March 2001. 35. J. Felten, R. Snogren, and J. Zhou, Embedded Ceramic Resistors and Capacitors in PWB: Process and Performance, In Proceedings of the Fall IPC Meeting, Orlando, FL, October 11, 2001. 36. P. Chinoy, M. Langlois, and J. Schemenaur, High Ohmic Value Embedded Resistor Material, CircuiTree, March 2002.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 4

DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

RICHARD K. ULRICH

It will be shown in this chapter that a very wide range of capacitor dielectric materials are potentially useful for integration. Ideally, their dielectric constant should be flat with regard to frequency, temperature, voltage, and time. The dielectric should be capable of being bent and stretched to a reasonable degree so that it will not suffer from the effects of CTE mismatch with other board materials during normal temperature excursions and so it can be used in applications with little packaging such as smart cards. It should be amendable to mass production at an economic cost using common materials and patterning techniques that do not harm other parts of the board or components already in place. Certainly, all of the technologies described in this chapter will compromise on some of these issues, which is why no one perfect integrated capacitor dielectric has yet to have been identified from the hundreds of journal and proceedings articles to date. The fact that so many different dielectric materials have been evaluated in just the past few years for applications as integrated capacitors is indicative of the uncertainty in this area. Scores of dielectrics representing all classifications of these materials (oxides, polymers, ceramics, etc.) have been evaluated experimentally in order to identify their technical advantages and disadvantages with regard to fabrication, electrical performance, and reliability as an integrated component. In any new technology, this is a necessary procedure to both cull out the materials that are clearly impractical and to provide the information to establish the economical viability of those that are feasible. The list includes almost every material that has ever been used as a capacitor dielectric as well as one class of material that was invented specifically for the purpose: ferroelectric powders dispersed in curable epoxy. As it turns out, very few out of this multitude are completely impractical for use as in integrated capacitors, which means that there is a large number of choices that have passed the technical challenges and remain to be evaluated economically. Therefore, a review of the fundamentals of capacitance as well as the materials science
75

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DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

behind dielectrics is in order for the purpose of understanding these issues sufficiently to make informed decisions about their applicability to integration. This is such a large and important topic that it will be broken down into three chapters: this one addresses the types of dielectric materials available for integrated capacitors, Chapter 5 covers the sizes and configurations attainable with these materials, and Chapter 6 deals with processing issues. This chapter begins with a description of the mechanisms and metrics of a dielectrics performance in a capacitor, such as the dielectric constant, dissipation factor, leakage, breakdown, and temperature effects. This is followed by a listing of the major materials that have been evaluated in integrated capacitors, sorted by type. One of the main purposes of this chapter is to compare the two major classes of dielectric materialsparaelectrics and ferroelectricsthen show how one or the other of these might be more suitable for certain integrated capacitor applications such as decoupling, filtering, A/D, and signal termination. It will be shown that the fundamental difference in the way the two materials store charge is very important to their respective suitability for these applications. It will also be shown that selecting the dielectric with the largest k is not always the optimal choice. Little regard is given in this chapter to how the films might be formed on various substrates; the following chapters will address that. There is a tremendous amount of research currently underway on high specific capacitance materials and structures, not only for integrated passives, but also for gate dielectrics and memory cells for ICs [1]. Many of the same goals are sought for all capacitor development programs: high specific capacitance, low leakage, high breakdown, and sufficient stability. However, what are considered good properties is very much a function of application. A gate dielectric with a leakage of a mA/cm2 at 5 V may be considered a low-leakage material for that application, but this is a tremendous amount of leakage for an integrated passive capacitor used in, for instance, an A/D converter. Similarly, a capacitor that might be considered very stable against frequency for energy storage applications might be far too variable to be used as a filter element. There are several excellent overviews of dielectric materials, some written long before integrated passives were conceived [25].

4.1 POLARIZABILITY AND CAPACITANCE The ability of a dielectric material to store energy under the influence of an electric field results from the field-induced separation and alignment of electric charges. Polarization occurs when the field causes a separation of the center of charge of the positives and negatives in the material. The larger the dipole moment arm of this charge separation in the direction of a field and the larger the number of these dipoles, the higher the materials dielectric constant. There are several possible contributions to this polarizability, which, depending on the mechanisms operative in a given dielectric, determine not only the value of k but also how it varies with frequency, temperature, bias, impurity concentration, and crystal structure [68].

4.1

POLARIZABILITY AND CAPACITANCE

77

The three general mechanisms important to candidate materials for integrated capacitors are electronic, atomic, and ionic polarization (Figures 4.14.3). Electronic polarization involves charge symmetry distortion of single atoms. Under the influence of an applied field, the nucleus and the negative charge center of the electrons shift in opposite directions, creating a small dipole. This induced dipole effect occurs in all materials, including air, but is usually very small compared to other polarization mechanisms since the moment arms of these dipoles are very short, usually a fraction of the size of an atom. Atomic polarization occurs in substances made up of more than one type of nonionic atom because the different elements will not normally share the electron cloud equally; it will be shifted toward the more electronegative atoms, resulting in a permanent dipole. The electric field will then produce forces on various parts of the molecules, causing these dipoles to align to some extent. It is the aligning with the field that creates enhanced capacitance, not the presence of permanent dipoles; if these randomly oriented permanent dipoles were somehow not capable of movement and alignment, there would be no dielectric constant for that material resulting from atomic polarization. Therefore, k is a function of the materials structure and lattice flexibility as well as its composition. Ionic polarization is similar to atomic polarization but involves the shifting of ionic species under the influence of the field. This shift can be considerable and can lead to very high dielectric constants, up to several thousand. All materials exhibit electronic polarization because they all have atoms, whereas atomic and ionic polarization require specific types of structures to be present. Purely electronic polarization would result in low dielectric constants, perhaps up to 24. Atomic and, especially, ionic polarization are responsible for much larger dielectric constants. The two major classes of dielectric materialsparaelectrics and ferroelectrics both exhibit electronic, atomic, and ionic polarization; the two classes of materials are not distinguished from one another in that regard. The distinguishing feature is that ferroelectric materials do not lose all of their ionic polarization when the field is removed but paraelectrics do. Because of lattice hindrances in ferroelectrics, the electric field can pull the ions into configurations that do not revert back to the pre-

Figure 4.1

Electronic polarization.

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DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

Figure 4.2

Atomic polarization.

vious state once the field is removed. As a result, ferroelectrics, analogous to ferromagnetic materials, can possess a residual polarization after the field is turned off. Furthermore, this residual polarization can be oriented in one direction or the other depending on the direction of the last field, which is the trait that gives them utility in nonvolatile memories. Paraelectric materials are those that cannot be left with a residual polarization once the field is removed because they do not have a mobile charged atom with more than one stable lattice position. The classic example of a ferroelectric is barium titanate (BaTiO3), shown in Figure 4.4. Above its Curie temperature of 120C, barium titanate is a cubic crystal with a lattice constant of 4.01 and a dielectric constant characteristic of paraelectrics at around 1540, but below this temperature it converts to the tetragonal form with unequal side lengths: 3.98 and 4.03 . Because of this asymmetry of the crystal, the Ti+4 ion has two stable positions it can occupy, neither in the center of the cell. Since the center of positive and negative charges are no longer in the same place, a permanent dipole moment exists that can be changed by moving the Ti+4 from one position to the other, and it will remain after the field is off. Although the

Figure 4.3

Ionic polarization.

4.2

CAPACITANCE DENSITY

79

Figure 4.4

Barium titanate becomes ferroelectric below 120C

distance between the two positions is small (a fraction of an angstrom), this displacement, together with the +4 charge on the cation, results in a substantial dipole moment that gives crystalline barium titanate a dielectric constant in the thousands, depending on the quality and alignment of its crystal structure. This residual polarizability defines ferroelectric and paraelectric materials but, while important in nonvolatile memories, this feature is irrelevant to any projected substrate-level integrated capacitor application. The important difference from the point of view of integrated passives is that ferroelectrics generally have much greater dielectric constants than do paraelectrics, sometimes by as much as three orders of magnitude, because of their mobile ionic charge.

4.2 CAPACITANCE DENSITY Table 4.1 is a list of the dielectric constants for various paraelectrics and ferroelectrics clearly showing the wide difference between them. The name dielectric constant is somewhat of a misnomer since it is not necessarily constant with regard to temperature, frequency, voltage, and time. The ks given for the ferroelectrics are maximum amounts because their specific values depend on grain size, crystal orientation, electrical bias, frequency, and film thickness. Ferroelectrics must possess a crystal structure in order to exhibit these high dielectric constants, otherwise their ks are no higher than typical paraelectrics. The dielectric constant of amorphous barium titanate is comparable with paraelectrics at a value of about 17 because the polarization contribution of the Ti+4 moving in the crystal cage is lost when there is no crystal structure to support it [9]. The values for ferroelectrics in Table 4.1 are for completely oriented bulk material single crystals at low frequency and no bias. Therefore, they represent maximum ranges of values for these materials. The dielectric constant for ferroelectrics is so highly dependent on processing and measurement conditions that it is not possible to be more specific but the values given for paraelectrics are only weakly dependent

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DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

Table 4.1 Composition

Dielectric constants for paraelectric and ferroelectric dielectrics Dielectric Constant 2.0 2.3 2.7 2.7 2.7 3.1 3.1 3.2 3.7 34 36 3.9 35 4.8 5 5.1 79 79 8 9 9 9.4 9.5 1217 17 20 24 25 26 40 23, 40 42 50 31 (anatase) 78 (brookite) 117 (polycrst) ~4060 (film) Up to thousands Up to thousands Up to thousands Up to thousands Dissipation Factor (%) 0.02 0.02 0.1 0.010.1 0.2 0.4 0.1 0.4 0.03 0.21.0 0.40.7 1.2 0.51.5 0.2 0.09 0.01 <0.1 11 14 11, 14 11 11 16 11 11, 15, 17, 18 11 11 14 11 11 18 11, 15, 19 TCC (ppm/C) 100 Reference 11 12 12, 13 11 12 12 11 11 11, 14 12 11 12 12 12 12 12, 15

Teflon Polyethylene BCB Parylene Low e BT Resin BPA Cyanate Polycarbonate Mylar SiO2 Polyimide Epoxies Epoxy resin for FR4 FR4 S glass E glass SiO Si3N4 BeO ZnO AlN Al2O3 Si3N4 MgO YOx BaTiO3 (amorohous) NbOx Ta2O5 (amorohous) SnO2 PbO SiC HfO WO2 Ta2O5 (polycrystalline) TiO2

<100

~200

0.41 <1

390

0.21 14

200

~1 0.6 25

125

300

BaTiO3 (tetragonal) BaSrTiO3 PbZrxTi1xO3 Ba0.8Pb0.2(Zr0.12Ti0.88)O3

Highly variable Highly variable Highly variable Highly variable

11, 20, 21 20, 22 23, 24, 25 26

4.2

CAPACITANCE DENSITY

81

on how they are fabricated or how the ks are measured and represent typically achieved values. Only a few paraelectrics exist in multiple crystal forms such as amorphous and hexagonal Ta2O5 [1, 10]. Because integrated capacitors are planar and area-ruled, the best way to express their value is as capacitance per unit area or specific capacitance. The following equation uses convenient units: dielectric constant nF specific capacitance in = 0.885 cm2 dielectric thickness in m One of these factors is a function of the dielectric material itself and the other depends on its form (film thickness). This chapter will be concerned mainly with the dielectric constant, what influences its intrinsic value, and how it is affected by operating conditions. Factors affecting film thicknesses are more specific to processibility and reliability are covered in the next chapter. The energy stored in a capacitor is: 1 E = CV2 2 where: E = energy stored, J C = capacitance, F V = voltage Table 4.2 shows the specific capacitances that might be expected from some common dielectric materials in thin but attainable thicknesses.

Table 4.2

Specific capacitances and energy storage density of some common dielectrics Dielectric Constant 4 50 2.7 3.7 6 9 24 40 ~2000 Thickness (m) 25 25 2.0 0.2 0.2 0.2 0.2 0.2 1.0 Specific Capacitance (nF/cm2) 0.14 1.8 1.2 16 27 40 110 180 1800 Energy Density at 5 V (J/cm2) 0.002 0.023 0.015 0.20 0.34 0.50 1.40 2.30 22

Dielectric Unfilled laminated polymer Ferroelectric-filled polymer Spin-on BCB SiO2 SiO Al2O3 Ta2O5 TiO2 Barium titanate

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DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

4.3 TEMPERATURE EFFECTS The temperature coefficient of capacitance (TCC), is defined as the temperature derivative of dimensionless capacitance and is usually expressed in ppm/C: 1 C 1 CT2 CT1 TCC = = C T CT1 T2 T1 A TCC of under about 200 ppm is considered low. In the absence of significant changes in film thickness with temperature, the capacitances may be replaced with dielectric constants to give a measure of TCC for the dielectric material only. TCCs tend to be positive due to the effect of greater interatomic spacing at higher temperature, which allows a larger dipole moment in the presence of an electric field. The TCC of paraelectrics tends to be fairly constant with temperature, in the neighborhood of 100300 ppm/C. Temperature has a greater effect on the dielectric constant of most ferroelectrics than paraelectrics because their polarization mechanisms are dependent on the crystal structure itself and is affected by phase transitions in the crystalline materials, which occur at specific temperatures. Figure 4.5 shows the ef-

Figure 4.5 materials.

Effect of temperature on the dielectric constant of paraelectric and ferroelectric

4.4

FREQUENCY AND VOLTAGE EFFECTS

83

fects of temperature on two ferroelectrics and one paraelectric, demonstrating the widely varied types of temperature-driven behavior ferroelectrics can exhibit [25, 27, 28]. The peaks in the BaTiO3 data are due to crystal transitions such as the tetragonal-to-cubic conversion at 120C described above. Some ferroelectrics can be modified with additives to reduce or favorably tailor these temperature dependencies. Additives called shifters move the k versus T peaks to a certain temperature range, and broadeners widen the peaks in order to decrease the temperature dependence somewhat. [26, 29]. Common paraelectrics, such as SiO2, Ta2O5, Al2O3, and BCB, do not show phase transition behavior within expected microelectronic operation temperatures of 50 to +150C. 4.4 FREQUENCY AND VOLTAGE EFFECTS Frequency and bias can affect the dielectric constant of both paraelectric and ferroelectric dielectrics by acting through the relevant polarization mechanisms. For instance, for a material to exhibit a constant k value with frequency, the dipole must reverse direction at the same rate for the polarization to remain in synchronization with the field. As the frequency increases, it may outrun the ability of the particular dipole to keep up with the reversals, resulting in the dipole arm being effectively shortened and a decrease in dielectric constant with frequency. Of the charge storage mechanisms described above, only the ionic motion in ferroelectrics, such as the Ti+4 in the 4 cage, is affected at frequencies below the infrared range. Figure 4.6 shows the BaO3 ratio of the dielectric constant measured at various frequencies to the value at low fre-

Figure 4.6 materials.

Effect of frequency on the dielectric constant of paraelectric and ferroelectric

84

DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

Figure 4.7 als.

Effect of bias on the dielectric constant of paraelectric and ferroelectric materi-

quencies for three ferroelectrics and three paraelectrics [26, 30, 31]. Although the paraelectrics show no significant decrease and the ferroelectrics show a sharp dropoff, it should be remembered that ferroelectrics may start with such a high k that, even at GHz frequencies, they may still have much higher dielectric constants. This fact is important in matching dielectric materials to integrated capacitor applications. These curves for BaTiO3 and BST are for sintered particles, whereas the PZT is a solgel thin film. The actual degree of this dropoff, where it begins in frequency and, for that matter, the dielectric constant of the ferroelectrics, are highly dependent upon crystal structure and orientation. Amorphous BaTiO3 gives a k of only 17, similar to paraelectrics, and also has flat frequency response [9, 32]. Figure 4.7 shows k versus bias for Ta2O5 and BST [33]. Many ferroelectrics exhibit a marked decrease in dielectric constant with increasing DC bias, which may be used to advantage in fabricating a variable capacitor for tuning applications but may be a distinct disadvantage for some integrated capacitor applications.

4.5 AGING EFFECTS Capacitors made with ferroelectric formulations can display a decrease of capacitance with time, number of charge cycles [16] and temperature [34]. This phenomenon, called dielectric fatigue or aging, occurs due to crystallographic changes

4.6

COMPOSITION AND MORPHOLOGY EFFECTS

85

related to the relaxation of lattice strain energy and does not occur with amorphous paraelectric materials to any measurable degree [29]. The rate of decay is logarithmic: k = k0 m(log t) The quantity m is sometimes expressed in percent per decade-hour. These effects are reversible with temperature and/or applied field and not all ferroelectrics exhibit them; PZT seems to show cycle fatigue but SrBi2Ta2O9 does not [34]. The loss of capacitance by ferroelectric materials can be completely reversed by heating above the Curie temperature, which turns the material into a paraelectric crystallographic form then, upon cooling, back to a refreshed ferroelectric form.

4.6 COMPOSITION AND MORPHOLOGY EFFECTS The dielectric constant of most ferroelectric materials is a function of film stoichiometry [29, 25], crystal structure, substrate characteristics [27], interfacial reactions, microstructural heterogeneities, lattice defects, mechanical stresses, film thickness [24], and electrode material [16]. Amorphous paraelectrics are largely immune to all of these effects except composition, but at the cost of a much lower k [35]. Figure 4.8 shows the measured dielectric constant of sputtered ferroelectric PZT and BST films deposited on Pt as a function of film thickness along with paraelectric

Figure 4.8

Dielectric constant versus film thickness.

86

DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

Ta2O5. Substrate effects such as stress, defects, grain size, and interdiffusion restrict the ferroelectrics dielectric constant to values below those of the bulk material until the film is at least a few thousand angstroms thick [23]. There is no film thickness or substrate composition dependencies for paraelectrics in general as long as the films are thick enough to be continuous [36]. For this diagram, the dielectric constant values have not been normalized in order to illustrate the large gap between them.

4.7 LEAKAGE AND BREAKDOWN Leakage across a dielectric is a measure of the current in the z-axis through a representative thickness of the film due to a DC voltage, whereas breakdown is the voltage at which the film suffers an irreversible high-current condition. These are simply measures of how good an insulator the material is, but through very thin sections where the conduction may not be strictly ohmic. Resistivities of the dielectric in bulk form are not usually measured or cited in capacitor applications because they often dont relate to thin films; the current is almost always larger than would be expected from bulk properties. That is because leakage and breakdown through thin films are influenced, even controlled, by phenomena at pinholes and other film defects that are not present in the materials in bulk form. Amorphous dielectric films generally have lower leakage currents, higher breakdown voltages, and are less sensitive to impurities. Since paraelectrics are usually amorphous, they may have an advantage in these areas over the same thickness of crystalline ferroelectrics. Figure 4.9 shows the leakage curves through anodized Ta2O5 for a variety of film thicknesses. The data may be displayed in other ways, such as leakage currents through various thicknesses at 5 V over various substrates, as shown in Figure 4.10. The acceptable amount of leakage is application-specific; the metric of under 1 A/cm2 at 5 V is often cited; this might be a large leakage for an analog-to-digital application but a small leakage for decoupling. It should be noted that, for most anodized oxides, the leakage current is somewhat higher in one direction than the other. Figure 4.10 shows the low-leakage direction with the positive plate on the same side as the anodized metal, passing current in the same direction as in the anodization process. Sputtered, CVD, solgel, and other deposition methods do not usually make rectifying oxides like this. Breakdown results in permanent damage to the film so that its leakage remains very high even at lower voltages. Most dielectric materials, inorganic or organic, have a breakdown strength of around 105107 V/cm. In thin films, breakdown is defect-driven by pinholes, cracks, and other flaws. There are two general mechanisms: 1. Thermal BreakdownCurrent flows at a defect causing localized heating which, in turn, results in more current until an avalanche breakdown occurs. 2. Electronic BreakdownConduction electrons are accelerated by the potential field until they reach ionizing energies, resulting in an avalanche breakdown of the material. This usually happens preferentially at defects.

4.7

LEAKAGE AND BREAKDOWN

87

Figure 4.9

Leakage curves through anodized Ta2O5 dielectric films.

Figure 4.10

Leakage current through anodized Ta2O5 films at 5 V.

88

DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

Breakdown voltage decreases with increased temperature and frequency. The breakdown voltage falls off rapidly for most dielectrics over about 100C. The choice of electrode metals can affect breakdown voltage due to roughness, injection of other carriers, and interfacial field effects [37]. Breakdown voltages for anodized and sputtered Ta2O5 are shown in Figures 4.11 and 4.12 [3842]. The reader must be cautioned that reported values of leakage current and, especially, breakdown voltage vary widely in the literature for the same films even when allegedly prepared in the same way. The measured values are a function of the number and size of pinholes and thin spots in the films which, in turn, is a function of the specifics of the deposition conditions and the surface roughness of the substrate. The breakdown field, expressed as MV/cm, will usually be higher for thicker films due to the decreased influence of flaws and pinholes; this is probably the case in Figure 4.12. Breakdown itself can be very locally destructive, resulting in visible holes in the overlaying plates and splashed metal. One interesting observation is that if the top electrode is thin (less than about 1500 ), defects will vaporize an area of electrode metal that is larger than the defect in the dielectric so that the resulting damage will be nonshorting. [41, 42]. This has been used in polymer film discretes as a way to actually clear out weak spots in a capacitor. These capacitors have sputtered metal electrodes on the polymer layers that can be as thin as 300 . Such thin electrodes are used because many layers are typically stacked in parallel to give a high capacitance, and using thin metal allows more layers to be placed in a given height. Since the electrodes are also in parallel, their overall resistance is low. As an additional

Figure 4.11 strates.

Breakdown voltages for anodized and sputtered Ta2O5 films over various sub-

4.8

DISSIPATION FACTOR

89

Figure 4.12

Breakdown voltages for thin Ta2O5 films plotted as electric fields.

benefit, these metal films are thin enough to be burned away from defects by high local current density and are, therefore, self-healing. The maximum working voltage is defined as the potential that results in either the highest acceptable capacitor failure rate or the maximum allowable leakage current and is usually set well below the breakdown voltage. If the capacitor lifetime is the limiting factor, the maximum working voltage is very hard to quantify with certainty, since field failure data may take so long to accumulate that it is never known precisely. Accelerated testing, with voltage and/or temperature, may only give a rough idea of the average lifetime in actual usage. If the maximum working voltage is set by the maximum allowable leakage current, this may be adjusted by changing the dielectric thickness. Figure 4.13 shows that, as a general trend, the breakdown field is lower for materials with higher dielectric constants, although even the high-k ferroelectrics exhibit breakdown fields of over 100 V for a 1 micron film (1 MV/cm) [16, 43]. Under high field conditions, the log of time to breakdown is proportional to applied field for ferroelectrics, as shown in Figure 4.14 [16, 23], whereas paraelectrics do not show this tendency.

4.8 DISSIPATION FACTOR The dissipation factor is a measure of how much energy is lost in the dielectric during AC operation. If the mobile charges in the dielectric cannot respond fast enough

90

DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

Figure 4.13

Relationship between breakdown field and dielectric constant.

Figure 4.14

Relationship between applied field and time to breakdown for ferroelectrics.

4.9

COMPARISON TO EIA DIELECTRIC CLASSIFICATIONS

91

to the changing fields or if there are resistive losses in the dielectric or capacitor plates, then the current and voltage deviate from exactly the ideal value of 90 out of phase. This angular difference is called the loss angle and usually has the symbol . The tangent of the loss angle is called the dissipation factor, and is zero for a capacitor that dissipates no wasted energy. The reciprocal of the dissipation factor is the quality factor, Q. A dissipation factor under 0.1% (tan = 0.001) is considered to be quite low and 5% is high. If the entire capacitor is considered, the dissipation factor must also include losses due to leakage through the dielectric and resistive losses in the plates and leads. This is explained in more detail in Chapter 8. Generally, very low dissipation factors are desired for RF applications in which signal losses must be avoided, but much higher values can be tolerated for energy storage applications such as decoupling.

4.9 COMPARISON TO EIA DIELECTRIC CLASSIFICATIONS The Electronics Industry Association (EIA) classifies capacitor dielectrics according to their dielectric constant, their value stability against temperature, and their tolerance. These codes are commonly used in the catalogs to describe discretes, providing a language for specification between the designer and the supplier. Dielectrics for integrated capacitors are not yet standardized to the point that they are assigned these codes, but this will certainly become necessary as the technology develops. To aid the transition, it might be instructive to list the codes here and suggest how they might be linked to various candidate dielectrics for integrated capacitors. The EIA temperature codes, shown in Table 4.3, give the suggested temperature range for the dielectric and the maximum amount its value would be expected to change over that span. As examples, three common classifications are: X7R: Operating temperature = 55C to +125C, maximum capacitance change = 15% Y5V Operating temperature = 30C to +85C, maximum capacitance change = +22% to 82% Z5U: Operating temperature = +10C to +85C maximum capacitance change = +22% to 56%. Consider the performance of two capacitors, each listed at 10 nF, but one is in X7R and one is in Z5U. Due to their very different temperature responses at 85C, the X7R could be as low as 8.5 nF, whereas the Z5U could drop to 4.4 nF. A second set of codes are used for temperature compensating capacitors, which have little or no temperature dependency. Examples include NPO, COG, N150, N750, and SL. A second stability issue arises from the degradation of the dielectric constant with time, as described in Section 4.5. Gradual changes in the crystal structure of ferroelectrics causes their k to decrease, an effect not observed in paraelectrics since they are almost all amorphous. This decline begins as soon as the film is formed and

92

DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

Table 4.3 Low Temperature X Y Z 55C 30C +10C

Electronics Industry Association (EIA) temperature codes High Temperature 2 4 5 6 7 +45C +65C +85C +105C +125C A B C D E F P R S T U V % Change +1.0% 1.5% 2.2% 3.3% 4.7% 7.5% 10% 15% +22% +22% to 33% +22% to 56% +22% to 82%

exhibits a logarithmic behavior. For instance, if the degradation is quoted to be 3% per decade, then the capacitance will drop 3% from 100 hours to 1000 hours, and another 3% from 1000 to 10,000 hours. Its the nature of ferroelectrics that raising their temperature past their Curie point resets the crystal structure, raising the dielectric constant back up to its original value and resetting the degradation clock to zero. Since most high-k discretes are based on various formulations of barium titanate, this reset temperature is around 120C. The EIA then groups these various behaviors into dielectric classes: Class 1 (low dielectric constant, ultrastable)Usually employs a dielectric with a k of less than 100 and almost always carries the EIA coding of C0G, which means it operates from 55 to 125C, and changes no more than 30 ppm over the entire temperature range. The aging effect is negligible. Class 2 (medium dielectric constant, stable)Dielectric constant is 20005000 and temperature stability is code A to R, up to 15%. Aging is up to 3% per decade. Example: X7R. Class 3 (high dielectric constant, stable)Dielectric constant is 400020,000 and temperature stability is code T to V, +22% to 82%. Aging is up to 6% per decade. Example: Z5U. In the world of discretes, Class 1 dielectrics are paraelectric in composition and behavior, and Class 2 and 3 are ferroelectrics, usually based on barium titanate. Class 2 may have various additives to moderate the behavior of the dielectric relative to Class 3. With the EIA designations now defined, how do they relate to the emerging integrated dielectrics? Class 1 will include all of the paraelectrics listed in Table 4.1 by virtue of their low k, temperature stability, and lack of aging effect. Class 3 will include the pure, single-crystal ferroelectrics. The authors literature search revealed

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93

no integrated capacitor dielectrics that purposely included additives intended to moderate the ferroelectric behavior of a Class 3 material into Class 2, but some thin-film ferroelectrics described achieved Class 2 status due to imperfect crystal structure as formed. One type of dielectric that might always be Class 2 is the combination of a high-k ferroelectric powder dispersed in a matrix of curable polymer, which is described in detail in Chapter 6. The idea behind this approach is to perform the high-temperature annealing on a powdered material, then combine it with an easily cured polymer, typically an epoxy, so that it can be easily processed on an organic board. Since it contains both Class 1 and Class 3 materials, its overall behavior is mixed. Its dielectric constant is under 100, typical of Class 1, but its temperature stability and aging effects put it in Class 2 or the lower part of Class 3, depending on its formulation. Finally, the EIA defines a set of tolerance codes as follows: A B C D F G J K M 0.05% 0.10% 0.25% 0.50% 1% 2% 5% 10% 20%

Both the literature and the authors experience indicate that it is difficult to do much better than 5% on a consistent basis for either thick or thin processing. As integrated capacitors come into more general usage, it might be important to use these codes in order to provide a bridge between the two technologies, discrete and integrated.

4.10 MATCHING DIELECTRIC MATERIALS TO APPLICATIONS Table 4.4 is a summary of the relative dielectric properties of paraelectrics and ferroelectrics. Ferroelectrics such as BaTiO3, PbxZr1xTiO3, and BaxSr1xTiO3 can exhibit dielectric constants up to three orders of magnitude higher than those of paraelectric materials such as SiO2, Al2O3, Ta2O5, and BCB. However, the dielectric properties of ferroelectrics are typically a stronger function of temperature, frequency, film thickness, and bias, resulting in significant nonlinearities in their performance. Also, the dielectric constant of some ferroelectrics degrades with time. All of these factors must be kept in mind when determining what dielectric material is right for a specific application. Required capacitor values for electronic systems can cover an enormous range,

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DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

Table 4.4

Comparison of paraelectric and ferroelectric dielectrics Paraelectrics Ferroelectrics Up to 1000s Can be highly dependent due to crystal phase transitions and ion mobility Decreases significantly, typically above a few GHz Highly dependent due to effects on crystal structure Decreases with DC bias k can decrease significantly with cycles and time Film must be crystalline May require up to 700C in O2

k k vs. T

250 Little dependence, <500 ppm/C Little dependence No dependence since amorphous No dependence None Little or no dependence None

k vs. frequency k vs. film thickness k vs. bias Dielectric fatigue k vs. film structure Cure requirements

from about 1 pF to thousands of F. Table 4.5 gives approximate values and requirements for acceptable leakage and stability for various capacitor applications. These trends are approximate but serve to show that, typically, lower-valued capacitors require more stringent leakage and stability behavior. As a result, certain types and thicknesses of dielectrics are more suitable than others for the various applications expected for integrated capacitors. The following subsections will give guidelines for selecting dielectrics for these applications, assuming that they could be fabricated on the substrates. The following two chapters deal more with the issues of how to fabricate these materials into practical integrated capacitors. Some of the more important applications for integrated capacitors, such as decoupling, will be addressed individually and in much more detail in subsequent chapters. 4.10.1 Decoupling and Energy Storage The ubiquitous need for high-frequency decoupling capacitors to supply the transient current requirements of fast logic devices is well documented [4448]. Since

Table 4.5 Application Filtering, timing A/D conversion Termination Decoupling Energy storage

Values and requirements for capacitor applications Tolerance Acceptable Requirements Leakage High High Lower Lower Lower Low Low Higher Higher Higher Stability Required Moderate Very high Lower Lower Lower Acceptable Parasitics Filtering: low Timing: higher Higher Higher Very low Lower

Value Range 1 pF100 pF 1 pF10 nF 50200 pF 1 nF100 nF 1 F and up

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95

the purpose of decoupling capacitors is to provide low-impedance power for a single clock cycle, their most important characteristics are high capacitance and low inductance. The values of these capacitors will typically be among the largest on the substrate, from perhaps 20 to 1000 nF. Even higher capacitor values may be required for other energy storage applications such as DRAM backup power. The inductance of an integrated capacitor is not a function of the dielectric material and is typically much lower than can be obtained with surface-mount discretes, making integrated capacitors ideal for this purpose. Tolerance is not important as long as they provide a minimum amount of capacitance. The resulting capacitance of the structure as a function of film composition, morphology, and thickness as well as the capacitance as a function of frequency, bias, and time is not an issue as long as the minimum capacitance level is maintained under all operating conditions. Ferroelectric films or ferroelectric powders in epoxy generally exhibit less stable and predictable electrical performance in all of these respects than paraelectrics but their much higher dielectric constant can enable enough extra capacitance to be designed in from the start to make up for these shortcomings. Paraelectric materials are much more stable and predictable but cannot achieve the high capacitance of ferroelectrics. As a result, the unstable nature of ferroelectrics is not so important in decoupling and energy storage, whereas their high capacitance density is an advantage. Table 4.6 shows the length in mils required for the side of a square integrated capacitor to provide 100 nF. Film thicknesses of 2000 were chosen for most materials in this comparison because this thickness may be practically achieved by deposition (sputtering or CVD), anodization, and solgel, although deposited films may suffer from yield problems when they are this thin [49]. From Table 4.6, low-k spinon paraelectrics such as BCB or silica glasses result in unacceptably large structures, whereas the higher-k anodized or deposited paraelectrics can provide 100 nF in areas which are larger than the footprint of a discrete but will fit in the area under a chip. A 3 micron layer of cured epoxy plus ferroelectric powder falls into the mid-

Table 4.6 Square plate size to provide 100 nF for various integrated capacitor technologies Dielectric Constant 2.7 3.7 3.7 9 24 50 90 2000 Thickness (m) 2 1 0.2 0.2 0.2 0.2 3 0.2 Specific Capacitance (nF/cm2) 1.2 3.3 16 40 110 220 27 8900 Length of Side for Square 100 nF Cap (mils) 3600 2200 970 620 380 270 760 40

Dielectric BCB Spin-on glass SiO2 Al2O3 Ta2O5 TiO2 Epoxy + ferroelectric paste High-k ferroelectric

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DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

dle of the range of thin-film paraelectrics. Only thin-film ferroelectrics can produce a decoupling capacitor that is smaller than a discrete of similar capacitance but, of course, footprint is a secondary consideration since the integrated component will not be on the surface anyway and will exhibit far less parasitic inductance. As an example, 1500 anodized Ta2O5 film would require 0.71 cm2 to provide 100 nF and, under 5 V bias, would leak approximately 1 A/cm2. The resulting power loss due to leakage is then only about 3.6 W, which would not overheat the capacitor or overtax the power supply. A similar calculation for high-k ferroelectrics is even more favorable since the films can be thicker to give the same specific capacitance, which will result in less leakage per unit area, and/or the plates can be made smaller in area. 4.10.2 Analog Functions In many analog functions such as RF/wireless, A/D conversion, and filtering and timing applications, required capacitor values range from about 1 to 100 pF, several orders of magnitude below those needed for decoupling. For these values, capacitor dielectrics that give high specific capacitance due to either high k or thin films should be avoided if the resulting plate size would be so small that precision would be unobtainable with board-scale lithographic resolution. For example, a 1 pF capacitor realized with 3000 of anodized Ta2O5 (about the thickest the film can be anodized) would be only about 1.5 mils on a side but the same capacitor made from 3 microns of BaTiO3 with k = 2000 would be 0.5 mils across. Achieving 5% tolerance on a 1 1 mil capacitor plate requires a photolithographic tolerance of 0.025 mils or 0.6 m. Thus, the use of thick layers of relatively low dielectric constant materials (<10) may be better for these low-valued components so that the resulting devices are large enough to be fabricated with sufficient dimensional tolerance to provide acceptable value tolerance. BCB and SiO2 dielectrics are feasible dielectrics for this; 5 microns of BCB would require 18 18 mils to give 1 pF, which requires 0.44 mils or 11 m for 5% tolerance. Thicker films are also favored for most analog applications since leakage is very important and higher yields will result. It may be possible to use the interlayer dielectric for these small capacitors, thus saving a masking step. Besides problems with capacitor size, ferroelectrics are not as suitable as paraelectrics in these applications because of their lack of stability and predictability with respect to frequency, film thickness, film morphology, temperature, bias, and time. Paraelectrics also tend to have a lower dissipation factor, which can be important in RF applications. However, the decrease in k with frequency and bias for some ferroelectrics has been used as a tuning feature. 4.10.3 Termination of Transmission Lines As system bus speeds increase, a significant number of lines must be terminated to avoid signal reflection. In CMOS systems, purely resistive termination may consume unacceptable amounts of DC power. Thus, an AC termination scheme con-

REFERENCES

97

sisting of series resistance and capacitance is preferred. Over 2000 discretes are used on a Pentium III mother board for termination [50]. Integrating R/C series terminators such as 50 /100 pF or 100 /50 pF into either passive networks or the mother board itself is highly desirable. Exact tolerance of these capacitors is not critical, as long as they have a significantly lower impedance than the series resistor at the frequencies of interest. 5% tolerance is much tighter than what is required. Leakage is also not an issue for capacitors in R/C terminations as the expected leakage currents are very low compared to the drive capabilities of buffer outputs that are required to drive transmission lines in the 50 range. Therefore, the choice of dielectrics for termination is driven by the same considerations for decoupling, except that less capacitance is required.

REFERENCES
1. S. Ezhilvalavan and T. Tseng, Preparation and Properties of Tantalum Pentoxide (Ta2O5) Thin Films for Ultra Large Scale Integrated Circuits Applications, A Review, Journal of Materials Science: Materials in Electronics, 10, 9, 1999. 2. R. Berry, P. Hall, and M. Harris, Thin Film Technology, Van Nostrand, New York, p. 271, 1968. 3. L. Maissel and R. Glang, Handbook of Thin Film Technology, McGraw-Hill, New York, 1970. 4. H. Nalwa, Handbook of Low and High Dielectric Constant Materials and Their Applications, 1st ed., vol. 2, Academic Press, New York, 1999. 5. H. Nalwa (ed.), Handbook of Thin Film Materials, vol. 3, Ferroelectric and Dielectric Thin Films, Academic Press, San Diego, p. 1, 2002. 6. J. Anderson, Dielectrics, Chapman and Hall, London, p. 49, 1964. 7. A. Von Hippel (ed.), Dielectric Materials and Applications, Wiley, New York, p. 5, 1954. 8. R. Ulrich, L. Schaper, D. Nelms, and M. Leftwich, Comparison of Paraelectric and Ferroelectric Materials for Applications as Dielectrics in Integrated Capacitors, IMAPS Journal, 23, 2, 172, 2000. 9. W. Liu et al., Low-Temperature Fabrication of Amorphous BaTiO3 Thin-Film Bypass Capacitors, IEEE Electron Device Letters., 14, 7, 320, 1993. 10. Y. Park, X. Li, et al., Effects of Annealing on O2 and N2 on the Microstructure of Metal Organic Chemical Vapor Deposition Ta2O5 Film and the Interfacial SiO2 Layer, Journal of Materials Science: Materials in Electronics, 10, 113, 1999. 11. L. Maissel and R. Glang, Handbook of Thin Film Technology, McGraw-Hill, New York, p. 16, 1970. 12. C. Coombs (ed.), Printed Circuits Handbook, 5th ed., McGraw-Hill, New York, 2001. 13. P. Garrou, Polymer Dielectrics for Multichip Module Packaging, Proceedings of the IEEE, 80, 12. 1992. 14. J. Sergent and C. Harper (eds.), Hybrid Microelectronics Handbook, 2nd ed., McGrawHill, New York, pp. 14, 1995.

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DIELECTRIC MATERIALS FOR INTEGRATED CAPACITORS

15. B. Gnade, S. Summerfelt, and D. Crenshaw, Processing and Device Issues of High Permittivity Materials for DRAMS, In Science and Technology of Electroceramic Thin Films; NATA ASI Series, Auciello and Waswer, eds., vol. 284, p. 373, 1995. 16. L. Manchanda and M. Girvitch, Yttrium Oxide/Silicon Dioxide: A New Dielectric Structure for VLSI/ULSI Circuits, IEEE Electron Device Letters, 9, 4, 1988. 17. B. Lai and J. Lee, Leakage Current Mechanism of Metal-Ta2O5-Metal Capacitors for Memory Device Applications, Journal of the Electrochemical Society, 146, 1, 266, 1999. 18. C. Chaneliere et al., Dielectric Permittivity of Amorphous and Hexagonal Electron Cyclotron Resonance Plasma Deposited Ta2O5 Thin Films, Electrochemical and SolidState Letters, 2, 6, 291, 1999. 19. R. Kambe, R. Imai et al., MCM Substrate with High Capacitance, In Proceedings of the MCM 94 Conference, 1994. 20. A. Gitellson et al., Physical Properties of (Ba,Sr)TiO3 Ferroelectric Thin Films in Weak Electric Fields, Soviet Physics Solid State, 19, 7, p. 1121, 1997. 21. W. Merz, The Electric and Optical Behavior of BaTiO3 Single-Domain Crystals, Physical Review, 76, 8, 1221, 1949. 22. J. Scott, High-Dielectric Constant Thin Films for Dynamic Random Access Memories (DRAM) In Annual Review of Materials Science, vol. 28, pp. 79100, 1998. 23. Y. Tu et al., Synthesis and Electrical Characterization of Thin Films of PT and PZT Made From a Diol-Based Sol-Gel Route, Journal American Ceramic Society, 79, 2, 441, 1996. 24. N. Tohge, S. Takahashi, and T. Minami, Preparation of PbZrO3-PbTiO3 Ferroelectric Thin Films by the Sol-Gel Process, Journal American Chemical Society, 74, 1, 67, 1991. 25. D. Liu et al., Integrated Thin Film Capacitor Arrays, In Proceedings of the International Conference and Exhibition on High Density Packaging and MCMs, IMAPS, p. 431, 1999. 26. U. Syamaprasad et al., A Modified Barium Titanate for Capacitors, Journal American Ceramic Society, 70, 7, C-147, 1987. 27. A. Gitellson et al., Physical Properties of (Ba,Sr)TiO3 Ferroelectric Thin Films in Weak Electric Fields, Soviet Physics Solid State, 19, 7, 1121, 1997. 28. W. Merz, The Electric and Optical Behavior of BaTiO3 Single-Domain Crystals, Physical Review, 76, 8, 1221, 1949. 29. NOVACAP Technical Brochure from www.novacap.com. 30. A. Von Hippel (ed.), Dielectric Materials and Applications, Wiley, New York, p. 300, 1954. 31. H. Yoshino, T. Ihara, S. Yamanaka, and T. Igarashi, Tantalum Oxide Thin Film Capacitors Suitable for Being Incorporated Into an Integrated Circuit Package, In IEEE/CHMT 89 Japan IEMT Symposium, p. 156, 1989. 32. J. Kim, A. Garg et al., High Frequency Response of Amorphous Tantalum Oxide Thin Films, IEEE Transactions of Component Packaging Technology, 24, 3, 526, 2001. 33. B. Lai and J. Lee, Leakage Current Mechanism of Metal-Ta2O5-Metal Capacitors for Memory Device Applications, Journal of the Electrochemical Society, 146, 1, 266, 1999.

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34. Arita et al., Ferroelectric Nonvolatile Memory Technology with Bismuth Layer Structured Ferroelectric Materials, In 10th International Symposium on Applications of Ferroelectrics, New Brunswick, NJ, IEEE, New York, p. 13, 1996. 35. R. Ramesh (ed.), Thin Film Ferroelectric Materials and Devices, Kluwer Academic, Boston, 1997. 36. N. Kim, K. Coates, G. Kunze, C. Chien, and M. Tanielian, Development of Multi-Chip Modules with Integrated Thin Film Passive Elements, In 1997 International Symposium on Microelectronics, Philadelphia, PA, 1997. 37. B. Hendrix and G. Stauf, Low Temperature Process for High Density Thin Film Integrated Capacitors, In Proceedings of the 2000 Conference on High-Density Interconnect and Systems Packaging, p. 342, 2000. 38. R. Pandey, Defect and Failure Mode Analysis of Large Area Ta2O5 Integrated Capacitors, MS thesis, Dept. of Chemical Engineering, University of Arkansas, May 2001. 39. A. Date, Fabrication of Capacitors, Inductors and Resistors on Single Flex Substrates, MS thesis, Dept. of Chemical Engineering, University of Arkansas, August 2000. 40. C. Gross, Integrated Stacked Capacitor and AC Transmission Line Termination Fabrication Using Ta Anodization Technology, MS thesis, Dept. of Chemical Engineering, University of Arkansas, December 2000. 41. E. Rymaszewski and P. Jain, Embedded Thin Film CapacitorsTheoretical Limits, IEEE Transactions on Advanced Packaging, to be published Aug. 2003. 42. N. Axelrod, Journal Electrochemical Society, 116, 460, 1969. 43. D. Scheck, Dow Chemical Corporation, private communication. 44. L. Schaper, R. Ulrich, D. Nelms, E. Porter, T. Lenihan, and C. Wan, The Stealth Decoupling Capacitor, In 47th Proceedings of the Electronics Components and Technology Conference, San Jose, CA, May 1997. 45. B. Sen and R. Wheeler, Performance Comparison of Discrete and Buried Capacitors, IMAPS Journal, 19, 4, 449, 1996. 46. J. Cain, The Effects of ESR and ESL in Digital Decoupling Applications, AVX Corporation, March 1997. 47. T. Roy, L. Smith, and J. Prymak, ESR and ESL of Ceramic Capacitor Applied to Decoupling Applications, In Proceedings of the 7th Topical Meeting on Electrical Performance of Electronic Packaging, IEEE, West Point, NY, p. 213, Oct. 1998. 48. R. Frye, Passive Components in Electronic Applications: Requirements and Prospects for Integration, International Journal of Microcircuits and Electronics Packaging, 19, 4, 483, 1996. 49. G. Morcan, T. Lenihan, L. Schaper, and W. Brown, Characterization of Thin Film Tantalum Oxide Capacitors on Polyimide Substrates, IEEE Transactions on Advanced Packaging, 22, 3, 499, 1999. 50. R. Heistand II et al., Advances in Passive Integration for C/RC Arrays and Networks with Novel Thin and Thick Film Materials, In Proceedings of the 36th IMAPS Nordic Conference, Helsinki, p. 41, 1999.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 5

SIZE AND CONFIGURATION OF INTEGRATED CAPACITORS

RICHARD K. ULRICH

The chapter begins with an analysis of the required footprints of integrated capacitors based on the dielectric properties discussed in the previous chapter and a short discussion of capacitor layout options and tolerance issues. This is followed by an evaluation of the advantages of using two dielectrics to cover the entire typical required range of capacitor values. Finally, the theoretical limits of capacitance and breakdown voltage are discussed.

5.1 COMPARISON OF INTEGRATED AND DISCRETE AREAS Table 5.1 shows the case sizes of surface-mount discretes, including a 10 mil keepaway distance, along with maximum capacitance values commonly available today. The capacitance densities on an area basis for the larger case sizes are much higher than are attainable from any integrated dielectric. The best that can be achieved for integrated components would be with about 2000 of ferroelectric with k = 3000, which would give only 13 F/cm2, whereas surface mounts can beat this by one or two orders of magnitude. High-k ferroelectrics require high-temperature processing; the best that can be achieved with a process that can be tolerated by an organic board would be a few tenths of a F/cm2. Integrated capacitors cannot compete purely on the basis of specific capacitance per footprint area but, of course, they do not since they could be buried and would take up zero surface space. (See Table 5.2.) An 0805 Ta capacitor as of the writing of this book can provide 20 F. It contains on the order of 100 cm2 of dielectric area, about the same as a sheet of notebook paper, in a volume of only a few cubic millimeters. It is beyond the scope of this book to review discrete capacitor technology but, in the case of Ta capacitors, anodized powder technology makes it possible to fold this kind of area into very small spaces, resulting in high volumetric capacitances.
101

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SIZE AND CONFIGURATION OF INTEGRATED CAPACITORS

Table 5.1 Size Code 0805 0603 0402 0201

Approximate capacitance values for surface-mount discretes Approximate Maximum Capacitance 100 F 10 F 1 F 10 nF Maximum Capacitance per Area 2300 F/cm2 400 F/cm2 67 F/cm2 1.3 F/cm2

Size with 10 mil Keep-Away (mm mm) 2.5 1.75 2.00 1.25 1.50 1.00 1.00 0.75

Figure 5.1 shows the length required for the side of a square integrated capacitor to provide a given amount of capacitance for various dielectric materials. The xaxis is the total capacitance of the structure, not the specific capacitance, and the yaxis is the required length of one side of the square plate of dielectric material in mils. Since integrated capacitors are area-ruled, the lines have a slope of 1/2 on loglog coordinates. A few representative dielectrics are shown for some practical thicknesses. Other dielectric materials of known dielectric constant and thickness may be interpolated into the diagram to show their required sizes. The four horizontal dashed lines represent the areas of common surface-mount components along with a 10 mil keep-away distance. For comparison purposes, these surface-mount components were converted to square areas so that the square plate width for these units is the average side length required (Figure 5.1). It is also clear from Figure 5.1 that integrated capacitors do not necessarily have a smaller footprint than their surface-mount counterparts. For instance, using 2000 of a paraelectric such as Al2O3 or Ta2O5 would result in a smaller footprint only for capacitor values below a few nF. For micron thicknesses of BCB, polyimide, SiO2, or SiN, the crossover is around 10100 pF. Figures 5.3 and 5.4 show the relative sizes of planar integrated capacitors and surface-mount discretes for values of 50 pF and 50 nF, respectively. The surface mounts are shown with a 10 mil keepaway distance around them. The median size of a capacitor in a cell phone is about 110 nF.
Table 5.2 Capacitance values for integrated capacitors Dielectric Constant 4 3.2 2.7 70 3.7 9 24 2000 Dielectric Thickness (m) 75 50 0.5 5 0.1 0.1 0.1 0.5 Specific Capacitance (nF/cm2) 0.047 0.057 4.8 12 33 80 210 3500 Capacitance in 0805 Area (nF) 0.0003 0.0038 0.32 0.81 2.2 5.4 14 240

Dielectric FR4 Mylar BCB Ferroelectric particles in epoxy SiO2 Al2O3 Ta2O5 Crystalline ferroelectric

Figure 5.1

Square plate sizes required for various integrated capacitor technologies.

Figure 5.2

Small-valued capacitors made from 5 microns of benzocyclobutene. 103

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SIZE AND CONFIGURATION OF INTEGRATED CAPACITORS

Figure 5.3

Relative sizes of integrated and surface-mount capacitors to give 50 pF.

Figure 5.4

Relative sizes of integrated and surface-mount capacitors to give 50 nF.

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LAYOUT OPTIONS

105

5.2 LAYOUT OPTIONS There are two basic configurations for integrated capacitors, parallel and floating plate, as shown in Figure 5.5. The floating plate design has the possible advantages in that connections need to be made to only the top level of metal, avoiding the necessity of making a via down to the bottom plate. Also, this configuration avoids having a higher leakage current in one direction than in the other if the dielectric is somewhat rectifying, as many anodized oxides are. The drawback of the floating plate capacitor is that it has four times less capacitance per unit area than the parallel configuration because the floating plate is actually two capacitors in series, each using only one-half the available area. An interesting aspect of these two configurations is how they respond to dielectric defects. If a parallel plate capacitor suffers a dielectric defect that shorts out the component, the capacitor simply disappears and becomes a DC conductor, although probably a high-resistance one. But a floating plate integrated capacitor that suffers a short in one side becomes a capacitor of double its original value! The author uses this phenomenon as an exam question in his microelectronics class every semester. The layouts in Figure 5.5 are somewhat schematic; a more accurate representation is shown for a built-up integrated capacitor in Figure 5.6. There are three main configurations for the top plate connection that can be used depending on the nature of the capacitor dielectric. Robust dielectric materials such as polymers thicker than about a micron should have no trouble tolerating a via directly on the top plate but very thin ceramics, such as submicron oxides, may be perforated by either the process or subsequent uneven mechanical stresses caused by thermal excursions during use. If the dielectric is thick enough to provide step coverage over the bottom plate, the middle configuration can be used. Some sputtered and even anodized films can do this, especially if the bottom plate has a slope to it due to purposeful undercutting of the mask when it was etched. If the dielectric is so thin that it cannot

Figure 5.5

The two basic configurations of integrated capacitors.

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SIZE AND CONFIGURATION OF INTEGRATED CAPACITORS

Figure 5.6

Connection options for built-up integrated capacitors.

provide the step coverage needed to separate the top and bottom plates, then another deposition and pattering step may be required to deposit some interlevel dielectric in between them.

5.3 TOLERANCE Since the value of an integrated capacitor is proportional to its area, the scatter in resulting capacitor values are a function of the square of the feature width variation of the patterning technique. As shown in Figure 5.7, if an area of L2 is desired for the component, then to achieve a 5% tolerance of this area, the patterning technique must have no more than 2.47% uncertainty. In general, the patterning tolerance must be significantly better than the required value tolerance. How much better depends on the size of the capacitor relative to the standard deviation of the patterning technology: L + sd Component tolerance = L

to L
2

L sd

where: L = desired length of one side sd = standard deviation of the patterning technique

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MIXED DIELECTRIC STRATEGIES

107

Figure 5.7

Relationship between patterning tolerance and capacitor tolerance.

5.4 MIXED DIELECTRIC STRATEGIES Board-level capacitor values in common microelectronic systems cover a very wide range, from about 1 pF to many F. If a single dielectric is used for all integrated capacitors, their areas would range over a million and their linear sizes would span a thousand. If that dielectric were 1000 of Ta2O5, the 1 pF capacitors would be only 22 microns on a side but the 1 F capacitors would be 21.7 mm. To achieve 5% tolerance on the small capacitor, the plate widths must be controlled to about half a micron, which is not practical for board-level patterning. At the other extreme, if 4 m BCB is used for all capacitors, the 1 pF would be 417 m to a side, which would require width control to about 10 microns for 5% tolerance, which is quite practical, but the 1 F would be very large (417 mm to a side). A capacitor over a foot wide could not be realistic even if split between several layers. One solution is to combine two dielectrics, one with low k and one with high k, to cover the entire range of integrated capacitor values. The vast majority of capacitors will fall into a range that can be covered with this strategy, whereas the few very large energy storage capacitors, maybe larger than a few F, would be left as surface discretes. The dielectric for the low values could be the interlayer insulating material, which is available on the board already. As an example, consider the two dielectrics in the preceding paragraph: 4 m BCB with a specific capacitance of 0.575 nF/cm2 and 1000 of sputtered Ta2O5 that gives 212 nF/cm2 (Figure 5.8). Perhaps the BCB is being used as a dielectric for an HDI flex substrate. The capacitor range requirement is 1 pF to 1 F. As mentioned above, the smallest cap, 1 pF, will be 0.417 mm to a side and would require a patterning reproducibility of 10 microns to achieve 5% value variance. Since this is the smallest capacitor size required, switching over to the higherk dielectric at this same size for the higher-capacitance material would minimize the total capacitor area on the board. A Ta2O5 capacitor 0.417 mm on a side would have a value of 260 pF. As a further benefit, the low-value capacitors are made with the

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SIZE AND CONFIGURATION OF INTEGRATED CAPACITORS

Figure 5.8 Two dielectrics of widely separated specific capacitances may be used to cover a wide capacitor range with reasonable patterning requirements.

thicker dielectric, which gives lower leakage in applications where that is important, such as RF functions and A/D conversion. A similar strategy could be employed with FR4 if it were made very thin. Intarsia used this approach for its builtup passive modules on glass. They used anodized Al2O3 with 0.5 nF/cm2 for large capacitors and 5 m BCB for those under 5 pF [1].

5.5 CV PRODUCT The CV product is a measure of the efficiency of a dielectric film to store charge. The voltage used is generally the rated voltage or the maximum voltage, which are considerably below the breakdown voltage. For a discrete capacitor, this is usually expressed as CV per gram of internal dielectric and metal in order to reflect a mass efficiency. For discrete capacitors based on anodized Ta powder, CV products of 80,000 F-V/gram are on the market. A capacitor filler with this CV product using 1000 of anodized Ta2O5 and a rated voltage of 10 V would have a dielectric area of about 38,000 cm2 per gram, a square almost two meters on a side. Since 1000 of Ta2O5 has a specific capacitance of 212 nF/cm2, this gram of material would have a capacitance of 8000 F. For integrated capacitors, CV per unit area would be more appropriate. That same 1000 of Ta2O5 rated at 10 V would have 2.12 F-V/cm2. Other measures related to the CV product are found in the integrated capacitor literature, such as the product of specific capacitance and breakdown field or the product of dielectric constant and breakdown field.

5.6

MAXIMUM CAPACITANCE DENSITY AND BREAKDOWN VOLTAGE

109

5.6 MAXIMUM CAPACITANCE DENSITY AND BREAKDOWN VOLTAGE A study by Rymaszewski and Jain uses an empirical correlation between the dielectric constant of a material and its breakdown voltage in order to suggest the limits of what is possible in capacitance density and maximum voltages for integrated capacitors [2]. It has long been known that the breakdown voltage is lower for dielectric materials with higher dielectric constants. They plotted the two quantities from literature [3] as shown in Figure 5.9 and determined that the maximum breakdown voltage for a wide range of dielectrics can be fitted by the empirical relationship 20 Ebd = MV/cm k where Ebd = breakdown field, MV/cm k = dielectric constant This data is for a wide range of film thicknesses and that combined with the fact that breakdown is defect driven probably accounts for the scatter below the line. 2 The form of the empirical fit, kEbd = constant, implies that all the dielectrics will have the same maximum energy density before breaking down, but the theoretical reasons for this are unclear. Rymaszewski and Jain utilized this observation to pre-

Figure 5.9

The breakdown field is lower for materials with higher dielectric constants.

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SIZE AND CONFIGURATION OF INTEGRATED CAPACITORS

dict the limits of integrated capacitor performance. Remembering that the capacitance density is C k = 0.885 nF/cm2 A t the following relations can be derived by eliminating t, k, or capacitance density: t Vbd = 2000 Volts k
k Vbd = 1770 Volts C/A t Vbd = 1880 Volts C /A

where C/A = specific capacitance, nF/cm2 k = dielectric constant t = thickness, m Vbd = breakdown voltage, Volts Ebd = breakdown field = Vbd/t, MV/cm Finally, the area-specific CV product using the maximum breakdown voltage is found to not be a function of film thickness since both capacitance and breakdown voltage use thickness with opposite exponents. Remember that this relationship is for the maximum observed breakdown voltages. Actual breakdown voltages are defect-driven and depend on the quality of the film and the roughness of the substrate. Also, it is more common to use the working voltage, which is derated from the breakdown voltage by at least 50%: nF Volts CVbd = 1770k A cm2 If the relationship between breakdown field and dielectric constant is true, then these equations provide the design space for deciding which dielectric to use (through the dielectric constant) and the film thickness to provide a given capacitance density at a required breakdown voltage. Referring back to the measured breakdown data for Ta2O5 films in Chapter 4, Figure 4.12, it can be seen that these equations predict a breakdown field at least twice as high as observed with 5002000 films of anodized Ta2O5 but are much closer for films thicker than 0.5 m, in which defects would not be expected to play such a large role. It must be emphasized that this is an empirical observation but is based on a large amount of data from various sources reporting on films that are candidates for

REFERENCES

111

integration. However, there are reports of data points that lie well above the line in Figure 5.9 [4].

REFERENCES
1. H. Clearfield, S. Wijeyesekera et al., Integrated Passive Devices using Al/BCB Thin Films, In Proceedings of the 1998 International Conference on Multichip Modules and High Density Packaging, IEEE Press, New York, p. 501, 1998. 2. E. Rymaszewski and P. Jain, Embedded Thin Film CapacitorsTheoretical Limits, IEEE Transactions on Advanced Packaging, to be published Aug. 2003. 3. L. Maissel and R.Glang, Handbook of Thin Film Technology, 1st ed., McGraw-Hill, New York, chapt. 16, pp. 2133, 1983. 4. A. Kingon, North Carolina State University, private communication.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 6

PROCESSING INTEGRATED CAPACITORS

RICHARD K. ULRICH

The various dielectric materials for integrated capacitor applications were discussed in Chapter 4 with no regard to how these materials could be formed or how thick the films might be, and Chapter 5 was concerned with the footprint and dielectric thicknesses required to reach specific values of capacitance and operating voltage. In this chapter, the overlay of effects brought about by the various fabrication methodologies is added in. The sections in this chapter are organized around processing techniquessputtering, anodization, CVD, MOCVD, spin-coating, solgel, pulse-laser deposition, dry calcination, hydrothermal, etc.and the various dielectric materials are listed in those sections. The integrated capacitor must be thought of not as an object, but as a technology with many facets, including composition, processing, and resulting performance, all of which contribute to the acceptance or rejection of that technology for a given application. The integrated capacitor literature was the primary source of information for this chapter although, from looking at the section headings, it might appear that the source was actually everything ever published about capacitors. That is because almost every dielectric material that can be made has been investigated for integrated capacitor applications. This is indicative of how far away the field is from settling on a few materials and processes based on a combination of performance, processability, and economics. A measure of progress in this area might be that this chapter may be much shorter in the next edition of this book. There are a large number of references in this chapter in order to enable the reader to access literature on the applications of specific dielectrics to integrated components. This chapter will concentrate on processes amenable to organic boards, which means a maximum processing temperature of about 250C. That is not to say that dielectrics requiring high-temperature anneal cannot be used, just that the annealing must be done prior to attachment to the organic material. An example of this would be DuPonts process of firing a ferroelectric dielectric onto the surface of Cu foil at
113

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900C and then laminating that to FR4. This technology is also described since it is applicable to organic boards.

6.1 SPUTTERING Dielectric films from a few hundred angstroms to a few microns may be formed by sputtering. Almost all paraelectrics may be formed as useful dielectrics by sputtering with no further processing, but most ferroelectric films must be annealed at high temperature following sputtering in order to achieve the correct crystallographic form and orientation to exhibit the very high k values of which they are capable [1]. Metal oxide films can be achieved in two ways: by direct sputtering with a target having the same composition as the desired film and by reactive sputtering, which involves using a metal target and an oxygen-containing gas in the chamber. For reactive sputtering, the sputtered metal atoms will combine with oxygen in the gas phase to form the oxide on the substrate. In practice, pure direct sputtering may be hard to optimize since it may even be necessary to have some small amount of oxygen present to offset losses of volatile oxygen from the target out through the vacuum pump. In either case, the deposition rate depends on many factors including RF power density, gas pressure, gas composition, gas flow rate, chamber geometry, and temperature. Sputtering has the advantage over CVD that it can generally be performed at lower temperatures but has the disadvantages of requiring a hard vacuum and not giving as conformal a deposition. For sputtered dielectrics of any sort, the roughness of the bottom electrode is critically important because steep slopes might not be sufficiently covered, resulting in unacceptable leakage or even shorts. It is not a problem having to do with peaks sticking up through a flat sea-like layer of sputtered material; sputtering is not a planar process. The concern is coverage of steep slopes of the rough bottom plate metal. Most investigations of implementing a sputtering procedure for integrated capacitors end up being fixated on this issue in order to bring the yield up to acceptable levels. As a result, obtaining acceptable yields for sputtered integrated capacitors with either dielectric type on Kapton and alumina substrates is more difficult than it is on Si due to the inherently higher roughness of these materials [27]. However, even over rough substrates, yield may be increased by utilizing plated Cu bottom plates for which the plating conditions have been optimized to give a smooth surface [8]. Ta2O5 may be sputtered to make dielectric films with dielectric constants of around 23, which would give about 100 nF/cm2 for a 2000 film [8, 9]. Sputtered Ta2O5 can be somewhat compressive, but annealing in oxygen at 425C for 30 minutes removes the stress and the film is still amorphous. Significant stress reduction begins around 200C. Further annealing over 550C gives polycrystalline Ta2O5 (orthorhombic) which has a much higher dielectric constant, nearly 50, but also has porous grain boundaries, allowing diffusion and penetration of etchants. Ta2O5 annealed in this way over Si lifted off after a few hours in BHF due to penetration of the liquid directly through the thin film, whereas nonannealed amorphous films

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withstood BHF for 100 hrs [10]. Direct-sputtered Ta2O5 may be oxygen deficient, so annealing in oxygen can regain proper stoichiometry and lower the leakage [11], or a higher partial pressure of oxygen in the sputtering chamber can be used. In order to improve the leakage characteristics, nitrogen may be added to the deposits by sputtering from a Ta2O5 target in Ar mixed with N2. This addition lowers the dielectric constant but improves leakage characteristics [1215]. There has been some noteworthy work on various mixtures of Ta2O5/TiO2 materials to optimize the combination of dielectric constant, leakage, and breakdown. Table 6.1 shows the results of the pure components, a homogeneous mixture, and a multilayer composite consisting of sputtered alternating layers tens of thick. The films were 2600 to 4000 so the leakage measurements at 0.50 MV/cm amounted to 13 to 20 V [16]. The heterogeneous alternating layers seemed to provide the combined benefits of the high dielectric constant of TiO2 and the low leakage and high breakdown voltage of Ta2O5. Alers, van Dover, et al. have studied various amorphous materials as dielectrics. The Zr-Sn-Ti-O system (aZTT) is a well-known microwave filter dielectric that is deposited as an amorphous film with multitarget reactive sputtering at 200C on Pt, Al, Au, and Ag electrodes. The best composition for capacitor dielectrics was found to be Zr2Sn2Ti6Ox, which gave k = 62, breakdown = 4 MV/cm, and leakage = 1 nA/cm2 at 1 MV/cm. The addition of Sn was the factor identified as lowering the leakage current. This material contains only metals with volatile halides, so it can be easily dry-etched. Because its amorphous, it is smoother than most ferroelectrics and can, therefore, be thinner. Another candidate is the class of Ti-lanthanide rare earthsO systems, which might be easier to process since they are binary alloys. An example of this is Ti0.9Dy0.1O2 which has a dielectric constant of 47, a breakdown voltage of 3.5 MV/cm, and a leakage less than 10 nA/cm2 at 1 MV/cm, which is orders of magnitude lower than pure TiO2 films [17]. Sputtered thin film SiO2, SiO, and SiNx are used in integrated passive arrays and networks consisting of Si substrates on which either capacitor arrays or simple devices, such as RC terminators, are formed on the surface using front-end techniques. These are usually packaged in the same manner as flip-chips and surface mounted to the board. The combination of gang bonding and internal passive-topassive connections provides cost and space savings over traditional SM discretes, but less than integrating all of the components into the primary interconnect board.

Table 6.1

Dielectric properties of sputtered combinations of Ta2O5 and TiO2 Dielectric Constant 22 67 38 44 Leakage at 0.5 MV/cm (A/cm2) 0.005 10 1.2 0.034 Breakdown Voltage (MV/cm) 5.0 0.9 2.3 2.3

Dielectric Ta2O5 TiO2 Homogeneous composite Heterogeneous composite, alternating layers

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These are low-capacitance-density processes, providing 1020 nF/cm2 with 2000 layers, which should have a breakdown potential of some tens of volts.

6.2 CVD, PECVD, AND MOCVD CVD-based methods require that the reactants be introduced into a low-pressure reaction chamber as a gas. The activation energy for deposition is overcome by thermal means or by the high electron energy of plasma. Looking back at the list of potential dielectrics in the previous chapters shows that almost all of them contain metal ions, which are difficult to create in gaseous form. One way to get metals into the chamber is in the form of a metallo-organic compound, which usually requires expensive liquid bubblers or solid sublimers along with thermally wrapped tubing and careful temperature control. On the beneficial side, metallo-organics can be dissociated at a sufficiently low temperature to be used with organic boards. They are usually called metallo-organic CVDs (MOCVDs) in order to distinguish their special reagents and low-temperature processing. These compounds are available from a wide range of chemical product vendors but may cost hundreds of dollars per gram. MOCVD is considered to be one of the most expensive ways to deposit a thin film. It has been used to deposit Ta2O5 [18, 19] and mixed oxides of Bi2O3 and Ta2O5 with dielectric constants of 20 to 40, depending on the Bi content, at 4050 /min in a mixture of 6090% gaseous oxygen and vaporized Bi(thd)3 and Ta(Oisopropoxide)4(thd), where thd is 2,2,6,6-tetramethyl-3,5-heptanedionato. Over very smooth substrates arising from single-crystal Si, the films can be made defectfree down to less than 100 and exhibit hundreds of nF/cm2 with leakage currents of under 1 A/cm2 [20, 21]. The films are amorphous since they never see temperatures high enough to achieve even a polycrystalline state, and so the dielectric constants can never approach those of ferroelectric materials. Diamond-like carbon can be deposited by more traditional CVD techniques. DLC refers to amorphous hydrogenated carbon, as opposed to carbon with a shortrange ring structure that is known as graphite-like carbon, and can be deposited with PECVD using a RIE type configuration. The ion energy affects the properties of the resulting film; higher energies tend to give more graphitic carbon. DLC may be etched in oxygen plasma. There are two varietieshard and softand the hard DLC is, indeed, much harder and more resistant to scratching. Hard DLC may be very leaky; 5 V over 1000 at 0.5 MV/cm gave almost 0.10 A/cm2, whereas the leakage through soft DLC was less than one nA/cm2. But the hard variety is more resistant to mechanical damage. 1000 of CVD DLC gave 3040 nF/cm2, which amounts to a dielectric constant of 3.44.5 [22, 23]. DLC can also be deposited with PECVD from methylethylkeytone. It was found to have better adhesion to Ti or Mo than to Cu so a few hundred angstroms of either was sputtered over Cu. The entire capacitor stack was formedbottom plate, dielectric, and top platethen dryetched all at once [24]. Combustion chemical vapor deposition (CCVD) involves dissolving the dielectric in a combustible solvent and spraying it as fine droplets with oxygen to make a

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flame. Passing the substrate through the flame can deposit crystalline ferroelectrics directly, at lower cost than sputtering. 1000 /min of strontium titanate, k = 263, at a substrate temperature of 600800C has been reported [25]. Ta and Hf oxide nanolaminates have been deposited by atomic layer CVD epitaxy in the form of sixteen layers alternating 30 of each. The resulting dielectric constant was the same as Ta2O523but leakage was low at 5 A/cm2 for a 500 film at 5 V, which gave 400 nF/cm2 and a TCC = 135 ppm/C [26].

6.3 ANODIZATION The aqueous-phase electrochemical oxidation of Ta is the most important method of forming capacitor dielectrics today due to the combination of ease of processing and the excellent properties of the resulting dielectric [2730]. Anodized Ta2O5 was described by Berry in 1959 [31, 32]. His writings, decades later, still provide useful processing and property information on this ubiquitous system. The equipment, methodology, and kinetics for anodizing Al [3335] and Ta are very similar, but this section will concentrate on Ta since it provides a dielectric constant that is 2.7 times greater. All metals except Au form a thermodynamically stable oxide when exposed to either oxygen or moisture and since this is an electrochemical oxidation reaction it can be promoted by making the metal the anode in an electrochemical cell. A mechanically stable and defect-free oxide may be formed this way if the resulting oxide is adhers to the underlying metal, has compressive stress, and is insoluble in the aqueous solution used in the cell. It is the same electrochemical reaction as corrosion, except that the reaction productmetal oxideremains on the surface instead of dissolving or flaking off. The compressive stress serves to create crack-free films and is the normal result since the volume of oxide produced is nearly always greater than the volume of metal consumed. If the oxide is, instead, soluble and dissolves in the electrolyte, the surrounding solution may become saturated, causing precipitation onto the anode, resulting in a loose, porous oxide. Cadmium, zinc, and magnesium exhibit this dissolution and precipitation behavior, and the resulting oxide coatings are leaky and noncontinuous. Anodized Ta2O5 has been stretched by as much as 50% before breakage [36] . The film will continue to thicken as long as the applied electric field is less than the breakdown field of the oxide but, once the critical field is exceeded, pinholes and other defects will result. The metals capable of satisfying these conditions, listed in Table 6.2 [37], are known as valve metals due to the mildly rectifying properties of their oxides, as described later. The word valve refers to the old term for a vacuum tube, not fluid control devices. Al and Ta have received by far the most attention over the decades as anodized dielectrics [38, 39]. The procedure is quite simple. The metal to be oxidized is made the positive side of an electrochemical cell by immersing it in a conductive solution as described below along with a cathode of a noble metal, such as Pt-coated mesh. The DC power supply should be capable of providing about 150 V and about 1 mA per cm2 of area

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Table 6.2 Metal Aluminum Zirconium Bismuth Antimony Tantalum Titanium Niobium Tungsten Hafnium

Anodizable valve metals with their dielectric constants Oxide Al2O3 ZrO2 Bi2O3 Sb2O3 or Sb2O4 Ta2O5 TiO2 Nb2O5 WO3 HfO2 Dielectric Constant of Oxide 9 12 18 ~20 23 40 41 42 45

to be anodized. 2000 of film formation on Al or Ta can be accomplished in about 20 minutes. The procedure is described in more detail below. 6.3.1 Benefits of Anodization for Capacitor Dielectrics Anodized films are useful as capacitor dielectrics for several reasons. They may be grown quite thin, a few hundred angstroms, without defects because thin spots in the oxide have lower local resistance, which results in higher anodization currents, whereas thick spots will have higher resistance. As a result, thin spots grow faster and thick spots slower, resulting in a uniform, defect-free film. Also, the final thickness is mainly a function of the voltage used in the electrochemical cell, which is easily set, and is only weakly affected by the processing time, composition of the bath, temperature, and current. [4044]. Anodization avoids the substrate roughness problem inherent with sputtering since a thick layer of anodizable metal can be deposited and the anodization procedure can be controlled to convert only enough metal into dielectric as is necessary to achieve the desired specific capacitance [4550]. Therefore, the composition or roughness of the capacitor bottom plate metal underlying the anodized metal is not an issue and this approach avoids having to planarize and monitor the state of the bottom electrode. The apparatus is quite inexpensive, uses safe chemicals, and produces almost no toxic waste products. Also, films formed by electrochemical means are inherently stochiometric, whereas sputtering may require careful control of the chamber gas composition and conditions to produce balanced oxides. 6.3.2 Film Formation During Anodization Anodized films are formed by a chemical reaction of a species already present on the surface, the metal, and oxygen from water in the aqueous solution. The electrochemical reaction at the anode is

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2 Ta + 5 H2O Ta2O5 + 10 H+ + 10 e The electrons are returned to the solution at the cathode where they reduce H+ to hydrogen gas, preventing the pH from changing appreciably. It is improper to say that anodized films are deposited because only the oxide part is; they are grown or formed. Some thickness of metal is consumed in order to form a given thickness of metal oxide, and this ratio is important in determining how much metal must be present initially to achieve a certain amount of oxide. At 100% current efficiency, Faradays law gives the rate of oxide growth: dzox i Mox = dt nF ox where zox = oxide thickness, cm t = time, sec i = current density, A/cm2 n = number of electrons given off in the half reaction at the anode (6 for Al, 10 for Ta) F = Faradays constant (96,500 coulombs/mole of electrons) Mox = molecular weight of the oxide, gms/mole (102 for Al, 442 for Ta) ox = density of the oxide, gms/cm3 (3.99 for Al2O3, 8.2 for Ta2O5) Therefore, 1 mA/cm2 will give an oxide growth rate of 265 /min for Al and 335 /min for Ta. Although it is possible to grow films of a given thickness by counting the number of electrons that went into forming it, in practice it is actually easier than that because the final thickness can be set according to cell voltage, as will be described later. Taking as a basis 1 cm2 of surface area, the thickness of metal consumed to make the oxide contains the same number of Ta atoms that end up in the resulting oxide film thickness in the same area:

Ta TaO zTa = 2zTaO atoms of Ta/cm2 MTa MTaO

where zTa = thickness of Ta metal consumed to make oxide, cm Ta = density of Ta metal, 16.7 gm/cm3 MTa = molecular weight of Ta metal, 181 gm/mole 2 = each molecule of tantalum oxide contains two atoms of Ta zTaO = thickness of Ta2O5 grown, cm TaO = density of Ta2O5 oxide, 8.2 gm/cm3 MTaO = molecular weight of Ta2O5 oxide, 442 gm/mole

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So the ratio of Ta2O5 formed to Ta metal consumed is 2.49, which means that anodizing one nm of Ta will produce a film 2.49 nm thick that will protrude 1.49 nm above the original surface (Figure 6.1). A similar analysis indicates that 1 nm of Al will form 1.28 nm of oxide, which will protrude 0.28 nm above the original surface. The mechanism of anodization is complex and not fully understood, but there is strong evidence that the rate-controlling step is the migration of ions within the oxide film. The main support for this is that the amount of current induced during anodization is linear with voltage and not exponential as would be expected from kinetic control. Also, agitation of the fluid has no effect on the rate of anodization and the anodizing solution also has little effect as long as it is sufficiently conductive to place ohmic current control in the film and not in the solution and does not chemically attack the film. Al anodization requires pH values between about 6 and 9 since the metal dissolves in strong acids and strong bases, but Ta may be anodized over a much wider range [49]. 6.3.3 Ta Anodization During anodization, hydrogen is liberated at the cathode and some bubbles will be seen near the anode, so an agitator should be used to prevent bubbles on the anode from hindering film formation. Films anodized from bcc Ta are soft and may crack upon anodizing; those from beta Ta are better. The bcc form is also known as the alpha form, the same as bulk metal, and, like most materials, has a resistivity slightly higher than the 14 -cm bulk value at 2040 -cm. The beta form is easily formed by sputtering, especially under conditions that exclude contaminants. This is a tetragonal form with the same density as bcc but considerably higher resistivity and gives better anodized films. It has a much higher resistivity of 180 cm and is unknown in bulk form [51]. The final film thickness is directly proportional to the final voltage used in the cell (Figure 6.2). Thus, the dielectric thickness can be dialed in with the electrochemical cells voltage control. For Ta, the constant of proportionality is 16 /V and for Al it is 3.5 /V so that a 2000 Ta2O5 film requires 2000/16 = 125 V. The maximum thickness of anodized films is limited by voltage-induced breakdown during anodization. A change in film color can make this apparent even during an-

Figure 6.1 consumed.

Relative thickness of tantalum oxide formed by anodization and tantalum metal

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Figure 6.2

Film properties of anodized Ta2O5 as a function of final cell voltage.

odization. Lower-conductivity solutions allow thicker films [52]. Some manufacturers, such as AVX, use the concept of a formation voltage, which is set at 3.5 times the required working voltage for Ta. If a working voltage of 20 V is required, the anodization would be carried out at a final voltage of 70 V, resulting in a film thickness of 70 16 = 1120 and a specific capacitance of about 180 nF/cm2. Attainable film thicknesses are given in Table 6.3. 6.3.4 Dielectrics from Anodized Ta Leakage currents and breakdown voltages for anodized Ta films are shown in Figures 6.3 and 6.4. Anodized oxides are mildly rectifying, exhibiting lower leakage currents in the direction of the original anodization current, as shown in Figure 6.5 [54].
Table 6.3 Metals that can be anodized to give nonporous adhesive oxides [53] Ratio of Final Thickness to Final Voltage (/volt) 3.5 16 43 15 1230 3.5 Maximum Film Thickness Attainable by Anodization (m) 1.5 1.1

Metal Al Ta Nb Ti Zr Si

Dielectric Constant 9 23 41 40 12 3.7

0.12

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Figure 6.3

Leakage current through anodized Ta2O5 at 5V.

Figure 6.4

Breakdown voltage of anodized Ta2O5.

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Figure 6.5 Leakage current is lower in the direction of the anodization current for 1200 of anodized Ta2O5.

Nitrogen is one of the most common dopants for tantalum films and has been well characterized because of the wide use of TaN as a thin-film resistor material. Upon anodization, it gives an oxynitride dielectric [5557]. The addition of nitrogen to the thin film makes the capacitors more stable to heat, especially in combination with oxygen, but the disadvantage is loss of capacitance. Carbon doping seems to penalize capacitance to a lesser extent, retaining between 70 and 90% of the capacitance density compared to undoped tantalum oxide. 6.3.5 Patterning Ta and Ta2O5 Ta metal and Ta2O5 are only effectively wet etched at room temperature by mixtures of hydrofluoric and nitric acid. 5% HF at room temperature etches Ta2O5 at 320 /hr, increasing semilogarithmically to 1400 /hr at 50% [58]. Table 6.4 shows some common etchants for this system and some of the expected collateral rates [59]. Both Ta and Ta2O5 may be rapidly dry etched with SF6 and oxygen in an RIE at about the same rate. Barlow has studied the conditions in a PlasmaTherm etcher and found this optimum set: Power = 150 watts Pressure = 250 mTorr Etch time = 3 min O2 flow rate = 35 cm3(STP)/sec SF6 flow rate = 30 cm3(STP)/sec The resulting etch rate for both films was 970 /min with a uniformity of 0.03% across a 5 inch wafer. The surface roughness of partially etched Ta2O5 was less than

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Table 6.4 Etchants 2.0% HF and 0.5% HNO3 (Ti Etch)

Wet etchants for Ta and Ta2O5 Metal/Oxide Ti Ta Ta2O5 Ta Ta Cu SiO2 Ta Ta Etch Rate (/min) 4800 <3 8.6 63 830 480 >10,000 860 <1.4

4.0% HF and 0.7% HNO3 8.0% HF and 0.5% HNO3

8.0% HG and 0.7% HNO3 (Ta Etch) 2.5% CH3COOH, 2.5% HNO3, 1.0% H2SO4, and 94.0% H2O

2 . Thick photoresist can be used as a mask and the etch rate of this process on Al is almost zero, enabling it to be used as either a mask or an etch stop. 6.3.6 Ferroelectrics by Anodization BaTiO3 has been made by anodization without a high-temperature anneal but, to date, with poorer dielectric properties than solgel films that were subsequently thermally cured. Also, the solution must be very alkalineas high as pH 14 [60, 61].

6.4 SOLGEL AND HYDROTHERMAL FERROELECTRICS Solgel involves the application of a thin layer of a liquid-phase metallo-organic compound followed by thermally induced removal of the organic portion, leaving a metal oxide behind. Solgel processes allow for the deposition of films with a high degree of chemical homogeneity at relatively low temperatures. The process starts with organometallic compounds such as metal alkoxides that are dissolved in alcohol to give a homogeneous solution. Various forms of titanium alkoxides are widely used to form titanate films along with other elemental sources such as barium hydroxide for BaTiO3, lead acetate for lead zirconate titanate, etc. The solution or sol is subsequently gelated by a hydrolysis reaction with water or exposure to the atmosphere. The gelation forms a polymeric network or a colloidal network. Many factors influence the gelation: the nature (acidic or basic) and concentration of the catalyst, the amount and composition of solvent, and the sequence of mixing. The gel is amorphous and mechanically weak because it has continuous pores and trapped organics, water, and hydroxyl groups. Thin-film coatings are typically obtained from polymer solution deposition techniques such as dip-coating or spin-coating. Heat treatment and densification of the gel form the final film. The high surface area of the dried gels results

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in very high reactivity, which in turn results in a relatively low-temperature process compared to conventional ceramic processes that involve sintering of micron-sized particles. It has been demonstrated for both thin-film high-k capacitors and low-k dielectrics. Solgel can be a low-cost technique yielding high dielectric constant films compared to sputtering and CVD since it requires less equipment and no vacuum steps. However, the temperatures required to form crystalline films to give k > 1000 are typically higher than 500C. Films formed at temperatures less than 400C may result in dielectric constants less than 100. Alternately, the films can be formed at higher temperatures separately on a copper foil and then integrated into the organic substrate. The sol can also be mixed with polymers to form nanoscaled ceramicpolymer-composite high-k films. In general, the electrical properties of solgel high-k films are not yet well characterized [62]. The liquid may be spun on or blade coated followed by a partial cure at around 300C, which turns the liquid into a very viscous and adherent gel. This procedure can be repeated to give thicker final dielectric materials and to decrease defect density. Each coating will result in only about 0.1 m; film thickness over a micron is prone to stress cracking. After all coating steps, a final cure at 600700C gives the cubic perovskite crystal structure needed for high-k materials [6372]. Lead zirconate titanate (PZT) solgel technologies based on 1,3-propanediol enable thicker films, up to 1 m at a time. The resulting 0.50 micron films are 2000 nF/cm2, twenty times that possible with anodized Ta, with a breakdown voltage of 1.3 MV/cm (65 V). These films show all the characteristics of ferroelectrics: decrease in k with bias and frequency as well as profound temperature effects [72]. These final cure temperatures are too high for organic boards, but solgel is worth mentioning due to the ability to achieve high capacitance at little expense. Perhaps a way can be found to either reduce the cure temperatures through rapid thermal processing or to mount precured coupons, such as layers of copper coated with dielectric, onto organic boards. Hydrothermal treatment involves dissolution of reactants and precipitation of crystalline compounds in hot, pressurized water. It is a standard technique to form fine powders with superior physical and chemical properties. The raw materials are typically similar to those used in the solgel process. A subsequent hydrothermal treatment of the sol can assist in the formation of thin films at lower temperatures. Water serves as a pressure-transmitting medium and also accelerates the kinetics. More importantly, the presence of water enables reactions to take place at lower temperatures because the free energy of hydrated ions is similar to that of crystalline BaTiO3. These unique process characteristics enable formation of crystalline ceramics at temperatures <100C. The reactions are carried out in closed vessels, typically under strong alkaline conditions. The bath conditions such as temperature, alkalinity, etc. can be predicted from the theoretical phase-stability diagrams of the relevant systems. The phase diagrams provide a thermodynamic basis for the formation of films. Hydrothermal synthesis of BaTiO3 films need a bath of pH >13. The film growth is dependent on the type of substrate. Substrates with structures closer to the films allow easier nucleation and growth of defect-free films. For the

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formation of BaTiO3, Ti-sputtered substrates, Ti foils or titanium-alkoxide-coated substrates are treated in Ba(OH)2 solution. The temperature can be less than 80 for crystalline film formation. These films are typically porous and show microcracking, resulting in poor yield. Films formed on Ti foils at temperatures of 90C yielded capacitance of 1.5 microfarad/cm2. Significant process development and film characterization is needed to yield reliable BaTiO3 films from hydrothermal techniques [73].

6.5 THIN- AND THICK-FILM POLYMERS Many polymer materials are available for application by spin-on or various panelcoating methods with a subsequent cure that is easily tolerated by organic substrates. These materials will be suitable only for the smallest-valued capacitors since the highest polymer dielectric constant known is only about 12. Both BCB (benzocyclobutene) and polyimide are available as spin-on or castable resins that can be formed as thin as a micron or layered to indefinite thicknesses. The highest practical specific capacitances achievable are 2.4 nF/cm2 for BCB at k = 2.6 and 3.3 nF/cm2 for polyimide at k = 3.7, both at 1 micron [74]. Polyester film laminated on FR4 gives around 0.1 nF/cm2 [75]. Avatrel dielectric polymers from DuPont are really designed as an interlayer dielectric, and so are tailored for low k of 2.6, low dielectric loss of 0.2%, good adhesion, low moisture absorption, and stable properties [76]. Other polymeric materials such as epoxies, thermoplastics, and fluorocarbons would all perform in a similar manner (Table 6.5). On the plus side, their dissipation factors tend to be low, much lower than high-k ferroelectrics, which makes them more suitable for small-valued RF applications that require low losses. Making a pF-sized capacitor from a high-k material might result in a component that is too small to achieve good tolerance. Polymer dielectrics may absorb moisture (k = 78), which typically increases both k and the dissipation factor. Breakdown voltages are the same as most metal oxides at around 15 MV/cm. They may be applied in multiple thin layers to decrease the defect density to negligible values.

Table 6.5 Dielectric Mylar Polystyrene BCB Parylene Polycarbonate Mylar Kapton Epoxies

Dielectric properties of some thin-film polymers Dielectric Constant 2.0 2.6 2.6 2.7 3.1 3.2 3.7 46 Dissipation Factor (%) 0.02 0.01 0.010.1 0.1 0.4 0.40.7

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6.6 THICK-FILM DIELECTRICS The attractive feature of thick-film processing for resistors, capacitors, or interconnects is that they can be printed on and cured in place with no patterning, photolithography, or waste. The resulting capital and operating cost should be much less than for subtractive processes, especially those involving vacuums. 6.6.1 Ferroelectric Powder Dispersed in Polymer This is one of the only dielectrics developed specifically for integrated capacitors. Its development was motivated by low cost and ease of processing, but may be near its limit of specific capacitance. Almost any high-k ferroelectric material can be produced in quantity as submicron powders. For example, BaTiO3 can be made by the dry calcination of BaCO3 and TiO2 at >1200C, resulting in particles well under a micron in diameter with dielectric constants in the thousands. These high-k particles can be mixed with a polymer resin such as epoxy or polyimide at up to 6080% loading by volume, then screen printed, spun-on, or stenciled onto the substrate, and the polymer phase cured at temperatures quite tolerable to organic boards. Multiple printings can eliminate pinholes. The mixing rules for composites of two materials with different dielectric constants are, unfortunately, such that the dielectric constant of the final composite will be much closer to that of the low-k material, which is generally the polymer with a k of about 3 to 5. The overall dielectric constant will end up being around 30100. The result is a film as thin as 5 microns that can be screen printed cheaply, made pinhole-free, and delivers in the low tens of nF/cm2. Dissipation factors are more typical of the ferroelectric powder, ranging from 17% [7787]. This method is not suitable for paraelectric powders because the mixture of these much-lower-k powders with polymer would have about the same dielectric constant of the polymer alone. The advantage of this approach is that much of the processing, and all of the high-temperature steps necessary to get high k from the ferroelectric phase, can be done in advance of application to the organic substrate. Application is additive and the dielectric is applied only where it is wanted so there is no patterning and little waste. No vacuum equipment is required. Because the films are thicker than sputtered, solgel, or CVD films, the working voltages are higher, on the order of hundreds of volts. However, screen printing or stenciling is not amenable to tight tolerances. Also, the highest composite dielectric constants reported to date do not exceed 100 and films thinner than a few microns are very difficult to produce with good tolerance, so the maximum capacitance densities are around 2030 nF/cm2. Finally, once the ceramic loadings approach 85% by volume, which amounts to about 98% by weight, adhesion to the metal electrodes is very poor, resulting in air gaps and lowered capacitance [88]. Figure 6.6 shows typical results of mixing lead magnesium niobate-titanate plus barium titanate (k = 17,800) with a polymer, in this case photodefinable Ultradel 7505 from Amoco (k = 3) for 100 hrs in a ball mill, spin coating to 1.1 m, and curing at 225C. After curing and with 35% filler, 4 mil vias could still be made. Even at 60% loading, less than 1% of the dielectric constant of the high-k phase was achieved.

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Figure 6.6 Dielectric constant and dissipation factor as a function of fraction ferroelectric filler in a polymer matrix.

There are several semiempirical equations that relate the dielectric constants of the filler and binder along with the volume fraction filler to give an overall composite dielectric constant [89]. The Lichtenecker logarithmic law of mixing is popular: log kcomp = (1 n)vf log kf + (1 vp)log kp where kcomp = dielectric constant of the composite of materials 1 and 2 vf = volume fraction of high-k filler in the composite vp = volume fraction polymer in the composite n = a constant between 0 and 1 Most models break down at high loading, above maybe 60%, probably due to imperfect particle dispersion or voids in the matrix. With decreasing particle sizes, the influence of the particle/polymer interface becomes more important due to the higher ratio of surface area to volume for the filler. Particle aggregation rather than uniform dispersion becomes a problem due to the difference between the hydrophobic polymer and hydrophilic ceramic particles, leading to difficulties in forming uniform thin films. Various surfactants are under investigation to prevent this, but the surfactants themselves may influence the dielectric constant [90]. The highest possible packing density for single-diameter spheres is 74% with the hexagonal closepack arrangement. To see an example of this, go to the grocery store and look at how the oranges are stacked; every grocer knows how to do hexagonal close pack. The only way to get higher filler fractions than this is to use multiple-diameter

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spheres so that the small ones fit in between the big ones, but this exacerbates problems, with particles agglomerating into clumps. It is difficult to print films thinner than a few microns, especially when highly loaded with solids. Spin coating is possible, even at 60% by volume, to a thickness of 15 m. The CTE of 60 vol% of BaTiO3 in epoxy has been measured at 17 ppm/C, a value conveniently close to that of Cu metallization and FR4 board materials [91]. The dielectric constant of the filler is certainly high enough, so development strategies for filled polymers have centered on increasing the fraction of filler in the composite, decreasing the cured film thickness, and increasing the dielectric constant of the polymer binder. In one study, 0.90 m PMT-PT (lead magnesium niobate-titanate) and 0.065 m BaTiO3 was mixed in a 3:1 ratio to optimize the filler packing. This was mixed with an epoxy with k = 3 in a ball mill for four days to achieve up to 80% by volume. Viscosity adjustment was obtained by adding solvents (NMP). The resulting composite had a dielectric constant of 82 at 10 kHz and a specific capacitance of 7.3 nF/cm2. Other projects have concentrated on increasing the dielectric constant of the polymer. 68% volume loading of PMT-PT in an epoxy of k = 34 gave an overall k of 74. But the addition of cobalt acetylacetonate (Co-acacs) to the epoxy raised its dielectric constant to about 6, enabling an overall k of 98 at 79% loading. This is the highest dielectric constant found in literature to date. Metal-acacs materials contain a structural group that is commonly used as a curing catalyst for epoxies. As mentioned in Chapter 4, ions that are permitted to move some distance in the dielectric provide a very high degree of polarizability; this is the mechanism that gives ferroelectrics their very high dielectric constants. The idea here is that the metal ion would be left behind by the Co-acacs after polymer cure and provide some of that ionic polarization mechanism to the otherwise very low-k epoxy material. In that study, it was added to the epoxy resin at up to 5% by weight and 10 m layers of this material were spin-coated and cured at 100C for 10 min, then up to 180C for 1 hour for final cure. Gold top and bottom plates were used. The resulting films were 25 nF/cm2 [92, 94]. Although the dielectric constant of the composite is much closer to epoxy than to the ferroelectric filler, large instabilities characteristic of ferroelectric materials are still seen from temperature, frequency and voltage excursions [94]. Figure 6.7 shows the decrease in dielectric constant with frequency for a BaTiO3/epoxy composite dielectric, a behavior characteristic of ferroelectrics. 6.7 INTERLAYER INSULATION The FR4 or flex insulation material used to separate interconnect, power, and ground layers has a low specific capacitance but costs very little since it is there anyway. When placed between power and ground planes, some degree of decoupling can be obtained due to the large area. Two mils of FR4 at k = 4.8 would give only 0.085 nF/cm2 but on a 1 ft2 computer-sized board would amount to around 80 nF. There is some work in progress in creating specialty layers for lamination that might include BaTiO3 powder, increasing k to around 25 [95].

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Figure 6.7 electric.

Loss of dielectric constant with frequency for a BaTiO3/epoxy composite di-

6.8 INTERDIGITATED CAPACITORS Very small values of capacitance can be obtained by interdigitating interconnect material, which will provide about 0.050.10 pF/mm. Figure 6.8 shows measurements from interdigitated 10 micron lines. Design of this approach can be complicated by floating plate capacitance between these structures and metallization on other layers. Due to the low area efficiency, this may only be useful for sub-pF

Figure 6.8

Capacitance from interdigitated conductors.

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131

values that would be difficult to achieve by patterning a dielectric to acceptable tolerance. 6.9 CAPACITOR PLATE MATERIALS Naturally, the first choice for the capacitor plate material would be the same metal used as the interconnect, typically Cu or Al. Not only is it already present, it also has low resistivity. If the contacts are both along the same edge, the current goes, on the average, one third of the way out and one third of the way back. That, plus spreading resistance, amounts to about one square of resistance for a square integrated capacitor, about 10 m for 2 m sputtered Cu or Al. If anodized Ta is used, it might appear advantageous to use Ta as the plate material, but the sputtered form of Ta almost always obtained is the beta, or tetragonal, structure that has a high resistivity180 -cm. This gives significantly better anodized films than the more conductive bcc bulk form. The downside is that beta Ta is 100 times less conductive than Cu or Al and is that much less suitable as a bottom plate. Therefore, it is usually necessary to have a more conductive metal under the Ta that is anodized. No matter what metal is used as the bottom plate, it is best to deposit more Ta than will be anodized since this removes much of the influence of any underlying roughness. For example, 2000 of Ta may be deposited over Cu or Al, then anodized to an anodic potential of 63 V, which will consume 400 of Ta to make 1000 of Ta2O5, giving a dielectric with 212 nF/cm2 and leaving 1600 of unanodized Ta to screen the roughness of the bottom plate. There is little reason to deposit only the required amount of Ta since the thickness of the oxide is easily controlled by the anodization voltage at 16 /V. Anodization of Al does not require a separate underlying bottom plate metal, of course. Another reason to have more Ta than is required for anodization is that contact with Al may reduce the TaO to Ta metal since the Al has a greater affinity for oxygen. This oxygen leaching can occur due to the high temperatures of subsequent polymer cure cycles. A thin barrier of TaN in between the Al and Ta can prevent this if it is necessary to anodize all of the Ta. W and Mo are also compatible with TaO and may provide a diffusion barrier [96, 97]. TaN can also be anodized, making it much less prone to oxygen loss, but at some cost of lower dielectric constant. The choice for the bottom electrode for ferroelectrics is often restricted to nonoxidizable materials such as Pt or Au, which can add complexity and expense when using ferroelectrics. More common metals, such as Al or Cu, can react during the high-temperature anneal to form their own oxides which, for thin dielectrics, will dominate the overall dielectric constant of the two layers. Pt is popular as the base electrode because, in addition to thermodynamic stability, it has a high Schottky barrier and, therefore, a lower leakage for thin films [98]. 6.10 TRIMMING INTEGRATED CAPACITORS As described in Chapter 3, integrated resistors can be trimmed to higher values by cutting the resistor material with a laser. By cutting across the resistor, the current

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Figure 6.9

Trim tabs for adjusting capacitance.

path is effectively increased and, depending on the length of the cut, the resistance can be adjusted to any value on a continuous basis. However, capacitance is area ruled and it would require the removal or addition of top or bottom plate sections to bring about trimming. This could be done on a continuous basis in principle but no technologies have been demonstrated to date. A technique used for many years in hybrid microelectronics involves the removal of trim tabs, as shown in Figure 6.9, enabling the capacitance to be adjusted downward in steps.

6.11 COMMERCIALIZED INTEGRATED CAPACITOR TECHNOLOGIES A few integrated technologies for capacitors are either commercialized or close to it (Table 6.6) [99]. These can produce singulated capacitors for one-to-one replacement of discrete components or can be left as a continuous layer between power and ground planes for integrated decoupling, replacing many discretes at once. 6.11.1 DuPont InterraTM DuPont is developing a high-k integrated capacitor process called Interra that involves firing a screen printed ferroelectric paste on one side of Cu foil at 900C, then firing a Cu-based paste over that to form a 3 m top plate, and flipping the stack onto FR4. The foil is then patterned to electrically separate the plates and form the interconnects, as shown in Figure 6.10 [100102]. Two separate dielectric printings and firings are performed to eliminate pinholes, resulting in a 2040 m total thickness. The dielectric is a formulation based on a doped barium titanate plus a glass that is compatible with board-level etching processes and does not dissolve the barium titanate phase during firing. The resulting dielectric constant is in excess of 1000, yields a capacitance density up to about 44 nF/cm2 and exhibits temperature, frequency, and voltage behavior characteristic of ferroelec-

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133

Table 6.6 Summary of integrated capacitor technologies either commercialized or under development Supplier DuPont Trademark Dielectric material and capacitor configuration Specific capacitance (nF/cm2) Loss tangent (%) Dielectric constant Thickness (m) Interra Fired ferroelectric paste on Cu foil ~44 1.5 1000 20 3M C-Ply Cu-clad BaTiO3 in epoxy 1.6 0.45 1523 8 DuPont HK Licensed from Sanmina BC2000

Cu-clad Cu-clad FR4 polyimide (filled or unfilled) 0.121.6 Unfilled 0.3 Filled 1.0 3.415 825 0.07 ~1 4 50

tric materials. The dissipation factor is 1.11.5% at 100 kHz and the breakdown voltage is 9001200 V. From here, the board may be further processed to add other layers of conductor and even other layers of capacitors. Ceramics are weak in tension and strong in compression, so the most important processing precaution is to avoid putting the capacitors under tension during lamination. If provided as clad copper foil, this might be processible by board shops using standard equipment. 6.11.2 3M C-Ply 3Ms C-Ply is a dielectric sandwiched in between two layers of Cu foil, typically one ounce. The foil can be patterned and included in an FR4 build for decoupling or as singulated integrated capacitors. The dielectric is barium-titanate-filled epoxy with k = 1523 and a thickness of 823 m to give 1.6 nF/cm2 with a 0.45% dissipation factor [103]. If provided as clad copper foil, this might be processible by board shops using standard equipment. 6.11.3 DuPont HK DuPonts HK laminate is a board-wide embedded planar capacitor material designed for use between the power and ground planes of FR4. The HK product family consists of unfilled and ferroelectric-filled polyimide laminated as a doublesided material with copper thicknesses from 18 m ( oz) to 72 m (2 oz). Thicker copper is available on special request. The dielectric constants range from 3.4 to 15 and thickness from 8 to 25 m, which allows for capacitance densities ranging

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Figure 6.10

DuPont Interra prefired integrated capacitor process for FR4.

from 0.12 nF/cm2 to 1.75 nF/cm2. This range of products permits use of these laminates for removing decoupling capacitors, reducing impedance, and reducing EMI for high-speed applications. Dissipation factors are approximately 0.3% at 1 MHz for unfilled products and rises to 1% for filled organics. Breakdown voltage ranges from a low of 1000 V/mil for highly filled offerings to a high of >6000 V/mil for unfilled products such as Interra HK 042536. Because the unfilled materials are low-k paraelectrics, their dielectric constants are very stable with regard to temperature (<2% from 55 to +125 deg. C), frequency, and voltage. They may be processed as thin flexible laminates with drop-in pro-

6.12

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135

cessing conditions within typical PWB processes. Most products will permit copper removal from both sides simultaneously. 6.11.4 Motorolas Mezzanine Capacitor Motorola has partnered with Vantico AG to develop a polymer material filled with high-k ceramic particles to be used on FR4. It is called Probelec CFP. The dielectric is a positive-acting photodielectric formed by roller coating, lamination, and solvent developing to form an embedded capacitor between the FR4 core and the HDI outer layer, which gives the concept the name mezzanine capacitor. Because of the positive-acting chemistry, the top electrode can be used as the mask, resulting in a self-aligned dielectric and top plate. The cured dielectric has a dielectric constant of about 21 and a thickness of 12 m, for a capacitance density of 1.7 nF/cm2 [105]. Typical of the ferroelectric-containing polymer thick-film dielectrics described earlier in this chapter, it exhibits a dissipation factor of 23%, considerably higher than paraelectrics, and shows more dependence on frequency and voltage as well. Measured tolerances were about 15%. 6.11.5 Sanmina BC2000 Sanmina Corporation produces a 2 mil thick glass-reinforced epoxy called BC2000 for use as a board-wide decoupling capacitor with a specific capacitance of about 0.068 nF/cm2. Research is underway to develop a 1 mil version to increase the capacitance. 6.11.6 nChip nChip of San Jose, California was an early pioneer of MCM-D technologies. They developed and produced MCM-D configurations of SiO2 and Al on Si substrates with chips and some discretes mounted on the surface. They anodized the surface of the Al power plane, and then deposited the ground plane over that to form an integrated decoupling layer with a specific capacitance of around 55 nF/cm2. This process was part of their nC1000 technology and was used to build several commercial modules [105]. nCHIP was purchased by Flextronics and no longer produces MCM-D substrates.

6.12 SUMMARY Of the large number of dielectric materials and processes that have been demonstrated for integration, a few are now coming onto the market, mainly for FR4 since this is the dominant board material in consumer systems. As flex and HDI increase their penetration into the consumer market, more of these technologies should appear, particularly those associated with thin films and requiring vacuum processes. Table 6.7 provides a comparison of the techniques described in this chapter.

136 Table 6.7 Summary of integrated capacitor technologies Advantages Well-established process and materials, from front-end technologies Many commercialized processes Properties stable with temperature, frequency, voltage, time Well-established process and materials High specific capacitance Requires vacuum processing Requires high temperature anneal k is sensitive to temperature, frequency, voltage, time Ceramic thin films may be fragile on FR4 or flex Requires vacuum processing May require high deposition temperatures MOCVD reagents and equipment are very expensive Ceramic thin films may be fragile on FR4 or flex Requires vacuum processing Very sensitive to underlying roughness Ceramic thin films may be fragile on FR4 or flex Disadvantages Development Status Commercialized in integrated passive arrays and networks Demonstrated on FR4 and flex Annealing requirements have limited its development for embedding in organic boards Well-established process and materials

Process

Materials

Maximum Specific Capacitance (nF/cm2)

Sputtered paraelectrics

SiO2, Al2O3, Ta2O5, TiO2

Low hundreds

Sputtered ferroelectrics

BaTiO3, BST, BZT

Thousands

CVD, MOCVD, PECVD

Paraelectric or ferroelectric

Para: hundreds Ferro: thousands

Solgel ferroelectrics

BaTiO3, BST, BZT

Thousands

High specific capacitance

Reagents expensive Requires high temperature anneal k is sensitive to temperature, frequency, voltage, and time Requires vacuum processing for sputtering Ta or Al Ceramic thin films may be fragile on FR4 or flex Very low specific capacitance

In production at AVX for integrated arrays

Anodized paraelectrics Films much less sensitive to roughness than those from sputtering, allows thinner films Easy, inexpensive processing Low defect density Low dissipation factor

Al2O3, Ta2O5,

Low hundreds

University of Arkansas, HiDEC, Intarsia nChip Bell Labs (1950s) DuPont (HK) Sanmina (BC2000 Intarsia (spin-on)

Unfilled organics

BCB, polyimide, Up to ~1 for <5 epoxy, FR4 m spin-on or cast Up to 0.3 for 1/2 mil laminate Easy, inexpensive processing Low defect density Separates the high-temperature firing step from the organic board Potential for high capacitance

Filled organics

BaTiO3 in BCB, polyimide, epoxy, FR4

Up to 23 in commercialized products

Low specific capacitance k is sensitive to temperature, frequency, voltage, time k is sensitive to temperature, frequency, voltage, and time Very high loss tangent Sensitive to mixing proportions

3M (C-Ply) DuPont (HK) Georgia Tech DuPont (Interra)

Ferroelectric fired onto Cu foil

BaTiO3

~50

ConductorAg flake in insulator epoxy nanocomposite

10 to date

Georgia Tech

137

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55. R. Berry, P. Hall, and M. Harris, Thin Film Technology. Van Nostrand, New York, pp. 271288, 371394, 1968. 56. M. Peters and M. Lee, Thermally Stable Thin Film Tantalum Pentoxide Capacitor for MCM Applications, International Journal of Microcircuits and Electronic Packaging, 19, 4, 364368, 1996. 57. M. Ikeda et al., Low Resistance Anodized Ta/TaN Line TFT-LCD, IEEE Proceedings, 1991. 58. C. Christensen, R. de Reus, and S. Bouwstra, Tantalum Oxide Thin Films as a Protective Coating for Sensors, IEEE, p. 267, 1999. 59. R. Pandey, Defect and Failure Mode Analysis of Large Area Ta2O5 Integrated Capacitors, MS thesis, Dept. of Chemical Engineering, University of Arkansas, May 2001. 60. S. Venigalla, P. Bendale, and J. Adair, Low Temperature Electrochemical Synthesis and Dielectric Characterization of Barium Titanate Films Using Nonalkali Electrolytes, Journal of the Electrochemical Society, 142, 6, 2101, 1995. 61. P. Bendale, S. Venigalla, J. Ambrose, E. Verink Jr., and J. Adair, Preparation of Barium Titanate Films at 55C by an Electrochemical Method, Journal of the American Ceramic Society, 76, 10, 2619, 1993. 62. T. Law, C. Liu, P. Cheng, I. Chong, and D. Lam, Novel Low Temperature BaTiO3 Film Capacitors, In Proceedings of ECTC, 2002. 63. K. Budd, S. Dey, D. Payne SolGel Processing of PbTiO3, PbZrO3, PZT and PLZT Thin Films, British Ceramic Proceedings, 36, 107, 1985. 64. G. Yi, Z. Wu, and M. Sayer, Preparation of Pb(Zr, Ti)O3 Thin Films by SolGel Processing, Journal of Applied Physics, 64, 2713, 1988. 65. Y. Tu et al., Synthesis and Electrical Characterization of Thin Films of PT and PZT Made from a Diol-Based SolGel Route, Journal of the American Ceramic Society, 79, 441, 1996. 66. D. Liu and J. Mevissen Thick Layer Deposition of Lead Perovskites using Diol-Based Chemical Solution Approach, Integrated Ferroelectrics, 18, 263, 1997. 67. J. Scott, High-Dielectric Constant Thin Films for Dynamic Random Access Memories (DRAM), Annual Review of Materials Science, 28, 79100, 1998. 68. N. Tohge, S. Takahashi, and T. Minami, Preparation of PbZrO3-PbTiO3 Ferroelectric Thin Films by the SolGel Process, Journal of the American Chemical Society, 74, 1, 67, 1991. 69. D. Liu et al., Integrated Thin Film Capacitor Arrays, In Proceedings of the International Conference and Exhibition on High Density Packaging and MCMs, IMAPS, p. 431, 1999. 70. T. Kutty and P. Padmini, Mechanism of BaTiO3 Formation through Gel-to-Crystallite Conversions, Materials Chemistry and Physics, 39, 200, 1995. 71. D. Hennings et al., Hydrothermal Preparation of Barium Titanate from Barium-Titanium Acetate Gel Precursors, Journal of the European Ceramic Society, 8, 107, 1991. 72. D. Liu, R. Kennedy et al., Integrated Thin Film Capacitor Arrays, In Proceedings of the 1999 International Conference on High Density Packaging and MCMs, p. 431, 1999. 73. D. Balaraman, P. Markondeya Raj, S. Bhattacharya, and R. Tummala, Novel Hydrothermal Processing of Ceramic-Polymer Nanocomposites for Integral Capacitors, In Proceedings ECTC 2002.

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74. N. Kim et al., Development of Multi-Chip Modules with Integrated Thin Film Passive Elements, In 1997 International Symposium on Microelectronics, 1997. 75. P. Harrey, P. Evans, and D. Harrison, Integrated Capacitors for Conductive Lithographic Film Circuits, IEEE Transactions on Electronics Packaging Manufacturing, 24, 4, 333, 2001. 76. W. McDougall et al., Avatrel Dielectric Polymers For HDP Applications, In Proceedings of the 1999 International Conference on High Density Packaging and MCMs, p. 17, 1999. 77. S. Liang et al., Barium Titanate/Epoxy Composite Dielectric Materials for Integrated Thin Film Capacitors, In Proceedings of the 1998 Electronics and Technology Conference, IEEE, p. 171, 1998. 78. R. Kambe, R. Imai, T. Takada, M. Arakawa, and M. Kuroda, MCM Substrate with High Capacitance, In MCM 94 Proceedings, p. 136, 1994. 79. S. Ogitani, S. Bidstrup-Allen, and P. Kohl, An Investigation of Fundamental Factors Influencing the Permittivity of Composite for Embedded Capacitors, In Proceedings of the 49th Electronic Components and Technology Conference, IEEE, p. 77, 1999. 80. D. Dasgupta and K. Doughty Polymer-Ceramic Composite Materials with High Dielectric Constants, Thin Solid Films, 158, 93, 1988. 81. D. Sinha and P. Pillai Polymer-Ceramic Composites as Potential Capacitor materials, Journal of Materials Science Letters, 8, 673, 1989. 82. K. Mazur, Ferroelectric Polymers, In H. Nalwa, ed., Chapter 11, Marcel Dekker, 1995. 83. S. Ogitani, V. Silverstrov et al., Development of a Ceramic/Epoxy Composite for Integral Capacitors: A Study of Particle Packing, Electroless Cu Plating, and Permittivity Temperature Dependence, International Journal of Microcircuits and Electronic Packaging, 23, 4, 367, 2000. 84. G. Min et al., Development of Polyimide Based Capacitors and Resistors for Integral Passives, In Proceedings of the Technical Conference in IPC Printed Circuit Exposition 2000, San Diego, CA, April 46, S08-4-1, 2000. 85. S. Ramesh, B. Schutzberg, and E. Giannelis, Integral Thin Film Capacitors: Fabrication and Integration Issues, In Proceedings of 2000 Electronic Components and Technology Conference, IEEE, p. 1568, 2000. 86. S. Liang, S. Chong, and E. Giannelis, Barium Titanate/Epoxy Composite Dielectric Materials for Integrated Thin Film Capacitors, In Proceedings of the 48th Electronics Components and Technolgoy Conference, p. 171, 1998. 87. P. Chahal, R. Tummala M. Allen, and M. Swaminathan, A Novel Integrated Decoupling Capacitor for MCM-L Technology, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, 21, 2, 1998. 88. L. F. Rao, C. Tison et al., Use of Dispersant in High K Polymer-Ceramic Nano-Composite to Improve Manufacturability and Performance of Integral Capacitors, In Proceedings of the 52nd ECTC Conference, San Diego, CA, May 2002, Session 22, Paper 4, 2000. 89. S. Ogitani, S. Bidstrup-Allen, and P. Kohl, An Investigation of Fundamental Factors influencing the Permittivity of Composite for Embedded Capacitor, In Proceedings of the 1999 Electronic Components and Technology Conference, IEEE Press, New York, p. 7, 1999. 90. S. Ramesh, C. Haung, S. Liang, and E. Giannelis, Integrated Thin Film Capacitors: In-

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91.

92.

93.

94.

95. 96.

97.

98.

99.

100.

101.

102. 103.

104.

105.

terfacial Control and Implications on Fabrication and Performance, In Proceedings of the 49th ECTC Conference, p. 99, 1999. J. Park, S. Bhattacharya, and M. Allen, Fully Integrated Passive Modules for Filter Applications using Low Temperature Processes, In Proceedings of the 1997 International Symposium on Microelectronics, IMAPS, p. 592, 1997. Y. Rao, S. Ogitani et al., Novel High Dielectric Constant Nano-Structure PolymerCeramic Composite for Embedded Capacitor Application, In Proceedings of the 2000 Electronic Components and Technology Conference, IEEE Press, New York, p. 183, 2000. S. Cho, J. Lee, and K. Paik, Study on the Epoxy/BaTiO3 Embedded Capacitor Films Newly Developed for PWB Applications, In Proceedings of the 52nd ECTC Conference, San Diego, 2002, Session 12, Paper 4, 2002. B. Schutzberg, Ch. Haung et al., Integral Thin Film Capacitors: Materials, Performance and Modeling, In Proceedings 2000 Electronic Components and Technology Conference, p. 1564, 2000. W. Borland, Designing for Embedded Passives, Printed Circuit Design, p. 16, August 2001. M. Peters, M. Lee et al., Thermally Stable Thin Film Tantalum Pentoxide Capacitor for MCM Applications, International Journal of Microcircuits and Electronic Packaging, 19, 4, 364, 1996. W. Worobey, and J. Rutkiewicz, Tantalum Thin-Film RC Circuit Technology for a Universal Active Filter, IEEE Transactions on Parts, Hybrids and Packaging, PHP12, 4, 276, 1976. B. Gnade, S. Summerfelt, and D. Crenshaw, Processing and Device Issues of High Permittivity Materials for DRAMS, In Science and Technology of Electroceramic Thin Films; NATA ASI Series, Auciello and Waswer (eds.), 284, p. 373, 1995. W. Borland and S. Ferguson, Embedded Passive Components in Printing Wiring Boards, a Technology Review, Advanced Embedded Passives Technology website: aept.ncms.org/papers.htm, 2001. W. Borland and J. Felten, Thick Film Ceramic Capacitors and Resistors inside Printed Circuit Boards, In 34th International Symposium on Microelectronics (IMAPS), Baltimore, MD, Oct. 911, 2001. J. Felten, R. Snogren, and J. Zhou, Embedded Ceramic Resistors and Capacitors in PWB: Process and Performance, paper presented at Fall IPC Meeting, Orlando, FL, October 11, 2001. J. Felten and W. Borland, Embedded Ceramic Passives in PWB: Process Development, paper presented at IPC Printed Circuit Expo, Anaheim, CA, April 2001. E. Diaz-Alvarez and J. Krusius, Modeling and Simulation of Integrated Capacitors for High Frequency Chip Power Decoupling, IEEE Transactions on Components and Packaging Technologies, 23, 4, 611, 2000. J. Savic, R. Croswell et. al, Embedded Passives Technology Implementation in RF Applications, paper presented at the IPC Printed Circuit Expo, Long Beach, CA, March 2428, 2002. D. Tuckerman, D. Benson, H. Moore, J. Horner, and J. Gibbons, A High Performance Second Generation SPARC MCM, In Proceedings of the 1994 International Conference on Multichip Modules, ISHM, Denver, CO, 1994.

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Additional References
C. Chaneliere, J. Autran et al., Tatalum Pentoxide Thin Films for Advanced Dielectric Applications, Material Science Engineering, R. 22, 269, 1998. Z. Fu and Q. Quin, Pulsed Laser Deposited Ta2O5 Thin Films as an Electrochromic Material, Electrochemical and Solid State Letters, 2, 11, 600, 1999. P. Jain, J. Kin et al., Integrated Thin Film Capacitors, In Proceedings of the CPES Annual Review, Blacksburg, VA, p. 155, 2000.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 7

DEFECTS AND YIELD ISSUES

RICHARD K. ULRICH

One of the main impediments to establishing integrated passives in mmercial processes is the potential for losing the entire board due to a defect in one single integrated component. Inductors are not expected to cause much of a problem since they are few in number compared to resistors and capacitors and since they are nothing more than shaped interconnect metal. Resistors will be somewhat more prone to yield losses, mainly due to being out of specification, but can be trimmed to tolerances of less than 1%. Integrated capacitors will probably be the main concern for board yield losses for two reasons. First, they are usually the most numerous passive component on the board, mainly due to their use in decoupling. Second, to have high specific capacitance, they must have thin dielectrics, which are more prone to leakage. This chapter discusses the causes of capacitor defects, gives an example of how defect density in integrated capacitors can be measured, and describes how this number can be used to predict the yield of boards that are limited by capacitor defects.

7.1 CAUSES OF FATAL DEFECTS IN INTEGRATED CAPACITORS Defects in integrated capacitors are manifested by high leakage currents, sometimes with leakage resistances under an ohm, and low breakdown voltages. As discussed in Chapter 4, dielectric breakdown in thin films occurs primarily at defects, which makes their resistance properties significantly poorer than those of the same materials in bulk form [1]. Integrated capacitor dielectrics are very delicate structures. Not only are they thin, but also their lateral dimensions may be over 10,000 times their thickness. Ceramics are much weaker in tension than in compression and, especially if they are on the wrong side of the neutral axis or subjected to CTE mismatch stresses, can fail during board flexure or thermal excursions. In fact, ceramic dielectrics can rarely be made much thicker than a micron even without external stresses because they may crack under their own internal stress. A thin-film ceramic dielectric
145

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DEFECTS AND YIELD ISSUES

might encounter a challenging environment if used in a flex substrate underneath surface-mount components. During FR4 lamination, movement of layers relative to one another can be 200500 ppm, up to 10 mils over a 20 inch distance. This sort of distance can be hundreds of times the thickness of these dielectrics. For anodized films, Cu, Au, and other nonanodizable particles can be left over from bottom plate sputtering, or dielectric breakdown can occur during anodization if the formation voltage is too high [2]. For sputtered films and to a lesser extent for anodized ones, rough substrates will always result in more defects than smooth ones, especially when the roughness is a significant fraction of the dielectric thickness [36].

7.2 MEASUREMENT OF DEFECT DENSITY No comprehensive studies of integrated capacitor defect density have been found in the literature, certainly due to the large number of processes under consideration, but a few mentions have been made, mainly with regard to thin-film dielectrics. Peters et al. measured the defect densities for anodized films at 0.02/cm2 and found them to be much lower than in similar sputtered films [7]. The authors of this book have studied the defect density in anodized Ta on a variety of substrate materials using a test structure consisting of 2300 1 1 mm capacitors that are processed simultaneously [8]. After fabrication, the individual capacitors were tested for leakage resistance as a measure of their yield using an automated flying-probe tester. Since all the capacitors shared a common bottom plate, only one probe had to be moved. As long as the defect density was not so large that multiple defects were occurring on one capacitor, an accurate measure of the number of defects per cm2 could be obtained.

Figure 7.1

Distribution of leakage defects in anodized Ta2O5 films over Kapton flex.

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DEFECT DENSITY AND SYSTEM YIELD

147

Figure 7.2

Defect density for anodized Ta2O5 dielectric films over Si substrates.

The upper limit of the apparatus to measure resistance was 8 M, which under 5 V would have resulted in a current density through the 1 mm2 capacitor of 62.5 A/cm2. The results for 500, 1000, and 1920 anodized Ta2O5 films over 2 mil Kapton flex substrates showed that the individual capacitors were either defective due to being very leaky, with a leakage resistance less than a k, or were good components showing a leakage resistance over 8 M, with little distribution in between, as shown in Figure 7.1. Extensive SEM examination of known bad capacitors did not reveal any obvious defects, even at magnifications of 1000 times over a search area of only 1 mm2. Based on these criteria, the defect density could be quantitatively measured, which provided a tool for optimizing the processing and substrate conditions. The defect density for anodized films on flex was found to be very highas much as one per cm2but this could be lowered considerably by coating the flex with BCB as a planarizing layer, leading to the conclusion that surface roughness contributes to the defect density. Defect densities measured over Si substrates, shown in Figure 7.2, were much lower than those on flex.

7.3 DEFECT DENSITY AND SYSTEM YIELD Since integrated capacitors generally cannot be tested before being added to a substrate, yield is a major concern in their implementation. As with the processing of any integrated structure, the fraction of working individual components (the yield) strongly affects the usable fraction of the final assemblies. For N integrated passives

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DEFECTS AND YIELD ISSUES

on a substrate, each with an individual yield Yi, the yield for a substrate will be of the form Yboard+passives = Yboard

Y
N ip,i i=1

where Yboard+passives = yield of the substrate with integrated passives in place Yboard = yield of the substrate prior to the addition of integrated passives Yi,pi = yield of the individual integrated passives N = the number of integrated passives on the substrate The effect of integrated passive yield is easier to visualize if there is only one type on the substrate and if the substrates themselves come into integrated passive processing with 100% yield prior to the addition of integrated passives. The overall yield is then Yboard+passives = (Yip)N Figure 7.3 shows that, even for only a few dozen integrated passives, any significant yield reduction of the individual components results in a large loss of assembly yield. 7.3.1 Predicting Yield from Defect Density If the same integrated component technology is used on the entire board, the density of fatal defects, D per cm2, should also be the same everywhere (Figure 7.4). That means that the number of individual passives doesnt matter, only their total

Figure 7.3 Yield of the substrate after addition of integrated passives as a function of the number and yield of the individual passives.

7.4

YIELD ENHANCEMENT TECHNIQUES FOR CAPACITORS

149

Figure 7.4

Passive set yield as a function of the average total number of fatal defects.

area, A cm2. Multiplying these together gives the average number of defects per board. From there, the Murphy equation can be used to estimate the expected board yield: 1 eDA Ypassives = DA

where Ypassives = yield of the passive set D = fatal defect density, defects/cm2 A = total capacitor area integrated into the board, cm2 DA = average total number of defects/total capacitor area For example, consider a board having a total integrated capacitance of 10 F using 2000 of anodized Ta. This would give 105 nF/cm2 so the required total capacitor area is 95.2 cm2. If this dielectric had a defect density of 0.04 per cm2, then the average number of fatal capacitor defects per board is 3.8, resulting in a board yield of only about 6%, which is far too low for economic manufacture. A board yield of, say, 90% requires an average defect number of 0.107 per board. A thicker dielectric with a lower defect density would also require more area so the shape of the defects/cm2 versus dielectric thickness curve, such as the one in Figure 7.2, is important in evaluating the trade-off. 7.4 YIELD ENHANCEMENT TECHNIQUES FOR CAPACITORS Flaws in thin oxide films may be made visible by placing the bottom plate and dielectric, with no top plate, in a solution of metal ions and making this stack cathod-

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DEFECTS AND YIELD ISSUES

ic. The metal ions in solution will plate over the defects since those are the only areas that current can pass. The amount of current gives some indication of the number and size of the defects [9]. This can also work if the top plate is not shorted to the bottom plate by the defect, which can occur if high leakage current has vaporized a portion of the top plate around the defect. The anodized Ta2O5 or NbOx dielectric of discrete capacitors is sometimes dipped in a solution of Mn(NO3)2 that is then pyrolytically decomposed at 250C into a solid layer of semiconducting MnO2 with a resistivity of only 110 -cm. This treatment significantly decreases the defect density of the resulting capacitor but at the cost of adding some series resistance. What seems to be happening is that current flowing through a defect site in the Ta2O5 dielectric locally heats MnO2. At about 400C, the conductive semiconductor MnO2 is changed to Mn2O3, a material that is much more resistive at about 10,000 -cm, which effectively plugs the defect [10, 11]. In addition, the oxygen liberated during the Mn oxide conversion, along with the localized heating, may reoxidize Ta back to the insulating oxide [12]. As mentioned above, when sputtered Cu bottom plates are oversputtered in the same equipment with Ta that is subsequently anodized, residual Cu particles may be incorporated into the Ta. Copper is not anodizable and can leave a conductive path through the resulting Ta oxide. Using an anodizable metal such as Al as the bottom plate will decrease the number of defects since any Al particles will be anodized, with about the same oxidation kinetics of Ta, and will not result in shorts. After anodization, Ta2O5 films can be electrochemically etched at 70% of the anodization voltage with the same polarization used in the anodization in a solution of LiCl or 0.01% AlCl3 in methanol to remove the metal from underneath defects. Then the part is returned to the anodizing bath for another 30 minutes of anodization [13]. There are also reports of burning out defects by increasing the voltage at the end of anodization or by reversing the voltage [14]. Breakdown itself can be locally very destructive, resulting in visible holes in the overlying capacitor plates and splashed metal. One interesting observation is that if the top electrode is thin (less than about 15003000 ), defects will vaporize a larger area of electrode than the area of the flaw in the dielectric, with the result that the defect is isolated and nonshorting. This has been suggested as a way to actually clear out weak spots in the capacitor [15, 16]. Thin-film polymers and solgel dielectric precursors are commonly applied in multiple thin layers to add up to the desired final thickness. This strategy can greatly decrease the number of pinholes for liquid-applied dielectrics but has not been investigated in detail for gas-deposited or anodized materials.

7.5 CONCLUSION Shortly after the invention of the integrated circuit, there were many who thought that yield problems would restrict the number of devices per chip to a few dozens at most. But advances in manufacturing technology have pushed that number into the

REFERENCES

151

tens of millions. Its not clear how far down the defect density can be pushed, especially with thin-film high-specific-capacitance structures. Yield may be one of the most important considerations in reducing the vast number of possible integrated passive materials and processes.

REFERENCES
1. C. Coombs (ed.), Printed Circuits Handbook, 5th ed., McGraw-Hill, New York, 2001. 2. L. Young, Anodic Oxide Films, Academic Press, New York, 1961. 3. S. Byeon and Y. Tzeng, High Performance Sputtered/Anodized Tantalum Oxide Capacitors, In Proceedings of the IEDM 88, San Francisco, CA, p. 722, 1988. 4. R. Kambe, R. Imai et al., MCM Substrate with High Capacitance, In Proceedings of the MCM 94 Conference, 1994. 5. K. Chen, M. Nielsen, S. Soss, J. Rymaszewski, T. Lu, and C. Wan, Study of Tantalum Oxide Thin Film Capacitors on Metallized Polymer Sheets for Advanced Packaging Applications, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B, 20, 2, 117, 1997. 6. H. Yoshino, T. Ihara, S. Yamanaka, and T. Igarashi, Tantalum Oxide Thin Film Capacitors Suitable for Being Incorporated Into an Integrated Circuit Package, In IEEE/CHMT 89 Japan IEMT Symposium, p. 156, 1989. 7. M. Peters, M. Lee et al., Thermally Stable Thin Film Tantalum Pentoxide Capacitor for MCM Applications, International Journal of Microcircuits and Electronic Packaging, 19, 4, 364, 1996. 8. R. Pandey, Defect and Failure Mode Analysis of Large Area Ta2O5 Integrated Capacitors, MS thesis, Dept. of Chemical Engineering, University of Arkansas, May 2001. 9. B. Mandakis, The Solid Tantalum CapacitorA Solid Contributor to Reliability, In Proceedings of the Capacitor and Resistor Technology Symposium, IEEE, p. 45, 1973. 10. T. Berry, P. Hall, and M. Harris, Thin Film Technology, Van Nostrand, New York, p. 271, 1968 11. D. McLean and F. Roxztoczy, Electrochemical Technology, 4, p. 523, 1966. 12. B. Smith, Failure Mechanisms in Passive Devices, In M. Minges (ed.), Electronic Materials Handbook, vol. 1, Packaging, ASM International, 1989, p. 995, 1989. 13. N. Schwartz and R. Berry, In G. Hass and R. Thun (eds.) Physics of Thin Films, vol. 2, p. 398, Academic Press, New York, 1964. 14. C. Standley and L. Maissel, Journal of Applied Physics, 35, 1530, 1964. 15. N. Axelrod, Journal of the Electrochemical Society, 116, 460, 1969. 16. E. Rymaszewski and P. Jain, Embedded Thin Film CapacitorsTheoretical Limits, IEEE Transactions on Advanced Packaging, to be published Aug. 2003.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 8

ELECTRICAL PERFORMANCE OF INTEGRATED CAPACITORS

RICHARD K. ULRICH AND LEONARD W. SCHAPER

A more complete and accurate model of each passive components electrical behavior leads to a better model and subsequent design of the system. For any passive, discrete or integrated, this model should include both the pure value of the ideal component together with its associated parasitics in a proper arrangement. The result will be a simple circuit made up of at least one capacitor, resistor, and inductor in some combination of series and/or parallel to accurately represent the observed frequency-dependent behavior of the component. For a capacitor, that would mean taking into account its resistive and inductive aspects as well. Purchased discrete passives sometimes come with a full set of electrical performance data from their suppliers, enabling designers to create models of systems that will closely match the manufactured article. If the inductance of a capacitor is included in the SPICE model when designing an LC filter, it could be interpreted that the parasitic was either taken into account or that is was utilized, depending on if you are a pessimist or an optimist. Either way, it is important to know the parasitics in a passive component. In the case of an integrated passive, that particular size, value, and configuration may never have existed before it was designed into a product. In the absence of a specification sheet, it may be necessary to understand what parastics to expect and how to measure them. The major difference between a surface mount and an integrated capacitor is that the latter will almost always have much less inductance. This is a major advantage of integrated capacitors and opens the door for their use in applications such as decoupling, in which inductance is an important issue. The inductance of the integrated capacitor itself can be so small that it is insignificant compared to that of the leads to it, vias on its leads, and other nearby contributions, whereas a surfacemount capacitor nearly always has a significant inductance. Because of this, it is important to be aware of all of the contributions to inductance that will be seen when measuring or utilizing an integrated capacitor. The purpose of this chapter is to describe the useful models of integrated or discrete capacitors, to show how and
153

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ELECTRICAL PERFORMANCE OF INTEGRATED CAPACITORS

why integrated capacitors differ, and to describe the best methods for measuring inductance in integrated capacitors.

8.1 MODELING IDEAL PASSIVES Ideal passives can be characterized by one number: resistance, capacitance, or inductance. The impedance of an ideal resistor is not a function of frequency, whereas the magnitude of impedance versus frequency for ideal capacitors and inductors are functions of opposite slope. The electrical models of ideal components are shown in Figure 8.1. Plotted together in Figure 8.2, capacitance moves downward and inductance upward with increasing frequency. Capacitors act as zero-order high-pass filters and inductors are low-pass filters. The impedance of an ideal resistor would, of course, be a flat line at an impedance equal to its resistance.

8.2 MODELING REAL CAPACITORS Figure 8.3 shows a practical model made up of four ideal components useful for a real capacitor and its parasitics. The impedance of this arrangement is: Zcap = 1 1 1 + 2 1 RDC 2 RAC + 2fL 2 fC (8.1)

This model works well for both discrete and integrated capacitors to match the observed total impedance versus frequency for a wide range of capacitor sizes, styles, and dielectric materials. The ESR is due to the finite conductance of the top plates, the bottom plates, and the associated leads to the capacitor and represents the resistance seen by a AC signal passing through the component. It is ideally zero. The

Figure 8.1 Electrical models of ideal components. Z = impedance, ; f = frequency, Hz; R = resistance, ; C = capacitance, F; L = inductance, H.

8.2

MODELING REAL CAPACITORS

155

Figure 8.2

The magnitude of impedance for capacitors and inductors.

leakage resistance of the capacitor dielectric is ideally infinite and the series inductance, ESL, is ideally zero. The solid line in Figure 8.4 is the impedance versus frequency for a 100 nF capacitor that exhibits only one parasitic20 pH of inductance. The ESR is very small since it does not show (less than about a milli-ohm), and the leakage resistance is very large. The dotted lines are ideal 100 nF and 20 pH behavior. The point in Figure 8.4 where the capacitive and inductive impedances are equal and the slope changes is the self-resonant frequency of the capacitor: 1 fsrf = 2 L C (8.2)

Figure 8.3 Four-parameter model for a capacitor. C = capacitance, F; RAC = parasitic AC resistance or equivalent series resistance (ESR), ; L = parasitic inductance or equivalent series inductance (ESL), H; RDC = DC or leakage resistance of the capacitors dielectric, .

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ELECTRICAL PERFORMANCE OF INTEGRATED CAPACITORS

Figure 8.4 Fit of individual C and L values (dotted lines) over the capacitors impedance (solid lines).

Above this point, the impedance begins to rise with frequency so the overall component is no longer a capacitor at all; it becomes an inductor. For this example, the resonant frequency is 113 MHz. This is also the point at which the phase passes through zero as it moves from 90 to +90 and is, exactly at fsrf, 0. This frequency is important to almost all applications since it marks the end of the components range of acting like a capacitor. An ESR as low as the value used in the previous example (<1 m) is rarely seen in any type of capacitor. A more realistic measured curve would look like the one in Figure 8.5. Inserting these three values into Equation 8.1 and setting RDC to infinity would give a model fit that would match the observed impedance curve very well, indicating that this model is valid for engineering analysis and design over this range of frequencies: Zcap =

1 2 R AC + 2 fL 2fC
2

(8.3)

The corresponding circuit model to be used in SPICE or other simulations is shown in Figure 8.6. It would then appear that these three components in series constitute C, L, and RAC for this capacitor but what about RDC? The leakage resistance will only become important when its value is about the same or less than the total im-

8.2

MODELING REAL CAPACITORS

157

Figure 8.5 Superimposed values of a 100 nF capacitor, a 120 m resistor, and a 20 pH inductor over the measured capacitor impedance.

pedance of the C/L/RAC leg, which, for this example, is below 1 for almost the entire frequency range. Therefore, unless this capacitor is very leaky, it would not show up in the model or in actual measurements. In fact, RDC would have to be around 10 before it would show up at all in the impedance plots such as those in Figures 8.4 and 8.5 but a DC resistance 1000 times larger may still be too small for a useful capacitor, especially in filtering and A/D applications. Figure 8.7 shows the same plot but with a leakage resistance of only 1 . The low resistance of the RDC branch pulls the total impedance down from the straight-line models of the individual series components at high and low frequencies. That would generally be a far leakier capacitor than could be acceptable for almost any application. In principle, Equation 8.1 could be used to perform a curve fit to the data in Figure 8.7 to come up with all four components but, for any useful capacitor, the leakage resistance will be so high that it will not show up in the overall impedance data

Figure 8.6

Circuit model for a real capacitor.

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ELECTRICAL PERFORMANCE OF INTEGRATED CAPACITORS

Figure 8.7

A very leaky capacitor: RDC = 1 .

except at very low frequencies. As a result, Equation 8.3, corresponding to the arrangement in Figure 8.6, is the most useful form for modeling discrete or integrated capacitors. In fact, many models of electrical measurement equipment will perform this very curve fit automatically and give numerical values of C, L, and RAC directly.

8.3 ELECTRICAL PERFORMANCE OF DISCRETE AND INTEGRATED CAPACITORS 8.3.1 Inductance of the Capacitor Alone The main difference between the electrical performance of discrete and integrated capacitors is that the integrated capacitors typically exhibit far lower parasitic inductance, which is a major advantage in a wide range of applications. Figure 8.8 shows measured data for a surface mount and an integrated capacitor, both with equal values of capacitance (8.5 nF) and equal values of parasitic resistance (40 m). Both curves are straight on log-log coordinates down to the lowest measured frequency, so DC leakage does not appear in the data. Therefore, both components can be accurately modeled using Equation 8.3. The parameters giving the best fit are shown in Table 8.1.

8.3 ELECTRICAL PERFORMANCE OF DISCRETE AND INTEGRATED CAPACITORS

159

Figure 8.8 tor.

Measured electrical performance for a surface mount and an integrated capaci-

The parasitic inductance of the integrated capacitor is almost two orders of magnitude less, giving it about an order of magnitude higher frequency range than the surface-mount component. There are two main reasons that an integrated capacitor usually exhibits lower inductance than the typical discrete capacitor. The first has to do with the size of the current loop through the component. The discrete will have a much larger loop because of the height of the component above its contacts to the board, whereas the entire integrated capacitor is within a mil or two of the level of the interconnects. The other effect has to do with the reduction of the self-inductance of the structure by mutual inductance. In the conventional SMD on the left side of Figure 8.9, current travels from left to right in the plates of both polarities. In the integrated capacitor on the right, the connections to the plates are arranged so that current flows in opposite directions in the plates, thereby canceling some of the structures self-inductance by mutual inductance.

Table 8.1 Best-fit parameters for the performance curves of the surface mount and integrated capacitors Capacitance (nF) 8.5 8.5 Parasitic Inductance (pH) 340 5 Parasitic AC Resistance (m) 41 38 Self-Resonant Frequency (MHz) 94 760

Component Surface mount Integrated

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ELECTRICAL PERFORMANCE OF INTEGRATED CAPACITORS

Figure 8.9

Current flow through discrete and integrated capacitors.

Concentrating now on integrated capacitors, it can be shown that the inductance of the structure is directly proportional to the thickness of the dielectric. This is best expressed in henrys/square just as resistance can be expressed in /square. For a parallel plate integrated capacitor with the current entering and leaving the same side and the contacts distributed over that entire side so there is not spreading inductance, the inductance is 0h H/square where 0 is 4 107 H/m and h is the plate separation. In convenient units this is: L = 1.26h where L = inductance/square for an integrated capacitor, pH/square h = plate separation, m Therefore, the inductance of a square integrated capacitor with current flowing in and out the same edge would have an inductance on the order of only 1 pH. This trend can be seen in the data in Figure 8.10, which is a set of impedance scans between the power and ground planes of three circuit boards with different dielectric thicknesses [1]. The capacitance can be pulled out in the linear portions at 10 MHz and, together with the resonant frequencies, Equation 8.2 can be used to deduce the inductance of the structures as a function of dielectric thickness. The results in Table 8.2 show that the inductance increases roughly linearly with plate separation thickness. Figure 8.11 shows the measured curves for five different sizes of the same type of integrated capacitor, all square in shape. Their capacitance increases linearly with their area, which, in this case, covers a range of over four thousand. The two smallest capacitors of the group do not reach their resistive floors, so the value of AC resistance cannot be determined but, on the other hand, it does not affect their performance either over this frequency range. Also because of the low value of the smallest capacitor, it does not reach resonance by the end of the scan so its ESL cannot be determined. The jog in the 0.1 nF curve at 200 MHz is a standing wave resonance probably in the cabling and is commonly seen when the wavelength of (8.4)

8.3 ELECTRICAL PERFORMANCE OF DISCRETE AND INTEGRATED CAPACITORS

161

Figure 8.10

Impedance of three circuits boards with different dielectric thicknesses.

the signal approaches the same order of magnitude as the linear size of the conductors. They disappear as the frequency moves away from that which produces the standing wave. Curvefitting this data gives the results in Table 8.3. There are some trends common to thin-film integrated capacitors that should be noted. Although the capacitor area and value change by two orders of magnitude, the parasitic inductance and resistance change very little since these are per-square quantities. If the capacitor plates are all square and the dielectrics are all the same thickness, the inductance will be the same. If the plates were rectangular with contacts along the long edges, the inductance would be smaller. The larger capacitors have a lower self-resonant frequency because, even though their inductances are all about the same, the capacitance values are larger. The resistance changes little because all of the capacitors were the same shape (square) and the resistance to AC current should be on the order of one square of plate metal since the current, on average, moves out one-half

Table 8.2

Inductance of capacitors with varying plate thicknesses 0.3 mil 1.0 mil 0.37 43 91 71 2.0 mil 0.79 20 100 130

Z at 107 Hz () C (nF) fres (MHz) L (pH)

0.25 630 33 37

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ELECTRICAL PERFORMANCE OF INTEGRATED CAPACITORS

Figure 8.11 pacitor.

Performance curves for five different sizes of the same type of integrated ca-

square and back one-half square. The resistance values are rather high because these capacitors used bottom plates of very thin Ta, a high-resistivity metal. Resistance and inductance have the same geometric relationship, based on the number of squares rather than on the absolute area, and are both subject to spreading effects. Figure 8.12 shows the performance of two surface-mount discretesan 0603 and a low-inductance capacitor arrayalong with a floating plate and a parallel plate integrated capacitor made from anodized Ta. The integrated capacitors have a higher self-resonant frequency and, hence, a larger working range than either of the discretes, even though the integrated components have higher capacitance values. Extracting the model parameters (Table 8.4) shows that the integrated capacitors have orders of magnitude less parasitic inductance than the discretes. Measurements of discrete capacitors from three manufacturers shows that their parasitic in-

Table 8.3 Best-fit parameters for the performance curves of the five sizes of integrated capacitors Capacitance (nF) 0.1 1 9 70 445 Parasitic Inductance, ESL (pH) Too small to measure 62 40 67 48 Parasitic AC Resistance, ESR (m) Too small to measure Too small to measure 170 120 110 Self-Resonant Frequency (MHz) Too high to measure >1800 640 270 73 34

8.3 ELECTRICAL PERFORMANCE OF DISCRETE AND INTEGRATED CAPACITORS

163

Figure 8.12

Comparison of two surface mount and two integrated capacitors.

ductance is typically much higher than any integrated capacitor (Table 8.5). The inductance of the integrated capacitors is very difficult to determine, since the extremely low impedance at high frequency pushes the measurement limits of the HP 4291 instrument. The main difference in the sets of values for discrete versus integrated capacitors is the much lower parasitic inductance for integrated units. ESL values for surfacemount discretes range from the nH range down to about 50 pH, whereas integrated capacitors are much lower, as little as a few pH. The lower ESL for integrated capacitors is a result of their planar structure, which provides smaller current loops and is a major advantage of integrated capacitors. The measurements of inductance for the

Table 8.4 Best-fit parameters for the performance curves of the discrete and integrated capacitors Capacitance (nF) 10 55 105 240 Parasitic Inductance (pH) 1900 30 ~2 ~1 Parasitic AC Resistance (m) 570 110 24 19 Self-Resonant Frequency (MHz) 36 120 ~400 ~400

Component Discrete 0603 Discrete LICA Integrated floating plate Integrated parallel plate

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ELECTRICAL PERFORMANCE OF INTEGRATED CAPACITORS

Table 8.5 Parameter fits to several discrete capacitors from three manufacturers and five floating-plate integrated capacitors Capacitance (nF) 100 10 2 10 2 55 270 106 79 51 10 Parasitic Inductance (pH) 707 594 568 79 71 30 <2 <2 <2 <2 <2 Parasitic AC Resistance (m) 126 445 481 55 487 108 19 18 16 15 17 Self-Resonant Frequency (MHz) 19 65 150 180 420 120 > 220 > 350 > 400 > 500 > 1100

Type Discrete Discrete Discrete Discrete Discrete Discrete Floating-plate integrated Floating-plate integrated Floating-plate integrated Floating-plate integrated Floating-plate integrated

integrated capacitors were below the resolution of equipment used to measure them. Much of this is probably contact inductance. To put the small magnitude of these values into perspective, a short loop of 1 mil bond wire is about 1000 pH, a solder bump is 50 to 100 pH, and a single circle of metallization 1 mm in diameter is about 2500 pH. The inductances associated with integrated capacitors are often going to be much smaller than the methods used to contact them in an electrical system. 8.3.2 Inductance of the Capacitors Leads and Contacts From Equation 8.4, it is clear that the inductance of a parallel plate capacitor, properly connected along one end of the pair of plates, can have a very small inductance. With a thin-film dielectric only 1000 angstroms thick, the inductance of a square capacitor is only 0.13 pH, far too low to measure. In fact, since measurement probes are basically point contacts, the measured inductance is mostly due to the connections, not to the capacitor itself [2]. Simulations based on measured data, but corrected for connection inductance, confirm that the intrinsic inductance of thin-film capacitors is extremely low. Thus, designers must be very careful in connecting to these capacitors in order to realize the benefit of their low inductance properties. It is best to connect with two closely spaced rows of vias or other connections, as close to the load as possible. In other words, try to approach the ideal of a continuous pair of line connections along one edge of the capacitor. The goal is always to minimize the loop inductance of the connection cross section. This connection inductance problem shows up in connections to discrete and integrated capacitors not only during measurement, but also in applications. Particularly when trying to get the benefit of low-inductance discretes, it is essential to minimize the inductance of connections from the power/ground planes to the solder

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165

Figure 8.13

Inductance of vias and interconnects from the power and ground plane.

pads, as shown in Figure 8.13 [3]. Depending on the geometry, there could be several nH present in the loop [4]. Even better than the via in pad design shown would be larger pads with multiple vias to the power and ground planes. Since integrated capacitors are in plane with the power and ground connections and do not require solder pads for mounting, they also avoid these contributions to total inductance. In many boards, however, the power and ground planes themselves are a problem, because of their spacing; they also follow Equation 8.4 for computing per square inductance. A plane separation of several mils can seriously affect capacitor performance, unless the capacitor is close enough to the load that only a small fraction of a square of the power distribution system lies between them. 8.3.3 Equivalent Series Resistance Since the current moves, on average, about halfway down and back the plates of an integrated capacitor, the AC resistance values are on the order of one square of top and bottom plate material since there are no leads to the integrated capacitors. For most capacitor plates made of copper or aluminum, the ESR is of little consequence. However, for very thin plates or plates made of valve or refractory metals, ESR should be considered and accounted for in power distribution system models. 8.3.4 Capacitors as Distributed Devices A discussion of the complexity of generalized power distribution models is beyond the scope of this book, and the topic is extremely complex. Istvan Novak and Larry

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Smith of Sun Microsystems, George Katopis of IBM, and Peter Krusius at Cornell have done excellent work in this area, as have others. A large, distributed capacitor with multiple source and sink locations is simply a special case of the generalized power distribution system, and can be modeled using a bedspring model, which breaks a plane (or a plate) up into a matrix of individual R, L, C, and M elements. Both plates must be modeled; each element represents a given subarea. The size of each of these elements must be a small fraction of the wavelength (in the dielectric between the plates) at the highest frequency of interest. Sources and sinks are connected to the bedspring at appropriate nodes. In this manner, a complete equivalent circuit can be developed for SPICE simulation [57]. For an edge-connected parallel plate capacitor, a multisection transmission line model gives accurate results to many GHz. This model is much easier to implement than the large bedspring if the connection points allow its use. Again, any model is valid only over a frequency range in which a given physical element is a small fraction of a wavelength.

8.4 DISSIPATION FACTOR OF REAL CAPACITORS The dissipation factor of an overall capacitor consists of contributions from the dielectric itself, resistance of the leads and plates, and leakage through the dielectric. The total dissipation factor is 1 Dtot = 2fCRAC + + Ddielec 2fCRDC where Dtot = total dissipation factor Ddielec = dissipation factor of the dielectric The contribution of leakage is often negligible. Consider a 1 nF capacitor operating at 100 MHz with an ESR of 10 m and an insulation resistance of 100 M. The ESR contribution is 0.006 and the leakage contribution is 2 108. Referring back to Table 4.1, 0.6% is on the order of the lower dissipation dielectrics.

8.5 MEASUREMENT OF CAPACITOR PROPERTIES Referring back to Equation 8.1, there are four parameters to be measured: capacitance, ESR, leakage resistance, and ESL. The capacitance is easily measured with a digital multimeter or LCR meter for almost any value required in common systems. The leakage resistance can be determined to at least a lower bound by the same type of equipment, but may require a variable voltage source and picoameter if true leakage curves are desired, such as the one in Figure 8.14.

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MEASUREMENT OF CAPACITOR PROPERTIES

167

Figure 8.14

Leakage current through thin-film anodized Ta2O5 integrated capacitors.

However, the exact shape of the leakage curve is usually not important in a production situation since it is typically required that the capacitor meet a maximum current leakage specification such as 1 A/cm2 at 5 V. Most capacitor dielectrics have a leakage resistance of 10121017 -cm. If this range is formed into 1000 films with an area of 1 cm2 and measured, the ohmic values would be 1071012 , and would give well under 1 A/cm2 at 5 V. Therefore, the value of RDC would have to be orders of magnitude lower than is generally acceptable to show up on most digital multimeters or LCR meters. For that reason, the leakage resistance is usually relegated to being an acceptance specification and the capacitor model actually used is the RCL series model of Equation 8.3. The other two parameters, ESR and ESL, may be difficult to measure for integrated capacitors due to their low values, particularly for the inductance. 8.5.1 ESR and ESL Measurement with an Impedance Analyzer The principle behind an impedance analyzer (IA) is shown in Figure 8.15, with the capacitor as the device under test (DUT). The voltage-source frequency is swept from some low value, perhaps a few kHz, to as high as a couple of GHz. Meanwhile, the magnitude and phase of the resulting current is measured and converted into impedance and phase angle for display. This has the convenience of being a one-port measurement, but is usually limited in frequency range. Although this is usually sufficient for discrete capacitors, integrated capacitors may resonate out of this range. Impedance analyzers should always be able to provide reliable values of capacitance regardless of ESL, ESR, or leakage resistance levels because it can make this measurement at frequencies high enough to reduce the impedance of the

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ELECTRICAL PERFORMANCE OF INTEGRATED CAPACITORS

Figure 8.15

Schematic of an impedance analyzer with a capacitor as the DUT.

capacitor well below the leakage resistance but at frequencies low enough to avoid interference from the inductive parasitics. For leakage resistance, many IAs cannot approach zero frequency and so can measure RDC values that are very low, much lower than would be desired in a capacitor. As a result, the IA usually cannot be used for this and the measurements should be made with a high-range resistance meter or, better yet, a voltage source and picoameter set up to measure leakage current curves. ESR shows up as a floor that appears in two ways depending on whether or not the capacitors parasitic inductance becomes dominant at high frequencies (Figures 8.16 and 8.17). In the first case, shown in Figure 8.16, the self-resonant peak, in theory, extends down to zero ohms since the reactance of the capacitive and inductive aspects of the component are equal in magnitude and opposite in phase. In the second case (Figure 8.17), the self-resonant frequency is off the scale of the IA1 GHz as shown in this exampleas it often will be for integrated capacitors. In this instance, it is easy to determine the minimum ESR that can be seen. A capacitor of value C would run off the scale of maximum frequency fmax at 1/(2fmaxC). Many HP impedance analyz-

Figure 8.16

Resistance floor cuts off the self-resonant peak.

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MEASUREMENT OF CAPACITOR PROPERTIES

169

Figure 8.17

Self-resonant frequency is off scale.

ers have a maximum frequency of 1.8 GHz. The impedance of a 10 pF capacitor at that frequency would be 8.8 and, for a 10 nF capacitor, 8.8 m, and no ESR values lower than this could be seen. The ESR of smaller capacitors is harder to measure because of their higher impedance but, if the resistance floor does not show up over the frequency of interest for the application, it is unimportant anyway. The resonant frequency of the capacitor must be well below the upper range of the impedance analyzer, perhaps several hundred MHz below, or the impedance will not change slope in time for the value of inductance to be measured. Many integrated capacitors, especially those with small values, will not meet this requirement before a couple of GHz and cannot be measured effectively with most impedance analyzers. Table 8.6 shows the minimum values of RAC and parasitic inductance that can be measured with an impedance analyzer with a maximum frequency of 1.8 GHz. An integrated capacitor with one square of resistance in the plates and contacts would have about 10 m of ESR, so a capacitor smaller than about 10 nF would

Table 8.6 Minimum values of parasitic resistance and inductance measurable on an impedance analyzer with a maximum frequency of 1.8 GHz Capacitance 1 pF 10 pF 100 pF 1 nF 10 nF 100 nF Possible Measurable ESR >88 >8.8 >0.88 >88 m >8.8 m >0.8 m Possible Measurable ESL >7.8 nH >0.78 nH >78 pH >8 pH >0.8 pH

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ELECTRICAL PERFORMANCE OF INTEGRATED CAPACITORS

run off the 1.8 GHz scale before the ESR became apparent in the data. It would also probably have an ESL no higher than about a pH and this would probably not be measurable on most impedance analyzers.

8.5.2 ESR and ESL Measurement with a Network Analyzer A network analyzer (NA) utilizes a two-port measurement designed to be used with microwave devices that have about 50 of impedance. A typical NA can sweep into the tens of GHz, which can push the small inductive parasitic impedance of an integrated capacitor high enough to see it above other impedances [8]. However, many capacitors for common electrical equipment are not designed to be microwave devices and may exhibit a variety of resonations and standing waves that may interfere with the measurement. Also, proper connections must be made with probes that have very close tipsas narrow as 150 mand not all capacitors are designed to accommodate this. Figure 8.18 shows a capacitor mounted in the shunt position in a network analyzer. The NA provides a frequency-swept excitation voltage through a 50 output impedance, shown as a resistor; the voltage is measured at a second port, also through a 50 impedance. Network analyzers typically give outputs in the form of S parameters, which are various ratios of measured to exciting voltages. Of the four S parameters available from a NA, the S21 parameter gives the most useful information about a capacitor under test and is obtainable from the configuration shown in Figure 8.18. S21 is the ratio of the magnitude of voltage measured with the DUT present divided by the voltage if no DUT is present. If the DUT has no gain, like all passive components, then S21 is a number less than or equal to one. If no DUT is present, then the measured voltage is one-half the source voltage since the source voltage is dropped over two identical resistors. So the definition of S21 is Vmeas S21 = 1 ( 2Vsource) (8.5)

Figure 8.18 uration.

Schematic of a network analyzer with a capacitor as the DUT in shunt config-

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MEASUREMENT OF CAPACITOR PROPERTIES

171

This is the magnitude of S21. If the instrument gives, instead, the two vector components, the magnitude is the Pythagorean sum:
2 2 S21 = S 21 S 21 ,x + ,y

(8.6)

Based on that definition, with a DUT present with an impedance of Z, Z S21 = 25 + Z (8.7)

Since the impedance of a capacitor at the high frequencies of an NA will typically be much less than 25 , Equation 8.7 may be closely approximated as Z/25 (Figure 8.19). Most NAs give S21 in dB: S21(dB) = 20 log S21 (8.8)

This will be a negative number since S21 < 1. Combining these two equations enables the measurement of capacitor impedance from the dB reported by the NA: 25 10dB/20 Z = 25 10dB/20 1 10dB/20 Most network analyzers have a noise floor around 90 dB, or about 1 m. (8.9)

Figure 8.19

Relationship between capacitors impedance and its S21 parameter.

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ELECTRICAL PERFORMANCE OF INTEGRATED CAPACITORS

As before, the three-parameter model from Equation 8.3 can be plotted versus frequency and curve fit, assuming that the leakage resistance has been tested with a resistance meter and is larger than about 100 : Z= + 2fL R 2fC
2 AC

(8.3)

As an example, Figure 8.20 shows the S21 readout from a NA for an integrated capacitor, which comes off the HP 8510 as dB with a linear frequency axis. This data can be turned into an impedance versus frequency diagram using Equation 8.9. The black dots in Figure 8.20 were converted from the S21 data and plotted on a log-log scale in Figure 8.21. The solid line is the three-parameter fit with C = 0.93 nF, ESR = 18 m and ESL = 3.0 pH. Again, the quality of the fit of this approach to measured data indicates that the model and parameter values are accurate over this frequency range. To summarize the utility of network analyzers for measuring the characteristics of integrated capacitors, the capacitance value can be measured at the low end of the frequency scale. As with LCR meters and impedance analyzers, the leakage resistance can only be measured quantitatively for values that are so low that the capacitor would certainly be considered leaky for almost any application. However, it could be used to see if the component meets a specification of minimum leakage resistance. ESR and ESL should be measurable, at least in principle, due to the much

Figure 8.20

S21 parameter data from the network analyzer for an integrated capacitor.

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MEASUREMENT OF CAPACITOR PROPERTIES

173

Figure 8.21

Curve fit of impedance versus frequency for an integrated capacitor.

higher upper limit of frequency compared to LCR and impedance analyzers. Interference from reflections and standing waves may become significant as the frequency increases into the microwave region. The wavelength of an electromagnetic signal passing through a conductor that is surrounded by a dielectric is c = f k where = wavelength, cm c = speed of light in a vacuum, 3 1010 cm/sec f = frequency, Hz k = dielectric constant of the surrounding As an example, a signal passing through an integrated capacitor with a dielectric made from Al2O3 (k = 9) would have a wavelength of 10 cm at 1 GHz and 1 cm at 10 GHz. Once these wavelengths approach the same order of magnitude as the dimensions of the capacitor in the signals direction, standing waves and reflections can show up as anomalous peaks, valleys, and slopes in the measured S parameters and impedance values. These can make the determination of the components CRL parameters difficult and uncertain. (8.10)

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8.6 SUMMARY The main difference between a discrete and an integrated capacitor is that the latter has much less parasitic inductance, so low that it may be difficult to measure. As a result, the resonant frequency of an integrated capacitor will be higher for the same value, giving it a wider range of applicability. The reasons for this are that the integrated capacitor moves current in opposite directions internally, providing a canceling effect on the resulting magnetic fields, and also because the plates are very close together, providing a small current loop. Additionally, the inductance of the conductors between the interconnects and the capacitor is lower for the integrated model because the capacitor is planar and in plane, also providing a smaller loop. Discrete capacitors normally require a via to the surface and back. Finally, integrated capacitors do not require solder connections. In electronic systems, the inductance of vias and interconnects may exceed that of an integrated capacitor to the point that the capacitors contribution to the total parasitics is negligible. Another difference is that both the inductance and the resistance of integrated capacitors is a per-square quantity rather than a per-area one. This refers to the capacitor itself if the current comes in distributed evenly over one edge so there is not spreading inductance or resistance, which would itself be a constant quantity with capacitor size above a small lower limit. With discrete capacitors, the units inductance tends to follow the case size since this creates a larger current loop. Figure 8.22 shows the effect of increasing value on both types. In each case, increasing capacitance causes the self-resonant frequency to move down, but less so in the case of the integrated capacitor because its inductance curve does not change. This figure also shows why it is easier to measure the inductance on larger values of both types of capacitors; the self-resonant frequency for smaller units may be off the frequency scale, particularly for integrated capacitors that have very small ESLs. Of course, if the inductive effects do not show up over the frequency range of interest, they are unimportant anyway. Table 8.7 outlines the best

Figure 8.22

Effect of value change for discrete and integrated capacitors.

REFERENCES

175

Table 8.7

Summary of measurement methods for integrated capacitors Impedance Analyzer Excellent May be used for specification testing, but some models cannot operate at zero frequency to give an exact value. Good Network Analyzer Excellent May be used for specification testing, but most models cannot operate at zero frequency to give an exact value. Good

LCR or Digital Multi-Meter Capacitance Leakage Resistance Excellent Good. Can at least determine if the value is high enough for the cap to not be leaky.

ESR

Some LCR meters can do this, but integrated capacitors may be too low to measure accurately. Integrated capacitors usually too low to measure this way.

ESL

Only useful if the resonant frequency is lower than the instruments upper range.

Can give good values by finding the resonant frequency if there is no interference from microwave frequency standing waves.

equipment to use for measuring the four components of a standard lumped capacitor model.

REFERENCES
1. Impedance and EMC Characterization Data of Embedded Capacitance Materials, In Proceedings of APEX2001, San Diego, CA, January 1618, 2001. 2. K. Chen, W. Brown et al., A Study of the High Frequency Performance of Thin Film Capacitors for Electronic Packaging, IEEE Transactions on Advanced Packaging, 23, 2, 293, 2000. 3. T. Roy and L. Smith, ESR and ESL of Ceramic Capacitor Applied to Decoupling Applications, In IEEE Topical Meeting on Electrical Performance of Electrical Packaging, West Point, NY, p. 213, Oct. 1998. 4. J. Cain, Interconnect Schemes for Low Inductance Ceramic Capacitors, AVX Corporation, avx.com. 5. G. Carchon, S. Brebels, et al., Accurate Measurements and Characterization up to 50 GHz of CPW-based Integrated Passives in Microwave MCM-D, In Proceedings of the 2000 Electronics Components and Technology Conference, IEEE Press, New York, p. 459, 2000. 6. E. Diaz-Alvarez and J. Krusius, Modeling and Simulation of Integrated Capacitors for

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ELECTRICAL PERFORMANCE OF INTEGRATED CAPACITORS

High Frequency Chip Power Decoupling, IEEE Transactions on Components and Packaging Technologies, 23, 4, 611, 2000. 7. K. Lim Choi and M. Swaminathan, Synthesis of Equivalent Circuits For Two-Port Integral Passive Components, In Proceedings 1999 International Conference on High Density Packaging and MCMs, p. 316, 1999. 8. I. Novak, Measuring Milliohms and PicoHenrys in Power Distribution Networks, In Proceedings of DesignCon2000, Santa Clara, CA, February 14, 2000.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 9

DECOUPLING
LEONARD W. SCHAPER

9.1 POWER DISTRIBUTION Power distribution is one of the principal functions of electronic packaging, and decoupling is one of the principal aspects of power distribution. Simply stated, the role of power distribution is to supply stable, noise-free power, at a constant, specific voltage, to integrated circuits (ICs) and other components that comprise an electronic system. The trends in electronic systems are for the supply voltages to decrease, required currents to increase, and clock speeds to increase, making it more difficult to distribute noise-free power to all parts of the system. Decoupling capacitors are necessary to achieve this, but the use of discrete capacitors in decoupling is becoming less effective due to their parasitic inductance. This opens the door to the use of integrated capacitors, with far less parasitic inductance, for this application. The ideal power distribution system would look like a battery of constant voltage, regardless of the current draw, connected to the IC by a zero-impedance line, as shown in Figure 9.1. From the viewpoint of the IC, it would see constant voltage no matter how much power it drew or how its current requirements changed with time over the space of a single clock cycle. In reality, of course, this is not the case. In most systems, one power supply distributes power for the entire system through a combination of wires, connectors, distribution planes within circuit boards, etc. All of these conductive paths have parasitic inductance, which has no effect on DC, but has a significant effect at the high frequencies typical of IC operation. They also have parasitic resistance, which affects both DC and AC current. The problem, particularly in digital systems, is that as ICs switch many devices between high and low logic levels at each clock cycle, their current demands change rapidly with time. Thus, the power supply is not just supplying a constant current at a particular voltage, but is being asked to supply a highly variable amount of current over a fraction of the clock cycle, which means that the current waveform has many components across a wide range of frequencies, from DC to several GHz. Any impedance present in the real power distribution
177

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DECOUPLING

Figure 9.1

An ideal power supply and power distribution system.

system will produce a voltage drop as shown in Figure 9.2. Individual ICs will not see the purely constant voltage they need for proper operation. Noise in the voltage supply can cause false logic triggering or insufficient potential to drive signals on or off the chip. The current changes demanded by the IC will not be supplied because of the series inductance. The solution to this problem is to put capacitors, called decoupling or bypass capacitors, across the power and ground distribution conductors, physically close to the ICs that are demanding the varying current. These capacitors act as short-term, low-impedance reservoirs of charge, and supply current that cannot otherwise be supplied by the power supply because of the low-pass filtering action of the parasitic inductances. They are referred to as decoupling because they decouple the power distribution system from the current surges of the IC, or as bypass because they bypass whatever noise is on the power supply conductors to ground. This is shown in basic form in Figure 9.3. Viewed as decoupling capacitors, they act as batteries to run the IC for one clock cycle. In between periods of high current demand, the power supply acts as a battery charger to recharge the capacitor. Viewed as bypass capacitors, they are high-pass filters that short high-frequency noise generated by the IC and prevent it from getting back into the power distribution system.

Figure 9.2 tors.

A real power supply and power distribution system without decoupling capaci-

9.1

POWER DISTRIBUTION

179

Figure 9.3

A real power supply and power distribution system with a decoupling capacitor.

Considered still another way, the job of the decoupling capacitor is to make the power distribution system have zero AC impedance when viewed from the IC. Since the parasitic series inductances are relatively small, the IC can see all the way to the power supply at low frequencies. That is, low frequency components of varying current can be supplied directly from the power supply and its output capacitors. At high frequencies, it is the decoupling capacitor that must provide nearzero impedance. The capacitor should be sized to make its impedance sufficiently low (ideally zero) over the frequency range of interest to satisfy the voltage stability requirements of the IC. The decoupling capacitor in Figure 9.3 is shown as a pure component with no parasitics of its own but, as described in Chapter 8, it would have a small amount of ESR and ESL of its own along with some in the leads and vias between it and the IC. The issue can also be examined in the time domain. The IC tries to draw a specific amount of charge from the power distribution system in a certain amount of time. Because of the parasitic inductance, the power supply itself is unable to deliver that charge; it all must come from the decoupling capacitor. The capacitor obeys the equation I t = C V. That is, pulling a current I out of a capacitor for a time t will reduce the voltage on that capacitor by V. The bigger the capacitor, the more charge it can store, and the less voltage drop will be produced by a given current drain. The chain of decoupling capacitors must be able to keep the supply voltage within the tolerance of the IC throughout the period when the IC is drawing current. This establishes the lower limit on capacitor values [1]. In normal operation, the power supply must be able to recharge the capacitor up to the full power supply voltage during one clock cycle, even though the IC is drawing large amounts of current during part of the cycle. If the intervening inductance is too large, this will not be possible. This gives rise to the idea of a hierarchy of decoupling in which each stage closer to the load is able to respond to higher frequency components of the load current than the stage before. This is shown in Figure 9.5. The capacitor closest to the power supply (furthest from the IC) supplies the lowest frequency components of the loads varying current, the middle one supplies mid-frequency components, and the capacitor closest to the load, with very little in-

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DECOUPLING

Figure 9.4

Impedance-frequency behavior of ideal and real decoupling capacitors.

tervening inductance, supplies the highest frequency currents. The power supply simply delivers the average current needed by the whole system. The values of the individual capacitors are a complex function of how the current requirements frequency components are distributed through the system, which is in turn a function of the ICs demands as well as the value and location of the distributed parasitics on the board and in the capacitors. The picture is further complicated because there are many ICs and many decoupling capacitors in the system, but the principle is the same. The low-frequency energy is typically supplied by large electrolytic capacitors, perhaps one on each board; the mid-frequency energy by large ceramic SMDs, with several on each board; and the high-frequency energy by smaller ceramic SMDs placed close to the ICs they decouple. Because the low-frequency capacitors are not as affected by the series inductances of the power distribution system, they can be anywhere on the board. Capacitors for higher frequencies have to be located closer to the loads they serve in order to minimize the inductance between them and the ICs they serve. It should be noted that the high frequencies and large current demands of the latest

Figure 9.5

Hierarchy of decoupling capacitors.

9.2 DECOUPLING WITH DISCRETE CAPACITORS

181

microprocessors means that locating decoupling capacitors immediately adjacent to the IC packages is no longer sufficient; the parasitic inductance of the package itself is enough to block the necessary high-frequency currents. Thus, we are starting to see decoupling capacitors mounted inside the IC packages themselves, and even provided on unused areas of the IC die itself, using gate oxide, which is, of course, an integrated capacitor [2, 3]. Also complicating the issue is the fact that not only the clock frequency needs to be decoupled. Because of system power-saving requirements, sections of microprocessors and other complex ICs do not operate all the time, but must power up (recharge) instantly, or at least within a couple of clock cycles, on demand to be ready to perform operations. This powering up and down can induce huge I demands on the power distribution system at mid-range frequencies well below the clock frequency. All of this charge must be available to the IC in a very short time (little inductance in the loop), which greatly increases the decoupling demand [4].

9.2 DECOUPLING WITH DISCRETE CAPACITORS A significant problem with decoupling capacitors, no matter where they are located in a power distribution system, is that capacitors are not ideal devices; they have their own internal parasitic resistance (ESR) and inductance (ESL), as was discussed previously. Because of this, no matter how close the capacitors are to the IC, there is still some inductance and resistance that prevents them from decoupling perfectly. For many discrete chip capacitors of the size normally used for decoupling (10100 nF), the ESR can be hundreds of m and the ESL can be several hundred pH. For decoupling, the way to overcome the ESR and ESL limitations is to place multiple capacitors in parallel. All three quantities change favorably: capacitance increases to the sum of the individual components while inductance and resistance decrease. The top curve in Figure 9.6 shows the impedance versus frequency for a 100 nF capacitor that also has an ESR of 50 m and an ESL of 300 pH, which are representative values for a ceramic chip capacitor. The bottom curve is for five of these identical capacitors in parallel. The effect is to move the entire curve down while maintaining its overall shape. This increases the frequency range that is below a desired impedance, such as 0.10 [57]. It is not unusual, in a complex, multiboard system, to have hundreds of capacitors used for decoupling, both to provide the necessary charge reservoirs as well as to reduce inductive effects. All of these discretes can occupy a substantial amount of PWB space and contribute to cost; the number of solder joints can also be a reliability concern. As was seen in Figure 9.6, a parallel combination of capacitors can reduce the impedance compared with one capacitor, but simply paralleling the same value of capacitor does not create the wideband, low-impedance power distribution system that is necessary. Figure 9.7 shows the result of a parallel combination of five capacitors of different values, in this case 470 nF, 100 nF, 50 nF, 20 nF, and 10 nF. In

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DECOUPLING

Figure 9.6

Comparison of one and five identical decoupling capacitors in parallel.

real discrete capacitors, corresponding parasitics run approximately in proportion to discrete component value or case size. In this example, the ESLs range from 500 to 100 pH, and ESRs from 80 to 20 m. Both the individual capacitor impedances as well as the impedance of the parallel combination are shown. Note that paralleling capacitors of different values rather than all the same value significantly broadens the range of frequencies with low impedance. However, decoupling at frequencies >100 MHz is still difficult because of the intrinsic inductance of standard surface-

Figure 9.7

Comparison of one and five different decoupling capacitors in parallel.

9.3

DECOUPLING WITH INTEGRATED CAPACITORS

183

mount devices. This has led to the development of low-inductance capacitors (~60 pH), such as the AVX LICA (low inductance capacitor array). Multiple devices must still be used in parallel to achieve a power distribution system impedance below 0.1 ohm at frequencies in the GHz range [8].

9.3 DECOUPLING WITH INTEGRATED CAPACITORS As described in Chapter 8, integrated capacitors have much less parasitic inductance than surface-mount discretes for three reasons. First, the current flows in opposite directions in the plates, which results in fields that tend to cancel each other out, lowering the inductance. Second, the plates tend to be flat and parallel in a single plane, which decreases the current loop size relative to folded capacitors in a surface-mount case. Third, the integrated capacitor is in plane with the interconnects, further reducing the current-loop area and eliminating vias that contribute to inductance. The result is that the total inductance of an integrated capacitor, including lead and spreading inductance, can easily be less than a few pH. For example, using anodized tantalum, dielectrics of 1000 can be produced with good yields, leading to a per-square inductance, as measured, of ~4 pH, and about one square of resistance (about 10 m using 2 m sputtered Cu as the plates). Figure 9.8 shows a comparison of the 100 nF discrete from Figure 9.6 and a 100 nF integrated capacitor, which would have an area of about 0.5 cm2 or 7 mm on a side. Even without the lower ESR, the improved ESL performance of the integrated capacitor would give it superior decoupling performance [9]. In fact, the high frequency performance of this integrated capacitor would be even better than pictured. The as-measured inductance reflects the problem of prob-

Figure 9.8

Comparison of 100 nF discrete and integrated decoupling capacitors.

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DECOUPLING

ing a device with a microwave probe, which is a two-point connection. In actuality, multiple connections could be made to the integrated capacitor. If they are made as power/ground pairs to minimize loop inductance, these numerous connections parallel the inductance of many two-point connections. Simulations have shown that with line connections instead of point connections into a one-square capacitor, the performance at 10 GHz would be at least five times better than a two-point connection would indicate. This is shown in Figure 9.9, which shows a capacitor of only 500 pF and very thin (resistive) plates. But the important feature is the difference in the two simulations at >3 GHz. The line contact has a significant beneficial effect on high-frequency performance [10]. Figure 9.10 shows an array of 25 nF Ta2O5 capacitors on flex that have distributed contacts along one half of their long side. Of course, the transition has to be made somewhere from narrow interconnect or solder ball to the wide connection, but careful design using integrated capacitors can lower the overall inductance below anything achievable with surface mounts. Since the inductance and the resistance of integrated capacitors, apart from leads and contacts, is constant per square of area rather than per area itself, a 1 mm2 integrated capacitor would have the same inductance and resistance as a 1 cm2 device. The fact that parasitic inductance and resistance do not scale with size but capacitance values do provides another important advantage for decoupling. A single integrated capacitor can replace the multiple discrete capacitors mounted in parallel; a certain total area is required for the integrated solution and it does not much matter how it is arranged, as long as the total number of squares is low. In order to determine the effectiveness of any decoupling scheme in todays high-frequency digital systems, it is necessary to model the power distribution system with a high level of detail. The power and ground planes are generally represented by a bedspring model with per-area values of self-inductance, resistance,

Figure 9.9

The advantage of line contact over a point contact to an integrated capacitor.

9.4 DIELECTRICS AND CONFIGURATIONS FOR INTEGRATED DECOUPLING

185

Figure 9.10

25 nF integrated capacitors with distributed contacts.

and capacitance. The mutual inductance between the power and ground planes must also be considered. The models of the planes alone can have hundreds of nodes and components. Then the models for decoupling capacitors and time-varying loads are connected at appropriate locations, and a detailed simulation can be run [11, 12]. The details of this level of modeling are, of course, well beyond the scope of this book. Accurate prediction of the performance of a power distribution system, including the effects of all decoupling capacitors, requires an extremely elaborate model that takes into account capacitor placement, the incremental inductance of portions of power distribution planes, and an accurate prediction of the time-variant current loads of all ICs in the system. Needless to say, most systems are never modeled to this level of detail. It has become clear from some modeling and measurement efforts that power distribution plane resonances can create problems when capacitors with very low ESR are used for decoupling. Lossy dielectrics, either for discrete or integrated capacitors, may be needed to quiet these effects [13].

9.4 DIELECTRICS AND CONFIGURATIONS FOR INTEGRATED DECOUPLING An extremely simple approach to integrated decoupling is to just reduce the thickness of the insulator between the power and ground planes, thereby forming a paral-

186

DECOUPLING

lel plate capacitor the size of the board. The Zycon buried capacitance material is a 2 mil layer of FR4 that can be used between power and ground planes. This provides a capacitance of 0.078 nF/cm2, which is a very small value. Some materials that have been proposed for integrated decoupling in printed wiring boards consist of fine particles of high dielectric constant material mixed into an epoxy or other organic that can be applied to copper foil in a thin layer. Even with very fine particles of barium titanate or other ferroelectric materials, there is a limit on the density of particles that can be mixed with an organic binder and still have the resulting material be processable. The resulting dielectric constant of many of these composite materials is around 4060. The inability to make extremely thin layers (<10 microns or so) means that the capacitance is, at most, around 20 nF/cm2. Their performance at the highest frequencies may be limited by inductance caused by the spacing between the plates or power distribution planes compared to thin-film integrated capacitors. If the specific capacitance is low and a large area of the board is used to boost the total available capacitance to the required value, care must be taken in the design to ensure that the entire board-sized capacitor can be seen by the ICs it serves. At very high clock rates, the time of flight may be too short for the highest-frequency components to reach very far from the chip. For a given design, say that the highest frequency to be considered is six times the clock frequency of 1 GHz. The distance of flight through the board at 6 GHZ is only about two inches, so whatever capacitance is intended to decouple these frequencies must be well under that distance from the IC. It may be necessary to utilize an integrated dielectric with a higher specific capacitance to put the decoupling within reach. Thin-film dielectrics are currently the only way to obtain over 100 nF/cm2. Tantalum, for example, can be sputtered on copper foil and anodized, or Ta2O5 can be sputtered directly to give up to 200 nF/cm2, with excellent high-frequency characteristics, as discussed in a previous chapter [14]. The same might be possible with Ti or Nb. These represent the high end of the paraelectrics. Ferroelectrics are even more suitable for decoupling since they provide very high specific capacitances, perhaps 1000s of nF/cm2, and since their frequency- and temperature-dependent behavior is not a problem for energy storage as long as they meet the minimum values. The problem with utilizing them in organic boards, as has been mentioned frequently before, is that they generally require a high-temperature anneal to achieve high dielectric constants. To circumvent this problem, integrated capacitors based on ferroelectrics can be formed on metal coupons separately from the organic board and laminated in later, as in the DuPont process [15, 16]. It was pointed out earlier that integrated capacitors are starting to be seen onchip, utilizing gate oxide over otherwise unused areas of the IC [17]. Gate oxide can provide up to several hundred nF/cm2 with the lowest possible parasitic inductance, but the areas are limited. It probably would never be economical to increase chip size solely for providing on-chip decoupling. Some preliminary work has been done on fabricating capacitors directly on top of the passivation layer of the IC, as shown Figure 9.11 [18] but this process would have to be very high yield to be feasible.

9.5

INTEGRATED DECOUPOING AS AN ENTRY APPLICATION

187

Figure 9.11

Decoupling capacitor fabricated on the passivation layer of an IC.

9.5 INTEGRATED DECOUPLING AS AN ENTRY APPLICATION Decoupling is an ideal candidate for an entry application for integrated passives. There are no critical tolerance issues; any amount of capacitance is a help. Although huge amounts of capacitance would be useful at the board level, it is not anticipated that integrated decoupling will replace the low-frequency bulk decoupling supplied by electrolytic capacitors, or even all of the mid-frequency decoupling required by rapid power fluctuations controlled by power management techniques. But integrated decoupling will replace a great many discrete ceramic chip capacitors that currently crowd around high-powered microprocessors, and will eliminate the board area and dozens of solder joints needed to mount them. [19] Surface space near these chips would be better utilized for memory access or on-board communication functions. With the proper low-inductance IC packaging, the integrated capacitor will be useful up to several gigahertz. Integrated decoupling requires no modifications to the CAD system to be useful. It must be accounted for in the design process, of course, and proper design rules for clearances must be implemented, but the integrated decap does not need the design system to understand that components can be located within a PWB, not just on the top and bottom. One of the most important unknowns in replacing discrete decoupling with integrated decoupling is determining how much capacitance is really needed. In discrete decoupling, much of the capacitance is present only because more capacitors were put in parallel in order to reduce the total inductance. When evaluating integrated decoupling, this thinking results in a desire to put in large amounts of capacitance, much more than is needed to run the IC for one clock cycle. However, due to

188

DECOUPLING

the inherently low inductance of integrated capacitors, the amount required should be evaluated on its own merits. The complexity of determining this, particularly with all of the various board, power supply, and IC configurations, probably means that some combination of modeling and experimentation is necessary [20]. As an example of how direct measurements of decoupling performance can be done, Figure 9.12 shows a side-by-side test structure used to measure decoupling performance, designed by Pat Parkerson at the University of Arkansas. Two identical high-current chips were mounted in a single enclosure, the one of the right with a 22 nF surface mount decoupling capacitor and the one of the left with a 22 nF integrated decoupling capacitor made of anodized Ta2O5 with the same value. The 4 4 mm integrated capacitor is beneath the two broad power-ground pads and cannot be seen. Figure 9.13 shows the measurements of power-to-ground noise for the two cases with the test ICs running at 6.7 MHz. The peak-to-peak waveform using the integrated capacitor was considerably less due to its reduced inductance. Decoupling is a function presently required by every electronic system and is currently satisfied using discrete capacitors only. However, integrated capacitors are very attractive for this application due to their low inductance, savings of surface area, and lack of solder joints. Decoupling is one of the few applications in which a single integrated component can replace multiple surface mounts, again due to the very low inductance of the integrated units. In the near future, highspeed systems will require considerably more current fed to them at higher frequencies and will require lower voltage noise levels. Integrated capacitors may be the only way to decouple some of these systems. The potential volume of PWBs with integrated decoupling will drive technology development and bring costs down. Since yield will be critical, introduction will probably be first implemented on small substrates, such as individual IC packages or small few-chip modules,

Figure 9.12 Side-by-side test structure for measuring the relative performance of integrated and surface-mount decoupling.

REFERENCES

189

Figure 9.13 coupling.

Comparison of power-ground voltage to an IC with integrated and discrete de-

rather than on large motherboards. As yields and economics allow, the integrated decoupling solution will move to larger and larger boards, until it is regarded as standard practice.

REFERENCES
1. L. Schaper and D. Amey, Improved Electrical Performance Required for Future MOS Packaging, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 283289, September, 1983. 2. L. Smith, Packaging and Power Distribution Design Considerations for a Sun Microsystems Desktop Workstation, In Electrical Performance of Electrical Packages Conference, Oct, 1997. 3. L. Smith, Decoupling Capacitor Calculations for CMOS Circuits, In Electrical Performance of Electrical Packages Conference, Nov, 1994. 4. W. Becker et al., Modeling, Simulation and Measurement of Mid-Frequency Simultaneous Switch Noise in Computer Systems, IEEE Transactions on Components, Packaging and Manufacturing Technology, Part B, 21, 2, 1998. 5. L. Schaper and G. Morcan, High Frequency Characteristics of MCM Decoupling Capacitors, In Proceedings of the 46th ECTC, pp. 358364, 1996. 6. A. Murphy and F. Young, High Frequency Performance of Multilayer Capacitors, IEEE Transactions on Microwave Theory and Techniques, 43, 20072015, 1995. 7. A. Murphy and F. Young, High Frequency Design and Performance of Tubular Capacitors, IEEE Transactions on Components, Hybrids, Manufacturing Technology, 16, 2, 228, 1993. 8. L. Smith et al., Power Distribution System Design Methodology and Capacitor Selec-

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DECOUPLING

9. 10.

11.

12.

13. 14.

15.

16.

17.

18.

19.

20.

tion for Modern CMOS Technology, IEEE Transactions on Advanced Packaging, 22, 3, 284, 1999. L. Schaper, R. Ulrich, D. Nelms, E. Porter, T. Lenihan, and C. Wan, The Stealth Decoupling Capacitor, In Proceedings of the 47th ECTC, pp. 724729, 1997. K. Chen, W. D. Brown, L. Schaper, S. S. Ang, and H. Naseem, A Study of the High Frequency Performance of Thin Film Capacitors for Electronic Packaging, IEEE Transactions on Advanced Packaging, 293302, 2000. W. Becker et al., Modeling, Simulation, and Measurement of Mid-Frequency Simultaneous Switching Noise in Computer Systems, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, 21, 2, 1998. S. Chun, M. Swaminathan, L. D. Smith, J. Srinivasan, Z. Jin, and M. K. Iyer, Modeling of Simultaneous Switching Noise in High Speed Systems, IEEE Transactions on Advanced Packaging, 24, 2, 132, 2001. I. Novak, Lossy Power Distribution Networks with Thin Dielectric Layers and/or Thin Conductive Layers, IEEE Transactions on Advanced Packaging, 23, 3, 353, 2000. Y. Imanaka, T. Shioga, and J. Baniecki, Decoupling Capacitor with Low Inductance for High Frequency Digital Applications, Fujitsu Science and Technology Journal, 38, 1, 22, 2002. R. Ulrich and L. Schaper, Materials Options for Dielectrics in Integrated Capacitors, In Proceedings of the International Symposium on Advanced Packaging Materials, 3843, 2000. R. Ulrich, L. Schaper, D. Nelms, and M. Leftwich, Comparison of Paraelectric and Ferroelectric Materials for Applications as Dielectrics in Thin Film Integrated Capacitors, International Journal of Microcircuits and Electronic Packaging, p. 172181, 2000. Howard H. Chen and J. S. Neely, Interconnect and Circuit Modeling Techniques for Full-Chip Power Supply Noise Analysis, IEEE Transactions on Components, Packaging, Manufacturing Technology, 21, 209215, 1998. M. Wasef, Fabrication of Anodized Tantalum Oxide Integrated Capacitors on Singulated Chips with Active Devices, PhD dissertation, Dept. of Chemical Engineering, University of Arkansas, May 2001. B. K. Sen, J. C. Parker, Jr., J.-Y. Liou, H. Adachi, and R. L. Wheeler, Performance Comparison of Discrete and Buried Capacitors, In Proceedings of the 1996 International Conference on Multichip Modules, Denver, CO, p. 333, April 1996. Z. Wu, Y. Chen, and J. Fang, Modeling and Simulation of Integral Decoupling Capacitors in Single and Multichip Module Electronics Packaging, In Proceedings of the 44th Electronic Components and Technology Conference, Washington, DC, p. 945, May 1994.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 10

INTEGRATED INDUCTORS
GEERT J. CARCHON AND WALTER DE RAEDT

10.1 INTRODUCTION Inductors integrated in todays typical silicon processes cannot meet the high performance specifications required for future RF ICs [1] as they typically use an Al/Cu metallization to pattern the spiral and underpass. This metal is inherently fairly resistive and, as the integration level increases, the metal thickness is typically thinned to decrease the achievable line pitch. As will be shown in Section 10.2, this thinning of metal layers and their associated interlayer dielectrics, creates a fundamental problem when trying to realize high-quality inductors on a Si chip as process technologies advance. There are basically two options to realize the high-quality inductors required for future high performance applications: 1. In the system in a package (SiP) approach, high-quality inductors and other passive components are realized off-chip using a passive integration technology such as LTCC or MCM-D [213]. In this case, a full codesign between the active and passive components is required. The SiP approach results in higher performance inductors as compared to on-chip Si-solutions as lowloss dielectrics and thick Cu layers can be readily used. In addition, due to the lower cost per-unit area, size constraints for the off-chip passive components are not as severe as for an on-chip solution, thereby further increasing the performance that may be achieved. 2. Another approach is to further increase the performance of on-chip inductors. This may be done by replacing the conventional Al/SiO2 technology with low-k materials and thick Cu metallization [1, 1418]. However, thick Cu is not a standard back-end process and the dielectric in between the spiral and the lossy silicon substrate is still relatively thin. 1. An alternative is the use of micromachining techniques to remove the
191

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INTEGRATED INDUCTORS

lossy substrate underneath the spiral inductor in a postprocessing step. This may be done from the top [19, 20] or the backside [21] of the Si wafer. Other possibilities are the creation of an air gap in between the spiral inductor and the substrate using air bridge technology [22] or the realization of spiral inductors using wafer-level packaging techniques [2327]. In the latter process, thick Cu layers with high accuracy and small dimensions may be realized above the passivation, on top of standard silicon wafers. Due to the availability of relatively thick dielectrics, the distance between the spiral and the lossy silicon substrate can be increased, thereby improving the high frequency performance of the inductors. Whichever of the two options described above, on- or off-chip, is selected for the integration of the inductors, the layout of the integrated spiral inductor is basically the same and governed by the same factors: material properties and inductor operating principles. The goal of this chapter is to study the performance of spiral inductors for RF applications and to see how their performance is related to material parameters (the conductivity of the used metals, the resistivity/loss tangent of the used dielectrics, their respective thicknesses, etc.) and to design parameters (inductor type and layout parameters). First we will describe several inductor layouts and briefly discuss the operating principle as this will help in understanding the limiting factors of performance. Then, the equivalent circuit model of a spiral inductor will be explained. The inductors quality factor, QL, will be presented and the relation between the quality factor and the equivalent circuit parameters will be outlined and illustrated. This will be used to explain how the performance of spiral inductors may be improved by technological, design, and layout changes. Several approaches to predict the performance of integrated inductors will be described and several examples of inductors integrated in various technologies (Si, GaAs MMICs, MCM-D, and LTCC) will be given. Finally, we will discuss some circuit applications to show how the overall circuit performance may be determined by the performance of the inductors.

10.2 INDUCTOR BEHAVIOR AND PERFORMANCE PARAMETERS 10.2.1 Inductor Layouts and Values Some layouts of integrated inductors are shown in Figure 10.1. The transmission line inductor uses a single metal strip, whereas the loop inductor is more compact and has a shape. Repeats of these layouts may be cascaded, thereby resulting in a meander inductor. Due to the enhanced inductive coupling between neighboring turns, spiral inductors (Figure 10.1d) allow a larger inductance/unit area, resulting in increased performance through reduced parasitic effects compared to single-layer configurations (layouts a, b, and c). Solenoid inductors (layout e) may also be integrated, although the three-dimensional (3-D) structure is difficult to realize using conventional planar technology.

10.2 INDUCTOR BEHAVIOR AND PERFORMANCE PARAMETERS

193

(a)

(b)

(c)

(d)

(e)

Figure 10.1 Layout examples of integrated inductor (a), transmission line inductor, (b) loop inductor, (c) meander inductor, (d) circular spiral inductor (the layout parameters are also indicated), and (e) solenoid inductor.

Spiral inductors require a multilayer process for the realization of the over- or underpasses to connect the inner part of the spiral inductor to the outside. In the following, we will mainly focus on transmission line inductors and spiral inductors. The loop inductor can be considered as a special case of the spiral inductor with less than 1 turn. The solenoid inductor will also be briefly discussed. Typical inductance values for RF applications in the 1 to 5 GHz range cover the range of 500 pH up to 5 nH, although values up to 10 nH may also be used. The maximum frequency at which an inductor may be used is its resonance frequency

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which is, in turn, determined by material and layout parameters. When the inductor is used as an RF biasing choke, it is used at the resonance frequency. In most other applications, such as filters, matching networks, resonators, etc., the inductor is used below its resonant frequency. In resonator applications, a variable capacitance is usually placed in parallel/series with the inductor. 10.2.2 Inductor Operating Principles An inductor is a passive electronic component that stores energy in the form of a magnetic field. It is of primary concern for time-varying problems. To understand the inductors operating principle, one may first consider the simple case of a transmission line inductor (Figure 10.2a): when the conductor is carrying a current I flowing in the direction into the page, indicated by the symbol , a magnetic field H is created as illustrated in Figure 10.2a. The magnetic field vector H is related to the magnetic flux density vector B by B = H. Here, the permeability is a property of the medium. The inductance L is defined in terms of flux linkage [28] by 1 L= I

B dS

(10.1)

where the surface S must be specified. Consider, for example, the loop of wire shown in Figure 10.2b. The current I produces a magnetic flux in the hatched area S bounded by the loop. Some of the flux produced by the current I is also inside the wire itself. It is convenient to separate the inductances related to these two components of flux and call them, respectively, external inductance and internal inductance. The self-inductance of a wire is the sum of the external and internal inductance. For high frequencies, there is not much penetration of the fields into the conductors, hence, the external inductance is the main contribution to the self-inductance. The mutual inductance M is defined as the inductance arising from the induced voltage in one circuit due to the current flowing in another circuit [28]. The mutual

(a)

(b)

Figure 10.2 (a) Relation between a current in a conductor and the resulting magnetic field vector H. (b) Loop of wire; hatching shows the surface used for calculation of the external inductance.

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195

inductance may be calculated by finding the magnetic flux 12 linking one circuit related to the current in the other circuit. Thus, for two circuits 1 and 2, we obtain

12 M12 = = I2 I2
S1

B dS

(10.2)

where B2 is the magnetic flux arising from current I2 and integration is over the surface of circuit 1. By reciprocity, M21 = M12 for isotropic magnetic materials, so the calculation may be made with the inducing current in either circuit. A vertical cross section of a spiral inductor is given in Figure 10.3a: the currents on the right-hand side flow into the page, the currents on the left hand side flow out the page, as indicated by the symbol . In a first approximation, the magnetic fields associated with the current in each of these conductors add constructively, thereby resulting in a large inductance per unit area. The inductance further increases by the inductive coupling between the different coils (mutual inductance) (see also Section 10.3.2.3). By applying the same principle to the meander inductor shown in Figure 10.1c, one can understand that the overall inductance/area ratio for this type is lower than for the spiral inductor because the magnetic fields in between two closely spaced lines do not add constructively. Hence, the mutual inductance between two closely spaced lines is not constructive. Magnetic fields also interact with conductive materials, such as conductors or low-resistivity dielectrics, hereby giving rise to eddy currents. This effect needs to be understood since it limits the performance of spiral inductors. Assume that conductor 1 in Figure 10.3b is carrying a current I1 flowing in the indicated direction. On the left-hand side of the conductor, this current has an associated magnetic field density B1, oriented perpendicular to the page, in the direction coming out of the page. The field B1 also crosses conductor 2. According to the law of FaradayLenz, an electrical field is magnetically induced in conductor 2, thereby generating circular eddy currents Ieddy. The direction of these eddy currents is such that they oppose

(a)

(b)

Figure 10.3 (a) Cross section of a spiral inductor indicating the direction of the current and the resulting magnetic field. (b) Creation of eddy currents in conductors due to the presence of a varying magnetic field.

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the original change in magnetic field. So the magnetic field density Beddy, resulting from the eddy currents, has a direction flowing into the page. Eddy currents manifest themselves as skin and proximity effects [29]: In the case of the skin effect, the time-varying magnetic field due to the current flow inside the conductor induces eddy currents in the conductor itself. The proximity effect takes place when the conductor is under the influence of a time-varying magnetic field produced by a nearby conductor carrying a time-varying current, as shown in Figure 10.3b. In this case, eddy currents are induced in the first conductor, whether or not it carries current itself. It can be easily understood that eddy currents flowing in a material with finite conductivity will result in an increase of the AC resistance. The distribution of the eddy currents depends on the geometry of the conductor and its orientation with respect to impinging time-varying magnetic fields. The most critical parameter pertaining to eddy current effects is the skin depth , defined in Equation 10.3, where and are the permeability and conductivity of the used material and f is the frequency.

1 f

(10.3)

The skin depth expresses the depth of penetration by the electric current and magnetic flux into the surface of a conductor at high frequencies. Hence, at high frequencies, the current can be regarded as flowing only at the surface of the conductor (rather than a homogenous distribution) up to a depth . The severity of the eddy current effect is determined by the ratio of the skin depth to the conductor thickness: the eddy current effect is negligible only if the skin depth is much greater than the conductor thickness. When referring to Figure 10.3a, one can understand that eddy currents are generated in every turn of the spiral inductor as every conductor shown in Figure 10.3a is under the influence of the magnetic field created by itself as well as the neighboring turns. The nature of eddy currents, explained above, also clearly illustrates the influence of a conductive material (e.g. a solid metal plane or conductive dielectric) present directly underneath the inductor. This will be discussed in more detail in Section 10.2.7.4. 10.2.3 Equivalent Circuit The equivalent circuit of a spiral inductor, valid for an inductor on a low-resistivity substrate (e.g., lightly doped silicon) is given in Figure 10.4a [15, 2934]. One may observe that, besides the primary inductance LS, several other components are present that are considered parasitic elements. They occur due to the nonideal behavior of the inductor: nonzero length, conductive and dielectric losses, etc. The location of these parasitic elements for a microstrip-based circular spiral inductor with the coils separated from the lossy Si by a thin low-loss dielectric is shown in Figure 10.5.

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197

(a)

(b) Figure 10.4 Lumped element spiral inductor model for (a) low-resistivity substrates, (b) high-resistivity substrates.

For high-resistivity substrates, such as alumina, glass, or quartz, RgL is very large and may be neglected. The capacitances CL1, CL2, and CL3 may then be replaced by a single capacitance CGL (similar for CGR and RGR). The resulting model is given in Figure 10.4 (b). When the substrate has a very low resistivity, eddy currents are induced in the substrate due to the penetration of the inductors magnetic field, as outlined in Section 10.2.2 [35]. The direction of this induced current is such that it opposes the original change in magnetic field. So the eddy currents flow in a direction opposite to the current in the conductor, thereby increasing the losses and decreasing the overall inductance. The substrate currents may be considered to flow in an imaginary coil in the substrate underneath the inductor. To account for this, an inductance coupled to the primary inductance LS and resistance can be added to the model to describe the additional losses and the loss in series inductance [36]. More information on the effect of substrate resistivity on the inductor performance may be found in [37].

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Low-K dielectric

Substrate

Ground

Figure 10.5 Cross section of a circular spiral inductor on a low resistivity substrate, illustrating the location and nature of the parasitic elements. RS represents the series metal losses in the spiral coils. Cfb represents the capacitive coupling in between the turns and the coupling between coils and over/underpass. RgL and RgR represent substrate losses, stemming from the penetration of the inductors electric field into the substrate. CL and CR represent the capacitances to ground: for an inductor on a low resistivity substrate, CL2 is the oxide capacitance (separating the spiral inductor and the low resistivity substrate), whereas CL3 is the silicon substrate capacitance.

A number of variations on the model shown in Figure 10.4a exist: inductances may be added at the input and output to represent the feeding lines, the feedback capacitance is omitted [38], capacitances CL1 and CR1 may be omitted if there is no ground plane in the plane of the spirals above the lossy substrate [29, 3133], capacitances CL3 and CR3 are sometimes omitted [15], and a resistance is also sometimes put in between CL2 and CR2 [39]. 10.2.4 Extraction of the Equivalent Circuit Parameters For a high-resistivity substrate, one can easily extract the equivalent circuit parameters from the components Y parameters as shown in Equation 10.4: 1 1 RS = Re ; LS = Im ; Y21 Y21 Im(Y11 + Y12) Im(Y21 + Y22) CGL = ; CGR = ; = 2f (10.4)

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The information in Y21 does not allow a unique determination of RS, LS, and Cf b because there are three unknowns with only two equations. Extracting the inductance value from measurements at the lowest frequencies, where the influence of Cf b is negligible, may solve this. The feedback capacitance Cf b can then be determined either from the resonance behavior of Y21 or by an optimization procedure. As reported in [40], the feedback capacitance can become negative when an optimization procedure is used due to the distributed nature of the spiral inductor; however, the capacitance of the lead-out bridge is usually dominant such that positive values are obtained. The relation between the feedback capacitance and the resonance frequency of the component is given in Equation 10.5. Here fres1 and fres2 are the resonance frequencies of the inductor with port 2 and port 1, respectively, connected to ground. 1 1 fres1 = ; fres2 = 2 L (CG L + Cfb ) 2 L (CG R + Cfb ) (10.5)

The result of the above extraction, for a MCM-D spiral inductor (the technology is described in section 10.4.3) with layout parameters (see Figure 10.1d) N = 2.5, Wcoil = 30 m, Scoil = 20 m, Rin = 100 m, and Dout = 200 m is shown in Figure 10.6a. At low frequencies, one may note that the extracted series inductance slightly decreases as the conductors reach the skin-effect range. At high frequencies, the extracted inductance increases due to the parallel resonance with Cf b. After the resonance of Y21, the extracted value becomes negative. For the ground capacitances CGL and CGR, a frequency range is found at which constant values can be extracted. The extracted resistance increases with increasing frequency from its DC value due to eddy currents and usually has a ripple at higher frequencies. The short-to-open resonance frequency of the above described spiral inductor is located at 13 GHz. Above this frequency, the input impedance of the spiral inductor becomes capacitive, which limits the use of the inductor in most applications. Due to the asymmetry of the spiral, the outer ground capacitance CGL, associated with the outer turns, is larger than the inner ground capacitance CGR, associated with the inner turns, causing a difference in the parallel resonance frequencies. Although the spiral itself shows multiple resonances, the lumped equivalent circuit has only one resonance, causing a deviation between the measurements and the simulation at higher frequencies. Additionally, at the highest frequencies, the dimensions of the spiral become comparable to the wavelength such that a distributed approach has to be used in order to correctly model the behavior. The agreement between the measured and simulated performance, using the model in Figure 10.4b, of the above spiral inductor is given in Figure 10.6b. A good agreement up to the resonance frequency (13 GHz) may be observed. When the inductor is to be modeled above the short-to-open resonance frequency, a cascaded version, using two or more stages, of the model shown in Figure 10.4b may be used [4144] to increase the accuracy of the model at higher frequencies.

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(a)

(b) Figure 10.6 (a) Extracted equivalent circuit parameters as a function of frequency. = Ls, = CGR, = CGL. (b) Agreement between measured () and simulated (, ) S parameters using the lumped element model in Figure 10.4b.

10.2.5 Figure of Merits: QL, QLC, FOML The performance of inductors is usually expressed by a quality factor, Q. A thorough understanding of this quality factor is, hence, mandatory. First we will describe the difference between the quality factor Q, used to describe the performance of a resonator, and the quality factor QL, commonly used to describe the performance of inductors.

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10.2.5.1 Quality Factor. An important parameter in the discussion of the performance of spiral inductors is the quality factor, Q [32, 43, 4547], defined as energy stored Q = 2 energy loss in one cycle (10.6)

Equation 10.6 also defines the Q of an LC tank. The definition is fundamental in the sense that it does not specify what stores or dissipates energy. The distinction between an inductor QL and LC tank QLC lies in the intended form of energy storage. For an inductor, only the energy stored in the magnetic field is of interest. Any energy stored in the inductors electrical field as parasitic capacitances is counterproductive. Hence, QL is proportional to the net magnetic energy stored. An inductor is at self-resonance when the peak magnetic and electric energies are equal. Therefore, QL vanishes to zero at the self-resonant frequency and becomes negative above the resonance frequency. QL can hence be expressed as peak magnetic energy peak electric energy QL = 2 energy loss in one cycle and may be obtained from the measurements as Im(Zin) QL = Re(Zin) (10.8) (10.7)

where Zin is the input impedance of the inductor when one side is connected to ground. It should be noted that Equation 10.8 only gives a good approximation of Equation 10.6 at the lowest frequencies, as long as the energy stored in the parasitic capacitances is negligible compared to the energy stored in the inductor. In contrast, for an LC tank, the energy stored is the sum of the average magnetic and electric energies. The Q-factor of an LC-tank at resonance may also be determined as the ratio of the resonant frequency to the 3 dB bandwidth of the resonator [28, 45]. The above described difference in Q-factor is quite often overlooked in the design/optimization of spiral inductors. As we will see in Section 10.5, the Q-factor of the LC-tank is very often important for the performance of the circuit (e.g., narrowband bandpass filters, VCOs, etc.), however, in most publications on spiral inductors, only the QL factor is considered. The two definitions are however different: Equation 10.7 may become negative, whereas equation 10.6 does not. 10.2.5.2 Mathematical Treatment of the Q-factor QL. To discuss the QL factor of a spiral inductor, it is more convenient to reorganize the circuit shown in Figure 10.4a to the form of Figure 10.7a, as the frequency-dependant parameters CLP, CRP, RLP, and RRP can be directly extracted from the Y parameters of the component. The relation between CLP, RLP, and CL1, CL2, CL3, and RGL (Figure 10.4a) is given in Equations 10.9 and 10.10.

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(a)

(b)

Figure 10.7 (a) Reorganized lumped-element spiral inductor model of Figure 10.4a. (b) Equivalent circuit if one port of the model shown in Figure 10.7a is connected to ground.

1 RGL(CL2 + CL3)2 RLP = + 2 2 2CL CL 2RGL 2

2 1 + 2(CL2 + CL3)CL3R GL CLP = CL1 + CL2 2 1 + 2(CL2 + CL3)2 R GL

(10.9)

(10.10)

The QL factor is calculated with one port shorted to ground. When port 2 is shorted to ground, the model shown in Figure 10.7a reduces to the one shown in Figure 10.7b. It can be shown [32] that the QL factor of the inductor can now be written as

LS RLP R2 S (Cf b + CLP) 1 2LS (Cf b + CP) (10.11) QL = 2 RS RLP + [(LS/RS) + 1]RS LS

LS QL = (substrate loss factor)(self-resonance factor) RS

where LS/RS accounts for the magnetic energy stored in the inductance and the ohmic loss in the series resistance. The second term in Equation 10.11 is a substrate loss factor representing energy dissipated in the lossy substrate. The last term is the self-resonance factor describing the reduction in QL due to the increase in the peak electric energy with frequency and the vanishing of QL at the self-resonant frequency. The different contributions in QL factor are shown in Figures 10.8 and 10.9 for an inductor realized on a 10 -cm silicon substrate using data from [14]. One may observe that QL is well described by the ratio LS/RS at low frequencies when both degradation factors have values close to unity. As frequency increases, the degradation factors decrease from unity, hereby reducing the QL factor of the spiral inductor. For this specific inductor realized on a 10 -cm Si substrate, the substrate loss factor is dominant up to about 20 GHz. For inductors realized on high-resistivity substrates, the self-resonance factor is dominant as the substrate loss can often be neglected.

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Figure 10.8 QL-limiting factors for an inductor realized on a 10 -cm Si substrate with parameters LS = 1.95 nH, CL2 = CR2 = 180 fF, Cf b = 30 fF, RS = 3.2 , CL1 = CL3 = CR1 = CR3 = 0, and RG = 800 (data from [14]).

Figure 10.9 QL contributions for an inductor realized on a 10 -cm Si substrate with parameters LS = 1.95 nH, CL2 = CR2 = 180 fF, Cf b = 30 fF, RS = 3.2 , CL1 = CL3 = CR1 = CR3 = 0, and RG = 800 (data from [14]).

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In the special case of high-resistivity substrates (where RLP in Figure 10.7 is infinity), the QL factor of the inductor may be written as
2 LS RS (Cfb + CP) QL = 1 2LS(Cfb + CP) RS LS

(10.12)

When the series resistance RS is assumed to be frequency independent, one can show that the QL factor reaches its maximum at a frequency fQmax, given by 1 fQmax = 2

2 1 1 RS 2 3 LS(CG + Cf b) L S

(10.13)

The QL factor becomes zero at a frequency fQ=0 given by 1 fQ=0 = 2

2 RS 1 2 LS(CG + Cf b) LS

(10.14)

which implies the following relation between fQmax and fQ=0: fQmax = f 3 1 (10.15)

Q=0

10.2.5.3 Graphical Interpretation of QL. In the following discussion, the parameters of a MCM-D spiral inductor (the technology is described in Section 10.4.3) with layout parameters N = 2.5, Wcoil = 30 m, Scoil = 20 m, Rin = 100 m, and Dout = 200 m are used as a benchmark. The equivalent circuit parameters are LS = 3.4 nH, CGL = CGR = 40 fF, Cfb = 4 fF, and RS = 0.84 . The variation of QL as a function of RS is shown in Figure 10.10 with RS being frequency independent. It can be seen that RS directly influences the low-frequency slope of QL and the maximum QL factor. The variation of QL for various capacitances to ground is shown in Figure 10.11. One may observe that CG does not influence the low frequency slope of QL because the self-resonance factor is 1. The influence on the inductors QL-factor at the lower microwave frequencies is also limited. The capacitances to ground primarily limit the high-frequency performance, given by the resonance frequency and, accordingly, the maximum QL-factor. It should be noted that increasing Cf b has the same effect on QL as an increased capacitance to ground. The variation of QL for various RG is shown in Figure 10.12 for an inductor realized on a 10 -cm Si substrate (data from [14]; the nominal values are LS = 1.95 nH, CL2 = CR2 = 180 fF, Cfb = 30 fF, RS = 3.2 , CL1 = CL3 = CR1 = CR3 = 0, and RG = 800 ). One may observe that RG does not influence the low-frequency slope of QL (the substrate loss factor 1).

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Figure 10.10 Variation of the inductor Q-factor QL for various RS. Example for an inductor on a high-resistivity glass substrate with parameters LS = 3.4 nH, CGL = CGR = 40 fF, Cf b = 4 fF, and RS = 0.68/0.84/1.0 .

Figure 10.11 Variation of the inductor Q-factor QL for various CG. Example for an inductor on a high-resistivity glass substrate with parameters LS = 3.4 nH, CGL = CGR = 28/40/52 fF, Cf b = 4 fF, and RS = 0.84 .

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Figure 10.12 Variation of the inductor Q-factor QL for various RG. Example for an inductor on a 10 -cm Si substrate with parameters LS = 1.95 nH, CL2 = CR2 = 180 fF, Cf b = 30 fF, RS = 3.2 , CL1 = CL3 = CR1 = CR3 = 0, RG = 8 , 80 , 400 , 800 , 4000 , and 8000 .

It can be noted that decreasing RG lowers the resonant frequency of the spiral. One may also note that the maximum QL factor for RG = 8 is higher than for RG = 80 800 . 10.2.5.4 FOML. As will be shown in section 10.5.5, the quality factor Q of a spiral inductor directly influences the performance of narrowband bandpass filters and voltage-controlled oscillators and is hence a good comparison criterion to compare the performance of several technologies for these applications. The previously discussed quality factors, however, do not take the consumed area into account. For this purpose, one may use another figure of merit, FOML, [11] given by QLLs FOML = Area (10.16)

The FOML will be expressed here in nH/mm2. This figure of merit is, however, less frequently used than the Q and QL-factor to compare the performance of integrated inductors. It generally gives a relatively high priority to the ratio inductance/unit area, thereby giving high values for inductors realized with a large number of turns or with very narrow strips and spaces. 10.2.6 Spiral Inductor Layouts Spiral inductors may be realized in various ways; however, the circular (Figure 10.1d), octagonal (Figure 10.13a), and rectangular (Figure 10.13b) realizations are

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207

(a)

(b)

Figure 10.13 Some layout alternatives to the circular spiral inductor: (a) Octagonal spiral inductor, and (b) rectangular spiral inductor (the layout parameters are also indicated) examples of a CPW-based GaAs MMIC technology.

the most common ones. For mask-making purposes, the octagonal and rectangular realizations are preferred as they only require a limited number of points. For processing reasons, on the other hand, rounded shapes are preferred since sharp angles and corners create stresses in thin films. The influence of the inductor layout on the Q-factor was experimentally studied in [48]. It was found that the resistance of circular and octagonal-shaped inductors is about 10% smaller than that of a square-shaped inductor with the same inductance value. On the other hand, for the same inductance value, a rectangular realization has a smaller distance between the input and output ports and may, therefore, result in a more area effective solution for some applications. These inductors also have a lower layout complexity. In the paper [48], however, the area consumption is not taken into account. In [49], circular and rectangular inductor layouts, realized using multilayer thin-film MCM-D technology, described in Section 10.4.3, are compared based on the following comparison criteria: Equal area consumption (equal cost): the circular/rectangular cut out from the ground plane is used (Figure 10.14). Equal strip width and slot. Equal DC resistance: this implies that the circular and rectangular coil realizations have an equal total length. Pictures of a circular and rectangular inductor (layouts based on the above described comparison criterion) are shown in Figure 10.14 (equal scale). The layout parameters of some investigated spiral inductor geometries are given in Table 10.1, the explanation of the symbols can be found in Figure 10.1d. Only the layout parameters of the circular realization are given, as the parameters of the

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(a)

(b)

Figure 10.14 Picture of an equivalent circular (a) and rectangular (b) MCM-D spiral inductor (on equal scale).

rectangular realization can be determined using the above-mentioned comparison criterion. The measured performance of the corresponding circular and rectangular inductors is given in Table 10.2. It can be noted that for an equal area and DC resistance, a circular layout consistently results in a higher inductance/unit area, a higher maximum QL-value and a higher FOML; however, the distance between the input and output ports is larger for the circular realization. In some cases, this may also be used as the size-determining fact. 10.2.7 Improving QL by Technology and Layout Parameters As has been explained in Section 10.2.5, the performance of an inductor with a given LS may be improved by modifying RS, RG, or CG. This may be done by changes in the technology as well as by layout optimization. In the following, we will first concentrate on technological improvements. The influence of the layout parameters will be discussed afterwards. 10.2.7.1 Improving QL by Reducing the Series Resistance. From a technological point of view, the most straightforward way to decrease the series re-

Table 10.1 # CL1 CL 2 CL 3 CL 4 CL5 N 2.5 3.5 1.5 2.5 4.5

Layout parameters of the circular MCM-D spiral inductor realizations Wcoil (m) 20 10 20 10 20 Scoil (m) 10 10 10 10 10 Rin (m) 100 50 100 50 100 Dout (m) 50 50 50 50 50 Area (mm2) 0.19 0.10 0.15 0.08 0.29

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Table 10.2 Measured performance of the circular and rectangular MCM-D spiral inductor realizations # CL1 RL1 CL2 RL2 CL3 RL3 CL4 RL4 CL5 RL5 Ls (nH) 2.6 2.3 2.6 2.3 1.1 1.0 1.4 1.2 8.0 6.8 Fres (GHz) 16 17 18 20 28 30 29 31 7.8 8.5 QL @ 5 GHz 36 30.6 26 21 29 26 22 19 40 34 Qmax 56 44 50 38 77 60 67 50 40 34 FQmax (GHz) 10 10 13 13 16 18 18 18 5 5 FOML (nH/mm2) 778 537 1293 853 580 411 1187 774 1097 792

sistance is to use a metal with a high conductivity and a sufficient thickness. This is demonstrated in the following situations: Si technologies in which thin Al layers are replaced by Cu layers [1, 1418]. The fact that LTCC has an advantage over HTCC as high-conductivity metals such as silver and gold can be used [50] since the melting point is well above the temperature at which the LTCC stack is fired. MCM-D (Section 10.4.3), in which thick Cu layers are preferred for the integration of the spiral inductors. When the thickness of the metal layer is increased above a certain threshold, however, a point of diminishing returns will be reached due to the skin effect. Increasing the metal thickness above this value will still result in a decreasing series resistance due to current-crowding effects in adjacent spiral turns which cause part of the current to flow along the edge of the spiral. This may be noted in Figure 10.15, where the simulated QL-factor is given for different Cu thicknesses. The simulations have been performed for an inductor realized on a 20 -cm Si substrate (technology cross section given in Figure 10.30b) using wafer-level packaging techniques (Section 10.4.5). In these simulations, Scoil is equal to the thickness of the Cu (aspect ratio of 1); the pitch in between the turns is kept constant. In this way, the resulting spiral inductors have roughly the same inductance and consume the same area. It can be observed that for the given frequency and layout, increasing the Cu thickness above 10 m only results in minor increases in QL-factor. Experimental results may be found in [17]. Here a spiral inductor with a Cu thickness of 4 m up to 33 m has been realized. Although the skin depth at 2 GHz is only 1.5 m, increasing the Cu thickness from 4 m to 8 m, 16 m, and 22 m increases the maximum QL from 27 to 29, 33, and 35, respectively. When a single thick metal layer is not available, one may improve the performance of the spiral by shunting several metal layers [14]. Naturally, a point of di-

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Figure 10.15 Simulated QL-factor (Ansoft HFSS) as a function of frequency for different Cu thicknesses t = 3 m (), t = 5 m (), t = 10 m (), t = 15 m (), and t = 20 m (). The relation between width and thickness is t + Wcoil = 35 m (Scoil = t), tBCB1 = 20 m. Other inductor layout parameters are N = 2.5 and Rin = 75 m.

minishing returns will also be encountered here. A drawback to shunting several metal layers occurs when low-resistivity substrates are used. When lower-level metals are shunted to the top metal level, the distance between the spiral inductor and the lossy substrate decreases, thereby resulting in increased substrate losses and parasitic capacitances. This limits the high-frequency performance of the inductor, as has been shown in Section 10.2.5. A last remark, which should be made, is that surface roughness also has an effect on the series resistance: the rougher the conductor surface, the higher the losses [51]. 10.2.7.2 Improving QL by Reducing Substrate Losses. For inductors realized on high-resistivity substrates, conductive losses are dominant and substrate losses can often be neglected. For inductors realized on low-resistivity substrates, substrate-induced losses become important, as was illustrated in Figure 10.9. Several ways exist to decrease these substrate-induced losses. A first possibility locally replaces the lossy silicon with a higher-quality dielectric such that the electric and magnetic fields do not penetrate as far into the lossy substrate. One option to obtain this is to increase the thickness of the low-loss dielectric layer in between the spiral inductor and the lossy substrate [1, 14, 16, 23, 5254]. This may be observed in Figure 10.16a where the extracted GLP (= 1/RLP) for two inductors (technology given in Figure 10.30b) are given. Increasing the thickness of the low-k dielectric layer underneath the spiral from 5 m to 16 m significantly increases RLP, thereby reducing the substrate losses.

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211

16 m

(a)

16 m

(b) Figure 10.16 Extracted GLP (a) and CLP (b) for a 2.8 nH inductor realized on a 20 -cm Si substrate (technology described in Figure 10.30b): one with 5 m BCB in between the spiral and the substrate, the other with 16 m BCB.

Another option is to etch away the silicon underneath the inductor, as shown in Figure 10.17a. This may be done in a postprocessing step from the top [19, 20] or the back [21] of the Si wafer. Other possibilities are the creation of an air gap in between the spiral inductor and the substrate by using airbridge technology [22] (Figure 10.17b). A nonexhaustive overview of MEMS-based techniques, which may be used to improve the performance of spiral inductors, may be found in [55]. Finally, one may also realize the spiral inductors using wafer-level packaging techniques [23, 24, 27]. Another way to reduce the substrate-induced losses is the use of metal or resistive ground shields underneath the spiral inductor to terminate the electric field before it reaches the lossy substrate. However, when a full metal shield is put directly below the inductor, one should be careful that it is at a sufficient distance as the inductance decreases significantly due to the negative mutual coupling be-

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(a)

(b)

Figure 10.17 (a) Schematic cross section of an inductor suspended on a thin membrane; the Si underneath the inductor is etched away. (b) Schematic view of a suspended inductor using airbridge technology; regularly spaced studs are used to support the spiral.

tween the spiral and the image currents in the solid ground shield (see also Figure 10.20). Hence, it is better to use a patterned ground shield when only a limited distance can be supplied. The slots in the patterned ground shields should be orthogonal to the direction of the current flow in the spiral to prevent the build-up of image currents. This technique is, for instance, used to improve the performance of spiral inductors integrated on standard Si [32, 56, 57]. A drawback to the use of shields is that they also increase the parasitic capacitances to ground, thereby lowering the resonance frequency of the inductor. This is not a problem as long as the resonance frequency is considerably higher than the maximum frequency of interest. Another technique [58] reduces the eddy currents in the substrate by inserting narrow strips of n+ regions perpendicular to the current flow. Another technique places a substrate contact almost completely around the spiral inductor [59]. This technique aims at reducing RG to zero, thereby making the substrate loss factor equal to 1 as shown in Figure 10.12. 10.2.7.3 Improving QL by Lowering the Parasitic Capacitances to Ground. For nonmagnetic substrates (with r = 1), changing the dielectric constant of the substrate does not influence the series inductance. Lowering the dielectric constant, however, reduces the parasitic capacitances to ground, thereby yielding higher maximum QL-factors as demonstrated previously (Figure 10.11). The limitation introduced by parasitic capacitances to ground is especially large for inductors integrated on low-resistivity substrates, as can be seen in Figure 10.16b where the extracted parasitic capacitance to ground (CLP in Figure 10.7b) is given for an inductor realized on a 20 -cm Si substrate, as described in Section 10.4.5; increasing the thickness of the low-k dielectric separating the spiral and substrate from 5 m to 16 m, decreases the extracted CLP, thereby increasing the resonance frequency and the maximum QL factor. Methods to decrease the parasitic capacitance have been discussed in the previous section. They basically replace the lossy silicon with a higher-quality, low-k dielectric. This can be done by removing the lossy substrate underneath the spiral inductor in a postprocessing step [1921], by creating an air gap in between the spiral

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inductor and the substrate using airbridge technology [22], or by realizing the spiral inductors using wafer-level packaging techniques [2325] that increase the thickness of the dielectric underneath the spiral inductor. Recently, solenoid on-chip inductors such as in Figure 10.1e have been proposed as an alternative solution to minimize both parasitic capacitive coupling to the substrate and inductor area [6062]. However, the 3-D structure of the solenoid inductor is difficult to realize using conventional IC technology as a sufficient distance between the top and bottom turns are required. In addition, it is difficult to combine this with a narrow distance in between the different turns, which requires small vias. The latter results in a decreasing mutual coupling between the turns. Hence, a linear dependence of inductance on the number of turns may be found in practical realizations. 10.2.7.4 Influence of Layout Parameters. In the previous paragraphs, we have primarily discussed the influence of several processing-related parameters on the spiral inductors performance. This section will discuss the influence of the inductors layout parameters. We will primarily focus on a circular layout, although similar conclusions are valid for the rectangular and octagonal layouts. The main layout parameters of a circular spiral inductor are: The number of turns N The width of the coils Wcoil The spacing in-between the coils Scoil The inner radius of the spiral Rin The distance between the spiral inductor and the ground plane (Dout for a CPW-based approach)

As may be expected, the inductance of the spiral inductor increases if one of the parameters N, Wcoil, Scoil, Rin, or Dout is increased while keeping all others fixed. However, not all parameters have a large influence on the series inductance. Increasing N or Rin is most suited to increasing the inductance value. In this respect, it should be noted that the inner turns of the spiral inductor only make a limited contribution to the series inductance; however, they do contribute significantly to the losses [23, 35, 63] due to eddy currents generated in the inner coils. Hence, a higher QL can be achieved by leaving a hole in the center of the inductor. This implies that Rin should not be made too small. The above situation is illustrated in Figure 10.18a, where the measured QL for two realizations of a 2.5 nH inductor are given. It can be noticed that the 2.5 turn realization with a larger Rin has a higher QL-factor compared to the 3.5 turn realization. This is due to the fact that the center of the 3.5 turn realization is very small and almost completely covered with metal. It should also be mentioned that increasing Rin, while keeping all other parameters constant, results in a more or less linear increase of the series inductance, as shown in Figure 10.18b [23, 64].

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(a)

(b) Figure 10.18 (a) Measured QL-factor for two realizations of a 2.5 nH inductor, (N = 3.5/Rin = 25 m; N = 2.5/Rin = 75 m) realized on a 20 -cm silicon substrate. (b) Variation of LS as a function of N and Rin. () N = 1.5, Wcoil = 30 m; () N = 2.5, Wcoil = 5 m; () N = 2.5, Wcoil = 30 m; (+) N = 3.5, Wcoil = 30 m.

Changing either Wcoil or Scoil results in a weak change in series inductance, especially when the pitch remains constant [29]. Widening Wcoil may be used to increase QL; however, a point of diminishing returns will be reached due to eddy currents generated in the coils, and due to the fact that most of the current is located at the edges of the strips [35, 48]. The losses related to eddy currents in the strips may be reduced by making the inner turns slightly narrower than the outer turns: narrow strips optimize the losses in the inner turns, where the magnetic field reaches its maximum, whereas wide strips optimize the outer turns, where

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ohmic losses are predominant [21, 65]. Another possibility is to split the strip into several parallel traces or to change the location of the different traces as was suggested and done in [35, 66]. The distance to the ground plane also has an influence on the spirals performance. When discussing the influence of Dout, it is important to distinguish between a microstrip and coplanar waveguide (CPW) design approach (Figure 10.19). In a microstrip approach, the spiral inductor is realized on the top of the wafer, whereas the ground plane is located below the spirals (usually at the back side of the wafer). Hence, the distance between spiral inductor and ground plane is usually not a design parameter. In a CPW approach, the ground plane is realized in the same plane as the spiral inductor. The influence of the distance to the ground plane for a microstrip- and CPWbased spiral inductor is illustrated in Figure 10.20. It can be noted that as the distance to the solid ground plane decreases, the series inductance decreases while the parasitic capacitances to ground increase. The QL-factor of the spiral, hence, decreases due to a decreasing LS, an increasing CG, and an increasing RS due to the generation of eddy currents in the ground plane. This is also shown in [50] for an LTCC-based spiral inductor. From the above observations, one may conclude that one should not put the ground plane too close to the spiral inductor. Hence, when one is only interested in the inductor performance, it is safe to say that inductors need a sufficient volume of space to allow the magnetic field to be unimpeded by other structures. On the other hand, the distance between the spiral inductor and the ground plane may not be too large for reasons of compactness and cost. Once Dout is larger than a certain threshold (depending on the spirals geometry), increasing it further will not have a drastic influence on the series inductance and QL-factor. When a small area is required, one can reduce Dout while simultaneously increasing N to obtain the same inductance value, thereby introducing additional losses. This implies a trade-off between cost, due to area, and performance. Many variables may, therefore, be optimized in the design of spiral inductors. Different solutions

(a)

(b)

Figure 10.19 Difference between (a) a coplanar waveguide (CPW) approach, in which the coils and ground plane are realized on the same metal layer, and (b) a microstrip approach, in which the ground plane is located at the bottom of the wafer.

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(a)

(b) Figure 10.20 Influence of the distance to the ground plane for a spiral with N = 2.5, Wcoil = 30 m, Scoil = 20 m, and Rin = 100 m. (a) Microstrip configuration () CG, () LS. (b) CPW configuration () CG, () LS. Simulations performed using Agilent Momentum.

will be found when the inductors are optimized for cost, small area, or performance (higher Q and larger area). How to predict the performance of a spiral inductor will be discussed in the next section.

10.3 INDUCTOR PERFORMANCE PREDICTION Predicting the performance of spiral inductors is an area of vast research. A detailed discussion of all modeling approaches is beyond the scope of this work. Hence, we will primarily concentrate on a discussion of the different methods to give some insight into the possibilities and limitations of the different approaches.

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10.3.1 Transmission Line Inductor The strip-type inductor (Figure 10.1a) can be regarded as a transmission line and can be very easily and accurately modeled accordingly. For short lengths (l < g/4), the inductance LS and shunt capacitance to ground CG, such as in the model shown in Figure 10.4b, are given by Equation 10.17, where Zc and g are the characteristic impedance and wavelength of the transmission line, respectively, f is the frequency at interest and l is the physical length of the strip. It may be noted that a high characteristic impedance is required to realize an inductance with small parasitic elements. This usually transfers into a larger separation from the ground plane. Zc 2l LS = sin 2f g

and

1 l CG = tan 2fZc g

(10.17)

To predict the transmission line properties, several approaches may be followed ranging from quasistatic approximations, to 2.5-D method of moment and full 3-D simulations. The performance of CPW and microstrip technologies using a single dielectric can be easily simulated using most commercial design simulators [67]. For multilayer substrates, fast and good results may be obtained using the quasistatic approximation from [68, 69]. 10.3.2 Spiral Inductors Predicting the performance of spiral inductors is more complicated and may be done in several ways: Using closed-form formulas derived using a large number of measurements or simulations. Approximating the performance of the spiral by decomposing the spiral inductor into its constituent elements and calculating the inductance using the Greenhouse algorithm (See section 10.3.2.3). Solving Maxwells equations using 2.5-D or 3-D simulators. The method of moments and the finite element method will be discussed in this respect. Choosing an experimental method by fabricating/measuring a large number of spiral inductors. Which method is preferred depends on the required accuracy, the flexibility of the modeling method, the time required to do a simulation, and the specific use that is being made from the spiral inductor simulation: From a circuit designer point of view, an optimal model should offer high accuracy and a continuous spectrum of inductances, require limited storage capacity, and give insight into the physical behavior of the component; optimizing the inductor in a design should be fast and easy.

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From a technology and component designer point of view, a good model should deliver a priori knowledge of the components behavior, thereby allowing the designer to optimize the technology toward achieving the required performance with regard to quality factor and taking area consumption into account. Closed-form formulas can be readily implemented in commercial simulators, however, they are usually only available for the inductance, usually with limited accuracy, not for the parasitic elements. The Greenhouse method predicts the inductance with reasonable accuracy; however, the parasitic elements have to be estimated by different means. 2.5-D and 3-D simulators are very convenient as they give rise to an unlimited range of inductors. The influence of a technological change on the performance of the spirals, inductors, and parasitic elements can also be easily simulated with good accuracy. A specific drawback is that these methods are relatively time consuming and, hence, less suited for the development of a large range of spiral inductors. Optimizing the layout of the spirals in a design is also difficult, if at all possible. The main advantage of closed-form expressions or expressions based on the Greenhouse method, is that these methods allow one to study the influence of the spirals geometry on its performance, as simulating the spiral only takes a limited amount of time. Naturally, this requires expressions/approximations for all elements of the equivalent circuit. If these are available, one may construct an inductor design space showing the influence of, for example, Wcoil and Scoil on Qmax and LS. One can also easily optimize the performance of the inductor for a given inductance value, frequency, and area. The accuracy of the simulation may not be sufficient for all applications, for example, when narrowband filters are being designed and trimming after fabrication is not available. 10.3.2.1 Measurement-Based Methods. From a design point of view, measurement-based methods are very attractive as they offer very high accuracy. They are usually the only way to take into account surface roughness effects, uncertainties in material parameters, planarization effects, etc. However, simply measuring a large range of inductors is relatively time consuming and only offers a limited set of inductors. An additional drawback is that the method does not provide any performance prediction before the component is made. The measured S-parameters are usually fitted to a lumped-element equivalent model, such as the one shown in Figure 10.4. A continuous range of inductances may be obtained by consistently varying one parameter of the spiral inductor such as the inner radius Rin in Figure 10.1d. The equivalent elements of the lumped element model are subsequently expressed as a function of the series inductance. The resulting model can then be easily incorporated into commercial design-software. This approach has been followed in [64], where the equivalent elements of the lumped element model are expressed as a function of the inner diameter of the rectangular CPW-based GaAs MMIC spiral inductors. The above-described procedure gives the designers access to a large range of in-

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ductance values, and the accuracy of the model is excellent. The major drawback is that the inductors themselves are not necessarily optimized for the frequency at interest. One also has to redo this step each time the technology is changed. 10.3.2.2 Closed-Form Inductance Formulas. An accurate model of a spiral inductor requires that the primary inductance, as well as the parasitic elements, are known. Exact closed-form formulas for spiral inductors do not exist as the component layout is far too complex. Closed-form formulas for some simplified structures, however, do exist, for example, the static self-inductance for a microstrip line with rectangular cross section given by [70] 2l 0l L = ln 1 2

2 2

(10.18)

25 1 ln = ln(2c) 12 6

w w t t ln 1 + + ln 1 + t w w t w 2 w t t + arctan + arctan 3 t w w t
2 2

(10.19)

w2 + t2 c = 2

(10.20)

where w is the width, t the thickness, and l the length of the microstrip line section. The formulas given above do not consider the inhomogeneous and frequencydependant current density over the cross-section of the conductor as predicted by skin-effect theory. For two coupled straight thin films of width w, length l, and zero metallization thickness, the mutual inductance for a certain spacing s between the lines can be analytically expressed as [70]

l l 2 M = [F(s/l) + F((2w + s)/l) 2 F((w + s)/l)] 4 w

(10.21)

1 q3 1 F(q) = q2 ar sinh + q ar sinh(q) + (1 + q2)3/2 q 3 3

(10.22)

The above formulas may be used to calculate the inductance of a rectangular spiral inductor using the Greenhouse method, discussed in the next section. Recently, several closed-form formulas have been presented (primarily targeted on Si-based technologies) that may be used to predict the performance of spiral inductors [29, 33, 34, 39, 7075]. Some methods rely on closed-form expressions for the inductance, whereas others use the Greenhouse method (explained in the next section) [29, 70, 73] to estimate the value of the inductance. Only a limited number

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of models give closed-form expressions for all parasitic elements. Most do not specify the parasitic elements, or use a number of measurement-based terms to obtain good accuracy. It should be noted that most expressions primarily target rectangular spiral inductors realized in planar technologies. Closed-form expressions for inductors realized in three dimensions are not available. 10.3.2.3 Greenhouse Method. The foundation for computing the inductance is built on the concepts of the self-inductance of a wire and the mutual inductance between a pair of wires. The method of Greenhouse [76] computes the inductance of planar rectangular spirals by summing the self-inductance (Li) of each wire and the positive and negative mutual inductance (Mij) between all possible wire segment pairs. The mutual inductance between two wires depends on their angle of interconnection, length, and separation. The current flow directions in the wires determine the sign of coupling: positive if the currents in the two wires are in the same direction, and negative for opposite currents. In this way, we obtain L = Li +
i=1 N N1

i=1 j=i+1

2Mij

(10.23)

Hence, circular and rectangular spiral inductors are modeled by breaking up the inductor into segments, which are straight lines in the case of the rectangular spiral inductor (Figure 10.21a) and circular one-turn elements [73, 7781] in the case of the circular spiral inductor (Figure 10.21b). For the circular case, it is assumed that the width Wcoil and spacing Scoil of the concentric ring model are identical to those of the spiral inductor. The overall dimension of the concentric ring model may be defined by two criteria [73]:

(a)

(b)

Figure 10.21 Greenhouse method. (a) Decomposition of a square spiral inductor into interacting parallel segments. (b) Approximation of a circular spiral inductor into a 2-D axisymmetric model.

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1. The perimeter of every circular loop must equal the perimeter of every turn of the spiral. 2. The area of every loop must be the same as the average area of every spiral turn. Choosing one or the other depends on the geometry, basically on the value of the pitch. For instance, for small pitches the first criterion would give a better description, whereas for large pitches it is better to use the second one. In addition to the modeling method described above, the inductance of the rectangular spiral inductor has also been modeled by treating the spiral as a network of single and coupled transmission lines [82, 83]. 10.3.2.4 Solving Maxwells Equations: Method of Moments. Momentum is an example of a commercial solver based on the method of moments [84, 85], able to compute the S-parameters of arbitrary shapes in multilayered circuits by solving mixed potential integral equations in the spatial domain. To simulate a structure, one first defines the dielectric layer build-up; all specified dielectrics are assumed to be infinite in the XY-plane. Metal planes can be drawn in between these dielectrics in strip or slot form. In the first case, metal is only present when drawn; in the second case, metal is assumed to be everywhere in between the two dielectrics except in the slots. The different metal planes can be connected to one another using vias. Only vertical currents can be accounted for in the vias, thereby giving rise to the name 2.5-D simulator: the simulator can account for XY-oriented currents in the metal planes and for Z-currents in the vias. Once the substrate is defined, the Greens functions of the substrate, which can consist of an arbitrary number of signal and connecting vias layer, are calculated. To solve the structure, a planar mesh consisting of both rectangular and triangular cells is generated. The calculation time mainly depends on the complexity of the structure and substrate and the density of the mesh. An example of a substrate and mesh definition is shown in Figure 10.22. A variety of components can be simulated: simple structures such as transmission lines, BCB capacitors, and spiral inductors, and more complex structures such as bandpass filters, matching networks, and Lange couplers. One of the main limitations of this method is that the conductor thickness is not accurately accounted for. Metal losses are calculated when drawn in strip form, however, it is assumed that the metal thickness is sufficiently larger than the skin depth. For the slot mode, conductive losses are neglected. The accuracy of CPW-based simulations is generally very good, as can be noted in Table 10.3, where the measured and simulated equivalent circuit parameters for circular spiral inductors, realized in a multilayer MCM-D technology (technology described in Section 10.4.3) are given. It can be seen that very good accuracy can be obtained. As the technology is CPW-based, a slot-based simulation approach has been used. 10.3.2.5 Solving Maxwells Equations: Finite Element Method. An example of a commercial 3-D simulator is Ansoft HFSS. It is based on the finite ele-

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(a)

(b) Figure 10.22 (a) Layer definition example for a technology using two metal layers (one strip-based, one slot-based). (b) Layout and mesh example of a circular spiral inductor: the inductor is drawn in slot form, whereas the vias and overpass are drawn in strip form.

Table 10.3 Comparison between equivalent circuit parameters that are measured and simulated in momentum for circular spiral inductors realized in a multilayer, CPW-based MCM-D technology Geometry _____________________________ Wcoil Scoil Rin Dout N (m) (m) (m) (m) 0.5 1 1.5 2.5 4.5 1.5 30 30 30 30 30 20 20 20 20 20 20 20 100 100 100 100 100 100 200 200 200 200 200 50 Measurements _____________________ Ls CgL CgR (nH) (fF) (fF) 0.65 1.12 1.55 3.36 10.08 1.18 22.1 27.6 31.2 42.3 64.9 28 21.4 28.1 31.1 37.5 49.9 25.5 Momentum ___________________ Ls CgL CgR (nH) (fF) (fF) 0.67 1.12 1.58 3.33 10.42 1.21 22.8 31.6 34.3 45.5 71.8 27.3 22.8 30.0 34.8 40.5 51.7 26.1

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ment method [86, 87]. It uses volume meshing and is appropriate for truly 3-D problems. In contrast to 2.5-D simulators, it can accurately account for vertical currents that occur when large vias and thick metal layers are used. The dielectric layers can also be drawn with finite dimensions. 3-D simulations are generally slower than simulators based on the method of moments and are hence more suited for structures with small complexity. The calculation time depends mainly on the overall size of the structure and the density of the mesh that is required to obtain accurate results; however, 3-D simulations may be used to predict the performance of spiral inductors [88]. A typical layout of a circular spiral inductor is shown in Figure 10.23a, in which

(a)

(b) Figure 10.23 (a) Layout of a circular spiral inductor in Ansoft HFSS; a full 3-D layout of the structure is drawn. (b) Simulated () versus measured S11 () and S21 () of a circular spiral inductor realized on a 20 -cm Si substrate using wafer-level packaging techniques.

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a fully 3-D structure is drawn. The obtained agreement between measured and simulated S-parameters for a 2.5 turn circular spiral inductor realized on a 20 -cm Si substrate (technology cross section given in Figure 10.30b) is shown in Figure 10.23b. A good agreement can be observed. The Q-factor can also be very well predicted.

10.4 INTEGRATED INDUCTOR EXAMPLES In the following, several approaches for integrating spiral inductors are discussed. Examples of on-wafer Si, GaAs MMIC, as well as system-in-package solutions based on MCM-D or LTCC will be described. Some information on inductors integrated on-chip using postprocessing techniques will be also given. 10.4.1 Inductors Integrated on 1020 -cm Si Substrates Inductors integrated in todays typical silicon processes suffer from low Q-values as they typically use an Al/Cu metallization to pattern the spiral and underpass, and the lossy substrate also significantly reduces the high-frequency performance. Hence, a lot of work is being done to improve the performance of on-chip Si-spiral inductors. Techniques to achieve this have been discussed at length in Section 10.2 and include, among others, replacing Al by Cu, increasing the thickness of the metal, interconnecting several metal layers, increasing the thickness of the dielectric underneath the spiral inductors, and use of resistive and conductive ground shields. Typical inductors are realized using relatively narrow strips and slots (especially when compared to off-chip realizations) as cost-per-unit area is relatively high. A cross section of a silicon technology [16] is given in Figure 10.24. Three Al metal layers are used. The top is a 4 m thick Cu layer separated from the standard backend layers using a 2 m intermetal dielectric (SiLK from DOW Chemical). The measured performance of the spiral inductors is given in Figure 10.25 [44]. When the 3 nH inductor is realized on the thin Al layers, a low QL value of 5 is obtained. Realizing the inductor on the 2 m Cu layer increases QL,max to 17, whereas the 4 m Cu layer increases the maximum QL-factor to 24. The inductor has a total length of 2900 m, Wcoil = 18 m, Scoil = 2 m, and an inner diameter of 83 m. 10.4.2 GaAs MMIC Inductors In MMIC design, cost-per-unit area is high, hence, the inductors are optimized primarily for cost, so the inductors are realized using relatively narrow strips and slots, especially when compared to off-chip solutions. An example of a technology cross section used for CPW-based GaAs and InP MMICs is shown in Figure 10.26a. Next to the spiral inductors, other passive components such as resistors and capacitors are also integrated. In a CPW-based MMIC technology, airbridges are often available. In this case, it is possible to suspend the spiral inductor on airbridges, thereby reducing the parasitic capacitances to ground. An example is shown in Figure

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225

Figure 10.24 m Cu layer.

Cross section of a three-metal level Al back-end layer. The top layer is a 4

(a)

(b)

Figure 10.25 Measured performance of inductors realized on a 20 -cm Si BiCMOS technology [44]. (a) Increase of the QL factor as the Cu thickness is increased from 2 m to 4 m. (b) Increase of the QL factor obtained by replacing the thin Al layers (standard TLM) by 4 m Cu.

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(a)

(b) Figure 10.26 Spiral inductors integrated in a CPW-based MMIC technology. (a) Technology cross section. (b) Picture of a suspended inductor using airbridge technology.

10.26b. The measured performance of a number of CPW-based rectangular spiral inductors is given in Table 10.4. For the measurements, the metallization was 2.1 m Au. An underpass is used to connect the inner part of the spiral to the outside. As this layer is very thin, the underpass makes a relatively high contribution to the overall series resistance of the spiral inductor. The QL-factors given above may be improved by increasing the thickness of the metal, e.g., in [48] a 7.4 m thick metal layer is being used, whereas in [89], multiple metal layers are connected in 3-D MMIC technology to decrease the series resistance. One may also vary Wcoil as a function of the number of turns to improve the performance, as was done in [65]. 10.4.3 MCM-D Inductors In this section, we describe the measured performance of spiral inductors integrated in a multilayer MCM-D technology on glass. A cross section of the technology is

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Table 10.4 Performance of CPW-based rectangular spiral inductors integrated on a GaAs MMIC substrate LS (nH) 0.50 0.50 0.95 1.36 1.54 1.63 2.03 2.96 QL,max 24.4 28.2 28 9.2 13.9 18.3 12.3 11 Freq (GHz) 19.7 20.3 12.6 7.9 7.9 7.9 5.9 5 N 1.5 1 1.5 2.5 2.5 2.5 2.5 3.5 w (m) 8 10 10 10 10 10 10 10 s (m) 6 10 10 10 10 10 10 10 Gap (m) 30 30 50 10 30 50 30 30 S0 (m) 120 160 200 200 200 200 240 240 Area (mm2) 0.035 0.053 0.096 0.053 0.073 0.096 0.096 0.096

Note. Freq is the frequency at which QL reaches its maximum value QL,max. The layout parameters are explained in Figure 10.13b.

given in Figure 10.27. For the realization of the spiral inductors, three different metal levels are available. The middle one, metal2, is used for the realization of the spiral inductors as this layer has the highest conductivity. Overpasses on metal3 are used to connect the inner part of the spiral to the outer part. The spiral inductors are only one passive component that may be integrated, along with TaN resistors (25 /) and capacitors (interdigital, BCB and Ta2O5). A low-loss glass substrate is usedAF45 from Schott, with r = 6.2 and tan = 8.104. The metal layers are separated by two 5 m thick BCB layers (Cyclotene from DOW Chemical), with r = 2.65 and tan = 5.104. More detailed information on the technology and overall design philosophy may be found in [4, 9092]. A CPW-based technology is being used, as this prevents the need for substrate vias and backside metallization. Thin-film microstrip, in which a ground plane is realized on the top of the wafer, on metal-1, is also quite often used in thin-film technologies [93], however, for the realization of the spiral inductors, this ground plane has to be opened underneath the spiral inductors; the presence of a ground plane directly underneath the spiral inductors would result in the creation of large eddy currents in the ground plane, thereby reducing the series inductance and increasing the series resistance (see Figure 10.20). Hence, from the inductor design

Figure 10.27

Cross section of IMECs MCM-D technology.

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point of view, a CPW-based technology and a thin-film microstrip based technology are more or less the same. For flexible circuit design, layouts optimized for either low cost or high performance have been developed. For the first case, minimal strip and slot dimensions (5 to 20 m) are used, whereas for the second, wider strips and slots, with values up to 100 m, have been supplied. The high-performance inductors also have a larger Dout. Integrated MCM-D spiral inductors are shown in Figure 10.28. The measured performance of the MCM-D inductors is illustrated in Table 10.5. It can be seen that the quality factors QL may go above 100 at 10 GHz for inductances less than

(a)

(b) Figure 10.28 A spiral inductor realized in MCM-D. (a) The layout parameters and inductor reference planes. (b) An inductor with 5 m wide slots.

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Table 10.5 N 0.5 1.5 2.5 3.5 4.5 5.5 1.5 1.5 1.5 1.5 1.5 0.5 1.5 Wcoil (m) 30 30 30 30 30 30 30 30 50 77 100 20 20

Measured performance of the integrated MCM-D spiral inductors Rin (m) 100 100 100 100 100 100 100 100 100 100 100 100 100 Dout (m) 200 200 200 200 200 200 200 200 200 200 200 50 50 Ls (nH) 0.65 1.55 3.36 6.15 10.08 14.77 1.72 1.84 1.62 1.72 1.8 0.35 1.13 Qmax >200 110 61 48 40 37 93 100 130 90 90 >200 120 Freq @ Qmax Fres (GHz) (GHz) 18.9 13.0 6.3 4.4 2.8 2.0 12.0 10.0 10.0 8.5 6.8 37 18 46.3 22.5 13.0 7.8 5.3 4.0 21.3 19.8 19.8 16.3 14.5 (64) 29 Area (mm2) 0.395 0.515 0.650 0.801 0.967 1.149 0.594 0.679 0.650 0.857 1.056 0.113 0.145

Scoil (m) 20 20 20 20 20 20 40 60 20 20 20 20 10

Note: Fres is the resonance frequency. The area of the circular cutout from the ground plane is also given. The other geometrical parameters are outlined in Figure 10.1d.

1.8 nH. Naturally, for inductors with larger values, the quality factor drops due to the increased losses and capacitive coupling between the turns but a good performance is still achieved; for example, an inductor of 18 nH still has a QL of 38 at 2 GHz, an inductor of 40 nH still has a QL of 29 at 1 GHz. The QL-values are, therefore, significantly higher than those reported on silicon or GaAs. It should be noted that the technology described here uses a 3 m thick Cu layer, however, Cu thicknesses of 5 m with critical dimensions of 5 m have also been demonstrated [23, 49]. This further increases the maximum QL-factor, especially for applications in the lower GHz range. The high quality factors obtained in the MCM-D technology may be attributed to several factors: In the MCM-D technology, high-conductivity Cu metallizations are used together with high-quality dielectrics. The lower dielectric constant of the glass and BCB as compared to GaAs- and Si-based solutions also help to increase the maximum QL-factor by reducing the parasitic capacitances to ground. The available area (cost) also determines the achievable performance of the inductors as a larger area allows one to decrease the number of turns to realize a specific inductance. It is also possible to increase Wcoil and Scoil. In this respect, MCM-D has a considerable advantage over GaAs- and Si-based inductors. MCM-D inductors may also be integrated on a variety of substrates such as low[88, 94, 95] and high-resistivity [11, 96] silicon, alumina [97], etc. For the first, a 10

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m thick Cu layer is combined with a 25 m thick oxidized porous silicon [98] layer, thereby resulting in high Q-factors on a low-resistivity substrate.

10.4.4 LTCC In LTCC, multiple dielectric and metal layers can be used, thereby allowing the integration of spiral inductors. High quality factors may be obtained [5, 50, 99101], however, primarily at low RF frequencies. This is mainly due to the quality of the materials, the large tolerances on dimensions of the screen-printed conductors, the minimum dimensions, and the vertical shrinkage during firing. Unlike HTCC, LTCC processes allow the use of high-conductivity metals such as silver and gold since the melting point of these metals is well above the temperature at which the LTCC stack is fired [50]. As discussed previously, this improves the performance of the integrated inductors. Miniaturization may be achieved by exploiting the three-dimensional capabilities of the technology, as illustrated in Figure 10.29. However, this 3-D configuration causes large modeling difficulties, hereby severely complicating the use of LTCC in practical circuit design. Photolithographic techniques may be used to reduce the accuracy problems [102]; however, this reduces the cost benefits over competing technologies. In [5, 50], results on integrated spiral inductors in multilayer LTCC are reported. A 20 layer LTCC process using 90 m thick Dupont 951AT tapes has been used with dielectric constant 7.8. Typical metallizations are either 5 m electroplated gold (surface and back side) and 6 m silver or silverpalladium alloy. Conventional designs require a minimum of 100 m line widths and slots, although 25 m is possible utilizing a photoimageable process. The reported spiral inductor performance is given in Table 10.6. In [50], it has been mentioned that increasing the height above the ground plane may increase the QL-factor further. This, however, will result in larger coupling in between circuits. It can be noted that the inductors in the 14 nH range are realized using a 2-D planar approach, hence, in this case, the 3-D possibilities of the technology do not aid in reducing the size of the integrated spirals. As the minimum dimensions are in the order of 100 m, the overall

Figure 10.29 Schematic diagram of a 3-D helical inductor structure: technology cross section and 3-D view.

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Table 10.6 Type 2-D 2-D 2-D 3-D 2-D 2-D 2-D 2-D N 2 2 2 2 3/4 1/2 3/4 3/4

Measured performance of LTCC-based inductors Wcoil LS (nH) 4.8 6.1 6.7 7.6 1.2 1.4 2.5 3.8 QL,max 37 @ 1.3 GHz 47 @ 1.3 GHz 52 @ 1.3 GHz 36 @ 1 GHz 100 88 70 78 Fres (GHz) 2.9 3.2 3.25 2.1 7.2 8 4.5 4.7

Height (m) 180 360 540 180 180 180 180 180

500 250 250 250

Note: According to [5, 50], height is the distance above the ground plane.

size of the spiral inductors is considerably larger as compared to the MCM-D-based implementations described in the previous section. 10.4.5 Integration of On-Chip Si Inductors Using Wafer-Level Packaging Techniques Another approach to realize high-performance spiral inductors on a Si chip is to perform postprocessing steps on Si wafers [23, 24, 26, 27, 5254]. One possibility is to integrate the spiral inductors in the redistribution layers. This concept is illustrated in Figure 10.30a, where two low-k and low-loss benzocyclobutene dielectric layers with r = 2.65 and tan = 5.104, and a thick Cu interconnect layer are formed on top of the passivation. The thick Cu layer can then be used for integrating the spiral inductors as well as for flip-chip redistribution. An additional advantage is that this method allows one to use contact masks for the realization of the inductors, as opposed to the more expensive Si reticules, thereby reducing costs. Patterned ground shields or substrate contacts to improve the performance of the inductors, as mentioned previously, may be realized in the silicon back-end layers. To characterize the above concept, the layer buildup shown in Figure 10.30b has been realized; substrate contacts and shields have not been used in this case. The measured QL-factor for a 2.5 nH inductor for different Cu and BCB layer thicknesses, separating the spiral and the lossy Si substrate, is given in Figure 10.31. The layout parameters of the inductor are also given there. Split 1 (3 m Cu, 5m BCB) results in a maximum QL-factor of 16 at 1.9 GHz. Increasing the Cu and BCB thickness to 5 m and 16 m (split 3), respectively, increases the QL-factor to 23 at 1.9 GHz, with a maximum QL-factor of 26 at 2.8 GHz. A 5 m thick Cu layer with 8 m BCB (split 2) results in a maximum QL-factor of 23 at 2 GHz. Using MCM-Dbased postprocessing, minimum feature sizes of 5 m are possible for a Cu thickness of 5 m. Increasing the Cu thickness results in a higher slope of the QL-factor at lower frequencies, determined by LS/RS. The small difference in slope between the inductor on splits 2 and 3 can be explained by small differences in the actual Cu thickness.

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(a)

(b) Figure 10.30 (a) Schematic cross section of the inductor above passivation concept; the MCM-D layers are postprocessed on top of passivation. (b) Layer buildup used to characterize the performance of the postprocessed spiral inductors.

Increasing the BCB thickness allows one to reduce the parasitic capacitances to ground, thereby shifting the resonance frequency from 12.5 GHz (split 1) to 15 GHz (split 3). At the same time, the substrate losses are reduced. The maximum FOML for the above mentioned inductors is 210/340 (split 1/split 3). Pictures of spiral inductors realized on top of a five-metal layer Cu back-end (Figure 10.30a) realized at IMEC are shown in Figure 10.32. Substrate contacts are present at the probe tips.

10.5 USE OF INDUCTORS IN CIRCUITS: EXAMPLES In the following, we will describe a number of applications in which inductors are being used. A more detailed discussion of the applications of integrated passives can be found elsewhere.

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USE OF INDUCTORS IN CIRCUITS: EXAMPLES

233

Figure 10.31 QL-factor as a function of frequency for a 2.5 nH inductor with N = 2.5, Wcoil = 20 m, Scoil = 10 m, and Rin = 100 m (area = 0.19 mm2) for different Cu and BCB thicknesses. Split 1: tCu = 3 m, tBCB = 5 m. Split 2: tCu = 5 m, tBCB = 8 m. Split 3: tCu = 5 m, tBCB = 16 m.

10.5.1 Filters The first application in which a high Q-factor is important is integrated filters, especially narrowband bandpass filters. A 5.2 GHz bandpass filter, realized in the MCM-D technology described in Section 10.4.3, and the equivalent circuit are given in Figure 10.33. At the 5.2 GHz design frequency, the two 0.625 nH MCMD inductors have a QL of 127. In the same figure, a comparison between mea-

(a)

(b)

Figure 10.32 Spiral inductors postprocessed on a five-metal layer Cu back end. (a) With postprocessed overpass. (b) Underpass on fifth Cu back end layer.

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(a)

(b) Figure 10.33 (a) Photograph of a 5.2 GHz MCM-D bandpass filter (3 1.5 mm2) using high-Q spiral inductors. The equivalent circuit is also shown. (b) Comparison of measurements (dotted lines) and simulation results (solid lines) of the bandpass filter indicate the influence of reduced Q values on the insertion loss.

surements and simulations of the complete filter are shown. In addition, the graph shows simulation results indicating the influence of a decreasing inductor quality factor. With the high-QL inductor, the insertion loss in the passband is 3 dB at 5.16 GHz. When the QL drops to 35 or 24 at 5.2 GHz (due to an increase in series resistance), the insertion loss of the filter increases to 4.9 dB or 6.2 dB, respectively. It should be noted that the insertion loss of bandpass filters is primarily determined by the Q-factor of the used LC resonators, however, the inductor is

10.5

USE OF INDUCTORS IN CIRCUITS: EXAMPLES

235

usually the performance-limiting factor. The Q-factor of a parallel resonator may be obtained by [45] 1 1 1 =+ Q Qcapacitor Qinductor (10.24)

Note that the Q-factor of the inductor is used in this definition, not the QL-factor. 10.5.2 Voltage-Controlled Oscillators The phase noise of a voltage-controlled oscillator (VCO) is also highly determined by the Q-factor of the used LC tank. In Equation 10.25, it can be seen that the phase noise is inversely proportional to the square of the quality factor Q of the LC tank and the square of the power [103]. Again, it should be noted that the Q-factor is used, not the QL-factor. 1 fosc S Q2 fm

2kT F 1 2 2 PS PQ

(10.25)

From this, one may conclude that the capacitive limitation, which lowers QL, is not necessarily a problem for a VCO: a capacitor is put in parallel with the inductor. If the inductor has a slightly higher capacitance to ground, which results in a lower QL, one only has to put a smaller capacitor to ground in parallel with the inductor. This illustrates that one should be careful when QL is used as a criterion to optimize the performance of the spiral inductors. 10.5.3 Size Reduction Techniques A quarter-wavelength transmission line is a key element in many microwave circuits; however, a straightforward realization requires a large amount of chip area, especially at the lower microwave frequencies. Different size reduction techniques are available to reduce the length of a transmission line with characteristic impedance Zc and electrical length 1 (Figure 10.34). In the lumped/distributed technique, a shorter transmission line is used. This results in a loss in distributed series inductance and shunt capacitance, which is compensated for by using a higher characteristic impedance (to compensate the inductance loss) and adding lumped capacitors to ground (to compensate the capacitance loss) at the edges of the line (Figure 10.34b) [104]. The maximum Zc value that can be obtained therefore determines the achievable size reduction. In the lumped element technique, the transmission line is replaced by the combination of lumped inductors and capacitors. A -equivalent (Figure 10.34 (d)) or T-equivalent circuit can be used. It should be mentioned that the structures are only equivalent at one fixed frequency; hence, reduced-size circuits usually have a more narrow frequency band than the distributed designs.

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(a)

(b)

(c)

Figure 10.34 Example of some size-reduction techniques used to reduce the length of a transmission line section. (a) With characteristic impedance Zc and electrical length . (b) Lumped/distributed technique using shunt capacitors. (c) -equivalent lumped-element circuit.

An example of the above-described approach can be found in [105], where distributed as well as lumped approaches have been implemented. The realized Wilkinson power dividers are shown in Figure 10.35, whereas the measured performance is summarized in Table 10.7. It can be seen that the use of miniature spiral inductors allows one to drastically reduce the size of the circuit (the lumped-element circuit only consumes about 30% of the size of the distributed approach), however, this does not have a significant impact on the circuits performance. So, although the Q-factor of the miniature spiral inductors is lower, the overall circuit performance is more or less the same, and the area is significantly reduced.

(a)

(b)

(c)

Figure 10.35 Different Wilkinson power divider architectures. (a) Distributed design using capacitively loaded high-impedance lines. (b) Lumped realization. (c) Lumped, very compact realization.

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237

Table 10.7 10.35

Measured performance of the Wilkinson power dividers depicted in Figure Figure 10.35 Part (a) (b)
2

(c)
2

Area Insertion loss 25 dB isolation 17 dB return loss

5.52 mm 3.42 dB 6.47.6 GHz 6.37.5 GHz

3.82 mm 3.44 dB 6.67.8 GHz 6.27.6 GHz

1.70 mm2 3.45 dB 6.87.8 GHz 6.77.8 GHz

10.5.4 Coupled Spiral Inductors Coupled spiral inductors employ the mutual inductance in between two neighboring spiral inductors. To increase the mutual coupling, the two spirals may be realized on top of one another (which results in fairly large capacitive coupling) or with alternating coils. Coupled spiral inductors may be used in the realization of baluns. An example of a balun using two coupled spiral inductors is given in Figure 10.36.

10.6 CONCLUSIONS In this chapter, the performance of spiral inductors for RF applications has been discussed. First, the layout and operating principle of inductors has been briefly reviewed. Then the inductors equivalent circuit has been presented, followed by a detailed discussion of the Q-factor, a commonly used figure of merit to describe the inductors performance. We have shown how the performance of the spiral inductor is related to material parameters such as the conductivity of the metals used, the resistivity/loss tangent of the dielectrics used, their respective thicknesses, etc., and design parameters such as inductor type and influence of layout parameters. Ways to improve the performance have also been discussed. Several approaches to predicting the performance of integrated inductors have been described, including

Figure 10.36

Picture of a 5.2 GHz balun using two coupled spiral inductors.

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closed-form formulas, the Greenhouse method, and 2.5-D and 3-D simulations. Next, several examples of inductors integrated in planar technologies such as onchip realizations (Si, postprocessed Si, and GaAs MMICs) as well as system in a package solutions (MCM-D and LTCC) have been given. Finally, we have briefly discussed the use of inductors in circuits.

ACKNOWLEDGMENTS The authors acknowledge the support of E. Beyne, K. Vaesen, S. Brebels, X. Sun, P. Pieters, Y. Baeyens, S. Jenei, and the MCM-D processing team.

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71. C. P. Yue, C. Ryu, Lau, T. H. Lee, and S. S. WOng, A Physical Model For Planar Spiral Inductors On Silicon, In International Electron Devices Meeting, San Francisco, CA, pp. 155158, December 811, 1996. 72. S. Jenei, K. J. C. Nauwelaers, and S. Decoutere, Physics-Based Closed-Form Inductance Expression for Compact Modelling of Integrated Spiral Inductors, IEEE Journal of Solid-State Circuits, 37, 7780, 2002. 73. J. Sieiro, J. M. Lopez-Villegas, J. Cabanillas, and J. Samitier, Accurate Physical Model for Designing RF and Microwave Integrated Planar Inductors, In European Microwave Conference, Paris, France, pp. 5962, October 26, 2000. 74. J. Crols, P. Kinget, J. Craninckx, and M. Steyaert, An Analytical Model of Planar Inductors on Lowly Doped Silicon Substrates for High Frequency Analog Design up to 3 GHz, In Symposium on VLSI Circuits, Honolulu, HI, pp. 2829, June 1315, 1996. 75. P. Li, A New Closed Form Formula for Inductance Calculation in Microstrip Line Spiral Inductor Design, In Electrical Performance of Electronic Packaging, Napa, CA, pp. 5860, October 2830, 1996. 76. H. M. Greenhouse, Design of Planar Rectangular Microelectronic Inductors, IEEE Transactions on Parts, Hybrids, and Packaging, 10, 101109, 1974. 77. R. L. Remke and G. A. Burdick, Spiral Inductors for Hybrid and Microwave Applications, In 24th Electronic Components Conference, Washington DC, pp. 152161, May 1974. 78. R. Rodriguez, J. M. Dishman, F. T. Dickens, and E. W. Whelan, Modeling of Two-Dimensional Spiral Inductors, IEEE Transactions on Components, Hybrids and Manufacturing Technology, 3, 535541, 1980. 79. I. Wolff and H. Kapusta, Modeling of Circular Spiral Inductors for MMICs, In IEEE MTT-S Digest, Las Vegas, NV, pp. 123126, June 911, 1987. 80. S. F. Mahmoud and E. Beyne, Inductance and Quality-Factor Evaluation of Planar Lumped Inductors in a Multilayer Configuration, IEEE Transactions on Microwave Theory and Techniques, 45, 918923, 1997. 81. P. Pieters, K. Vaesen, S. Brebels, S. F. Mahmoud, W. De Raedt, E. Beyne, and R. P. Mertens, Accurate Modelling of High-Q Spiral Inductors in Thin Film Multilayer Technology for Wireless Telecommunication Applications, IEEE Transactions on Microwave Theory and Techniques, 49, 589598, 2001. 82. D. Cahana, A New Transmission Line Approach for Designing Spiral Microstrip Inductors for Microwave Integrated Circuits, In IEEE MTT-S Digest, Boston, MA, pp. 245247, 1983. 83. F. J. Schmuckle, The Method of Lines for the Analysis of Rectangular Spiral Inductors, IEEE Transactions on Microwave Theory and Techniques, 41, 11831186, 1993. 84. R. F. Harrington, Matrix Methods for Field Problems, IEEE Proceedings, 55, 136149, 1967. 85. Agilent Momentum, Manual, Agilent 2000. 86. Agilent HFSS, Manual, Agilent 2000. 87. K. S. Yee, Numerical Solution of Initial Boundary Value Problems Involving Maxwells Equations in Isotropic Media, IEEE Transactions on Antennas and Propagation, 302307, 1966. 88. F. Ling, J. Song, T. Kamgaing, Y. Yang, W. Blood, M. Petras, and T. Myers, System-

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atic Analysis of Inductors on Silicon Using EM Simulations, In Electronic Components and Technology Conference, San Diego, CA, pp., May 2831, 2002. B. Piernas, K. Nishikawa, K. Kamogawa, T. Nakagawa, and K. Araki, Improved Three-Dimensional GaAs Inductors, In IEEE MTT-S Digest, Phoenix, AZ, pp. 189201, May 2025, 2001. G. Carchon, S. Brebels, W. De Raedt, and B. Nauwelaers, Design of Distributed Elements in Ku-band in Coplanar-Waveguide based MCM-D, In Electronic Components and Technology Conference, Las Vegas, NV, pp. 15541559, May 2124, 2000. G. Carchon, S. Brebels, K. Vaesen, P. Pieters, D. Schreurs, S. Vandenberghe, W. De Raedt, B. Nauwelaers, and E. Beyne, Accurate Measurement and Characterization of MCM-D Integrated Passives up to 50 GHz, In International Conference and Exhibition on High Density Interconnect and Systems Packaging, Denver, CO, pp. 307312, April 2628, 2000. G. Carchon, P. Pieters, K. Vaesen, W. De Raedt, B. Nauwelaers, and E. Beyne, MultiLayer Thin Film MCM-D for the Integration of High-Performance Wireless Front-End Systems, Microwave Journal, 44, 96110, 2001. R. G. Arnold, C. C. Faulkner, and D. J. Pedder, Silicon MCM-D Technology for RF Integration, In International Conference on Multichip Modules, Denver, CO, pp. 340344, April 24, 1997. C.-M. Nam and Y.-S. Kwon, High performance Planar Inductor on Thick Oxidized Porous Silicon (OPS) Substrate, IEEE Microwave and Guided Wave Letters, 7, . 236238, 1997. J.-S. Lee, M.-L. Ha, and Y.-S. Kwon, MCM Technology for RF Tunable Band Pass Filters Implemented by Integration of GaAs FETs and Selectively Oxidized Porous Silicon (SOPS), In Electronic Components and Technology Conference, Las Vegas, NV, pp. 426431, May 2124, 2000. L. Zu, Y. Lu, R. C. Frye, M. Y. Lau, S.-C. S. Shen, D. P. Kossives, J. Lin, and K. L. Tai, High Q-Factor Inductors Integrated on MCM Si Substrates, IEEE Transactions on Components, Packaging and Manufacturing Technology, 19, 635643, 1996. P. Pieters and E. Beyne, Spiral Inductors Integrated in MCM-D Using The Design Space Concept, In International Conference and Exhibition on High Density Interconnect and Systems Packaging, Denver, CO, pp. 478483, April 1517, 1998. Y.-H. Xie, M. R. Frei, A. J. Becker, C. A. King, D. Kossives, L. T. Gomez, and S. K. Theiss, An Approach for Fabricating High-Performance Inductors on Low-Resistivity Substrates, IEEE Journal of Solid-State Circuits, 33, 14331438, 1998. D. Heo, A. Sutono, E. Chen, Y. Suh, and J. Laskar, A 1.9 GHz DECT CMOS Power Amplifier With Fully Integrated Multi-Layer LTCC Passives, IEEE Microwave and Wireless Components Letters, 11, 249251, 2001. A. Sutono, A. Pham, J. Laskar, and W. R. Smith, Development of Three Dimensional Ceramic-Based MCM Inductors for Hybrid RF/Microwave Applications, In IEEE Radio Frequency Integrated Circuits Symposium, Anaheim, CA, pp. 175178, June 1319, 1999. J. Muller, High-Quality RF-Inductors in LTCC, In Proceedings of ISHM International Symposium on Microelectronics, Minneapolis, MN, pp. 6065, October 810, 1996. P. Barnwell, Microwave MCM-C Utilizing Low Loss LTCC and Photo-Patterning Processes, Microwave Journal, 42, 1999.

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103. C. T.-C. Nguyen, L. P. B. Katehi, and G. M. Rebeiz, Micromachined Devices for Wireless Communications, IEEE Proceedings, 86, 17561768, 1998. 104. T. Hirota, A. Minakawa, and M. Muraguchi, Reduced-size Branch-Line and Rat-Race Hybrids for Uniplanar MMICs, IEEE Transactions on Microwave Theory and Techniques, 38, 270275, 1990. 105. G. Carchon, W. De Raedt, and B. Nauwelaers, Integrated Wilkinson Power Dividers in C-, Ku- and Ka-Band in Multi-Layer Thin-Film MCM-D, In European Microwave Conference, Paris, France, pp. 171174, October 26, 2000.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 11

MODELING OF INTEGRATED INDUCTORS AND RESISTORS FOR MICROWAVE APPLICATIONS

ZHENWEN WANG, M. JAMAL DEEN, AND A. H. RAHAL

11.1 INTRODUCTION The expanding wireless communications market is one of the driving factors for the increased use of microwave integrated circuits (MICs). With MICs, the size of lumped elements (R, L, C) can be reduced to values much smaller than the signal wavelength so that good performance is obtained at microwave frequencies. In addition, more circuits per unit area can be realized for lower-cost, high-volume integrated microwave systems. Precise modeling of lumped elements is very important for microwave circuit design. Modeling even simple passive elements is complicated at high frequencies because many parasitics contribute to the HF characteristics. The full-wave electromagnetic (EM) analysis techniques can be used to model the lumped elements, with very high accuracy; however, these techniques requires a large amount of computing time. Furthermore, it usually does not provide a clear analysis review of the relation of geometrical dimensions to circuit performance. Although circuit simulators are very fast, the circuit element models utilized in computer-aided-design tools are often inaccurate. Artificial neural network (ANN) based modeling techniques have recently been used to generate parameterized models. ANN can provide highly accurate models, and the size of the model does not grow exponentially with the number of input parameters. However, the training needed to use the model can be very long and it is not always easy to find a good topology because of the number of hidden layers and nodes. Because of this, we explore a different approach using semidistributed equivalent circuit models to represent the passive components. The elements in the equivalent circuit model are physicsbased.
247

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MODELING OF INTEGRATED INDUCTORS AND RESISTORS

11.1.1 Miniature Hybrid Microwave Integrated Circuit (MHMIC) In many microwave technology companies, miniature hybrid microwave integrated circuits (MHMICs) are realized by combining MICs with passive elements. This technique improves manufacturing efficiency, reproducibility, and reliability compared to the traditional method of manufacturing microwave hybrid circuity, since all passive components are constructed during the photolithography process. Monolithic microwave integrated circuits (MMICs) have the advantages of small size, low cost, and high integration, and require very little labor for implementation. However, MMICs are only economical when large production runs are required. Therefore, there remains a large arena of applications in which MMICs are not used because of the price and performance trade-offs [1]. The advantage of the MHMIC approach is its flexibility and its cost advantage for small to mid-sized production runs. The advantages and disadvantages of MHMICs, when compared with MMICs, are listed in Table 11.1 [2]. Passive lumped elements, such as resistors, capacitors, and inductors, are extensively used in MHMICs for impedance matching, DC biasing, load, and many other functions. Figure 11.1 shows typical MHMICs. In addition, vias are extensively used to make good high-frequency connections to the ground plane. 11.1.2 Goals of this Chapter The purpose of this chapter is to present highly accurate models for spiral inductors, thin-film resistors, and interdigital capacitors in MHMIC technology. It will be demonstrated that a semiempirical approach can be implemented to model spiral inductors and thin-film resistors. This approach is based on the characteristics of microstrip line and microwave theory. For completeness, a short overview of the char-

Table 11.1 MHMICs

Advantages and disadvantages of MHMICs MMICs Cheap in large quantities; especially economically efficient for complex circuits Very good reproducibility Highest possible reliability Substrate is expensive Very limited choice of components Very expensive to start up

Simple circuits can be cheaper; automatic assembly is possible Poor reproducibility due to device placement and bond wires Hybrids are mostly glued together, so reliability suffers Substrate is cheap, which allows microstrip and lumped elements to be used abundantly A vast selection of devices and components is available Very little capital equipment is required

11.2

MODELING OF SPIRAL INDUCTORS

249

Resistor Network

Via Hole Spiral Inductor

Figure 11.1

Typical MHMICs.

acteristics of microstrip lines is presented in the Appendix. This is required because analytic expressions for the microstrip line are used either directly or as a starting point for modeling resistors and inductors, the main components discussed here.

11.2 MODELING OF SPIRAL INDUCTORS The spiral inductor is implemented on-chip using microstrip lines. When a small section (l < 1) of a microstrip line is terminated in a short circuit, the input impedance may be written as Zin = ZLl = (R + jL)l (11.1)

where ZL is the characteristic impedance of the microstrip line, is the propagation constant for a microstrip line of length l, and R, and L are the resistance and inductance per unit length, respectively. Since the sheet resistance of the metal microstrip line is very low, then the input impedance is predominantly inductive. A narrow microstrip has a higher characteristic impedance, so narrow microstrips are used to spiral inwards to realize a high inductance in an economical amount of area. In this first section, we will consider several aspects of spiral inductor modeling such as inductance calculation, ground plane effects, series resistance, parasitic capacitance, and quality factors. We will also discuss inductor synthesis, deemdbedding and measurement techniques, and model verification using a low-pass filter circuit. Finally, in this section, we will also consider inductors fabricated on silicon substrates because of their immense technological importance at present. 11.2.1 Geometry of the Spiral Inductor An example of a rectangular planar spiral inductor is shown in Figure 11.2. The key device geometry parameters are also indicated in the figure. L1 is the length of first segment, L2 is the length of second segment, L3 is the length of third segment, Ln is

250

MODELING OF INTEGRATED INDUCTORS AND RESISTORS

Figure 11.2

Example of microstrip rectangular inductor (1-turn).

length of last segment, W is conductor width, and S is the spacing between the conductors. In designing the layout of a spiral inductor, the objective is to obtain the desired value of inductance in the smallest area, while keeping the parasitic capacitance low to ensure that the self-resonance frequency of the element is outside of the designed frequency band. The Q-factor is a very important parameter in the design of the inductor, and it is a function of frequency and geometrical parameters. By changing the geometry, the inductors Q-factor can be optimized to the highest value for the frequency range at which the inductor will operate. 11.2.2 Inductor Circuit Model Generally, the spiral inductor is a distributed structure. There are capacitive and inductive couplings between each of the microstrip lines and the series resistance is distributed over the entire microstrip structure. These complicated effects can be ignored up to the inductors first self-resonance frequency. The distributed model of the spiral inductor can be reduced to a lumped one. A basic lumped-element representation of the spiral inductor is shown in Figure 11.3. In this model, Ls represents the series inductance of the structure, Rs represents the series resistance of the metallization, Ci models the interturn capacitance between the metal traces, and Csub1 and Csub2 represent the capacitance from the metal layer to the ground plane. Because alumina is a low-loss dielectric, the substrate conductance is neglected in this model. 11.2.3 Calculation of Inductance The inductance of a spiral inductor is a complex function of its geometry. Generally, designers use the Greenhouse method [5] to compute the inductance.

11.2

MODELING OF SPIRAL INDUCTORS

251

Ci Port 1 Ls Csub 1 Rs Csub2 Port 2

Figure 11.3

Equivalent circuit of a spiral inductor on alumina substrate.

The flexibility and computational efficiency afforded by this approach have been adopted for the scalable inductor model. In Greenhouses method, the inductance of each segment of the spiral inductor is computed, and the total inductance is equal to the sum of inductance from every segment. The calculation of each segment of a spiral inductor includes self-inductance and mutual inductance, which means that the magnetic coupling between parallel conducting microstrips is taken into account. However, Greenhouse only calculated the inductance for the ideal case of an inductor in free space without a ground plane. The ground plane effect should be included because the inductance is typically lower by 20% when the spiral diameter is large compared to the ground plane distance [6]. In order to reduce the model complexity, the weak coupling between orthogonal strips is neglected [7]. 11.2.3.1 Self-Inductance. The exact self-inductance Lself for a straight conductor is calculated from Grovers formulation [8]. For a single rectangular conductor, the inductance is given by [5] W+t 2l Lself = 2 107 l ln + 0.50049 + W+t 3l where t is the thickness of the metal. 11.2.3.2 Mutual Inductance. The mutual inductance among the segments of a spiral plays an important role in computing the total inductance. The mutual inductance M between two parallel conductors of equal length l and the geometric mean distance GMD between them is given by [5] l M = 2 107 l ln + GMD

(11.2)

+ + 1 l l l 1+ GMD
2

GMD

GMD

(11.3)

where M is in henrys, l is in meters, and GMD is calculated by [5]

252

MODELING OF INTEGRATED INDUCTORS AND RESISTORS

GMD = exp ln(D)

1 1 1 1 + + + D 2 D 4 D 6 D 8 12 60 168 360 W W W W

(11.4)

with D being the center-to-center distance of the two conductors in meters. The generic mutual inductance model for all possible relative-position cases between two segments requires two configurations of two parallel segments, as shown in Figures 11.4a and b. In Figure 11.4a, the mutual inductance can be given by [9] Mj,m = 0.5[(Mm+j+d + Md) (Mj+d + Mm+d)] (11.5)

where d is positive for nonoverlapping segments and negative for overlapping ones. The individual M terms are calculated using Equation (11.3) and the lengths corresponding to the subscripts. In Figure 11.4b, the mutual inductance is given by Mj,m = 0.5[(Mm+p + Mm+q) (Mp + Mq)] 11.2.4 Ground Plane Effect on Inductance The ground plane reflection can be treated as an image spiral located at a distance of twice the substrates thickness, as shown in Figure 11.5. It contributes a net negative mutual inductance M m because the current flow is in the opposite direction in the return path. Mm can be calculated by using Equation 11.3. The inductance of a segment of spiral inductor is Lj = Lself, j + (11.6)

n=1,n

Ns

m (1)|jn|/2 Mj,n + (1)|jn|/2+1Mj,n n=1

Ns

(11.7)

Here, Lself,j is the self inductance value of segment j, Mj,n is the mutual inductance m is the mutual inductance value of actual inductor value of segments j and n, Mj,n segment j and image inductor segment n, and Ns is the number of segments.

GMD d (a) m

GMD

q (b)

Figure 11.4

Two parallel filament geometry.

11.2

MODELING OF SPIRAL INDUCTORS

253

I
Ground Plane

I
Figure 11.5

Mirror Inductor

Spirals produce a reflected image in the ground plane [6].

The total inductance Ls of the spiral inductor is the sum of inductance of all the segments, that is Ls = Lj
j=1 Ns

(11.8)

11.2.5 Series Resistance For substrates such as alumina, the substrate loss is very small compared to the conductor loss; therefore, it is neglected and the series resistor models the losses in the inductor structure. For a multiturn spiral inductor operating at high frequencies, the conductor loss is known to increase dramatically above its DC value. This phenomenon is due to the skin effect and the current crowding effect. The skin effect resistance will be discussed in the Appendix in section, and it is determined using Equation A.23. The basic mechanism behind current crowding typically cited in the literature is illustrated in Figure 11.6. As the magnetic field of adjacent turns in the inductor penetrates a metal trace normal to its surface, eddy currents are produced within the trace edge and substrate from the excitation current on the outside edge. This constricts the current, increasing the effective resistance above the value that would exist for a uniform flow throughout the trace width. According to [10], the resistance caused by the current crowding effect is given by f Rcrowd = 0.1 Rdc fcrit with 310 Dout Din + 2W fcrit = W 0.65 S 0.28 0t l

(11.9)

(11.10)

254

MODELING OF INTEGRATED INDUCTORS AND RESISTORS

Magnetic Field

Spiral Trace

Eddy loops

Excitation Current

Figure 11.6

Illustration of current crowding [10].

Here l is the length of conductor, Dout = L is the conduc2L 3, Din = L NsL Ns 1, W tor width normalized to 1 mil and S is the conductor spacing normalized to 1 mil. (Note that 1 mil = 25.4 m.) The series resistance Rs can now be given as the sum of the skin effect resistance, the ground resistance, and the current crowding effect resistance: Rs = Rskin + Rcrowd + Rg Here, Rskin and Rg are given by Equations A.23 and A.25, respectively. 11.2.6 Parasitic Capacitance Semiempirical design equations for the even- and odd-mode characteristics of coupled microstrip lines are used to calculate capacitance Ci, Csub1, and Csub2 in the model in Figure 11.3. In [11], a very simple formula to calculate the capacitance of coupled microstrip lines is provided. Here, the line capacitance is divided into several capacitances, as shown in Figure 11.7. In the even mode, the capacitance is de(11.11)

S Cga

Cf

Cm

Cf

Cf

Cm

Cf

Cf

Cm

Cge

Cm

Cf

(a)

(b)

Figure 11.7 Fringing capacitance of coupled microstrip lines excited in (a) the even mode and (b) the odd mode.

11.2

MODELING OF SPIRAL INDUCTORS

255

composed into Cf, Cm, and Cf. In the odd mode, the capacitance is decomposed into Cf, Cm, Cga, and Cge. The total even- and odd-mode capacitances can be written as Ce = Cm + Cf + Cf Co = Cm + Cf + 2(Cga + Cgd) (11.12) (11.13)

where Cm is the main capacitance of a microstrip line of width W on a substrate of thickness h and with a relative dielectric constant r, and Cm is

0rW Cm = h

(11.14)

Cf, Cf, Cga, and Cge represent various fringing capacitances. Capacitance Cf can be calculated using 1 ef f Cf = Cm 2 c0ZL

(11.15)

where c0 is the velocity of light in free space, ZL is the characteristic impedance of a microstrip line of width W given by Equation A.19, and eff is the effective dielectric constant of the microstrip line given by Equation A.13. The even-mode fringing capacitance Cf is obtained empirically [11]: Cf Cf = 1 + A(h/S)tan h(8S/h) (11.16)

where A = exp[0.1 exp(2.33 2.53 W/h)] and S is the spacing between two microstrips. Cga represents the capacitance in odd mode for the fringing field across the gap, in the air region:

0 K(k) Cga = 2 K(k)

(11.17)

where K(k) is the complete elliptical integral, K(k) is its complement, k = S/h(S/h + k2 . K(k) is given by [11] 2W/h), and k = 1 K(k) =

/2

1 d 1 k2 si n2

(11.18)

Cge represents the capacitance in odd mode for the fringing field across the gap, in the dielectric region [11]:

0r S Cge = ln coth 2 4H

+ 1 + 0.325C S

0.02h

2 r

(11.19)

256

MODELING OF INTEGRATED INDUCTORS AND RESISTORS

Interturn Capacitance. The capacitive coupling between the turns, modeled by Ci in, is determined by the odd-mode coupling. Its value is obtained by multiplying the capacitance per unit length by lt, which is the perimeter of the center spiral turn [12]. Capacitance to Ground and Line-Segment Model. Capacitance to ground calculations were accomplished using the method discussed in [13]. Due to the complicated capacitive and inductive coupling between turns, the voltage phase difference between the turns is very small, so the microstrip capacitance coupling is dominated by even-mode coupling. The capacitance of each segment can be given by Csj = (Cf L + Cm + Cf R)lsj (11.20)

where ls is the length of segment, and Cf L and Cf R represent the left-side and rightside fringing capacitance of the segment. If there is an adjacent strip at the strip left side, the CfL value is given by Equation 11.16, otherwise it is given by Equation 11.15. CfR is obtained in a similar way as CfL. The inductance, capacitance, and resistance of each segment j of the spiral inductor can be determined using the expressions given above. For example, for a line of length l divided into segments of length lj, the resistance of each segment is Rsj = (Rs lj)/l. Lj is from Equation 11.7 and Csj is from Equation 11.20. An equivalent circuit shown in Figure 11.8 can be found for each line segment of the spiral inductor. The ABCD matrix of this equivalent circuit is

As Cs

Bs Ds

= j

jCsj 1 + ( jLsj + Rsj) 2 jCsj 2 jCsj + ( jLsj + Rsj) 2

jLsj + Rsj

jCsj 1 + ( jLsj + Rsj) 2

(11.21)

Because of the asymmetrical geometry of the spiral inductor structure, capacitances of Csub1 and Csub2 are not equal. A slightly higher capacitance value is obtained for the outside end of the spirals due to a broader extension of the electrical field. The inside of the spiral is associated with a more confined field, shielded by the outside turns.

Port 1 Lsj Csj / 2 Rsj Csj / 2

Port 2

Figure 11.8

Equivalent circuit of a line segment.

11.2

MODELING OF SPIRAL INDUCTORS

257

By cascading all the equivalent circuits of the line segments and connecting an interturn capacitor between the two ports, the Y parameter of the inductor model can be found from classical circuit theory. The capacitance of Csub1 and Csub2 can be obtained from Im(Y11 + Y12) Csub1 = Im(Y22 + Y21) Csub2 = 11.2.7 Summary of Spiral Inductor Model Table 11.2 shows the methods and equations for the model parameters shown in Figure 11.3. 11.2.8 Quality Factor of a Spiral Inductor Below the first resonance frequency, the quality factor of the inductor is defined by Im(Y11) Ls 2L 2 s Q = = Rs + (Csub1 + Ci) Re(Y11) Rs Rs (11.22)

(11.23)

(11.24)

Conductor Factor

where Ls, Rs, Csub1, and Ci are the lumped elements shown in Figure 11.3. At low frequencies, the Q-factor increases with the frequency because the conductor factor is dominant and is approximately equal to Ls/Rs. However, as the frequency increases, the effect of substrate parasitic capacitance, Csub1, comes into play, and then the Q-factor will decrease with increasing frequency. Because the curve of Q-factor versus frequency is convex below the first resonant frequency, the frequency fQ at which the Q-factor is maximum may be found by setting dQ/df = 0, and fQ is approximately given by 1 1 1 fQ = = fres 3 2L su b1 + C 3 s(C i) (11.25)

Table 11.2 Ls from Eq. (11.8) Rs from Eq. (11.1) Ci Csub1 and Csub1

Equations for the model parameters

Components of LsEqs. (11.2), (11.5)/(11.6), and (11.7) Components of RsEqs. (A.23), (A.25), and (11.9) Determined from Eqs. {(11.17) + (11.18)}*lt Eqs. (11.22), (11.23)

Substrate Factor

258

MODELING OF INTEGRATED INDUCTORS AND RESISTORS

where fres is the first self-resonance frequency. However, in practice, the series resistance Rs is a function of frequency and the maximum Q-factor point frequency fQ is approximately equal to fres/2. 11.2.9 Inductor Synthesis Using Greenhouses method, the inductance error can be constrained to 5%, although it is very hard to derive the geometrical parameters from the value of inductance, quality factor, and first self-resonance frequency. However, a fairly accurate expression for the inductance is given in [14]: D Ls = a0 T 2De[b(T1)(W+S)/D] W

(11.26)

where D = L 2L 3, T is the number of turns; 0 is the permeability in vacuum; and a, b, and c are fitting parameters that depend on the fabrication technology and substrate parameters. For a 25 mil alumina substrate, the values of a, b, and c are given in Table 11.3. To design an inductor with minimal area, the inductor is optimized to be a square shape. From this point of view, we can let the geometrical parameters be as simple as shown in Table 11.4. In Table 11.4, T is the number of turns, which is equal to (i + 0.5), and i is an integer. For example, in one technology, S is equal to 1 mil, because the minimal spacing of the technology is 1 mil and the minimal spacing is used to increase the inductive coupling. Increasing W results in a higher quality factor. However, the area of the inductor becomes larger. This results in higher parasitic capacitances, which lowers the inductors self-resonance frequency. Magnetic flux must be allowed to pass through the center of the spiral. This ensures that negative mutual coupling between opposite sides of the inductor does not significantly affect the inductance and the Q-factor. Thus, the four groups of coupled lines that form the sides of the inductor must be spaced sufficiently far apart. A spacing greater than five conductor widths is recommended [7]. Therefore, Ln must be greater than 2.5 times the conductor width. Once the Q-factor and inductance values are known, the conductor width can be chosen according to the design rules of a certain technology. Ln is initially as 2.5 times the conductor width. From Table 11.4, L1, L2, and L3 can be represented by Ln and T. In Equation 11.26, T is the only unknown value. Using solve function in Matlab, T can be solved. If i + 0.5 T < i 1.5, T is set to be i + 0.5, where i is integer. Now T = i + 0.5 can be put back into Equation 11.26 to solve for Ln.

Table 11.3 a 0.96

Parameters in Equation 11.26 b 4 c 0.26

11.2

MODELING OF SPIRAL INDUCTORS

259

Table 11.4 Geometrical parameters represented by the number of turns T and the length of last segment Ln Ns 4T + 1 L1 Ln + (T 0.5)(W + S) L2 2L1 L3 L2 W W W S S

11.2.10 Design and De-Embedding of Inductor Test Structure To experimentally investigate the accuracy of the model expressions developed, 20 rectangular spiral inductors designed on a test chip are used. They are different in the number of segments, the conductor width, the conductor spacing, and the length of the last conductor segments. The number of turns can be derived from Ns, L1, and Ln. The inductance of these 20 inductors ranges from 1 nH to 15.53 nH, and the first self-resonance frequency is from 3.2GHz to 25GHz. All the geometrical parameters are given in Table 11.5. To measure the spiral inductor scattering parameters, the groundsignalground (GSG) structure was used in an on-wafer microwave measurement system. The layout of the test structure is shown in Figure 11.9. Two groups of ground signalground pads are used in the two-port measurement. The ground pads are connected by four through-substrate vias to the ground plane contact. In order to

Table 11.5 Cell name Ind1 Ind2 Ind3 Ind4 Ind5 Ind6 Ind7 Ind8 Ind9 Ind10 Ind11 Ind12 Ind13 Ind14 Ind15 Ind16 Ind17 Ind18 Ind19 Ind20 # of turns (T) 1.5 2.5 3.5 4.5 1.5 2.5 3.5 4.5 1.5 2.5 3.5 4.5 1.5 2.5 3.5 4.5 1.5 2.5 3.5 4.5 Ns 7 11 15 19 7 11 15 19 7 11 15 19 7 11 15 19 7 11 15 19

Parameters of 20 inductors test structures Width (mil) 1 1 1 1 2 2 2 2 1 1 1 1 2 2 2 2 2 2 2 2 Spacing (mil) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 L1 (mil) 6.0 8.0 10.0 12.0 7.0 10.0 13.0 16.0 8.0 10.0 12.0 14.0 9.0 12.0 15.0 18.0 10.0 14.0 18.0 22.0 L2 (mil) 12.0 16.0 20.0 24.0 14.0 20.0 26.0 32.0 16.0 20.0 24.0 28.0 18.0 24.0 30.0 36.0 20.0 28.0 36.0 44.0 L3 (mil) 11.0 15.0 19.0 23.0 12.0 18.0 24.0 30.0 15.0 19.0 23.0 27.0 16.0 22.0 28.0 34.0 18.0 26.0 34.0 42.0 Ln (mil) 3.5 3.5 3.5 3.5 3.0 3.0 3.0 3.0 5.5 5.5 5.5 5.5 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0

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Ground

Ground

Signal

Signal

Ground

Ground

Figure 11.9 A typical Inductor test structure (3.5-turn inductor) in a groundsignalground configuration. The ground vias are labeled in the figure.

minimize the effect of ground pads, the spacing of DUT (device under test) to ground pad is more than five times the conductor width of the spiral inductor. To de-embed the feeding microstrip at the right side and bond wire with a feeding microstrip at the left side, the two other dummy structures were designed as shown in Figures 11.10a and b. The de-embedding procedure developed in [15] is used to de-embed the measured DUT data. This de-embedding technique is based on the cascade configurations without the requirement of any equivalent circuit models for the probe pads or the interconnections.

(a)

(b)

Figure 11.10 (a) Test structure for de-embedding the bond wire with a microstrip feed line at the left side in Figure 11.9. (b) Test structure for de-embedding the microstrip at the right side in Figure 11.9.

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MODELING OF SPIRAL INDUCTORS

261

11.2.11 Measurement Setup and Calibration Specifications The S-parameter measurement system is shown in Figure 11.11. The system consists of a HP 8510 vector network analyzer system, a microwave probe station, and a computer. The network analyzer and microwave probes are connected by highfrequency cables. The measurement data are transferred from the network analyzer to a computer via the HP-IB bus. In our measurements, we used 150 m pitch GSG microwave probes, made by GGB Industries Inc. The probe tips have three in-line contacts, spaced 150 m apart. The two outside contacts provide ground connections and the center contact provides the signal connection. CS5 calibration substrate in the calibration kits is used for calibration. The calibration method used in our system calibration is SOLT (short, open, load, through). The accuracy of the system calibration is mainly limited by the accuracy of the impedance standards and the accuracy of the probe placement. When the open measurement is performed, the probes contact open pad structures because the electrical fields at the probe tips are very similar to those of the matched load and the through structures. 11.2.12 Experimental Verification The spiral inductor test structures and dummy structures were measured by the measurement set up shown in Figure 11.11. The intrinsic S-parameters are extracted by using the de-embedding procedure which was developed in [15]. Figure 11.12 shows S-parameters of Ind5 to Ind8, whose geometrical parameters are given in Table 11.5. The agreement of measurement data and model simulation is quite good.

Computer

HB-IB HP 8510B Network Analyzer

High Frequency Cable

G S G

PROBE

PROBE

Probe Station
Figure 11.11 S-parameter measurement setup.

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1.0

MODELING OF INTEGRATED INDUCTORS AND RESISTORS

Ind8 0.8 S11 Magnitude

Ind7 Ind6 S11 Phase (Degree)

80 60 40 20 0 20 0 Ind8 4 Ind7

Measurement Model

0.6 Ind5 0.4 0.2 0.0 0 4 8 12 16 Frequency (GHz) Measurement Model

Ind5

Ind6 20

8 12 16 Frequency (GHz)

1.0 S12 Phase (Degree)

0 -20 -40 -60 -80 Ind8 20 -100 0 4 Ind7 8 12 16 20 Frequency (GHz) Ind5 Measurement Model

S12 Magnitude

0.8 Ind5 0.6 Ind6 0.4 Ind8 0 4 Ind7

Measurement Model

Ind6

8 12 16 Frequency (GHz)

1.0 Ind8 0.8 Ind6 S22 Magnitude 0.6 Ind5 0.4 0.2 0.0 0 4 8 12 16 Frequency (GHz) 20 Measurement Model S22 Phase (Degree) Ind7

80 60 40 Ind5 20 0 -20 Measurement Model

Ind8 Ind7 0 4

Ind6 20

8 12 16 Frequency (GHz)

Figure 11.12 S-parameters comparison of Ind5, Ind6, Ind7, and Ind8 (measurement and model simulation).

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MODELING OF SPIRAL INDUCTORS

263

In order to see the performance of the inductors from the measured S-parameters, S-parameters are converted to Y-parameters. Therefore, the Q-factor and inductance of spiral inductor are extracted by using Equations 11.24 and 11.27: Im(1/Y11) L = (11.27)

Figure 11.13 shows the Q-factor of Ind5 to Ind8. The Q-factor of Ind5 is higher than other inductors because it has only 1.5 turns and suffers less ground capacitance and current crowding effects. With increasing number of inductor turns, the parasitic capacitance from metal layer to ground plane increases, so that the first self-resonance frequency decreases. The first self-resonance frequency is located at the frequency where the Q-factor is zero. Figure 11.14 shows the inductance of Ind5 to Ind8. It is obvious that the inductance increases with the number of turns. The inductance increases very sharply near the first self-resonance frequency because of the resonance effect. Similar good agreement between model predictions and experiments were obtained for the other 16 test inductors, verifying the model expressions developed and discussed here. 11.2.13 Low-Pass Filter From an engineering perspective, the inductor model will be verified using a simple circuit. This is done using the inductors in a third-order, low-pass filter circuit,

60 50 40 30

Measurement Model
Number of turns

Ind5 20 10 0 -10 Ind8 0 4 Ind7 8 Ind6

12

16

20

Frequency (GHz)

Figure 11.13

Q-factor of spiral inductor.

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MODELING OF INTEGRATED INDUCTORS AND RESISTORS

60 50 Inductance (nH) 40 30 Ind6 20 10 0 0 5 10 Frequency (GHz) Ind8 Ind7

Measurement Model

Number of turns Ind5

15

20

Figure 11.14

Inductance of spiral inductors (Ind5Ind8).

shown schematically in Figure 11.15. The inductance of L1 and L2 is 1.5 nH and the capacitance is 0.5 pF. Figure 11.16 shows the layout of the low-pass filter. The inductor is implemented with a 1.5-turn spiral inductor and the capacitor is implemented with an interdigital capacitor. 11.2.13.1 Interdigital Capacitor. The model of interdigital capacitor which is used in the low-pass filter is shown in Figure 11.17. The model is a two-port Tnetwork. C is the most important element and it represents the capacitance of the interdigital capacitor. L1 and L2 represent the series inductances. R1 and R2 represent series resistances, which are frequency-dependent. Ci1 and Ci2 are the distributed capacitances. The parameters in the model are derived by fitting the model-simulated S-parameters to experimental S-parameters. The parameters values are shown in Table 11.11. R1DC and R2DC are the DC values of resistances R1 and R2. Figure 11.18 shows the S-parameters comparison of interdigital capacitance in which good agreement between measurement and model simulation is obtained.

Port 1 L1 C1 L2

Port 2

Figure 11.15

Schematic diagram of a third-order low-pass filter.

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MODELING OF SPIRAL INDUCTORS

265

Figure 11.16

Test structure of the low-pass filter.

By applying the models of the spiral inductors and the interdigital capacitor in Figure 11.15, the S-parameters of model simulation can be obtained from the ADS circuit simulator. Good agreement of model simulation and measurement is obtained as shown in Figure 11.19 for the third-order, low-pass filter. 11.2.14 Extension of the Model to Spiral Inductors on Silicon Substrates Today, due to the demand for system-on-chip solutions, inductors need to be designed on a silicon wafer. During the past few years, much effort has been focused on the modeling and design of integrated inductors for silicon RF ICs [6,7,16]. The most challenging part of the inductor modeling on a silicon substrate is to exactly model the substrate loss. This is because the substrate loss is very significant compared to the conductor loss and the mechanism of the loss is not easily represented by analytical expressions. In some publications, the inductor models are expressed in terms of physics-based parameters [6,7,16]. However the errors of these models are quiet large because it is very difficult to get a good ground reference point due

Ci1 L1 R1 L2

Ci2 R2

Figure 11.17

Equivalent circuit model of an interdigital capacitor.

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MODELING OF INTEGRATED INDUCTORS AND RESISTORS

1.0 0.8 0.6 0.4 Measurement Model

S21

Magnitude

S11 0.2 0.0 0 4 8 12 16 20

Frequency (GHz)

180 120 Phase (Degree) 60 0 -60 -120 S11 -180 0 4 8 12 16 20 S21 Measurement Model

Frequency (GHz)

Figure 11.18 simulation).

S-parameter comparison of an interdigital capacitor (measurement and model

to the lossy silicon substrate. In some of the reported works, curve fitting techniques are used to get the model parameters from either measurements or EM simulations. In most publications, the model is given as a lumped-element equivalent circuit shown in Figure 11.20. In this model, the substrate network is more complex than that of an alumina substrate because of the metalinsulatorsilicon (MIS) structure. Here, Cox1 and Cox2 represent the capacitance of the inductor metal layer to substrate, Csub1 and Csub2 represent the capacitance of the silicon substrate, and Rsub1 and Rsub2 represent the resistance of lossy silicon substrate. Once the circuit model is developed, parameters for the circuit elements must be obtained. Here, a general technique was developed to extract lumped-element para-

11.2

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267

0 S11

-10 Magnitude (dB)

-20 Measurement Model Momentum 0 5 10 Frequency (GHz) 15

S21

-30

20

180 135 90 Phase (Degree) 45 0 -45 -90 -135 -180 0 4 8 12 16 20 Measurement Model Momentum S11 S21

Frequency (GHz)

Figure 11.19 S-parameter comparison of a third-order low-pass filter (measurement, momentum simulation, and model simulation).

Ci

Port1
Cox1

Ls

Rs Cox2

Port2

Rsub1

Csub1

Rsub 2

Csub2

Figure 11.20

Equivalent circuit of a spiral inductor on a silicon substrate.

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meters of the model from measured S-parameters. The extraction procedure is described in the following 3 steps. 1. The experimental S-parameters are transformed into Y-parameters using the expressions (1 S11)(1 + S22) + S12S21 Y11 = Y0 (1 + S11)(1 + S22) S12S21 S12 Y12 = Y0 (1 + S11)(1 + S22) S12S21 S21 Y21 = Y0 (1 + S11)(1 + S22) S12S21 (1 + S11)(1 S22) + S12S21 Y22 = Y0 (1 + S11)(1 + S22) S12S21 where Y0 = 1/(50) 2. Y1, Y2, and Y3 in the two-port -network can be represented by Y-parameters as Y1 = Y11 + Y12 Y2 = Y12 Y3 = Y22 + Y21 Figure 11.21 shows the structure of two-port -network. Ym1, Ym2 and Ym3 are two-port -network parameters of the inductor model given as jCox1(1/Rsub1 + jCsub1) Ym1 = 1/Rsub1 + j(Cox1 + Csub1) jCox2(1/Rsub2 + jCsub2) Ym2 = 1/Rsub2 + j(Cox2 + Csub2) 1 Ym3 = jCi + jLs + Rs (11.30) (11.29) (11.28)

Port1 Y1

Y3

Port2 Y2

Figure 11.21

Two-port -network.

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MODELING OF SPIRAL INDUCTORS

269

Table 11.6 Parameter for circuit elements of interdigital capacitor model C 0.48 pF L 1 , L2 0.376 nH R1DC, R2DC 0.29 Ci1, Ci2 74 fF

3. The parameters of the lumped-element inductor model are obtained from an optimization program for the fitting of the models Ym1, Ym2, and Ym3 to Y1, Y2, and Y3, respectively that are derived from experimental S-parameters. The optimization employed a least-mean-square algorithm, which is built in the Matlab software. For the optimization, the convergence is very important and it depends on the starting values of parameters and the numbers of parameters. The starting values are derived based on the physical dimension of the spiral inductor and electrical parameters of the substrate. Table 11.7 lists the equations for the starting values. In the table, l is the length of inductor, hox is the thickness of the insulator layer, hsub is the thickness of the substrate, h56 is the distance between metal 5 to metal 6, Cox is the starting value of Cox1 and Cox2, Csub is the starting value of Csub1 and Csub2, and Rsub is the starting value of Rsub1 and Rsub2. A 2.5-turn square spiral inductor is designed in 0.18 m CMOS technology. The test structure layout of the inductor is shown in Figure 11.22. Similar to the spiral inductors on alumina substrate, the groundsignalground design is used for onwafer probe measurement for this spiral inductor. The geometrical parameters of this inductor are shown in Table 11.8. The extracted model parameters are given in Table 11.9. Figure 11.23 shows that good agreement is obtained between the measured and modeled S-parameters of the inductor. Figure 11.24 also shows the good agreement between the measured and modeled quality factor and inductance obtained using expressions discussed above. The equivalent-circuit model parameters used in the simulations are shown in Table 11.9.

Figure 11.22

Test structure layout of a 2.5-turn spiral inductor on a silicon substrate.

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MODELING OF INTEGRATED INDUCTORS AND RESISTORS

Table 11.7 program

Equations for the model parameters used as initial values in optimization

Ns

Ls = Lself, j +
j=1

n=1, n

Ls

(1)
j

|jn|

Mj,n + (1)
n=1

Ns

+1 2

|jn|

Mm j,n

(11.31)

l Rs = , eff = (1 et/2) 2W eff NW 2 Ci = 0r,ox h56

(11.32)

(11.33)

Wl 1 Cox = 0r,ox 2 hox

(11.34)

1 (L2 + W)(L3 + W) Cf 0r,siW 1 ef f Csub = 0r,si , W = W , Cm = , Cf = Cm 2 hsub Cm hsub 2 c0ZL

(11.35) 1 hsub Rsub = sub 2 (L2 + W)(L3 + W)

(11.36)

Table 11.8 # of turns (T) 2.5 Ns 11

Geometrical parameters of spiral inductor on silicon substrate Width (m) 30 Spacing (m) 1.5 L1 (m) 180 L2 (m) 360 L3 (m) 330 Ln (m) 102

1.0 0.8
Mag. S11 Mag. S12 Phase S11 Phase S12

60 40 20 0 -20 -40 -60 Phase (Degree)

Magnitude

0.6 0.4 0.2 0.0

2 3 Frequency (GHz)

Figure 11.23 Comparison between measured and model-simulated S-parameters of a 2.5turn silicon spiral inductor.

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MODELING OF THIN-FILM RESISTORS

271

5 8 4 6 L (nH) 3 Q 4
Measurement Model

2 1 0

Frequency (GHz)

Figure 11.24 Comparison between measured and model simulated Q-factor and inductance of a 2.5-turn silicon spiral inductor on a silicon substrate.

11.3 MODELING OF THIN-FILM RESISTORS Thin-film resistors (TFRs) are used in microwave circuits to implement components such as passive attenuators and terminal loads. To date, the TFR model considers the parasitic series inductance and shunt capacitance to be the same as those of a lossless microstrip line [17]. However, this model does not provide good results when the width of resistor is much smaller than the substrate thickness. In addition, the self-capacitance has to be taken into account to improve the model accuracy. The self-capacitance of planar resistors was introduced in [18]. If a voltage is applied at the terminals of a resistor, a potential difference will exist across two arbitrary points A and B in the resistor. Therefore, a parasitic capacitance exists between A and B [27]. In microwave integrated circuit (MIC) technology, a thin-film resistor is realized as a thin strip of a lossy conductor on top of a dielectric substrate. The resistive layer can be a self-passivating tantalum nitride (TaN) compound. The sheet resistivity of the process is adjusted by controlling the thickness of the resistive layer. In most processes, a sheet resistivity of 50 per square is selected due to the convenience that it provides to circuit designers. A small area of highly conducting metal is deposited at the ends of the element as contacts to the resistor. The exposed resistive area defines the resistance of the structure. The fabrication design rules generally require that the resistive layer be narrower than the width of the conducting contact by some minimum distance. This requirement arises due to the need to have a good contact between the resistive layer and the conducting layer to take into account the process alignment tolerances. Figure 11.25 shows the layout cross section of a thin-film resistor. The measurement reference planes at the ends of the conductor contacts are shown in Figure 11.25a, so that the conductor contact is removed from the measurement. However, the electrical effect of the step discontinuity will not be removed from

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MODELING OF INTEGRATED INDUCTORS AND RESISTORS

Figure 11.25

(a) Overhead and (b) side views of a thin-film resistor.

the measurement. As a result, the thin-film resistor model should be divided into three sections, as shown in Figure 11.26. The middle section is the intrinsic thinfilm resistor, which is modeled as a lossy microstrip transmission line. The other two sections model the step discontinuities at both sides of the intrinsic thin-film resistor. In this section, various aspects of thin-film resistors important for developing an accurate equivalent-circuit model will be discussed. Step-discontinuity, sheet resistance, and design of test structures for experiments and model verification will be discussed. In addition, the S-parameters measurement system, measurement calibration, and comparison between measurements and model will be presented and discussed.

Port 1 Ref. Plane

Port 2 Ref. Plane

Step

Lossy Microstrip Line

Step

Port 1 Ref. Plane

Port 2 Ref. Plane

Figure 11.26

Equivalent circuit of a thin-film resistor.

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MODELING OF THIN-FILM RESISTORS

273

11.3.1 Step Discontinuity in Microstrip Width Since the width of the thin-film resistor must be narrower than that of the contacting conductor layer, a step discontinuity exits at both ends of the resistor. The electromagnetic field is discontinuous at the steps because the current density increases from the wider to the narrower conductor and scattered electric fields exist on the front edge of the wider conductor, as shown in Figure 11.27a. Figure 11.27b shows the equivalent circuit of the step in conductor width. Ls represents the current compression and Cp represents the electrical scattering fields. An approximate expression Cp [21] is given by Cp = Cf1(W1 W2) (11.37)

Here, Cf1 is the fringing capacitance per unit length of the wider microstrip [21]: 1 ef f1 Cf1 = 0rW1/h [F/m] 2 c0ZL1

(11.38)

where c0 is the speed of light in free space, and ZL1 and eff1 are the characteristic impedance and effective dielectric constant of the wider microstrip, respectively. In some cases, TFRs may have very small lengths, and the two step discontinuities can be very close to each other. In this case, capacitance Cp at one end of resistor will decrease because the electrical scattering field is constrained by the step at the other end of the resistor. To calculate Cp under this condition, the method that derives the even-mode fringing capacitance Cf1 of two parallel microstrip lines is employed, and it can be expressed as [11] Cf 1 C f 1 = [F/m] 1 + A(h/l)tan h(8l/h) (11.39)

Electrical scattering fields T T W1 W2 Ls Cp Current Lines T (a) (b)

Figure 11.27 circuit [21].

Step in microstrip. (a) Width construction. (b) Lumped-element equivalent

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MODELING OF INTEGRATED INDUCTORS AND RESISTORS

where A = exp[0.1 exp(2.33 2.53 W1/h)] and l is the length of the resistor. By putting Equations 11.38 and 11.39 into 11.37, Cp can be obtained as 1 0rW1 f1 ef (W1 W2) h 2 c0Z01 Cp = 1 + A(h/l)tan h(8l/h)

(11.40)

The closed-form expression for inductance Ls has been derived by curve fitting the numerical results, and Ls [21] is Ls = [a( 1) b log(() + c( 1)2)]h [nH] where a = 40.5, b = 75, c = 0.2, and = W1/W2. 11.3.2 High Sheet Resistance Microstrip Model As a two-port network, a high sheet resistance microstrip line can be represented by an ABCD matrix [19]: (11.41)

A C

B = D

cosh(l) sinh(l) ZL

ZL sinh(l) cosh(l)]

(11.42)

where ZL is the characteristic impedance and is the propagation constant. It is well known that ZL and can be given by the series impedance per unit length Z and the shunt admittance per unit length Y of the microstrip line: ZL = Y Z (11.43) (11.44)

= Z Y

Due to the low value of the losses in the alumina substrate, the shunt conductance per unit length is neglected. Therefore, Y can be given by the shunt capacitance per unit length C as Y = jC (11.45)

For a low-loss microstrip line, Z can be given by the sum of the per-unit length resistance R and the per unit length inductance L: Z = R + jL (11.46)

However, for a high sheet resistance microstrip line, the self-capacitance must be taken into account. In [18], the self-capacitance was derived by numerical calcula-

11.3

MODELING OF THIN-FILM RESISTORS

275

tion. Here, however, the self-capacitance was derived by using a commercially available full-wave electromagnetic simulator (HP-Momentum). Two sets of microstrip lines were simulated by HP-Momentum. One set consisted of microstrip lines with high sheet resistance of 50 per square; the other set consisted of lossless microstrip lines. Electromagnetic simulations were performed from 1 GHz to 40 GHz in 4 GHz steps. The dimensions of the microstrip lines are shown in Table 11.9. The series resistance, inductance, and shunt capacitance per unit microstrip length were extracted from the simulated S-parameters. The four-step extraction procedure is now described. 1. Convert S-parameters into ABCD parameters using the standard expression. (1 + S11)(1 S22) S12S21 A = 2S21 (1 + S11)(1 + S22) S12S21 B = Z0 2S21 1 (1 S11)(1 S22) S12S21 C = Z0 2S21 (1 S11)(1 + S22) + S12S21 D = 2S21 where Z0 = 50. 2. Determine the propagation constant as = acosh(A)/l and the characteristic impedance as ZL = B/{sinh[achosh(A)]}. 3. Determine the series impedance per unit length Z and the shunt admittance per unit length Y of the microstrip line from Z = ZL and Y = /ZL, respectively. 4. Obtain the series resistance per unit length as equal to the real part of Z, series inductance per unit length as L = Im(Z)/, and shunt capacitance per unit length as C = Im(Y)/. Figure 11.28 shows the capacitance per unit length versus frequency and microstrip width. The capacitance increases as the microstrip width increases. The values of the capacitance are nearly identical in Figures 11.28a and b, which verifies that the shunt capacitance per unit length of a high sheet resistance microstrip line can be simply derived from the lossless line case. Figure 11.29 shows that the series resistance per unit length of high sheet resistance line decreases with the frequency because of the self-capacitance effect.

(11.47)

Table 11.9 Ls (nH) 3.56 RsDC () 4.396 Ci (fF) 2.17 Cox1 (fF) 188

Extracted model parameters Cox2 (fF) 192 Csub1 (fF) 145 Csub2 (fF) 161 Rsub1 () 225 Rsub2 () 213

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MODELING OF INTEGRATED INDUCTORS AND RESISTORS

Capacitance (pF)

200 150 100 50 0.6 0.4 Width (mm) 0.2 0.1 0 10 20 30

Capacitance (pF)

250

250 200 150 100 50 0.6 0.4 Width (mm) 0.2 0.1 0 10 20 30

40

40

Frequency (GHz)

Frequency (GHz)

(a)

(b)

Figure 11.28 less line.

Shunt capacitance per unit length of (a) resistive line (50/) and (b) loss-

Clear differences can be seen between Figures 11.30a and b. This means that the series inductance per unit length of a high sheet resistance microstrip line cannot be simply obtained from the case of a lossless line. Further, we find that the series impedance per unit length cannot be represented by just a resistor in series with an inductor. An appropriate first-order model for the series impedance Z is shown in Figure 11.31 and is given by Equation 11.48. R2Cs/4 (RCs/2)2 + j L Z = R 1 2 1 + (RCs/2) 1 + (RCs/2)2

(11.48)

In Equation 11.48 L is equal to the series inductance per unit length in the case of a lossless line, R is the series resistance per unit length at DC, and Cs represents the self-capacitance, which has been derived by curve fitting of the numerical Momentum simulation results:

Normalized resistance

0.95 0.9

0.85 0.8 0.6 0.4 0.2 Width (mm) 0.1 0 10 20 30

40

Frequency (GHz)

Figure 11.29 Frequency dependent series resistance per unit length normalized to DC series resistance per unit length of resistive line (50/ ).

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MODELING OF THIN-FILM RESISTORS

277

Inductance (nH)

450 400 350 300 250 0.6 0.4 Width (mm) 0.2 0 10 20 30 40

Inductance (nH)

500

800 700 600 500 400 300 0.6 0.4 Width (mm) 0.2 0 10 20 30 40

Frequency (GHz)

Frequency (GHz)

(a)

(b)

Figure 11.30 line.

Series inductance per unit length of (a) resistive line (50/) and (b) lossless

W Cs = 1.58 1018 + 1.26 h

(11.49)

where W is the width of resistor and h is the substrate height, which is 15 mil for these samples. In the model given by Equation 11.48, the real part of Z is the series resistance per unit length, which decreases with frequency, in agreement with the trend in . The equivalent inductance per unit length is a function of the DC resistance per unit length R, self-capacitance Cs, and series inductance per unit length L in the case of lossless line, and it is smaller than that of the lossless line case. The series inductance per unit length L and shunt capacitance per unit length C of a lossless line can be directly calculated from the empirical formula for ZL and eff of a lossless transmission line, which are given by Equations A.19 and A.11. The resistance per unit length R is determined by the technology. Cs is given by Equation 11.48. Thus, the impedance per unit length Z and the admittance per unit length Y of a high sheet resistance microstrip line can be calculated from L, R, Cs, and C. By using Equations 11.43 and 11.44, the characteristic impedance ZL and propagation constant can be calculated. Finally, the model can be implemented in matrix form by using the ABCD matrix shown in Equation 11.42.

Cs

R/2

R/2

Figure 11.31

Equivalent circuit of per unit length series impedance.

278

MODELING OF INTEGRATED INDUCTORS AND RESISTORS

11.3.3 Experimental Verification Nine thin-film resistors (TFRs) were fabricated and measured. They had different widths and lengths. The height of the substrate is 15 mil. The planar physical dimensions of the TFR test structures were measured using a microscope. The DC resistance of the TFRs were measured using a digital multimeter. Based on the measured resistance and the physical dimensions of a resistor, the sheet resistance of the resistive layer was determined. The physical parameters of thin-film resistors are presented in Table 11.10. The layout of resistors 3 and 9 are shown in Figure 11.32. The microstrip feed lines are 5080 m long and 361 m wide. Although the width of resistor 9 is larger than the width of microstrip feed line, a short length (100 m) of wider conductor had to be added between the end of the microstrip feed line and the resistor. Since the measurement reference planes are at the ends of the microstrip feed lines, the effect of the short length of wide conductor was included in the measurements. Therefore, this short length of wide conductor has to be included in the resistor model, which is shown in Figure 11.33. The model of wider resistors, such as resistors 7 to 9, is divided into seven sections as shown in Figure 11.33. The middle three sections are the same as the model shown in Figure 11.26. A low-loss microstrip transmission line is used to model the short length of wide conductor. A step in microstrip width exists at the connection of the microstrip feed line and wide microstrip, so a step model is used to model this effect. 11.3.4 S-parameter Measurement Setup The block diagram of a measurement setup is shown in Figure 11.34. The measurement setup consisted of a Wiltron 37396A vector network analyzer (VNA), two high-frequency cables, and a universal test fixture (UTF). The Wiltron 37396A VNA was used to make the S-parameter measurements of the thin-film resistors. The coaxial cables from the VNA are attached to the two connector blocks of the UTF. The connector of UTF provides a coaxialmicrostrip transition. S-parameters were measured over a frequency range of 1 to 40GHz. 11.3.5 Measurement Calibration At microwave frequencies, a proper calibration is critical for high measurement accuracy. The goal of calibration is to remove the influences of elements other than the

Table 11.10 Input Parameter Frequency (GHz) Width (m) Length (m)

Parameters of simulated microstrips Minimum Value 1 100 200 Maximum Value 40 500 500

11.3

MODELING OF THIN-FILM RESISTORS

279

Table 11.11 Resistor 1 2 3 4 5 6 7 8 9

Measured physical parameters of thin-film resistor test structures Length (m) 70 140 280 130 265 530 260 510 1020 DC Resistance () 27.1 52.8 104.3 26.2 52.4 103.4 26.1 51.1 104.2 Sheet Resistance (/) 56 2 52 1 52 1 53 1 51.2 0.8 52.7 0.8 51.2 0.8 51.1 0.8 52.1 0.8

Width (m) 145 140 140 265 270 270 510 510 510

(a) Microstrip Feed Lines Resistor Layer

(b)

Figure 11.32

Layout of resistor test structure. (a) Resistor 3. (b) Resistor 9.

Port 1 Reference Plane

Resistor Layer

Port 2 Reference Plane

Microstrip Feed line

Microstrip Feed line

Step

Step

Lossy Microstrip Line

Step

Step

Port 1 Reference Plane

Low-Loss Microstrip Line

Port 2 Reference Plane

Figure 11.33

Equivalent circuit for wider resistor.

280

MODELING OF INTEGRATED INDUCTORS AND RESISTORS

Vector Network Analyzer

High Frequency Cables

Universal Test Fixture

Figure 11.34

Block diagram of measurement setup.

0.6 0 S11 Phase (Degree) 0.5 S11 Magnitude 103.4 -15 -30 -45 -60 103.4 Measurement Model 0 10 20 30 Frequency (GHz) 40 52.4

0.4 0.3

52.4

Measurement Model 0.2 0 10 20 30 40

Frequency (GHz)
0.8 52.4

0 S12 Phase (Degree) 52.4 103.4 Measurement Model 0 10 20 30 40

0.7 S12 Magnitude 0.6 0.5

-20

Measurement Model

-40

103.4 0.4 0 10 20 30 40

-60

Frequency (GHz)

Frequency (GHz)

Figure 11.35 Comparison between measured and simulated S-parameters for two TFRs [Cell 5 (52.4) and Cell 6 (103.4)].

11.3

MODELING OF THIN-FILM RESISTORS

281

device under test (DUT). All cables, transitions, and feed lines connecting the DUT to the VNA influence the S-parameter measurements. Therefore, the effects of the transmission medium must be removed through measurement calibration. Calibration involves the measurement of a series of standards relative to the measurement reference planes. The reference planes are generally placed at the ports of the DUT. After calibration, the effect of all influences behind the reference planes are mathematically removed from measurements. In the measurement of TFRs, the reference planes are placed at the end of microstrip feed lines, as shown in Figures 11.26 and 11.33. The TRL (Thru reflect line) calibration method was used for the measurement calibration. This calibration method avoids the difficulty of producing precision impedance structures. In the TRL calibration procedure, the Thru standard is measured with two ports connected with a 10.16 mm 50 microstrip line, and the measurement reference planes are placed in the middle of the line. The reflect standard is realized as an open-end 5.08 mm 50 microstrip line. The S-parameters of two TFRs (resistors 5 and 6), whose widths are smaller than microstrip feed line, are shown in Figure 11.35. As is shown, good agreement between model simulations and measurements has been obtained. The S-parameters of two TFRs (resistors 8 and 9), whose widths are larger than the microstrip feed line, are shown in Figure 11.36. As before, good agreement between model simulations

0.5
S11 Magnitude

104.2
S11 Phase (Degree)

0 -30 -60 -90 Measurement Model

0.4 0.3 0.2 0

51.1
Measurement Model

51.1 104.2
0 8 16 24 32 Frequency (GHz) 40

-120 -150

8 16 24 32 Frequency (GHz)
51.1
Measurement Model

40

0 S12 Phase (Degree)

0.6
S12 Magnitude

-45 -90 -135 -180

51.1 104.2
Measurement Model 0 8 16 24 32 Frequency (GHz) 40

0.5 0.4 0
104.2

8 16 24 32 Frequency (GHz)

40

Figure 11.36 Comparison between measured and simulated S-parameters for two TFRs [Cell 8 (51.1) and Cell 9 (104.2)].

282

MODELING OF INTEGRATED INDUCTORS AND RESISTORS

and measurements was obtained. Similar good agreement between experiments and simulations for the other five resistors listed in in Table 11.11 were obtained.

11.4 CONCLUSIONS In this chapter, equivalent circuit models for spiral inductors, interdigital capacitors, and thin-film resistors were proposed. Twenty test structures of spiral inductors were designed and tested to verify the scalable inductor model. A low-pass filter was designed to verify the spiral inductor model for circuit applications. Good agreement has been found between measurement and model simulation. The inductor model was extended to the silicon substrate. Due to the complex substrate effect in silicon substrates, the model is not scalable, but a technique to extract the model parameters was presented. An accurate scalable model for thin-film resistors has been represented in ABCD matrix form. Details of the inductive and capacitive parasitics in the TFR have been discussed. A self-capacitance is used to get better fitting of the model. Good agreement between simulations with the proposed model and measurements has been obtained up to 40GHz.

REFERENCES
1 C. J. Mattei, Advanced Alumina: A Manufacturing Medium for Microwave Oscillators and Amplifiers, Microwave Journal, 36, 2, 6474, 1993. 2. I. D. Robertson and S. Lucyszyn, RFIC and MMIC Design and Technology, The Institution of Electical Engineers, London, 2001. 3. www. nanowavetech. com. 4. Advanced Design System 1.3Momentum Menu, Agilent Technologies, November 1999. 5. H. M. Greenhouse, Design of planar rectangular microelectronic inductors, IEEE Transactions on Parts, Hybrids, and Packaging, PHP-10, 2, 101109, 1974. 6. M. Parisot, Y. Archambault, D. Pavlidis, and J. Magarshack, Highly Accurate Design of Spiral Inductors for MMICs with Small Size And High Cut-off Frequency Characteristics, In IEEE MTT-S Digest, 1984. 7. J. R. Long and M. A. Copeland, The Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF ICs, IEEE Journal of Solid-State Circuits, 32, 3, 357369, 1997. 8. F. Grover, Inductance Calculations, Working Formulas and Tables, New York: Dover Publications, 1962. 9. Y. K. Koutsoyannopoulos and Y. Papananos, Systematic Analysis and Modeling of Integrated Inductors and Transformers in RF IC Design, IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, 47, 8, 699713, 2000. 10. W. B. Kuhn and N. M. Ibrahim, Analysis of Currnet Crowding Effects in Mutiturn Spiral Inductors, IEEE Microwave Theory and Techniques, 49, 1, 3139, 2001.

REFERENCES

283

11. R. Garg and I. H. Bahl, Characteristics of coupled microstriplines, IEEE Transactions on Microwave Theory and Techology, 27, 700705, 1988. 12. P. Pieters, K. Vaesen, S. Brebels, S. F. Mahmoud, W. D. Raedt, and R. P. Mertens, Accurate Modeling of High-Q Spiral Inductors in Thin-Film Multilayer Technology for Wireless Telecommunication Applications, IEEE Transactions on Microwave Theory and Technology, 49, 4, 589599, 2001. 13. E. Pettenpaul, H. Kapusta, A. Weisgerber, H. Mampe, J. Luginsland, and I. Wolff, CAD Models of Lumped Elements on GaAs up 18 GHz, IEEE Transactions on Microwave Theory and Technology, 36, 2, 294304, 1988. 14. H. Ronkainen, H. Kattelus, E. Tarvainen, T. Riihisaari, M. Andersson and P. Kuivalainen, IC Compatible Planar Inductors on Silicon, IEEE Proceedings on Circuits, Devices, and Systems, 144, 1, 1997. 15. C. H. Chen and M. J. Deen, A General Noise and S-Parameter De-Embedding Procedure for on-Wafer High Frequency Noise Measurements of MOSFETs, IEEE Transactions on Microwave Theory and Techniques, Electronics Letters, 49, 5, 10041005, 2001. 16. A. M. Niknejad and R. G. Meyer, Analysis, Design and Optimization of Spiral Inductors and Transformers for Si RF ICs. IEEE J. Solid-State Circuits, 33, 14701481, 1998. 17. G. Carchon, S. Brebels, W. De Raedt, and B. Nauwelaers, Accurate Measurement and Characterization up to 50 GHz of CPW-based Integrated Passives in Microwave MCMD, In 2000 Electronic Components and Technology Conference, pp. 459464, 2002. 18. S. N. Demurie and G. De Mey, Parasitic Capacitance Effects of Planar Resistors, IEEE Transactions on Components, Hybrids, and Manufacturing Technology, 12, 3, 348351, 1989. 19. H. Patterson, Modeling Lossy Transmission Lines from S-Parameter Data, Microwave Journal, 36, 11, 96104, 1993. 20. M. J. Deen and M. Urteaga, Modeling of Passive Microwave Circuit Elements, Technical Report to Nanowave Technology, Etobicoke, Ontario, 140 pages (May 1999). 21. R. K. Hoffmann, Handbook of Microwave Integrated Circuits, Artech House, Norwood, MA. 22. E. Hammerstad and O. Jensen, Accurate Models for Microstrip Computer-aided Design, In IEEE MTT-S International Microwave Symposium Digest, pp. 407409, 1980. 23. E. Yamashita, K. Atsuki, and T. Ueda, An Approximate Dispersion Formula of Microstrip Lines for Computer-Aided-Design of Microwave Integrated Circuits, IEEE Transactions on Microwave Theory and Technology, MTT-27, 12, 10361038, 1979. 24. M., Kirschning, and R. H. Jansen, Accurate Model for Effective Dielectric Constant of Microstrip with Validity up to Millimetre Wave Frequencies, Electronics Letters, 18, 6, 272273, 1982. 25. D. M. Pozar, Microwave Engineering, 2nd ed., Wiley, New York, 1998. 26. R. Faraji-Dana and Y. L. Chow, The Current Distribution and AC Resistance of a Microstrip Structure, IEEE Transactions on Microwave Theory and Techniques, Electronics Letters, 38 9, 1268 1277, 1990. 27. Z. Wang, M. J. Deen, and A. Rahal, Accurate Modelling of Thin-Film Resistor up to 40 GHz, In 32nd European Solid-State Device Research Conference (ESSDERC 2002), Firenze, Italy, pp. 307310, 2426 September, 2002.

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MODELING OF INTEGRATED INDUCTORS AND RESISTORS

APPENDIX: CHARACTERISTICS OF MICROSTRIP LINES The microstrip line has been used extensively in microwave circuits as a transmission line for a wide range of applications because it is easily made using standard photolithographic fabrication technology. The characteristics of microstrip lines are the basis for modeling thin-film resistors (TFRs), spiral inductors, and through-substrate vias. There are numerous publications dealing with the analysis, design, and applications of microstrip lines [21,22]. The resistor layer of a TFR can be assumed to be a lossy microstrip line; the spiral inductor can be decomposed into a few segments of microstrip line and the via pad can be treated as a short piece of microstrip line. The properties of microstrips are determined by the characteristic impedance ZL, the effective dielectric constant eff, and the attenuation factor c [21]. A MHMIC microstrip line is shown in Figure A.1. It consists of a thin strip of conductor separated from a ground plane by a dielectric substrate. The conductor strip is defined by its width W and thickness t. The ground plane is completely metalized to a thickness t. The substrate is described by its thickness h, relative permittivity r, and dielectric loss factor tan For MHMIC, the substrates are typically made of alumina (Al2O3) with thickness h of 0.254 mm (10 mil), 0.381 mm (15 mil), or 0.635 mm (25 mil). Metal film of t = 5m is used for the microstrip and ground plane. r is 9.9 and tan is 0.0001. A.1 Characteristic Impedance ZL and Effective Dielectric Constant eff under Static TEM Approximation Because a microstrip line is surrounded by an inhomogeneous dielectric (Al2O3 and air), it is incapable of supporting a pure transverse electromagnetic mode (TEM) wave. The fundamental mode of a wave propagating in a microstrip is hybrid. However, the longitudinal electric EL and magnetic HL fields are small compared to transversal electrical ET and magnetic HT fields at low microwave frequencies.

Figure A.1

Microstrip configuration [21].

APPENDIX: CHARACTERISTICS OF MICROSTRIP LINES

285

Therefore, the microstrip line can be analyzed under static TEM approximation at low microwave frequencies. The upper frequency at which static approximation can be used in practical circuit designs is given empirically by [21] 21.3 fstat = [GHz] (W + h) + 1 r (A.1)

where W and h are in mm. Approximate formulas for the circuit parameters of a microstrip can be derived by various methods [21,22]. Among these approaches, Hammerstad and Jensen produced highly accurate equations for ZL0 and eff of microstrips by functional approximations of analytical equations. ZL0 is defined as the characteristic impedance of a microstrip without substrate (r = 1) for zero conductor thickness and is given by F1h 0 + (2 h /W )2 ZL0 = ln + 1 2 W

(A.2)

with F1 = 6 + (2 6)e(30.666h/W)0.7528 (A.3)

The effective eff of microstrip without substrate (r = 1) for zero conductor thickness was derived by functional approximations of numerically calculated values from the static Greens function method [21]:

r + 1 r 1 10h eff = + 1 + ab 2 2 W

(A.4)

with W 2 (W/h)4 + 52h 1 a = 1 + ln 49 (W/h)4 + 0.432 and

W 1 + ln 1 + 18.7 18.1h

(A.5)

r 0.9 b = 0.564 r + 3

0.053

(A.6)

Due to the effect of the finite conductor thickness of the microstrip, a concept of equivalent width Weff0 was used [22]: 4e t Weff0 = W + ln 1 + 2 t/h coth (6 .5 1 7 W /h)

(A.7)

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MODELING OF INTEGRATED INDUCTORS AND RESISTORS

For a microstrip with substrate (r > 1), the equivalent width is given as [22] 1 4e t 1 1 + Weff = W + ln 1 + t/h coth2(6 .5 1 7 W /h) 2 cosh 1 r

(A.8)

Finally, the characteristic impedance and effective dielectric constant for finite conductor thickness are given as [21] Weff ZL0 , t = 0 W t Weff h ZL , , r = ZL , t = 0, r = h h h Weff eff , t = 0, r h

(A.9)

W t eff(, , r) = h h

Weff0 ZL0 t = 0 h, Weff ZL , t = 0, r h

Weff = eff , t = 0, r h

Weff0 ZL0 , t = 0 h Weff ZL , t = 0 h

(A.10)

A.2 Dispersion Models of Effective Dielectric Constant eff and Characteristic Impedance ZL Because the wave propagating in a microstrip is intrinsically dispersive, the characteristic impedance ZL and effective dielectric constant eff are frequency dependent. Therefore, the dynamic analysis method is required for the calculation ZL and eff above the upper static approximation frequency fstat. Approximate formulas for the circuit parameters for microstrip can be derived by various methods [21,23,24]. Among these approaches, Yamashita et al. published a dispersion model that describes the frequency dependence of eff [23]:
0 ) r ef f( eff(f) = + ) ef f(0 1.5 1 + 4F

(A.11)

with W 4h 1 r F = 0.5 + 1 + 2 log10 1 + 0 h

(A.12)

where 0 is the wavelength in free space, eff(0) is the static effective dielectric constant given by Equation A.4.

APPENDIX: CHARACTERISTICS OF MICROSTRIP LINES

287

More accurate dispersion equations for effective dielectric constant are given by Kirschning and Jansen [24]:

r eff(0) re( f ) = r 1+P

P = P1P2[(0.1844 + P3P4)10fh]1.5763

(A.13) (A.14)

0.525 W ] 0.065683e8.7513(W/h) (A.15) P1 = 0.27488 + [0.6315 + h (1 + 0.157 fh)20 P2 = 0.33622(1 e0.03442r) P3 = 0.0363e4.6(W/h)[1 e(fh/3.87)4.97] P4 = 1 + 2.751[1 e(r/15.916)8] (A.16) (A.17) (A.18)

where h is in cm and f is in GHz. The accuracy of this expression is better than 0.6% in the range 0.1 W/h 100, with 0 h/0 0.13 and 1 r 10. The closed-form expression describing the effect of frequency on the characteristic impedance ZL is given by [21]

eff( f ) 1 ZL( f ) = ZL0 eff(0) 1

(f)
eff

eff(0)

(A.19)

The frequency dependence of effective dielectric constant and characteristic impedance are shown in Figure A.2. In this figure, the effective dielectric constant increases with frequency.

80

10.0 9.5 9.0

75 70 65 60 55 50 45 1E9 1E10 1E11

8.5 8.0 7.5 7.0 6.5 6.0 5.5 5.0 1E12

Frequency (Hz)

Figure A.2 The frequency-dependent effective dielectric constant and characteristic impedance for a microstrip with W = 361 m, h = 381 m, and r = 9.9 (alumina).

Effective Dielectric Constant, eff

Characteristic Impedance ()

288

MODELING OF INTEGRATED INDUCTORS AND RESISTORS

A.3 Lumped-Element Model of a Microstrip Line A short piece of microstrip line of length z can be modelled as a lumped-element circuit, as shown in Figure A.3. Here, R is the series resistance per unit length in /m and it represents the losses of the conductor, L is the series inductance per unit length in H/m, G is the shunt conductance per unit length in S/m and it represents the losses of the substrate, and C is the shunt capacitance per unit length, in C/m [25]. If the length of microstrip line is of the same order as the wavelength or larger, a large chain of the circuit blocks in Figure A.3 are cascaded together to model the microstrip line. Usually, 100 circuit blocks are good enough to represent a onewavelength microstrip line. According to the transmission line theory, L and C of a low-loss microstrip line can be calculated from characteristic impedance ZL and effective dielectric constant eff:
ef f ZL L= c ef f C= cZL

(A.20)

(A.21)

A.4 Microstrip Losses There are four kinds of microstrip losses: conductor losses, dielectric losses, radiation losses, and leakage losses . Since the models discussed here are for applications below 40 GHz, the leakage losses and radiation losses can be neglected in alumina substrates. Therefore, only conductor losses and dielectric losses are discussed. Conductor Losses. The total conductor loss in a microstrip line is composed of two parts: the loss in the rectangular strip and the ground plane loss.

Rz

Ll

Gl

C l

Figure A.3 l.

Lumped-element circuit model for a short piece of microstrip line of length

APPENDIX: CHARACTERISTICS OF MICROSTRIP LINES

289

The DC resistance of a conductor is calculated from l RDC = Wt (A.22)

where is metal conductivity, and l, W, and t are its length, width, and thickness, respectively. At high frequencies, the skin effect due to magnetic fields causes nonuniform current flow in the conductor, causing most of the current to flow near the surface of the metal traces, as shown in Figure A.4. The resistance can be calculated from l l Rskin = = 2Weff 2W(1 et/2) where is the skin depth of the metal given by (A.23)

(A.24)

eff is the effective skin depth. The derivation of eff is illustrated in Figure A.5, in which the area under solid line is the same as the area under the dashed line. The solid line represents the current density inside the conductor. It is well known that the current density decreases exponentially inside the metal. At DC and low frequencies, is much larger than conductor thickness t, so that eff is approximately equal to t/2, and Rskin is equal to the DC resistance. At high frequencies, is much smaller than conductor thickness t, thus eff is approximately equal to . Therefore, by introducing eff, Equation A.23 can model the resistance of the conductor from DC to microwave frequencies.

eff

E eff

Figure A.4

Skin effect in a microstrip.

290

MODELING OF INTEGRATED INDUCTORS AND RESISTORS

J J0 eff =
t2

e
0

dx = ( 1 e

t 2

J0 e

eff
Figure A.5

t /2

Metal Thickness

Illustration of the effective skin depth.

The distribution of current density in microstrip structure is shown in Figure A.6. The exact analytical expression for the distribution is very difficult to determine. Therefore, curve fitting techniques are typically used to determine this distribution. A curve-fitted approximation formula for ground plane AC resistance is given by [26] t Rg = 0.55RDC (1 eW/1.2h) (A.25)

J(x) bottom of strip

top of strip Ground plane

-W/2

W/2

Figure A.6

Microstrip surface current density distribution [26].

APPENDIX: CHARACTERISTICS OF MICROSTRIP LINES

291

Dielectric Losses. The substrate has a dielectric loss factor tan The dielectric losses can be represented by the shunt conductance per unit microstrip length G, given by G = C tan (A.26)

where C is the capacitance per unit length. Because the loss factor tan of alumina substrate is smaller than 0.001 at frequencies below 40 GHz, the dielectric loss is much smaller than the conductor loss. Therefore, the dielectric loss is neglected for the passive devices on an alumina or other insulating substrate.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 12

OTHER APPLICATIONS AND INTEGRATION TECHNOLOGIES

ELIZABETH LOGAN, GEERT J. CARCHON, WALTER DE RAEDT, RICHARD K. ULRICH, AND LEONARD W. SCHAPER

The use of integrated passives offers wide capability for the realization of a variety of highly compact, lightweight, and high-performance devices. In this section, a number of examples of both demonstrators and commercial products will be discussed, which will clearly show the potential of the integrated passives approach in a broad range of applications. Indeed, as some of these examples will show, the passive components can be successfully used in devices from portable phone and Bluetooth applications (in the 12 GHz frequency range) up to Ka-band satellite applications (30 GHz and higher), as well as for simpler filtering and termination. The main driving forces for integration are primarily those of reduced system cost, smaller form factor and mass, improved reliability, and increased design flexibility. Passive integration, in and of itself, brings little to the table in the way of new and novel circuit configurations and so replacement of surface-mount with integrated components often tends to be close to a one-to-one trade. The main exception to this rule is decoupling (see Chapter 9), in which the close proximity of the capacitors to the circuitry and active elements can lead to greatly reduced series inductance and improved electrical performance. At higher frequencies, where it is often not possible to use surface-mount components, integrated passive components can also provide unique solutions. In general, however, typical devices made from integrated passives will have a similar schematic and number of components to the equivalent device made from discretes. An examination of the commercialized surface-mount integrated passive arrays and networks described in this chapter supports this; it is expected to also be true once integrated passives migrate into the main boards. Although surface-mount discretes are available in a greater range of values and tolerances, the advantages of integration often outweigh any compromises a designer may make in forgoing the convenience of an extensive discrete product catalog. Moreover, when a suitable design library with high-frequency models is available,
293

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OTHER APPLICATIONS AND INTEGRATION TECHNOLOGIES

the device design cycle becomes fast and reliable, leading to efficient solutions for a variety of analog applications within the component values and tolerances available from the integrated passive technology. When devices are designed in this way, it is often found to be possible to avoid the use of expensive, tightly toleranced components in order to meet the performance specification. From a manufacturing perspective, the simplification of the circuit assembly and reduced conversion costs may also favor the use of smaller numbers of integrated devices rather than the corresponding discretes. These devices can be custom sized and, therefore, have the potential to replace groups of discretes that have been arranged in series or parallel to achieve a specific component value, or to provide multiple terminations or filters. To date, integrated passives have found commercial application in the form of surface-mounted modules or devices containing multiple passives of the same kind (integrated passive arrays) or of different kinds (integrated passive networks) that are installed as a unit on the surface of the primary interconnect board. However, very few main boards manufactured today utilize integrated passives, which reflects an early stage in the progression of a technology seeking to enter a well-established industry. It is hoped that, ultimately, increasing numbers of potential board-level applications will be realized by matching them to some of the R, C, and L component technologies described earlier in this book. A survey of the integrated passive literature shows that most papers in the journal and proceedings literature are concerned with materials and processing and utilize multicomponent devices only for the purpose of demonstrating the fabrication technologies. Although demonstration circuits may be complex, the commercialized components, with a few exceptions, usually involve simple RC filters, terminators, or voltage dividers. This chapter is divided into two parts, starting with an overview of some of the devices that have been demonstrated in the literature and concluding with a description of some of the types of devices and technologies currently available from vendors. 12.1 DEMONSTRATION DEVICES FABRICATED WITH INTEGRATED PASSIVES 12.1.1 RC Terminators Signal line terminators are used in large numbers on high-speed digital and analog circuit boards. For instance, a 32-wide parallel port may require 32 terminators, each consisting of a resistor and a capacitor in a small area of the board. RC terminators are, therefore, very attractive candidates for passive integration. In a circuit, if the rise/fall time of the signal is faster than twice the time of flight along the transmission line, then reflections and other signal distortions can occur that may result in errant switching. A termination resistor with a value matching the line, typically 50 , will decrease or totally prevent these reflections [1]. AC termination consists of a capacitor in series with the termination resistor to form the configuration shown in Figure 12.1. The advantage of this over simple resistive termination (DC termination) is that there is no loss of direct current to ground.

12.1 DEMONSTRATION DEVICES FABRICATED WITH INTEGRATED PASSIVES

295

Figure 12.1 flection.

Resistor and capacitor termination of a transmission line to prevent signal re-

The value and tolerance of the passives are not critical but must meet some general criteria. Effective termination is assured if their time constant is much larger than time of flight down the transmission line [2]: CTRT > 25 tf where CT = terminating capacitance, F RT = terminating resistance, tf = time of signal flight down the transmission line, sec Increasing the capacitor value increases the undesired power dissipation, whereas decreasing it can lower the RC time constant and make the termination less effective. 50 pF and 50 are commonly used, for an RC of 2.5 ns, which is the time of flight through about 15 inches of interconnect line. Integrated 100 pF plus 50 RC terminators have been fabricated using only two deposited metals: Ta and Cu [3, 4]. The Ta may be used as the capacitor bottom plates, the resistor, and as the source of Ta2O5 dielectric for the capacitor. Cu is used as the top plates for the capacitors, and also serves as the contacts. Utilizing one material for multiple purposes reduces the required number of masking steps to only two. Forty of these terminators are shown in Figure 12.2 along with a schematic of the layout and circuit. In order to form a 100 pF capacitor in series with a 50 resistor, two 200 pF capacitors were fabricated at either end of the structure so that their top plates can serve as terminal pads. These terminators were fabricated with dimensions of 34 by 18 mils, placing them inside the footprint of an 0402. In order to achieve the required capacitor value in this area, a capacitance density of 140 nF/cm2 was required, which was produced by a film of tantalum oxide 1520 thick. The 50 resistor was made from an extension of the sputtered Ta metal that makes up the bottom plates of the capacitors, which serves to connect the two bottom plates to put the capacitors in series. A large range of sheet resis-

296

OTHER APPLICATIONS AND INTEGRATION TECHNOLOGIES

Figure 12.2

Forty integrated RC terminators in a 20 mm2 area.

tance may be exhibited from sputtered Ta thin films depending on the crystal structure. The common phase of Ta in bulk form is bcc, with a resistivity of 13 -cm, but thin-film bcc Ta has a resistivity as high as 65 -cm. Thin-film Ta can also be found in a beta phase that is tetragonal in structure with a resistivity of 180 -cm. This phase is not stable in bulk form but is commonly found as the product of sputtering [5, 6]. In order to achieve 50 at a sheet resistance of 0.83 /square, 60 squares were required. At 180 -cm, this would require a Ta film 2.16 m thick. To produce a Ta2O5 dielectric layer 1520 thick, 610 of Ta metal is consumed. The bottom plate of the capacitor therefore ended up being 21,600 610 = 20,990 = 2.10 m thick. Glass or other highly insulating substrates are preferred for this application over silicon because of the possibility of capacitive coupling to the conductive Si. The cross section of this structure is shown in Figure 12.3.

Figure 12.3

Cross section of an integrated RC terminator.

12.1 DEMONSTRATION DEVICES FABRICATED WITH INTEGRATED PASSIVES

297

Figure 12.4

Impedance analyzer scan of an integrated RC terminator.

The magnitude of impedance versus frequency is shown in Figure 12.4. The device exhibits series R/C behavior as desired. Figure 12.5 shows two RC terminators fabricated by Integral Wave Technologies for NASAs Langley Research Center with the same resistor material but two different capacitor dielectrics. The high-k material allows for a smaller footprint, but probably at higher cost since low-k interlevel dielectrics are usually already present in the board. 12.1.2 Voltage Dividers Integrated voltage dividers can be made in compact footprints by using combinations of the same resistor material in series and in parallel. Figure 12.6 shows some

Figure 12.5

Integrated RC terminators with low- and high-k dielectric capacitors.

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Figure 12.6

Low-ratio voltage dividers.

low-ratio dividers that consist of two CrSi resistors with a tap in between them. Figure 12.7 shows a 10/1 divider and a portion of a nearby 100/1 divider that can be seen at the right. Vin would be across the top and bottom pads and Vout would be from the middle and bottom pads. The division ratio for this sort of layout is 1 Vout = Vin 1 + NpNs where Np = number of resistors in parallel Ns = number of resistors in series The ohms/square of the resistor material is irrelevant, but it must be the same for all parts of the divider to deliver accurate division ratios. Of course, for a given geometry, higher resistivities will result in less current draw over the Vin terminals. 12.1.3 Reliability Test Structures Thin-film dielectrics are capable of much higher specific capacitances than thick films but will be more prone to mechanical damage. The highest-valued thick-film materials in use today consist of ferroelectric particles, such as barium titanate, dispersed in a polymer matrix and applied to a minimum of a little less than a mil thick. These can provide maximum values of around 30 nF/cm2, which is enough to replace only the smallest capacitors on a typical board and provide some decoupling. Thin-film paraelectrics can deliver about an order of magnitude more capacitance, but are typically less than a micron thick and are composed of various metal oxides, which are relatively brittle. Because they are thinner and more brittle than

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Figure 12.7

A 10/1 integrated voltage divider.

polymers, there is a potential problem with the yield and reliability of these structures during board fabrication and use. A 100 nF capacitor made from anodized Ta2O5, sputtered Al2O3, or PECVD Si oxide or nitride might require around a cm2 of area but would only be 1000 thick, an aspect ratio of 100,000. Something this thin would have no appreciable strength compared to the forces of board lamination, flexure, and CTE mismatch so it is not certain that these materials could be used in laminated polymer boards or even as build-up structures on more forgiving substrates such a glass or Si. Figure 12.8 shows a schematic of a test structure for evaluating the reliability of stacked thin-film capacitors and resistors built up over a Si substrate. The bottom layer consists of alternating 0.25 0.25 cm capacitors made from 2000 of Ta2O5 and 4 m BCB along with sputtered CrSi resistors. The second layer provides the same types of structures positioned to overlap the bottom layer devices in various combinations, and the top layer consists of Cu pads for placing an underfilled flip chip over these. This project was commissioned by Erik Brandon of NASAs Jet Propulsion Laboratory; the structure was designed by Richard Ulrich and fabricated by Matt Leftwich of Integral Wave Technologies. The finished product is shown in Figure 12.9, magnified to emphasize the overlap of the various capacitors, resistors, and the chip. The structure will be subjected to temperature shock (85/85), hightemperature storage, and other standard reliability tests in order to evaluate the viability of stacked large area, thin-film devices. 12.1.4 Filters and RF Devices Filters are by far the most widely used demonstration vehicle for integrated passive technologies in the literature and many examples are available for those wishing to

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Figure 12.8

Schematic of a three-layer reliability test structure.

Figure 12.9

The fabricated test structure before the flip chip was mounted.

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implement them. [713]. Filters and signal conditioners, as discussed later in this chapter, make up a large fraction of commercial integrated passive network sales, which are in the form of surface-mounted modules. Figure 12.10 shows a typical examplea low-pass filter designed by one of the editors of this book (Ulrich) and made by Integral Wave Technologies for NASAs Langley Research Center, demonstrating the advantage of being able to fabricate components with exact values. A thin-film technology with integrated passive components can be used in many applications. For most RF applications, narrowband bandpass filters (BPF) are needed. The following examples show bandpass filters operating in three different frequency bands: 2.45 GHz (ISM band), 15 GHz (Ku band), and 30 GHz (Ka band). Most of the filters are based on a two-coupled resonator topology, such as that in Figures 12.11 and 12.12. For the 30 GHz filter, a topology based on coupled transmission line sections is also discussed. The filters described below also provide insight into the different design approaches/constraints applicable for the different frequency bands.

Figure 12.10

Low-pass integrated filter.

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Figure 12.11 Schematic representation of the two-coupled resonator bandpass filter topology. (Courtesy of IMEC.)

The MCM-D technology used for the fabrication of the following devices has been described in Section 10.4.3. More information on the technology may be found in the references [14, 15]. 12.1.4.1 Bandpass Filters. As illustrated in Chapter 10, the realization of low-loss filters requires the availability of high-quality (Q-factor) passive components, especially high-quality inductors, as these are quite often the performancelimiting devices. In the following examples, some typical bandpass filters (BPFs) are designed and implemented at various frequencies. [16, 17]. A schematic of a 2.45 GHz BPF is shown in Figure 12.11 and the fabricated device in Figure 12.12. The circuit is based on the two-coupled resonator topology consisting of two parallel resonator circuits (L1, C1 and L2, C2) that are capacitively coupled by capacitor C3. This bandpass filter makes use of two 3.9 nH spiral inductors that have a maximum Q-value of 74 at 6 GHz; at the filter design frequency of 2.45 GHz, the Qvalue is about 45. The high Q-values of the spiral inductors make it possible to achieve narrowband, low insertion loss filters. The measurements of the performance of such a filter are shown in Figure 12.13. For a bandwidth of 100 MHz, at a center frequency of 2.45 GHz, an insertion loss below 2.5 dB was obtained. The return loss at both ports is better than 20 dB. The performance of this filter may be

Figure 12.12 2.45 GHz bandpass filter, based on the two-coupled resonator topology. (Courtesy of IMEC.)

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Figure 12.13 Measured insertion loss [S21 (top)] and return loss [S11(bottom)] of the 2.45 GHz filter. For a 100 MHz at 2.45 GHz, the insertion loss is better than 2.5 dB. (Courtesy of IMEC.)

further improved by increasing the thickness of the Cu used to form the spiral inductors. 15 GHz and 30 GHz band pass filters, based on the two-coupled resonator topology, are shown in Figure 12.14. For both implementations, the inductances L1 and L2, like those in Figure 12.11, are formed by the shunt-shorted transmission lines, whereas the capacitances to ground (C1 and C2) are realized by a combination of BCB capacitors and the parasitic capacitances of the T junctions. For the 30 GHz filter, only the parasitic capacitance of the T junction is used to resonate with the shunt stubs. The measured and simulated performance of the filters are shown in Figure 12.15. Very good agreement is observed over a wide frequency band and a low insertion loss of 1.75 0.25 dB was obtained over the 14.316.3 GHz band, whereas 2.3 0.2 dB was obtained over the 29.633.1 GHz band.

dB from S21

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(a)

(b) Figure 12.14 A 15 GHz (a) and a 30 GHz (b) bandpass filter. The location of the components from the schematic, depicted in Figure 12.11, are also indicated. (Courtesy of IMEC.)

Other topologies may also be used for the realization of bandpass filters. For example, the 30 GHz filter shown in Figure 12.16 is based on multiple coupled transmission line sections using interdigitated capacitors, which are very well suited for the implementation of small capacitance values. Moreover, their values are very insensitive to BCB thickness variations, in contrast to parallel plate capacitors, in which the capacitance is a strong function of dielectric thickness. In an interdigitated capacitor, the capacitance value is mainly determined by the lateral dimensions, especially the gap between the fingers, which may be very accurately controlled by the Cu electroplating process. For narrow gaps, the thickness of the Cu also becomes important; however, this factor may be very accurately defined. This filter has a measured insertion loss of 3 dB over the 28.630.6 GHz frequency band, and a return loss better than 15 dB, both at input and output. 12.1.4.2 Broadband Couplers. The versatility of the technology is further illustrated by a high-performance broadband coupler, such as that shown in Figure 12.17. Over a band of 700 MHz centered at 1 GHz, an insertion loss better than 3 dB was achieved together with a phase error smaller than 3 degrees and an input/output return loss below 14 dB.

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(a)

(b) Figure 12.15 Measured return loss () and insertion loss (), together with simulated return loss (b) and insertion loss (), of the 15 GHz (a) and 30 GHz (b) bandpass filter. (Courtesy of IMEC.)

This broadband performance was achieved due to the successful use of coupled spiral inductors. Other examples of integrated couplers at 14 GHz and 30 GHz can be found in the literature [1820]. 12.1.5 Functional Modules and Subsystems It is clear from a preliminary analysis of the requirements of RF and wireless applications that integrated passive technology can have a significant impact on the implementation of more complex wireless systems. The combination of the large passive-to-active ratios and large overall numbers of passive circuit elements, as outlined in Chapter 1, combined with the lower ranges of component values, make

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Interdigital capacitors

Figure 12.16 A 30 GHz (Ka band) bandpass filter realized using multiple capacitively coupled transmission lines. Interdigital capacitors are used to realize the coupling. (Courtesy of IMEC.)

wireless applications an appealing market for many integrated passives technologies. The fact that most of these applications are under severe size and weight constraints also helps to drive the systems manufacturers to seek ever better ways to include greater functionality in a smaller volume. This combination of factors resulted in many of the early demonstrations of passive integration being focused on the fabrication of wireless functional modules and subsystems. 12.1.5.1 Bluetooth Wireless Systems Implementations. Many manufacturers and researchers have turned to the emerging Bluetooth market for their first demonstrations of the capabilities of integrated passives. Teams from a number of research centers and industry have published accounts of the fabrication of Blue-

Figure 12.17 IMEC.)

1 GHz broadband (0.7 GHz) 90 degree combiner (3 2 mm2). (Courtesy of

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tooth modules using integrated passives technology. Examples include both lowtemperature cofired ceramic (LTCC) and thin-film build-up structures. The LTCC approach has been taken by a number of groups [22, 23] and is a logical extension of the technology used by Ericsson to demonstrate the first commercially available Bluetooth module [24]. The LTCC substrate includes a number of integrated passive components, which make up sections of the Bluetooth circuit such as the balun, output matching circuit, and filters. The active components, such as the transceiver chips, are mounted onto the LTCC. In many cases, additional passive devices, which for reasons of tight tolerance or large value could not be embedded within the LTCC layers, are mounted onto the LTCC substrate in order to complete the circuit. The PRC group at Georgia Institute of Technology also demonstrated that a 3-D loop antenna could be added to the module. Companies such as National Semiconductor Corp. and Murata Manufacturing Co. Ltd., have since commercialized Bluetooth modules based on LTCC technology, and a brief description is included in the section on commercialized products. A different approach was taken by Intarsia Corporation which, in collaboration with Ericsson Mobile Communications (now Ericsson Mobile Platforms), demonstrated a thin-film build-up version of a Bluetooth module. The module incorporated a Bluetooth single chip transceiver and wire-bonded active components for the VCO circuit, all mounted onto an integrated passive substrate. The integrated passive substrate was used to implement a receive matching balun for the on-chip LNA, a transmit matching balun for the on-chip PA, a resonant tank circuit for the 2.4GHz VCO, and a VCO loop filter. A wire-bonded version of the module, attached to a board for initial testing, is shown in Figure 12.18 [24]. This module, when tested for the first time, showed oscillation in the Bluetooth band and was measured with an output power that was close to specification, the slight shortfall being attributed to the initial design having been performed without accurate S-parameter measurements of the output flip chip.

Figure 12.18 Prototype thin-film-on-glass integrated passive Bluetooth module. (Courtesy of Intarsia Corp. and Ericsson Mobile Platforms.)

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In a later iteration, the RF filter and Tx/Rx switch were also added and the module was configured to be attached to the board using a solder ball or direct module attach (DMA) approach, further reducing the final module size. The DMA technology is analogous to direct chip attach, in which the device is mounted directly onto the circuit board by means of solder balls. In this case, the device itself forms the package, thus eliminating the additional costs and area of an extra level of packaging [25, 26]. The DMA version of the Bluetooth module is shown in Figure 12.19. Other demonstrations of integrated passive functional modules have been made by a number of organizations, using both LTCC and thin-film build-up technologies. One of the research groups active in this field is IMEC, based in Leuven, Belgium. They use passive components as a means to codesign active circuits together with thin-film passives in order to achieve more optimal (performance, cost, etc.) microwave integrated modules. Their technology is discussed in Chapter 10 and has been used to demonstrate numerous filter functions, as described earlier in this chapter. IMEC has demonstrated not only these simple filters but also more complex functional blocks, including a DECT VCO and a 5.2GHz wireless LAN LNA. [27, 28]. 12.1.5.2 WLAN Receiver Function. Figure 12.20 shows a low-noise amplifier (LNA) section for a 5.2 GHz wireless LAN. All passive components for matching and biasing are integrated into the MCM-D substrate. Bandpass filters are also included before and after the amplifier stage, for use in a superheterodyne architecture, making 23 integrated passives in total. The active device is a commercial GaAs pHEMT, flip-chip mounted on the MCM using gold stud bumps. The LNA was optimized for high gain performance: NF below 2.4 dB, gain of 12.9 dB, 1 dB compression point of 5 dBm at the input, and power consumption = 28 mW (14mA @ 2V).

Figure 12.19 Direct module attach version of the integrated passive Bluetooth module. (Courtesy of Intarsia Corp. and Ericsson Mobile Platforms.)

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(a)

Frequency (GHz)

(b) Figure 12.20 (a) Photograph and (b) simulated and measured performance of a 5.2 GHz wireless LAN LNA with integrated bandpass filters, realized in thin-film MCM-D. The module measures 7.0 5.1 mm2. (Courtesy of IMEC.)

Measurements of the module, including the bandpass filters, are also shown in Figure 12.20. The noise figure for the combined circuit now becomes 5.4 dB, with gain of 6.8 dB, input matching less than 9 dB, and output matching less than 15 dB. This performance is better than that which can be achieved with similar integrated solutions in silicon, including integrated bandpass filters. One can go a step further by codesigning the passive components of a function

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together with the active silicon chip. A trade-off between on-chip passives and high-Q passives on the embedded passive substrate can be easily made. Since the design of the whole module is done in the same design environment, with performance and cost optimization based on area, it can be done in a straightforward way. The result of such an optimization cycle is illustrated by the WLAN receiver function developed at IMEC and depicted in Figure 12.21. Filters, bias and matching networks, and the required high-Q inductors of the VCO tank are built on the thinfilm passives substrate, whereas the active BiCMOS die, which is flip-chip mounted, contains the LNA, the VCO, and the downconvertor mixer functions [29]. 12.1.5.3 Ku Band Subharmonic QPSK Modulator. The integration of thin-film passive components becomes even more attractive at microwave frequencies and the availability of a microwave model library [30] associated with this technology allows a MMIC (monolithic microwave integrated circuit) style design for more complex microwave circuits up to mm-wave frequencies. These powerful capabilities are illustrated by the design of the subharmonic QPSK modulator, shown in Figure 12.22 [31]. This I/Q linear vector modulator has been developed for VSAT (very small aperture terminals) applications with an RF output frequency of 1414.5 GHz. A subharmonic configuration has been used, which means that the I and Q baseband signals are mixed with the second harmonic of the LO frequency (LO = 77.25 GHz). The design band of the modulator was taken in the range 13.614.9 GHz. The architecture of the QPSK modulator and subharmonic mixer is shown in Figure 12.23. A 3 dB power splitter (Wilkinson power divider) delivers the LO input power to two identical subharmonic mixers (BPSK modulators), which multi-

Figure 12.21 Receiver section of a WLAN front-end consisting of a 0.8 m BiCMOS chip (LNA, mixer, VCO) with a size of 2 1.7 mm2, mounted on a thin-film passives substrate with high-Q passive functions (inductor for the VCOs LC tank, bandpass filters, and matching and bias networks). (Courtesy of IMEC.)

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Figure 12.22 IMEC.)

17 mm by 7 mm, 14 GHz subharmonic QPSK modulator. (Courtesy of

(a)

(b) Figure 12.23 (a) Top-level architecture of a subharmonic linear vector modulator. (b) Subharmonic mixer architecture. (Courtesy of IMEC.)

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ply the I and Q of the IF input signal with the second harmonic of the LO signal. The resulting RF signal is combined at the output with a 90 phase shift between the two branches. For the latter, a quadrature Lange coupler has been selected due to its good isolation, amplitude, and phase balance. Moreover, the structure is not prone to BCB-thickness variations as compared to other quadrature coupler realizations [19]. Each subharmonic mixer consists of a beam-lead antiparallel diode pair (HSCH9251) and four filters: LO filter, RF filter, IF filter, and LO block filter. The resulting chip, shown in Figure 12.22, contains more than 160 standard passive library components such as transmission lines, resistors, capacitors, inductors, and discontinuities. The measured characteristics are summarized in Table 12.1, together with the initial specifications put forward in the design phase. From this table, it can be concluded that all the important specifications are met, in a frequency band that is wider than specified. Only the return loss at the LO port was slightly above the specification, due to some BCB thickness variation, however, this parameter is only of minor importance for the specific design. It should be noted that these results were obtained from a first design and fabrication cycle and it is clear that there is tremendous potential for realizing highperformance, ultrasmall subsystems and modules by means of these technologies, together with their associated component design libraries. Although most of these more complex implementations remain in the realm of the demonstrator module, many less complex integrated passive functions have made the leap from demon-

Table 12.1 Parameter

List of the QPSK modulator specifications versus measured characteristics Specification at 77.25 GHz < 2 < 0.2 dB > 25 dB 10 dBm 40 dB 25 dB 8 Mbps 18 dB 15 dB 0.2 dB image > 25 dB < 3 dBpp Measured < 2 over 6.77.6 GHz < 0.2 dB over 6.77.6 GHz > 25 dB over 6.77.6 GHz > 32 dB in the VSAT band 10 dBm 34 dBa at max output power 43 dB > 100 Mbpsb 18 dB 13 dBc 0.2 for BPSK, 0.25 QPSK image > 25 dB 1 dB Result OK OK OK OK OK(1) OK OK(2) OK (OK)(3) OK OK OK

Vector phase error Vector magnitude error Image rejection Output level Harmonics Carrier rejection (2 LO) Modulation bandwidth RF return loss LO return loss Conversion flatness Input power variation 1.5 dB Output level variation

Source: Courtesy of IMEC. a The harmonic specification can be met by slightly lowering the output power. This specification is not heavily related to design, but more to the specified diodes. b The 3 dB bandwidth of the QPSK output power is 2.4 GHz. c 20 dB was simulated in the original design. This dropped, in simulation, to 14 dB due to the increased BCB thickness on the specific run.

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strator to commercial product. The following section gives a brief overview of some of the commercially available products and their associated technologies.

12.2 COMMERCIALIZED THIN-FILM BUILD-UP INTEGRATED PASSIVES A number of companies have adopted the approach of using thin-film build-up technology to fabricate integrated passives. This form of approach offers a means of building fine geometry, tightly toleranced components using readily available processing equipment and materials already in use within the integrated circuit industry. This combination of factors has led to thin-film build-up, along with LTCC, being one of the more widely adopted of the integrated passive technologies. Although the details vary, most of the thin-film build-up technologies focus around a common set of features. An inorganic substrate supports two or more metal layers, separated by a thick organic dielectric. Thin dielectric and resistive films are formed and patterned to provide the resistor and capacitor elements, and the inductors are created by patterning the metal layers. The process used by IMEC was described in Chapter 10 and some of the other commercially available technologies, together with their associated products, are briefly described in the following sections. A wide variety of surface-mount arrays and networks are available in quantity, mostly from companies that have long produced passive components such as AVX, KOA, Vishay, Bourns, etc., but also from companies that specialize more in integrated passives like California Micro Devices, Viking Tech, Evox Rifa, Kyocera, CTS, Integral Wave, and Intarsia. These products extend over almost every possible RC combination, along with some inductors and, if the substrate is Si, diodes and even transistors. Available configurations include clock terminators, all manner of filters, voltage dividers, AC and DC bus terminators, clock terminators, ladder networks, and many others, some with built-in diodes for ESD protection. The products offered cover a continuous range of configurations from simple single-component discretes, which are not integrated passives at all, through passive arrays and networks, to devices that are essentially simple analog ICs with large-valued passives. Similarly, the packaging for these devices ranges from 0402, through chipscale packages, to quad flat packs. The upper end of this range falls into these NEMI definitions: Integrated Passive DevicesMultiple passive elements of more than one function and possibly a few active elements, such as diodes for ESD protection, in a single SMT or CSP case. Supercomponents or Functional ModulesModule-like packages that incorporate 20 or more passives and provide for active mounting on its surface. Examples include VCO, Bluetooth, and GPS. Another appropriate name for these devices, from California Micro Devices, is Application Specific Integrated Passive (ASIP). This continuum of products is a

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blessing for designers who are aiming for small form factor and for manufacturers who want to produce more powerful systems without expanding their operation. The word continuum is applicable here since surface-mounted devices are available with almost any number and configuration of integrated passives and, with active devices thrown in, can be almost complete systems unto themselves. Since the majority of the cost for installed discrete passives is from conversion, the savings from even simple arraying can be significant. A four-unit capacitor or resistor array requires one-fourth the conversion cost of four individual devices. The conversion cost for arrays with internal connections is about the same as if they were all terminated to the outside, but is still lower than mounting the components individually, and there are fewer solder joints to fail. Many resistor and capacitor arrays are made the same way as individual units, with fired oxide resistors and electrolytically processed Ta and Al or ferroelectric dielectrics. However, capacitor arrays that are optimized for low inductance may have unique internal structures that guide the current in such a way as to cancel out internal inductance. On the higher end, integrated passive devices (IPDs) and functional modules are commonly fabricated on Si substrates using either sputtered TiNx or CrSi resistors along with SiOx or SiNx capacitors. The advantages of fabricating on Si include: The manufacturing infrastructure is in place since it uses, essentially, 30-yearold technology and geometries. In most cases, cast-off front end equipment will suffice. The substrates are plentiful. If there are no diodes or transistors, then the purity and doping of the substrate may be unimportant, particularly if a field oxide is grown first. Glass panels may also be used, especially if the substrate needs to be fully insulating. Si is very smooth so the passive component yields are high and tolerance is not degraded. It can withstand high-temperature processing. The tolerances of thin-film processes are usually much better than for thick film. Schottky, zener, and varactor diodes can be added to the systems for rectification, filtering, and ESD protection. The ability to add transistors creates the possibility of the devices being selfcontained functional modules. If Si is used as the substrate for integrated passives, it should be remembered that it is a conductive material so there exists the potential for capacitive coupling between components and also for interference with magnetic fields of integrated inductors, which can lower their performance. Using glass substrates avoids these problems. 12.2.1 Capacitor Arrays Arrays of two and four capacitors per package with the same or different values are widely available and in common use in packages as small as 0402. Each individual

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capacitor can be terminated to the outside, or they can be internally connected in parallel to provide lower ESR and ESL. If they have different values, they can be internally connected in order to broaden the range over which they have low impedance and, hence, will decouple more effectively than would any single capacitor in the same package. The line between surface-mount single passive units and surface-mount integrated passives can be blurred in the case of low-inductance capacitors. The unit may function as a single capacitor, but may have a more complex internal structure consisting of multiple capacitors and plates designed to lower the total inductance of the part. In the traditional end-terminated SM capacitor, the current enters one end of the component and exits the other, always flowing in the same direction internally, as shown on the left side in Figure 12.24. As described in Chapter 8, the length of the component becomes part of the loop so that larger cases result in capacitors with more parasitic inductance. Some capacitors sold and mounted as individual units are actually arrays that have internal plates and contact configurations so that the current is opposed internally, resulting in opposing, self-canceling magnetic fields and lower inductance, as shown on the right in Figure 12.24. Additional strategies to lower inductance include the use of multiple contacts and low profiles. [32]. These can have very low parasitics, down to less than 10 pH for the new HiFLI decoupling capacitors from AVX. It should be noted that using an array of multiple contacts on the bottom of a discrete SM capacitor forces the board to use an array of contacts, which results in a lower-inductance arrangement at the board level and creates opposing fields between them. Still, capacitors integrated into the primary interconnect substrate will always have the potential to be lower in inductance because they are in the plane of the interconnects, have much lower component profiles, and have inherent self-canceling fields. 12.2.2 Termination AVX has developed a surface-mounted integrated device in which the resistance and capacitance are distributed through a multilayer hybrid structure as shown in

Figure 12.24

High- and low-inductance configurations for surface-mount capacitors.

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Figure 12.25. It consists of an interdigitated capacitor in which the electrodes are made of resistive RuO2 and function simultaneously as a distributed resistor at the 100 level. This oxide is used because it has a combination of high conductivity and stability and a proven track record in ceramic substrates. The dielectric is composed of a glass-loaded ceramic material, so the mechanical and thermal properties of the resistor and capacitor elements are well matched, leading to good reliability. [33, 34] This has the advantage of small size and parallel integration, but may take some design iteration to get the resistance right since current is not the same through all parts of the electrodes. The actual performance is close to ideal RC series behavior, but the resistive floor falls off slightly, 35% per decade, due to the distributed nature of the resistors. This is predictable and can be modeled. 12.2.3 Intarsia Perhaps the most far-reaching production technology for integrated passive networks came from Intarsia, during the period between their establishment as a joint effort between Dow Chemical and Flextronics in 1997 and their closing in 2001. Intarsia manufactured a variety of filters, terminators, amplifiers, and other integrated passive modules on 350 400 mm glass panels using Al and Cu interconnects and photo-BCB insulator. The resistors were reactively sputtered TaNx, deposited to give either 10 or 100 /square films, depending upon the application. Three different capacitor materials were used in the technology. The larger-value capacitors were formed from anodized Al, about 1500 thick, to give a capacitance density of 50 nF/cm2. A Si3N4 film technology was also added, giving a capacitance density of 10 nF/ cm2, which enabled tighter tolerance capacitors to be added at the lower capacitor values. It was also possible to utilize the BCB already present as the dielectric to form small-value capacitors at 0.5 nF /cm2. The inductors were thin-film metal spirals with inductances in the range of 1100 nH and typical line widths and spaces of around 30 m and 10 m [35, 36]. In addition to this basic technology, Intarsia also developed and implemented a design kit, named PassPort [37]. Recognized by Electronic Products magazine, which awarded it its 25th Annual Product of the Year Award, the PassPort design

Figure 12.25

Integrated RC terminator employing resistive capacitor plates.

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palette enabled Intarsia to quickly design, simulate and layout single- and multifunction modules that integrated numerous individual passive and semiconductor devices into a single thin-film-on-glass microcircuit. Such design tools are a key factor in insuring design success with integrated passive components and a similar approach was followed by other integrated passive groups, notably IMEC [30, 39]. Although used by some of the thin film build-up technology manufacturers, the concept of an available design kit appears to be less prevalent among the LTCC manufacturers, most of whose design activities are still retained in-house due to the complexity of designing embedded passives in the LTCC substrate. Although multiple layers are available to build complex microwave components, full 3-D simulations are usually needed in order to take into account all the coupling effects in these layers. This makes it much more difficult to develop a library-kit-based design style. Although Intarsia demonstrated many different levels of integration, from the complex Bluetooth and similar modules discussed earlier in this chapter to simple filter devices [39], the main thrust of the product strategy was to incorporate the integrated passive components into functional blocks. These blocks would replace predetermined sections of the RF circuitry, such as low-noise amplifiers or power amplifiers, primarily in telecommunications applications. To this end, Intarsia developed a range of LNA and PA products using not only its own Direct Module Attach packaging technology but also the more conventional SOIC and PLCC plastic packages. Clearly, further integration would allow the incorporation of additional functions such as the Tx/Rx switching filters and matching networks and, ultimately, integration of the complete transceiver. A picture of some of the Intarsia integrated passive networks and a DMA version of the LNA are shown in Figure 12.26. The initial products were aimed at a range of wireless applications, from broadband wireless access to WLAN, point-to point radio, and cellular. For example, the LNA-015-01-S08, a low-noise amplifier with a low noise figure of 0.65dB minimum, operated in the range 1.52.7GHz and satisfied requirements for cellular base

Figure 12.26 Three integrated passive devices including a Direct Module Attach (DMA) version of the low-noise amplifier. (Courtesy of Intarsia Corp.)

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station, Bluetooth wireless systems, broadband wireless access, and MMDS applications. Other products in the initial offering covered the frequency range from 800 MHz to 6 GHz. The products were packaged using conventional SOIC overmolded packages as shown in the diagram in Figure 12.27, and thus were compatible with standard board-assembly techniques. Intarsia also developed a range of power amplifiers incorporating matching networks, which were packaged into molded leadless chip carriers as shown in the schematic cross section in Figure 12.28. An example of one of the products is the 1.751.91GHz three-stage amplifier, designed for U.S. and Korean PCS bands. The performance characteristics of this particular power amplifier are shown in Table 12.2. Unfortunately, Intarsia Corporation ceased operation in June 2001 and so these particular products are no longer available. It is clear, however, that they played an important role in raising the awareness of the capabilities of an integrated passive approach to wireless solutions. 12.2.4 SyChip Founded as a spin-off of Lucent (Bell Laboratories) in 2000, SyChip focuses on the design and marketing of modules for wireless applications, based on the Micro System Integration Technology developed at Bell Labs during the 1980s and 1990s. [40] The technology uses a low-loss silicon substrate for fabrication of a high-Q passive component structure, with Al metallization and polyimide for the interlayer dielectric. Two metal layers are used, one to form the component contacts and the upper capacitor plates, the other to form the contact pads. Inductors are patterned as spirals in the Al layer and Q-values as high as 50 to 80 can be obtained. TaSi film is used as the resistor layer, which also forms the bottom contact of the capacitor

Figure 12.27 Cross-sectional representation of Intarsia low noise amplifier module. (Courtesy of Intarsia Corp.)

12.2 COMMERCIALIZED THIN-FILM BUILD-UP INTEGRATED PASSIVES

319

Figure 12.28 Cross-sectional representation of a power amplifier integrated passive module. (Courtesy of Intarsia Corp.)

structure, and the capacitor dielectric is Si3N4. The upper metal layer can be metallized with a solder-wettable metal to provide attachment sites for flip chip components [41]. SyChip has demonstrated their integrated passive technology in a number of wireless modules, including a General Packet Radio Service (GPRS) module and Bluetooth radios. In this instance, a custom designed chip was used in conjunction with an integrated passive substrate to provide a high-performance solution in a

TABLE 12.2 Performance characteristics of 1.751.91 GHz integrated passive power amplifier module Frequency Small-signal gain Pout for IS136 TDMA ACPR for CDMA @ Pout = 28.5 dBm Harmonics Return loss VD VG Standby current Supply current Efficiency
Source: Courtesy of Intarsia Corp.

2nd 3rd Input Output

IS-136 Mode CDMA Mode IS-136 @30 dBm CDMA @ 28.5 dBm @ 30 dBm @ 28.5 dBm

1.751.91 GHz 38.0 dB 30.0 dBm 45 dBc/30 kHz 30 dBc 35 dBc 10 dB 8 dB +3.5 V +0.3 to 1.0 V 250 mA 100 mA 850 mA 600 mA 40% 35%

320

OTHER APPLICATIONS AND INTEGRATION TECHNOLOGIES

small form factor. Although SyChips current product offerings do not include integrated passive components, the capability forms part of a wide portfolio of technologies available for future performance enhancement and size reduction. SyChip anticipates that the integrated passive technology will be utilized in next-generation product implementations, such as the next version of their WLAN 802.11b module, or in combo modules, which require the integration and isolation of multiple circuits operating at different frequencies. 12.2.5 Telephus A recent entrant to the thin-film build-up integrated passives community is Telephus, a Korean company whose integrated passives business forms part of a larger silicon fabrication and packaging materials portfolio. Telephus technology uses a silicon substrate but, unlike other manufacturers that use silicon to provide diode functions or control dopant levels to give a higher resistivity and improved RF performance, Telephus uses an ultrathick oxide layer, grown on the wafer surface, to improve RF characteristics. This oxide layer is used to improve the isolation of the passive circuitry from the effects of the silicon substrate. The thick oxide is grown using an electrochemical process to give an oxidized porous silicon surface with films of the order of 35 m in thickness. These films do not have the high stresses associated with conventionally deposited films so greater thicknesses can be achieved. In addition, the processing time is relatively short. The thin-film passive layers are built up on top of the thick oxide. Copper is used as the main metallization and for the interconnections, inductors, and capacitor plates. Three metal layers are used, two of Ti/Cu and one of thick plated Cu for the top pads, allowing crossovers and, hence, routing to the center of the inductor. The dielectric is photoimageable BCB. Resistors are fabricated using a thin NiCr layer, whereas the capacitors use a Si3N4 film [42]. The RF properties of the thick oxide substrate mean that products built using this technology can readily operate at frequencies above 10 GHz so they can be applied to a wide range of wireless applications. The current thrust of the product offerings, however, is in the cellphone and WLAN arena, with low-pass filters, baluns, diplexers, and power dividers available in flip-chip and wire-bond format. Passive arrays and a foundry service are also available. A typical product is a flip-chip, 900MHz, low-loss, low-pass filter with insertion loss of 0.35dB and attenuation at two and three times the operating frequency of 15dB (min.) and 22dB (min.), respectively. Applications would be in antenna switch modules, RF front ends, and other RF/microwave modules.

12.3 OTHER INTEGRATED PASSIVE TECHNOLOGIES It is fair to say that the companies and technologies mentioned in the preceding sections of this chapter represent only a selection of those involved in the field of integrated passives and is by no means an exhaustive list. A brief scan of the recent literature and company publications indicate that many other organizations have an

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OTHER INTEGRATED PASSIVE TECHNOLOGIES

321

interest in, or are actively working on, integrated passive technologies, although only a few are, as yet, making these technologies available in the form of products. Although this book has concentrated on the available thin-film build-up technologies, no review of the commercially available integrated passive devices would be complete without mention of ceramic-based technologies. It is wise to remember that integrated passives have formed a part of ceramic technology from the days of the early hybrids. Today, both high-temperature cofired ceramic (HTCC) and lowtemperature cofired ceramic (LTCC) capabilities include the incorporation of buried and surface-layer integrated passive devices. A comparison of the technologies can be long and complex as both the ceramic and the thin-film build-up techniques have different capabilities and, hence, different advantages. Whereas the thin-film approach allows for tighter control of passive tolerances during fabrication and finer geometries, the ceramic technology allows multiple buried layers and tight control of surface-layer printed components by means of laser trimming. Ceramic modules often include a number of surface-mounted discrete passives for high-tolerance, high-Q-value components, whereas thin-film technologies seek to include most of these components within the substrate. Both have successfully demonstrated functional modules. In the United States, one of the main proponents of the integrated passive LTCC approach is National Semiconductor, and an extensive range of information and product data is available on their website. Kyocera, traditionally associated with the HTCC package market, has also demonstrated a number of integrated passive ceramic technologies in LTCC. Both Murata and National Semiconductor have successfully used LTCC to fabricate passive substrates for Bluetooth modules, and although a large number of the passive devices were incorporated as surface-mounted discretes in the earlier versions, the numbers of components integrated into the substrate are rising. Murata, announcing the worlds smallest Bluetooth module in May 2001, claimed to have embedded the bandpass filter, balun, and other passives within the substrate. Their recently announced Blue Module, shown in Figure 12.29, is

Figure 12.29 Blue Module, an ultra-compact HCI module for Bluetooth. (Courtesy Murata Manufacturing Co., Ltd.)

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OTHER APPLICATIONS AND INTEGRATION TECHNOLOGIES

Figure 12.30 National Semiconductors LMX9814 WPAN Bluetooth module. (Courtesy of National Semiconductor.)

a host-controller interface (HCI) module that incorporates RF circuitry, baseband signal processing circuitry, flash memory, and other Bluetooth circuit components. The passive components are embedded within the multilayer, LTCC substrate. National Semiconductors Bluetooth module, the LMX9814 wireless personal area network (WPAN) shown in Figure 12.30, also incorporates multiple features, including USB and UART host-control interfaces together with flash memory, receive/transmit switching, front-end filtering, and localized supply voltage decoupling. The adoption of advanced integration allows this to be included in a module that measures 10.1 14 1.9 mm. In order to advance the ceramic interconnect industry, many of the ceramic manufacturers have joined a collaborative effort aimed at bringing together suppliers and manufacturers of ceramic circuits. This collaboration, the Ceramic Interconnect Initiative, a part of IMAPS, is actively participating in the development and introduction of new ceramic-based technologies and provides a useful source of information on ceramic-based passive integration capabilities.

12.4 SUMMARY The adoption of integrated passive technology is rapidly becoming more widespread. Although mainly focused on the telecommunications and computing sectors, the number of potential and current applications is considerable and new approaches and implementations are arising all the time. Within these pages it is clearly not possible to feature every available technology, demonstration, and product. It is hoped, however, that the examples chosen will give the reader an appreciation for the types of offerings currently available and provide a foundation from which it will be possible to gain a better understanding of the capabilities and opportunities that integrated passives have to offer.

REFERENCES

323

ACKNOWLEDGMENTS The authors would like to acknowledge the support of E. Beyne, S. Brebels, Wim Diels, S. Donnay, P. Pieters, and K. Vaesen from IMEC, and of P. Garrou and J. Plonka (The Dow Chemical Company), C. von Scheele (Ericsson Mobile Platforms), Naoko Igarashi (Murata Manufacturing Co., Ltd.), M. Brozda (National Semiconductor Corp.), N. Miglani (SyChip, Inc.) and Inho Jeong (Telephus Inc.) who helped make this chapter possible. The authors would also like to acknowledge the contributions of the former Intarsia team and to thank D. Pedder and J. Young for their reviews of the Intarsia material.

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1. H. Bakoglu, Circuits, Interconnections, and Packaging for VLSI, Addison-Wesley, Reading, MA, p. 253, 1990. 2. S. Hronick, Effective Use of Line Termination in High Speed Logic, In Integrated Device Technology, Conference Paper CP-23, pp. 8188. 3. C. Gross, Integrated Stacked Capacitor and AC Transmission Line Termination Fabrication Using Ta Anodization Technology, MS thesis, Dept. of Chemical Engineering, University of Arkansas, December 2000. 4. L. Schaper, C. Gross, R. Ulrich, and P. Parkerson, Novel High Density R/C Terminating Networks, In Proceedings of the 2000 Electronic Components and Technology Conference, IEEE, Las Vegas, pp. 15601563, May 2000. 5. P. Catania, R. Roy, and J. Cuomo, Phase Formation and Microstructure Changes in Tantalum Thin Films Induced by Bias Sputtering, Journal of Applied Physics, 74, 2, 10081014, 1993. 6. R. Berry, P. Hall, and M. Harris, Thin Film Technology, Van Nostrand, New York, pp. 271288, 371394, 1968. 7. P. Pieters, K. Vaesen et al., High-Q Spiral Inductors for High Performance Integrated RF Front-End Sub-Systems, Journal of the International Microelectronics and Packaging Society, 23, 4, 442, 2000. 8. C. Herbert and I. Doyle, A New Generation of Integrated Passive Devices for Portable Electronics, ECN Magazine, p. 83, May 15, 2000. 9. S. Jenei, G. Vanhorenbeek et al., High Performance Modules for Integrated Passives in Silicon Technologies, Microwave Engineering, p. 41, June 2001. 10. S. Gong, J. Hilsson, and P. Blomqvist, RF Passive Device Integration for Wireless Communication Systems, In Proceedings of the 2000 International Conference on High-Density Interconnect and Systems Packaging, p. 357, 2000. 11. M. Nielsen, H. Cole et al., Demonstration of Integral Passives on Double Sided Polyimide Flex, In Proceedings of the 2000 International Conference on High-Density Interconnect and Systems Packaging, p. 351, 2000. 12. K. Vaesen, S. Donnay et al., Chip-Package Co-Design of a 4.7 GHz VCO, Journal of the International Microelectronics and Packaging Society, 23, 3, 272, 2000.

324

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13. K. Vaesen, P. Pieters et al., Integrated Passives for a DECT VCO, Journal of the International Microelectronics and Packaging Society, 23, 3, 325, 2000. 14. G. Carchon, P. Pieters, K. Vaesen, W. De Raedt, B. Nauwelaers, and E. Beyne, MultiLayer Thin Film MCM-D for the Integration of High-Performance Wireless Front-End Systems, Microwave Journal, 44, 96110, 2001. 15. G. Carchon, K. Vaesen, S. Brebels, W. De Raedt, E. Beyne, and B. Nauwelaers, Multilayer Thin-Film MCM-D for the Integration of High-Performance RF and Microwave Circuits, IEEE Transactions on Components and Packaging Technologies, 24, 510519, 2001. 16. P. Pieters, K. Vaesen, G. Carchon, W. De Raedt, E. Beyne, and R. P. Mertens, High-Q Inductors for High Performance Integrated RF Front-End Sub-Systems, In International Symposium on Microelectronics, IMAPS-2000, Boston, MA, September 2022, 2000. 17. K. Vaesen, G. Carchon, S. Brebels, W. De Raedt, and E. Beyne, RF Multi-Layer Thin Film Technology with Integrated Passives for the Realization of RF-Front-End Systems, In Conference Proceedings of the 13th European Microelectronics and Packaging Conference and Exhibition, pp. 9094, 2001. 18. G. Carchon, W. De Raedt, and B. Nauwelaers, Integration of CPW Quadrature Couplers in Multi-Layer Thin-Film MCM-D, IEEE Transactions on Microwave Theory and Techniques, 49, 17701776, 2001. 19. G. Carchon, S. Brebels, K. Vaesen, P. Pieters, W. De Raedt, B. Nauwelaers, and E. Beyne, Design of Microwave MCM-D CPW Quadrature Couplers and Power Dividers in X-, Ku- and Ka-Band, International Journal of Microcircuits and Electronic Packaging, 23, 257264, 2000. 20. P. Pieters, S. Brebels, E. Beyne, and R. P. Mertens, Generalized Analysis of Coupled Lines in Multilayer Microwave MCM-D TechnologyApplication: Integrated Lange Couplers, IEEE Transactions on Microwave Theory and Techniques, 47, 18621872, 1999. 21. F. Barlow, M. Van, and A. Elshabini, Miniaturization of Bluetooth Transceivers in LTCC, In Ceramic Technologies for Microwave Conference, Denver, CO, March 2001. 22. S. Chakraborty, K. Lim et al., Development of an Integrated Bluetooth RF Transceiver Using Multi-Layer System on Package Technology, In IEEE Radio and Wireless Conference, p. 117, 2001. 23. Ericsson Microelectronics Product Datasheet PB 313 01/2 (Bluetooth 1.0b) and 01/3 (Bluetooth 1.1). 24. R. Arnold, C. Faulkner et al., Thin-Film Passive Integration Yields Tiny Bluetooth Module, Wireless Systems Design, August 2330 2000. 25. D. Pedder, Advanced RF Packaging using Passive Integration, In Proceedings of Microtech 2001 Conference, January, 2001. 26. C. Faulkner, D. Pedder et al., Realizing a Bluetooth Radio Transceiver in Less Than 90 sq. mm, In Proceedings of the Bluetooth Conference, pp. 345353, October 2000. 27. P. Pieters, K. Vaesen et al., High-Q Integrated Spiral Inductors for High Performance Wireless Front-End Systems, In IEEE Radio and Wireless Conference, p. 251, 2000. 28. G. Carchon, K. Vaesen, S. Brebels, W. De Raedt, B. Nauwelaers, and E. Beyne, ChipMCM Co-design of a 14 GHz LNA, In Proceedings of the International Conference and Exhibition on High Density Interconnect and Systems Packaging, April 1720 pp. 6469, 2001.

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29. S. Donnay, P. Pieters, K. Vaesen, W. Diels, P. Wambacq, W. De Raedt, E. Beyne, M. Engels, and I. Bolsens, Chip-package Co-design of a Low-Power 5 GHZ RF FrontEnd, IEEE Proceedings, 88, 15831598, 2000. 30. G. Carchon, P. Pieters, K. Vaesen, S. Brebels, D. Schreurs, S. Vandenberghe, W. De Raedt, B. Nauwelaers, and E. Beyne, Design-oriented Measurement-based Scaleable Models for Multilayer MCM-D Integrated Passives. Implementation in a Design Library Offering Automated Layout, In International Conference and Exhibition on High Density Interconnect and Systems Packaging, Denver, CO, pp. 196201, April 2628, 2000. 31. G. Carchon, D. Schreurs, W. De Raedt, P. Van Loock, and B. Nauwelaers, A Direct Ku-band Linear Subharmonically Pumped BPSK and I/Q Vector Modulator in MultiLayer Thin-Film MCM-D, IEEE Transactions on Microwave Theory and Techniques, 49, 13741382, 2001. 32. J. Galvagni, S. Randall, P. Roughan, and A. Templeton, So Many Electrons, So Little Time, The Need for Low Inductance Capacitors, AVX Corporation website. 33. A. Ritter, A. Templeton, and B. Smith, Multilayer Cofired RCs for Line Termination, Paper presented at AVX Corporation, 1998 International Symposium on Microelectronics, 1998. 34. D. Liu, R. Moffatt, et al., Integrated Thin Film Capacitor Arrays, In Proceedings of the International Conference and Exhibition on High Density Packaging and MCMs, IMAPS, p. 431, 1999. 35. H. Clearfield, S. Wijeyesekera et al., Integrated Passive Devices using Al/BCB Thin Films, In Proceedings of the 1998 International Conference on Multichip Modules and High Density Packaging, IEEE Press, New York, p. 501, 1998. 36. B. Arbuckle, E. Logan, and D. Pedder, Processing Technology for Integrated Passive Devices, Solid State Technology, November 2000, p. 84. 37. M. Robinson, C. Faulkner, and R. Arnold, A Tool Kit for Integrated Passive Device and RF Module Design, In Proceedings of the Second International Workshop on ChipPackage Co-Design (CPD2000), pp. 3136, March 2000. 38. G. Carchon, P. Pieters, K. Vaessen, W. De Raedt, B. Nauwelaers, and E. Beyne MultiLayer Thin-Film MCM-D for the Integration of High Performance Wireless Front-End Systems, Microwave Journal, 44, 2, 96110, 2001. 39. S. Whelan, Simplifying Passive Integration and Simulation, In Proceedings of the IEEE Radio and Wireless Conference, p. 255, 2000. 40. R. Frye, K. Tai et al., Silicon-on-Silicon MCMs with Integrated Passive Components, In Proceedings of the IEEE MCM Conference, p. 155, March 1992. 41. J. Gregus, M. Lau, et al., Chip-Scale Modules for High-Level Integration in the 21st Century, Bell Labs Technical Journal, 3, 3, 1998. 42. I. Jeong, C. Nam et al., High Quality RF Passive Integration Using 35m Thick Oxide Manufacturing Technology, In Proceedings of the ECTC, p. 1007, May 2002.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 13

THE ECONOMICS OF EMBEDDED PASSIVES

PETER A. SANDBORN

13.1 INTRODUCTION In the past, engineers involved in the design of electronic systems did not concern themselves with the cost-effectiveness of their design decisions; that was someone elses job. Today, the world is different. Every engineer in the design process for an electronic product is also tasked with understanding the economic trade-offs associated with their decisions. Nowhere is the need for economic analysis more critical than when emerging technologies, materials, and processes are involved, for it is the decisions of if, when, and where to insert new technologies that often separate the winners from the losers in high-tech products. Economics encompasses an assessment of the total life cycle cost of a design decision, where the life cycle includes the design, manufacturing, testing, marketing, sustainment, and end of life of the product. The decision to convert discrete passives to embedded passives is much more far-reaching than simply reducing the cost of part procurement and paying more for the board. There are a host of other cost and benefit issues to be considered that translate into life cycle economics at some level. In this chapter, we attempt to touch on the economic attributes of a systems design, production, and support that impact the decision to use embedded passives. Embedded passives are fabricated within substrates, and although embedded passives will never replace all passive components, they provide potential advantages for many applications. The generally expected advantages include: Increased circuit density through saving substrate area Decreased product weight Improved electrical properties through additional termination and filtering opportunities, and shortening electrical connections Cost reduction through increasing manufacturing automation
327

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THE ECONOMICS OF EMBEDDED PASSIVES

Increased product quality through the elimination of incorrectly attached devices Improved reliability through the elimination of solder joints Potentially the biggest single question about embedded passives is their cost. . . of all the inhibitors to achieving an acceptable market for integral substrates, the demonstration of cost savings is paramount [1]. There is considerable controversy, however, as to whether applications fabricated using embedded passives will be able to compete economically with discrete passive technology. On the bright side, the use of embedded passives reduces assembly costs, shrinks the required board size, and negates the cost of purchasing and handling discrete passive components. However, these economic advantages must be traded off against the higher cost per unit area of boards fabricated with embedded passives, a situation that will not disappear over time, and possible decreases in throughput of the board fabrication process. Several different cost estimates for embedded passives have been presented. These estimates range from embedding resistors in a digital application, resulting in a 73% savings [2]; embedding inductors and capacitors in a RF application, resulting in a 27% savings [2]; the cost per square inch of embedded resistor ranging from $0.15 to $0.30 on 6 6 inch to 24 24 inch substrates [3]; and combined 80% improvement in cost/size figures of merit for MCM-D/embedded passives over a surface mount on PCB solution for a GPS receiver front end [4]. All these estimates, though not necessarily inaccurate, are also obviously application-specific and of limited use in decision making for an unrelated application. Understanding the true economic impact of introducing embedded passives cannot be captured in a single simple number, and trade-off decisions should not be made based on such simplified metrics. The application-specific costs depend on many effects when embedded passives are present in a board: Decreased board area due to a reduction in the number of discrete passive components Decreased wiring density requirements due to the integration of resistors and decoupling capacitors into the board Increased wiring density requirements due to the decreased size of the board Increased number of boards fabricated on a panel due to the decreased board size Increased board cost per unit area Decreased board yield Decreased board fabrication throughput Decreased assembly costs Increased overall assembly yield Decreased assembly-level rework

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MODELING EMBEDDED PASSIVE ECONOMICS

329

Several other recurring system costs may also be affected by the use of embedded passives; for example, the need to electromagnetically shield the board may be reduced or eliminated when certain passives are embedded, saving on expensive materials and their assembly, and the costs associated with thermal management of the board may be affected. Due to the opposing nature of many of the effects listed above, the overall economic impact of replacing discrete passives with embedded passives is not trivial to determine and, in general, yields application-specific guidelines instead of general rules of thumb. In fact, the very nature of trade-off analysis is one in which the greater the detail necessary to accurately model a system, the less general and more application-specific the result.

13.2 MODELING EMBEDDED PASSIVE ECONOMICS Several authors have addressed cost analysis for embedded passives and thus provide varying degrees of insight into the economic impact of embedded passives. The target of all these economic analyses is to determine the effective cost of converting selected discrete passive components to embedded components. The most common approach to economic analysis of embedded passives consists of three steps: 1. Reduce the system cost by the purchase price and conversion costs associated with the replaced discrete passives, including the costs of handling, storage, and assembly associated with a discrete component. 2. Reduce the board size by the sum of the layout areas associated with the replaced discrete passives and determine the new number of boards on the panel. 3. Determine the new board cost based on a higher per unit area cost for the embedded passive panel fabrication and the new number of boards on a panel computed in step 2. The results of these three steps determine the new system cost. The effects included in this first-order approach are critical; however, the approach ignores several additional elements, most notably: decreased throughput for embedded passive board fabrication means that board fabricators will have to apply higher profit margins for embedded passive boards to justify their production on lines that could otherwise be producing conventional boards; routing analysis of the board to determine not only what layers may be omitted, but what layers may have to be added to maintain sufficient wiring capacity as passives are integrated and the board is allowed to shrink; yield of both discrete passive components and the variation in board yield due to embedding passives; and potential reductions in rework costs due to both assembly defects and intrinsic functional defects associated with discrete passives. Brown [2] presents an outline of all the potential contributions to the life cycle

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THE ECONOMICS OF EMBEDDED PASSIVES

cost of embedded passives. Rector [1] provided the economic analysis that appeared in the 1998 NEMI Passive Component Technology roadmap [5], using the first-order approach outlined above. Rector concluded that embedded passives can be economically feasible, but only if one considers more than the effects in the firstorder model outlined above. Ohmega Technologies Inc. has also generated a cost model for assessing cost trade-offs associated with its Ohmega-Ply embedded resistor material, [6]. The Ohmega cost model follows the first-order approach described above and includes yield and rework effects. Ohmega concludes that 24 embeddable resistors per square inch are required to make the use of the OhmegaPly material economically practical. Realff and Power developed a technical cost model for board fabrication and assembly [7]. The model includes tests for board assembly, yield, and rework. The focus of the model is on the equipment requirements. Under the assumption that embedded resistors are fabricated using a dedicated resistor layer, they conclude that for embedded resistors to have a significant impact on the cost of a system, their use must allow the removal of equipment or in some other way fundamentally change the assembly process such as changing from double- to single-sided assembly. Power et al. [8] extend the model in [7] to embedded capacitors and cast it in the form of an optimization problem targeted at choosing which discrete passives to integrate based on an assumption of assembly and substrate-manufacturing process details, and material properties. Another analysis that recently appeared, focused on design trade-offs for a GPS front end [4]. This analysis includes detailed cost modeling of thin-film embedded resistors and capacitors performed using the Modular Optimization Environment software tool from ETH [9]. A recent manufacturing cost model from Sandborn et al. [10] incorporates quantitative routing estimation and assesses board fabrication throughput impacts for setting profit margins on board fabrication, effects that have not been included in previous models. This model is outlined in Figure 13.1. Qualitatively the model in Figure 13.1 works in the following way: 1. Accumulate the area of the footprints of discrete passives to be embedded. 2. Reduce board area by the accumulated discrete passive area from step 1, maintaining the aspect ratio of the original board. This step is optional, i.e., the board area may be fixed. 3. For plated or printed resistors, determine the area occupied by each plated or printed embedded resistor on wiring layers. Perform routing analysis, removing nets and vias associated with resistors that are embedded and accounting for area blocked by embedded resistors on wiring layers. Routing is assumed to be unaffected by discrete resistors embedded using Ohmega-Ply or similar dedicated layer addition approaches. For decoupling capacitors, if distributed, all nets and vias associated with embedded decoupling capacitors are removed from the routing problem. For singulated capacitors, assume that there is approximately no affect on the routing analysis. Using these assump-

13.2

MODELING EMBEDDED PASSIVE ECONOMICS

331

Component Descriptions
Embedded Passives

Discrete Passives

9) Assembly/Test/ Rework Cost 5) Layer Pair Yield Analysis

Conventional Board Size and Shape 2) Board Size Analysis

1) Component Size Analysis ApplicationSpecific Wiring Details

7) Board Fabrication Cost

Total Cost

3) Routing Analysis

6) Trimming Time and Cost

4) Layer Calculation

8) Throughput Model

Board Size Layer Count

Figure 13.1

Embedded passive board cost trade-off model [10].

4.

5. 6.

7.

8. 9.

tions, determine the relative change in routing resources due to embedding selected passives. Using the layer requirements, the relative routing requirements for the embedded substrate, and either a fixed measure of the routing efficiency associated with the conventional board or a range of possible efficiencies determined under the assumption that the conventional version of the board did not include any more layer pairs than it needed to route the problem, compute the number of required layer pairs for the embedded passive implementation. Determine the yield of layer pairs that include embedded passives. Determine the trimming cost for embedded resistors. The necessity of trimming is determined by the resistors tolerance. The application-specific cost per trim is determined by modeling the throughput of a laser trimming process. Compute the number of boards per panel from the board size (number-up) and the effective panel fabrication costs from the layer and material requirements, yields, and resistor trimming costs. Determine the relative board fabrication profit margin from layer pair throughput modeling (see discussion in Section 13.3.3). Accumulate assembly cost, test, rework, and board fabrication costs and include profit margin to obtain total relative cost.

The analysis in Figure 13.1 focuses on differences in system cost between embedded passive and discrete passive solutions, therefore, all cost elements that are ap-

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THE ECONOMICS OF EMBEDDED PASSIVES

proximately equivalent for the embedded and conventional system are igonored; e.g., all functional testing of the system and procurrement and assembly costs associated with nonembeddable parts.

13.3 KEY ASPECTS OF MODELING EMBEDDED PASSIVE COSTS In this section, several of the key aspects that are necessary for the assessment of embedded passive costs are discussed in detail by providing trade-off level analyses. Note that the following focuses on embedded resistors and capacitors; however, the concepts are generally applicable to inductors as well. 13.3.1 Board Size and Routing Calculations Board size is critical to the cost analysis because it determines the number of boards that can be fabricated on a panel (number-up) and is a key input to the determination of the number of required layers for wiring. As discrete passive components are converted to embedded passives, the physical size of the board can either remain fixed or be allowed to decrease by the layout area associated with the discrete passives given by Anew = Aconv (li + S)(wi + S)
i=1 N

(13.1)

where Aconv = the conventional board area S = the minimum assembly spacing li and wi = the length and width of the ith discrete passive N = the total number of discrete passives that are converted to embedded passives If the board is double-sided, the calculation in Equation 13.1 can be performed independently for each side of the board; the larger of the two sides determines the new board size. The area consumed by the embedded passives fabricated directly on internal wiring layers impacts the trade-off analysis by decreasing the wiring available on internal layers. Embedded resistors that are fabricated using a dedicated layer pair, e.g., Omega-Ply and Gould TCR, do not have a first-order effect on the wiring availability to the application. The area occupied by an embedded resistor on a board inner layer is given by

AR =

0.8R m2 Rs Rs m2 0.8R

for 0.8R > Rs (13.2) for 0.8R Rs

13.3

KEY ASPECTS OF MODELING EMBEDDED PASSIVE COSTS

333

where R = the value of the resistor, Rs = the sheet resistivity of the resistor material, /square m = the minimum feature size for embedded resistor fabrication Since embedded resistors are designed and fabricated to smaller resistance values than required and then trimmed, a factor of 0.8 is included in Equation 13.2. The factor of 0.8 can be derived assuming a symmetric distribution of fabricated resistor values, where the lowest trimmable resistor is 55% of the application target value, and a 5% design tolerance on the resistors, and then maximizing the number of resistors between the high-specification limit and the lowest trimmable resistor (see Figure 13.3 in Section 13.3.4). There are two types of capacitors that must be considereddecoupling capacitors and singulated or nondecoupling capacitors. It is assumed that decoupling capacitors can be absorbed into dedicated decoupling layer pairs through the use of planar distributed capacitance layers and the nondecoupling capacitors must be fabricated individually on a dedicated capacitor layer pair if they are to be embedded. The area occupied by an individual nondecoupling embedded capacitor on a capacitor layer pair is C Ac = c where C = the value of the capacitor c = the capacitance per unit area of the capacitor layer pair. Assuming square capacitors, the number of embedded capacitor layer pairs for nondecoupling capacitors required in the board is given by (13.3)

Nintegral cap layers =

Anew

2 (A cj + Sc) j=1

Nc

(13.4)

where NC = the total number of nondecoupling capacitors that are converted from discrete to individual embedded capacitors Sc = the effective spacing between individual embedded capacitors on the embedded capacitor layer pair Sc is usually set larger than the minimum spacing possible to allow for perforation of the embedded capacitor layer by vias and through holes, and to allow area for interconnection. Instead of decreasing the board area as passives are embedded, decreases in the required board surface area could be used to convert a double-sided board applica-

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THE ECONOMICS OF EMBEDDED PASSIVES

tion to a single-sided board, as discussed in [1]. This conversion would decrease assembly costs by increasing the throughput and yield of the assembly process. Whether it is realistic or even economically wise to convert a double-sided board to a single sided one depends on whether there is an advantage in allowing the board to shrink. A smaller area board only saves money if it results in the ability to fabricate a greater number of boards per panel. It should be noted that there may be other performance or application-specific benefits to a smaller board size as well. Besides estimating the physical size of the board after embedding of selected discrete passive components, we also need to consider the routing requirements. The following first-order routing assumptions can be made with respect to embedded passives: The IO (effectively the nets and vias) associated with discrete resistors that are replaced by embedded resistors that are directly fabricated on existing board inner layers are effectively removed from the routing problem, i.e., the embedded resistors are fabricated in series with the nets they are attached to on the wiring layers; however, the area occupied by the embedded resistors blocks routing and is accounted for (see Equation 13.6). Singulated nondecoupling discrete capacitors converted to embedded capacitors and embedded resistors fabricated using dedicated layer pairs have no effect on the routing problem. The IO associated with discrete decoupling capacitors converted to embedded capacitors are effectively removed from the routing problem. With these assumptions and the routing information from the conventional implementation, the routing requirements, and thereby the number of layers required, for an implementation that includes embedded passives can be determined. An estimation of the minimum number of layers required to route the application proceeds as follows: Wusednew + Wblocked Uconv Nlayersnew = Wlayernew Ulimit

(13.5)

where Ulimit = the maximum fraction of the theoretically available wiring in the board that can be used for routing Uconv = the fraction of that wiring that is actually used to route the conventional application The ratio of Uconv to Ulimit measures the routing efficiency of the conventional implementation. When the ratio is large (close to unity), the implementation has effectively used all the wiring that is available and any additional wiring would require the addition of another layer pair or an increase in board area. At some smaller value, any decrease in wiring would allow the omission of a layer pair. The wiring blocked (Wblocked) by embedded resistors (the length of wiring that

13.3

KEY ASPECTS OF MODELING EMBEDDED PASSIVE COSTS

335

cannot be used) is given by

Wblocked =

ARi i=1 Anew

NR

Anew Wlayerconv Aconv

(13.6)

where NR = the number of embedded resistors Anew is give by Equation 13.1 AR is given by Equation 13.2 The second multiplier is the wiring per layer in the embedded passive board with no embedded resistors included (Wlayernew). The total length of wiring used for the new implementation is given by, Wusednew = f (Wusedconv) where f is the the fractional change in required total wiring length. The wiring used in the conventional implementation is found from Wusedconv = Wavailconv (13.8) (13.7)

where Wavailconv is the the total length of wiring theoretically available in the conventional board, which is equal to Wlayerconv multiplied by the number of layers in the conventional board minus layers on which wiring is not done, e.g., reference planes. Assuming that the total wiring length required is proportional to the total number of system IOs that require routing, a fundamental assumption in routing estimation approaches that compare requirements and resources, [11], f is found from NIOnew f= NIOconv (13.9)

where NIOnew = NIOconv 2NR 2NDC, the total number of system IOs in the new implementation assuming two IOs per resistor and capacitor, assuming resistors are printed or plated directly onto wiring layers NR = number of embedded resistors NDC = number of decoupling capacitors absorbed into a decoupling capacitance layer pairs NIOconv = total number of system IOs in the conventional implementation Note that N in Equation (13.1) is NR + NC + NDC, where NC is the number of nondecoupling capacitors that are integrated into the board. The number of IOs in the conventional implementation is given by,

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THE ECONOMICS OF EMBEDDED PASSIVES

NIOconv = Nnetsconv(fanout + 1)

(13.10)

where fanout = average number of IOs that a net attaches together minus one, assumed to be the same for the conventional and embedded passives implementations Nnetsconv = number of nets in the conventional implementation Since layers occur in pairs in printed circuit board manufacturing, the result given by Equation 13.5 is rounded up to the nearest multiple of two for use in the model. Note that the final value of Nlayersconv given by Equation 13.5 will be independent of Wlayerconv.

13.3.2 Recurring Cost Analysis Using the size and routing relationships developed in the last section, we can predict the board fabrication costs. The price per conventional board is given by Clayer pairAconvNlayersconv Pconv = (1 + Mconv) Nupconv (13.11)

where M = profit margin (see Section 13.3.3) Clayer pair = cost per unit area per layer pair Nupconv = number-up (number of boards that can be fabricated on a panel) Nlayersconv = total number of layers (wiring and reference) in the conventional implementation of the board The Nupconvis computed from the board length and width, panel length and width, minimum spacing between boards, and the edge scrap allowance, using the model in [12]. The price per embedded passives board is similar to Equation 13.11, with the addition of the capacitor layer costs if embedded decoupling or nondecoupling capacitors are present: (1 + Mnew) Pnew = [Clayer pairnewAreanewNlayersnew + Nbypass cap layersCbypass cap layer Nupnew + Nintegral cap layersCintegral cap layer] (13.12)

where Nlayersnew = minimum number of layers required to route the application given by Equation 13.5 Nintregral cap layers = number of embedded capacitor layers given by Equation 13.4 Ndecoupling cap layers = number of decoupling capacitor layers

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The new layer pair cost in Equation 13.12 is given by Clayer pairnew = Clayer pair + (Cresistor material)(Nupnew) AreaRi + NRCtrimNupnew + Cprint
i=1 NR

(13.13) where the sum in Equation 13.13 is taken over all embedded resistors in the particular layer pair of interest (NR), and Cresistor material = cost per unit area of the resistive material printed on the wiring layers to create embedded resistors Ctrim = the average cost of trimming one resistor Cprint = the average cost of printing or plating all embedded resistors onto one layer pair The board price is combined with component-specific assembly, test, and rework costs to determine the system cost. The average effective cost associated with a single instance of a discrete passive is computed as follows: Cdiscrete = Pdiscrete + Chandling + Cassembly + CAOI + (1 Yassembly)(Cassembly rework + Pdiscrete + Chandling) (13.14) + (1 Yfunctional)(C functional rework + Pdiscrete + Chandling) where Pdiscrete = purchase price of a discrete passive component Chandling = storage and handling costs associated with a discrete passive component Cassembly = the cost of assembly of a discrete passive component per site CAOI = cost of inspecting a discrete passive component per site Yassembly = assembly yield for discrete passive components Yfunctional = functional yield of discrete passive components Cassembly rework = cost of reworking an assembly fault per site Cfunctional rework = cost of diagnosing and reworking a functional fault The (1 Yassembly) term in Equation 13.14 represents the fraction of discrete passives requiring rework, which includes replacment due to assembly faults, and the (1 Yfunctional) term in Equation 13.14 represents the fraction of discrete passives requiring rework due to functional faults. Equation 13.14 assumes that all assembly and functional faults associated with discrete passives are diagnosable and reworkable. The total system cost for relative comparison purposes only is given by
Ndiscrete

Csystem =

i=1

Cdiscretei + Pboard

(13.15)

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THE ECONOMICS OF EMBEDDED PASSIVES

where Cdiscretei = the cost associated with the ith discrete passive component from Equation 13.14 Pboard = the board price from Equation 13.11 or Equation 13.12 Ndiscrete = number of discrete passive components assembled on the board Note that the following costs are not included in the formulation because they are assumed to be the same whether or not the system contains embedded passives: all functional testing costs are ignored, all costs associated with other nonembeddable system components are ignored. 13.3.3 Throughput A fundamental issue that has to be addressed for embedded passives is the throughput of the process that is used to manufacture the boards. Throughput is a measure of the number of products that can be produced in a given period of time, and is the inverse of the interdeparture time, the time elapsed between completed products. Throughput is key to understanding the profit margin that will be required to justify manufacturing embedded passive boards. The objective of this portion of the analysis is the computation of application-specific relative profit margin values for conventional and embedded passive versions of a board. The situation faced by the board manufacturer may be the following. Assume that there are two types of boards that could be fabricated on a process line. One is a conventional board with a known profit margin and the other is an embedded passive board. To simplify the problem, assume that the number of boards to be manufactured will be the same for both types of board. The manufacturing cost of the embedded passive board will be larger. Assuming that the interdeparture time of the embedded passive process will be longer than that for conventional boards, the manufacturer must decide what profit margin to use for the embedded passive board so that the total profit per unit time made by selling embedded passive boards equals or exceeds what can be made by selling the conventional boards. This is necessary to justify the use of a line to fabricate embedded passive boards when it could otherwise be producing conventional boards. To explore throughput effects and determine the relative profit margins of the printed circuit boards, a model has been developed that is similar to cost of ownership models for capital equipment [13]. The model captures the costs due to maintenance (scheduled and unscheduled), yield loss, interdeparture time variations, and changeovers. The labor costs associated with scheduled and unscheduled maintenance and changeovers are given by Equation 13.16: Scheduled maintenance: Unscheduled maintenance: Lsm = NsmTsmRL MTTR Lusm = (Ttotal)RL MTBF (13.16a) (13.16b)

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339

Changeovers:

Lco = NcoTcoRL

(13.16c)

where Nsm = number of scheduled maintenance activities in a given period of time Tsm = average labor time or touch time associated with a scheduled maintenance activity Nco = number of changeovers in a given period of time Tco = average labor time associated with a change over RL = labor rate MTTR = mean labor time to repair for an unscheduled maintenance event MTBF = mean time between failures requiring unscheduled maintenance Ttotal = total time in the period of interest We must now evaluate the throughput impacts of various critical manufacturing events. Computing throughput loss is basically determining lost opportunity costs; i.e., how much good product does not get manufactured because the process has been slowed or stopped, or because defective product is produced instead. We assume that scheduled maintenance does not affect the throughput; i.e., it is performed during periods when the process would not be operational. Therefore, only the cost of performing the scheduled maintenance is important for our trade-off. Also, we assume that the scheduled maintenance periods for lines producing conventional and embedded passive boards are of the same length and occur at the same frequency. Note that if there is no effective off-shift (no time when maintenance can be performed that does not effect the throughput), then Nsm is set to zero and all maintenance is treated as unscheduled maintenance. The throughput impact of process yield can be computed from the number of multilayer panels lost in a fixed time period due to process yield losses: Ninner layers Lostyield = (1 Yilp) Ninner layers per board where Yilp = yield of the panel inner layer process Ninner layers = number of panel inner layers produced in a fixed time period Ninner layers per board = number of inner layer pairs in a single board Unscheduled maintenance, assuming it is performed during time when the process line would otherwise be producing good product, contributes the following lost time: Ttotal Lostusm = (MTTR + 2Tc/s) MTBF (13.18) (13.17)

where Tc/s is the cool down/startup time associated with the line being stopped for the unscheduled maintenance activity. Similarly, the changeovers result in lost opportunity to produce products:

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THE ECONOMICS OF EMBEDDED PASSIVES

Lostco = Nco(Tco + 2Tc/s)

(13.19)

Knowing the interdeparture time, the average number of multilayer boards that can be obtained from the process line during the time period defined by Ttotal is given by Lostusm + Lostco Ttotal Nboards = 1 Lostyield Nboards per panel TinterNinner layers per board Ttotal (13.20) where Tinter = interdeparture time of the inner layer process (time/inner layer pair) Nboards per panel = number-up; i.e., the number of boards that can be fabricated on a panel The parameter that needs to be evaluated for comparison purposes is the total profit in a fixed period of time from fabricating a specific board type. Note that the profit per board is not a good comparison metric because it does not account for the number of boards that are produced. The average profit in the time period associated with the constituent variables is computed from Average Profit = NboardsV (Lsm + Lusm + Lco) where the value of a board, V, is given by V = (1 + M)Cboard where M = profit margin Cboard = manufacturing cost per board The example results shown in Figure 13.2 were generated using the model described by Equations 13.1613.22. If interdeparture times of inner layer production for conventional and embedded passive layers and the average profit margin for conventional boards are known, then the minimum required profit margin for embedded passive board fabrication can be determined. Note that this cost model must be repeated for each board manufacturing scenario since the number of layers in the multilayer board and the dimensions of the individual board are application-specific. The example shown in Figure 13.2 indicates that if conventional boards have a 15.7% profit margin and 15 second interdeparture time per layer pair, then 30 second per layer pair embedded passive board production is only feasible for profit margins of 26% or more. The most important property obtained from this analysis is the difference between the profit margins; the trade-off analysis results are much less dependent on the absolute values of the profit margins. We consistently observe profit margin differences of ~10%. The analyses presented in Section 13.4 as(13.22) (13.21)

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2000 1800 1600

Profit Margin: 30% 26% 20% 30% 20% 15.7% Integral Passives Board

Profit ($/hour)

1400 1200 1000 800 600 400 200 0 5 10 15 20

Conventional Board

25

30

35

40

Interdeparture Time (sec/layer pair) Inter-Departure Inter Departure Time (sec/layer pair) Figure 13.2 The relationship between profit margin and production interdeparture time for conventional and embedded passive board fabrication.

sume profit margins that make the average profit per hour of each type of board fabrication equal. Additional throughput and manufacturing modeling impacts such as manufacturing cycle time and capacity analysis for embedded passive board manufacturing appear in [14]. 13.3.4 Trimming Embedded Resistors Laser trimming of film resistors has been performed for many years. For many applications, depending on design tolerances, embedded resistors will need to be trimmed. Resistors are trimmed by machining a trough in the resistive element, the length and path shape of which determine the resistance change obtained (see Chapter 2). It is also possible to consider reworking embedded resistors prior to completion of the board fabrication process, as discussed in Chapter 3. Resistors may be reworked to higher values by laser trimming or to lower values by printing conductive ink on the surface of an embedded resistor, thus adding a lower-value parallel resistor [15]. A cost of ownership model for a laser trimming process has been developed by ESI [16]. The ESI model allows the amount of time to trim a layer pair to be

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THE ECONOMICS OF EMBEDDED PASSIVES

computed as a function of the number of resistors to be trimmed per layer pair and the size of the panel, allowing the laser trimming throughput to be calculated. A version of the ESI model is used in the analysis process shown in Figure 13.1 (Step 6). Unfortunately, trimming and rework equipment is expensive and both processes potentially represent bottlenecks in the board fabrication process. Therefore, the question that naturally arises is, under what conditions pertaining to application properties and resistor fabrication processes is it economically feasible to perform trimming and possibly rework versus disposal of layer pairs or boards that do not meet design specifications? When resistors are fabricated, the resulting values form a distribution as shown in Figure 13.3. If the resistors are to be trimmed, the fabrication target resistance is below the application target resistance so that the greatest number of fabricated resistors can be trimmed to values in the specified range. The high-specification limit (HSL) and the low-specification limit (LSL) are determined from the design tolerance associated with the resistor. The area under the curve between the HSL and the LSL represents the yield of the untrimmed resistor. There is a lower limit to the ability to successfully trim a resistor that is approximately 55% of the application

Lowest Trimmable Resistor

HSL Application Target

LSL

Frequency

Resistance Value
Figure 13.3 Distribution of fabricated resistor values.

Fabrication Target

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343

target. The area between the lower trimming limit and the HSL represents the yield of trimmed resistors assuming no trimming defects. Resistors in the distribution that have values below the lower trimming limit or above the HSL would generally be considered yield loss because they are both unusable and untrimmable. Rework allows resistors above the HSL to be recovered and used. In cases where no trimming is planned, the process would be centered so that the fabrication target and the application target are the same. Figure 13.4 shows the result using the model developed in [17] for three different applications. The three regions identified in Figure 13.4 provide the conditions under which it is most economical to trim, trim and rework, and simply scrap nonconforming inner layer pairs. This example result assumes no resistor thickness variation. See [17] for additional assumptions and modeling parameters associated with this result. 13.3.5 Yield and Test The discussion in Section 13.3.2 considers the assembly and functional yield of discrete passives, e.g., Equation 13.14. The critical yield parameter not explicitly considered is the board yield (see Chapter 7). The foregoing discussion effectively assumes that the layer pair cost with embedded passives, Clayer pairnew, computed in Equation 13.13 is a yielded cost, i.e., the cost per good layer pair [18]. This quantity can be interpreted as yielded cost only if we assume that all the defective embedded passive layer pairs can be identified and removed from the production process before they are incorporated into multilayer boards.

5 4.5

One Printing/Plating Standard Deviation (mils)

4 3.5 3 2.5 2 1.5

No trimming, no rework (centered process)

Trimming + rework

Fiber channel card 12 x 18 in 1 boards/panel 610 resistors/panel 2.8 embedded res/in2 Picocell board 2.27 x 6.87 in 18 boards/panel 1260 resistors/panel 4.5 embedded res/in2 High density picocell 2.17 x 2.17 in 60 boards/panel 4410 resistors/panel 15.6 embedded res/in2

Trimming, no rework
1 0.5 0 0.1 1 10

20%

100

Design Tolerance (%)

Figure 13.4 Application-specific economical regions of trimming and reworking embedded resistors.

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THE ECONOMICS OF EMBEDDED PASSIVES

If the yield of the embedded passive layer pairs going into board layup and lamination is not 100%, then we assume that some fraction of the defects will be detected at some later point during the board fabrication, system assembly, or final test. Obviously, the cost impact of undetected defective embedded passive layer pairs is greater the later in the process they are discovered. The following simple exercise demonstrates this. Consider the outgoing cost per assembled board from the final in-circuit test step that discovers a defect caused by an embedded passive layer pair: Cin + Ctest Cout = fc Y in where Cin = the total investment in the board and assembly prior to the test Ctest = the cost of performing the in-circuit test Yin = the yield of the board coming into the test fc = the fault coverage of the test As an extreme case, assume that Cin = Cboard + Cassmbly & components = $100 + $50 = $150 has been invested in a board and assembly, the test costs Ctest = $7.50 to perform per assembly, the yield of the assemblies is Yin = 0.8 or 20 out of every 100 assemblies are defective (assuming all the defects are the result of defective embedded passive layer pair and assume further, for simplicity, that we are fabricating only one board per panel), and fc = 0.9, such that 90% of the defects are successfully detected by the in-circuit test. Then the outgoing cost per good board is effectively Cout = $192.53. This result assumes that all the defective assemblies are scrapped and none can be reworked. Note that the yield of assemblies that pass the test is given by
fc Yout = Y 1 in

(13.23)

(13.24)

So for our example case, the yield out of the test activity is Yout = 97.79% (2.21% test escapes), and the final yielded cost of the assemblies is Cout/Yout = $196.88. If, on the other hand, the defective embedded passive layer pair had been detected prior to its lamination into the multilayer board, applying Equation 13.23 during the board fabrication (assuming that $20 was spent on the embedded passive layer pairs that have a 80% yield and we have a 90% fault coverage test, assuming the test costs $2/layer pair) the effective embedded layer pair cost would be $26.89. The total board cost would now increase to $106.89, but the yield also increases to 97.79%. Now, applying Equations 13.23 and 13.24 with an incoming yield of 97.79% instead of 80% at assembly gives us Cout = $160.08, Yout = 99.78%, and Cout/Yout = $160.43, much less than the original case that did not detect the defective board until assembly began. Although this is obviously a very oversimplified case, the point is that layer pair yield will have a different effect on the system manufacturing cost depending on where in the process you are able to detect the problem.

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In general, embedded passives represent increased complexity and possibly an increased layer count in the board, which translates into a greater probability of test escapes at the bare board level, leading to more scrapping at the assembly level. To summarize, the economic viability of using embedded passives in some applications may lie in how accurately defects can be detected at the layer pair level prior to completion of the board and assembly. 13.3.6 Life Cycle Costs Thus far, we have only considered system manufacturing and size issues. This only represents a portion of the economic impacts of converting discretes to embedded passives. Life cycle effects, which for many applications will dominate manufacturing costs, include all other activities associated with the product. Generally speaking, life cycle effects are more difficult to quantify into costs than manufacturing activities. Life cycle activities include: Design CostsCosts of engineering and other technical personnel to design boards that include embedded passives. If designers require specialized training or new CAD and/or other specialized design tools to successfully perform embedded passive board design, then the costs of these activities must be considered. A summary of the design tool requirements for embedded passives is included in the NEMI 2002 Industry Roadmap [19]. One must also consider costs associated with effort and tools for design verification and functional test development. Extra design costs may also include libraries of models for embedded passives, ranging from symbol libraries to high-performance RF models for use in electrical simulation. The inclusion of embedded passives may also affect the degree to which a design can be reused and upgraded. Also included in the design costs are prototyping costs. Are embedded passive applications going to require additional prototype boards? Nonrecurring CostsTo what extent will embedded passives require board fabricators to invest in new equipment [7]? Equipment is not the only nonrecurring cost that may be associated with embedded passives. There will be additional tooling and artwork for layer pair production, additional chemistry to be managed in the board fabrication process, and licensing fees and royalties to be paid for the use of technology, material, and/or processes. Time-to-MarketDoes the design, verification, and prototyping of embedded passive boards require more calendar time than that for conventional systems? Delays in time-to-market of weeks or months for a new product can cost substantial money and in some cases mean missing the market for the product completely. See [20] for a typical time-to-market cost model that forecasts revenue as a function of delays in time-to-market and the length of the market window. Performance ValueEmbedded passives may result in size or performance improvements in a system that enable increases in market share for the manufacturer. It may be the case that for some quantifiable increase in system cost,

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THE ECONOMICS OF EMBEDDED PASSIVES

a manufacturer can differentiate itself from its competition by providing a product that is lighter, smaller, faster, more reliable, or more functional than its competition, and the customer is willing to pay extra for one or more of these improvements. This type of value increase can be mapped to a life cycle cost; however, it requires a business-oriented financial modeling capability. Qualification and CertificationThe introduction of new materials and processes into board fabrication requires material providers and board fabricators to assess and possibly update safety certifications, such as for UL certification. Although the cost of this type of certification is not directly borne by the users of embedded passives, it will be reflected in the board costs. On the other hand, there will be a reduction in the costs associated with qualifying discrete component manufactures. LiabilityEmbedded passives, or any new technology, material, or process, may carry with it unforeseen financial liabilities. The liabilities may be in the form of causing injury to customers, employees of the manufacturer, or the environment. Long-term studies of the effects of the materials and the processes used to incorporate them into boards may be necessary to prove or disprove liability claims. SustainmentSustainment is a collection of many activities, all of which have an economic impact. In general, sustainment is all the activities necessary to: Keep an existing system operational, that is, able to successfully complete the purpose it is intended for Continue to manufacture and field versions of the system that satisfy the original requirements Manufacture and field new versions of the system that satisfy evolving requirements. The foremost concern with embedded passives is reliability. Conventional wisdom is that system reliability will improve because of the reduction in the number of solder joints; however, this will only be realized if the reliability does not commensurately decrease due to other embedded-passive-specific effects. Reliability questions arise from two origins. First, are the specific embedded structures as reliable or more reliable than the rest of the components and packaging? Second, are there embedded-passive-specific processing conditions during board fabrication that reduce the life of other conventional board structures? Changes in system reliability appear either as warranty costs requiring replacement or as maintenance costs requiring repair. General warranty cost models appear in [21]. For systems that are subject to repair, embedded passives may change the ease with which problems in the system can be diagnosed, physically repaired, and retested. In turn, if the faulty board is to simply be replaced, its reliability impacts the number of spare boards that must be manufactured to fulfill expected replacement commitments. Sustainment, however, goes further than reliability-driven replacement and repair. Sustainment also means that the system should remain manufac-

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EXAMPLE CASE STUDIES

347

turable through the end of its support life to fulfill additional requirements for new products and spare replenishment. This is not generally difficult for manufacturers of laptop computers and other short-life consumer products, but is a huge concern and cost issue for long-life products such as avionics for aircraft. The biggest component-related problem that long-field-life systems see is obsolescence [22]. Most electronic parts have short lifetimes, from an availability perspective, relative to even the design cycle of an aircraft, let alone an aircrafts support life. For systems like aircraft, qualification and certification requirements may make simple substitution for obsolete parts with newer parts prohibitively expensive. Embedded passives will mitigate some obsolescence problems by replacing discrete parts that would become obsolete. On the other hand, if the materials used to manufacture the embedded passives within the boards become obsolete and are replaced by newer materials, the overall obsolescence problem may well become much worse. Models for the application-specific economic impact of part obsolescence appear in [23]. Environmental and End of LifeThe fabrication of passives within boards obviously increases the volume of waste produced during the board fabrication process. Disposition of board fabrication waste is a significant contributor to the price of boards. If any of the embedded-passive-specific contributions to the waste steam are considered hazardous, then the waste disposition costs could increase significantly. Waste disposition is also a factor at the other end of the life cycle, i.e., at end of life. Depending on the type of product that the embedded passive board is being used in and the location in the world where the product is being sold, the manufacturer may bear some or all of the cost of disposing of the product when the consumer has finished with it, as is the case of television sets in Germany. FinancialSeveral costs associated with creating and holding inventorysuch as handling, storage, and procurementassociated with discrete passives are potentially avoided; this includes the cost of money that is invested in stored passives as opposed to invested elsewhere.

13.4 EXAMPLE CASE STUDIES In this section, we present the results of size/cost trade-off analyses performed on several different single-board applications, including a picocell board, the NEMI hand-held emulator, and a fiber-channel card. It is not the intent of these analyses to prove that embedded passives lead to less expensive systems; rather, we wish to understand the economic realities should we decide to use embedded passives. The following case studies only include manufacturing costs; no life cycle effects are included. The relevant characteristics of the applications are given in Table 13.1 and the common data assumptions for all the applications are shown in Table 13.2.

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Table 13.1 Picocell board, hand-held emulator, and fiber-channel card application characteristics Picocell Board Number of embeddable discrete resistors 27 (< 100) 19 (1001000) 22 (1 10 k) 1 (10 100 k) 1 (> 100 k) Hand-Held [19] 40 (< 100) 134 (0.11 k) Fiber-Channel Card 210 (< 100) 181 (1001000) 150 (1 10k) 63 (10 100 k) 6 (> 100 k)

Size of embeddable discrete resistors

69 0805 (80 50 mils) 0402 (40 20 mils) 561 0603 (60 30 mils) 1 1201 (120 100 mils) 10 0805 (80 50 mils) 31 120 60 mils 8 250 120 mils 1 (< 100 pF) 29 (100 1000 pF) 13 (1 10 nF) 0805 (80 50 mils) $0.0045 per part 69 (< 100 pF) 40 (100 1000 pF) 88 (0.001 F) 38 (0.01 F) 116 (0.1 F)

Number of embeddable discrete capacitors Size of embeddable discrete capacitors Discrete passive cost

0402 (40 20 mils) 159 0603 (60 30 mils) 82 0805 (80 50 mils) $0.0045 per part $0.015 per part 30 cm2 (square board assumed) 6 $0.0045 per part $0.015 per part 12 18 inches 12

Conversion cost $0.015 per part (excluding assembly) Board size Number of board layers 2.27 6.87 inches 10

13.4.1 Picocell Board Application Figure 13.5 shows analysis results for the picocell board when discrete resistors, but not capacitors, are replaced by embedded components. Each data point represents the embedded passive solution for a specific routing resource assumption, the ratio of resources actually used to route the conventional implementation of the board, and the theoretical maximum amount of resources that could be used; the gray band represents all possible embedded passive solutions for this application; and the solid horizontal line is the system cost of conventional implementations. Only resistors 10 k were considered embeddable. Relative system cost is plotted in Figure 13.5 and throughout this section (the system cost less the cost of all the nonembeddable components and functional testing). The specific solution, shown by points in Figure 13.5, indicates that the embedded passive board becomes economical when approximately 10% of the embeddable discrete resistors are embedded. The relative system cost (the system cost less the cost of all the nonembeddable components and functional test) resistors considered in this study are considerably more economical than embedded resistors in previous studies due to the assumption of fabrication of the embedded resistors directly on wiring layers as opposed to a dedicated embed-

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EXAMPLE CASE STUDIES

349

Table 13.2

Data assumptions used in the modeling

Panel Fabrication Panel size = 18 24 inches (except where otherwise noted) Edge scrap = 0.75 inches Minimum spacing between boards = 0.15 inches Cost per layer pair = $12.50/ft2 Assembly Min. Assembly Spacing = 20 mils Yield = 0.992/discrete passive [6] Cost = $0.0045/discrete passive AOI = $0.0001/discrete passive Assembly Rework = $4/site [6] Functional Rework = $4/site [6] Throughput Analysis Change overs = 4/week Change over time = 15 minutes Cool down and start up = 30 minutes MTBF of the process = 200 hours (conventional) MTBF of the process = 150 hours (embedded passive) MTTR of the process = 1 hour Labor rate (repair) = $25/hour Production hours = 5000/year Routing Analysis Average fanout = 2.1 Embedded Passives Capacitance layer: 10 nF/cm2 Resistive material 200 ohms/square Minimum feature size for embedded components = 15 mils Cresistor material = $0.08/in2 Cin = $0.002/embedded resistor Cout = $7.43/layer pair Cost of capacitor layer material = $14.40/ft2 (> 10 nF/in2) Spacing between nonbypass embedded capacitors (Sc) = 50 mils

ded resistor layer. The data point at $18.30, when no resistors are embedded, represents the board price increase due only to the need for a higher profit margin to justify embedded passive board fabrication (see Section 13.3.3). The next point on the vertical axis (~$19.00) is the relative cost of the system when the first resistor is embedded. The resistor results appear as a gray band in Figure 13.5 due to the range of values that Uconv/Ulimit can take in Equation 13.5. The upper edge of the band, the closed data points in Figure 13.5, represents the assumption that the conventional board used all available routing resources efficiently; i.e., Uconv/Ulimit is close to 1.0. The lower edge of the band, the open data points in Figure 13.5, represents the assumption that the conventional board made poor use of the available routing resources; i.e., Uconv/Ulimit is smaller. The minimum value is determined by finding the smallest value of Uconv/Ulimit that predicts the correct number of layers in

350

THE ECONOMICS OF EMBEDDED PASSIVES

Figure 13.5

The economics of embedded resistors for the picocell board application.

the conventional solution. Practically speaking, all solutions start at the top edge of the band (10 layers for the picocell board) and may step down to the lower edge of the band (8 layers for the picocell board) at some point, depending on the actual value of Uconv/Ulimit for the application. Another type of step discontinuity can also appear in the results if the board shrinks in size enough so that more boards can be fabricated on a panel. In the picocell board case, the board size never decreases sufficiently to allow more boards to be fabricated on an 18 24 inch panel, however, potential board size decreases may still be important to the customer using this board and Figure 13.6 shows the board area change as the fraction of embedded resistors is varied. Next, consider the integration of capacitors. Figure 13.7 shows the relative system costs as the embeddable capacitors, but no resistors, are integrated. Only capacitors 100 nF were considered embeddable. Since embedding of decoupling capacitors requires material replacement and nondecoupling capacitors require the addition of an extra layer pair for the technologies we assumed, the very first decoupling capacitor embedded increases the cost of the board dramatically, but as more capacitors are embedded, the added cost of the replacement material layer is gradually offset by the avoidance of discrete capacitor part and assembly costs. The driver that determines whether capacitor embedding is economical or not is the density of embeddable discrete capacitors on the board. Figure 13.8 shows that if additional embeddable capacitors were added to the picocell board application, thus increasing the capacitor density, decoupling embedded capacitors would become economically viable at approximately 6.9 capacitors/square inch, whereas the actu-

13.4

EXAMPLE CASE STUDIES

351

15.7

15.6

Board Area (square inches)

15.5

15.4

15.3

15.2

15.1

15 0 10 20 30 40 50 60 70 80 90 100

% of Embeddable Resistors Embedded

Figure 13.6 tion.

Board size decrease with resistor embedding for the picocell board applica-

26 24
Relative System Cost ($)

22 20
Conventional Board

18 16 14 12 10 0 10 20 30 40 50 60 70 80 90 100

% of Embeddable Capacitors Embedded

Figure 13.7

Capacitor embedding for the picocell board application.

352
Cost Difference Between Conventional and Integral Passives Solution ($)

THE ECONOMICS OF EMBEDDED PASSIVES

Actual Picocell Board capacitor density

4 2 0 -2 -4 -6 -8 0 2 4 6 8 10 12 14 16
Number-up = 18 Number of layers = 10

Breakeven

Number-up = 21 Number of layers = 10 Number-up = 21 Number of layers = 12

No Shrink Allow Shrink

Embedded Capacitor Density (capacitors/square inch)

Figure 13.8 The impact of embeddable capacitor density on system cost for the picocell board application.

al picocell board application has only 2.76 capacitors/square inch. When the density of embeddable decoupling capacitors is increased, the number-up first decreases due to the decreased board size if the size is allowed to change, and later, as density increases, a layer pair addition is required to support routing requirements of the application with the smaller board size. 13.4.2 NEMI Hand-Held Product Sector Emulator Analyses similar to those performed for the picocell board have been applied to the NEMI hand-held emulator described in Table 13.1. Figure 13.9 indicates that the embedded passive board becomes economical when approximately 3% of the embeddable discrete resistors are embedded. A discontinuity in the embedded passive board data is labeled on the plot. The discontinuity appears when enough resistors have been embedded to sufficiently reduce the board size so that additional boards can be manufactured on the panel or, in other words, the number-up increases. In the hand-held emulator case, the boards are small so that the number-up on the panel is large and the overall price of the boards is low, under about $2/board; therefore, increasing the number-up has a minimal effect on the system cost. Figure 13.10 shows the relative system costs as the embeddable capacitors, but no resistors, are embedded. When decoupling capacitors are embedded, the cost initially increases by the material replacement cost. We have assumed that when a decoupling capacitance layer pair is added, less total decoupling capacitance will be necessary (see Chapter 9). Note that a much better economic case can be made for

Figure 13.9 The economics of embedded resistors for the NEMI hand-held product sector emulator (5.5 5.5 cm board fabricated on an 18 24 inch panel). The data points represent specific embedded passive solutions; the solid horizontal line is the relative system cost of the conventional implementation.

20

Relative System Cost ($)

18

Conventional Board

16

6 layers
Relative System Cost ($)

6 layers 8 layers

14

12

10

63 boards/panel

70 boards/panel

10

20

30

40

50

60

70

80

90

100

% of Embeddable Capacitors Embedded

Figure 13.10 Capacitor embedding for the 5.5 5.5 cm NEMI hand-held product sector emulator. No embedded resistors are fabricated in this example. The baseline for this plot (the horizontal line) is the board with none of the embeddable capacitors embedded. 353

354

THE ECONOMICS OF EMBEDDED PASSIVES

embedded decoupling capacitors in the hand-held emulator than for the picocell board due to the larger embeddable decoupling capacitor density23.44 capacitors/square inch. Similar to the embedded resistor characteristics, eventually enough decoupling capacitors are embedded to reduce the size sufficiently to allow a number-up increase. Note that there are fewer embeddable capacitors than resistors, so this discontinuity occurs later in the embedding process than for resistors. Also note that a second discontinuity appears in Figure 13.10a layer change. As board area decreased, so did the available wiring resources. Eventually, an additional layer pair had to be added to interconnect the system components.

13.4.3 Fiber Channel Card Figures 13.11 and 13.12 show the results of embedding resistors and decoupling capacitors into the fiber-channel card described in Table 13.1. In this case, the board is large and only one can be fabricated per panel. The results for two different panel sizes are considered in these figures. Because all the cost associated with fabricating embedded resistors on a panel has to be borne by a single board, 2535% of the 610 embeddable resistors need to be embedded to realize a cost savings. Figure 13.11 also shows that when there is less panel waste when the board is fabricated on a smaller panel, embedded resistors become economical more quickly. Figure 13.12

Figure 13.11 The economics of embedded resistors for the fiber channel card. The data points represent embedded passive solutions; the solid horizontal lines are relative system costs of conventional implementations.

13.4

EXAMPLE CASE STUDIES

355

440

Relative System Cost ($)

400 360 320

Conventional Board (18 x 24 inch panel)

280 240 200 160 0 10 20 30 40 50 60 70

Conventional Board (16 x 20 inch panel) 18 x 24 inch panel 16 x 20 inch panel

80 90 100

% of Embeddable Capacitors Embedded

Figure 13.12 Capacitor embedding for the fiber-channel card. Note that in this case there are no embeddable discrete nondecoupling capacitors.

shows the effect of integrating decoupling capacitors for the fiber-channel card. For this example there are only 242 embeddable capacitors on a 12 18 inch board, which gives 1.12 embeddable capacitors per square inch. As indicated in the handheld and picocell examples, with such a low embeddable capacitor density it is not likely to be economical to embed the capacitors. The economics of embedded decoupling capacitors can be generalized by observing the application-specific embeddable capacitor density necessary to break even on costs, i.e., by plotting the embeddable capacitor densities where the cost difference between the conventional and embedded passive implementations is zero. For the picocell board application with a constant board area assumed, this point is 6.9 embeddable decoupling capacitors per square inch (Figure 13.8). Figure 13.13 shows the general result for the three applications considered in this chapter. The critical assumptions for this plot are that the board size and the number of layers required for routing are not allowed to change. The primary differentiator between the applications as far as this plot is concerned is in the panelization efficiencythe total board area on the panel divided by the panel area. The dielectrics used to produce embedded capacitor layers are relatively expensive and would be purchased and used at the panel size. Therefore, a low panelization efficiency indicates that the application is wasting a lot of the expensive material, and a larger panelization efficiency indicates less waste so that lower breakeven capacitor densities are possible.

356

THE ECONOMICS OF EMBEDDED PASSIVES

Capacitor Breakeven Density (embeddable capacitors/square inch) Capacitor Breakeven Density (embeddable

12

10

Fiber Channel Board (18 x 24 inch panel) Fiber Channel Board (16 x 20 inch panel) Hand-Held Emulator Picocell Board

capacitors/square inch)

10 nF/in2 10 nF/in2

2 ~500 pF/in pF/in2 ~500

2 0.03

0.05

0.07

0.09

0.11

0.13

Material Cost ($/square inch)

Figure 13.13 Decoupling capacitor breakeven densities as a function of dielectric material replacement costs. Only single-layer substitution is considered in this plot. The actual capacitor densities are: fiber-channel board = 1.12 caps/in2, picocell board = 2.76 caps/in2, NEMI hand-held emulator = 23.44 caps/in2.

13.5 SUMMARY In this chapter, we have presented the results of an application-specific economic analysis of the conversion of discrete resistors and capacitors to embedded passives that are embedded within a printed circuit board. The model has been demonstrated on a picocell board, the NEMI hand-held emulator, and a fiber-channel board. In these cases, we found embedded resistors to be generally cost-effective, with the most significant economic impact resulting from either number-up increases due to board size reductions or layer count decreases due to reductions in routing requirements. Because we considered embedded resistors fabricated directly on wiring layers as opposed to dedicated embedded resistor layers assumed in previous studies [6, 7], we can not generalize to components per unit area because the results are driven by the board fabrication profit margin. The profit margin is a fractional increase in board cost and thus much smaller in absolute terms for high number-up, whereas cost reduction is achieved through omission of discrete part costs. As expected, when a technology that adds resistors directly to the wiring layers is used, embedded resistors become economically viable when considerably fewer are integrated than for layer addition technologies. For the applications considered, embedded decoupling capacitors become economical when the capacitor density reaches 78.5 capacitors/square inch or greater

REFERENCES

357

for reasonable panelization efficiencies in which dielectric replacement material with a cost of $0.10/square inch is assumed. These densities decrease if less expensive dielectrics can be used. It must be reiterated that due to the opposing nature of many of the effects outlined in this chapter, the overall economic impact of replacing discrete passives with embedded passives, in general, yields application-specific results instead of general rules of thumb. We also need to point out several factors that should be kept in mind when interpreting the results in this chapter: 1. Several system implementation details are not addressed in this analysis including: a. Waste disposition in board fabricationwe only account for additional waste disposition costs associated with the fabrication of embedded passive boards in the profit margin differential. b. Nonhomogeneous panelizationsome panel fabrication technologies and materials allow boards to be laid out on the panel with 90 degree relative rotations, resulting in the potential for more boards on a panel. We have assumed homogeneous panelization in this analysis. c. We have not considered the possibility that the conversion of discrete to embedded passives may allow some double-sided assemblies to become single-sided, thus saving significant assembly costs. 2. With any trade-off analysis, the results are only as good as the input data; i.e., inaccuracies in the input data will change the results of the analysis.

ACKNOWLEDGMENTS The author wishes to acknowledge the members of the Advanced Embedded Passives Technology (AEPT) ConsortiumNCMS, ITRI, 3M, Compaq Computer, Delphi Delco Electronics, DuPont Photopolymer and Electronic Materials, DuPont High Performance Films, ESI, Foresight Systems, MacDermid, Merix Corporation, MicroFab, Nortel Networks, ORMET Corporation, and Sanminaand the members of the NEMI Passive Components Technology Working Group.

REFERENCES
1. J. Rector, Economic and Technical Viability of Integral Passives, In Proceedings of the Electronic Components and Technology Conference, Seattle, WA, pp. 218224, May 1998. 2. D. Brown, The Economics of Integrated Passive Component TechnologiesAn Ongoing Exploration of a Life Cycle Cost Analysis, Advancing Microelectronics, 25, 3, 5558, 1998. 3. R. Tummala, G. E. White, V. Sundaram, and S. Bhattacharyam, SOP: The Microelec-

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THE ECONOMICS OF EMBEDDED PASSIVES

4.

5. 6. 7.

8.

9.

10.

11. 12.

13.

14.

15.

16. 17. 18.

19. 20.

tronics for the 21st Century with Integral Passive Integration, Advancing Microelectronics, 27, 1, 1319, 2000. M. Scheffler, G. Trster, J. L. Contreras, J. Hartung, and M. Menard, Assessing the Cost-Effectiveness of Integrated Passives, Microelectronics International, 17, 3, 1115, 2000. Passive Components Technology Roadmap, National Electronics Manufacturing Technology Roadmaps, NEMI, Inc., 1998. Ohmega-Ply Cost Analysis, white paper available from Ohmega Technologies, Inc., Culver City, CA, www.ohmega.com. M. Realff and C. Power, Technical Cost Modeling for Decisions in Integrated vs. Surface Mount Passives, In Proceedings of IMAPS 3rd Advanced Technology Workshop on Integrated Passives Technology, Denver, CO, April 1998. C. Power, M. Realff, and S. Battacharya, A Decision Tool for Design of Manufacturing Systems for Integrated Passive Substrates, In Proceedings of IMAPS IMAPS 4th Advanced Technology Workshop on Integrated Passives Technology, Denver, CO, April 1999. M. Scheffler, D. Ammann, A. Thiel, C. Habiger, and G. Trster, Modeling and Optimizing the Costs of Electronic Systems, IEEE Design & Test of Computers, 15, 3, 2026, 1998. P. A. Sandborn, B. Etienne, and G. Subramanian, Application-Specific Economic Analysis of Integral Passives, IEEE Transactions on Electronics Packaging Manufacturing, 24, 3, 203213, 2001. P. Sandborn and P. Spletter, A Comparison of Routing Estimation Methods for Microelectronic Modules, Microelectronics International, 17, 1, 3641, 1999. P. A. Sandborn, J. W. Lott, and C. F. Murphy, Material-Centric Process Flow Modeling of PWB Fabrication and Waste Disposal, In Proceedings of IPC Printed Circuits Expo, San Jose, CA, pp. S10-4-4S10-4-12, 1997. D. Dance, T. DiFloria, and D. W. Jimenez, Modeling the Cost of Ownership of Assembly and Inspection, IEEE Transactions on Components, Packaging, and Manufacturing TechnologyPart C, 19, 1, 5760, 1996. M. M. Chincholkar and J. W. Herrmann, Modeling the Impact of Embedding Passives on Manufacturing System Performance, In Proceedings of ASME Design for Manufacturing Conference, SeptemberOctober, 2002. V. G. Shah and D. J. Hayes, Trimming and Printing of Embedded Resistors Using Demand-Mode Ink-Jet Technology and Conductor Polymer, In Proceedings of the Technical Conference IPC Printed Circuits Expo, pp. S14-4-1S14-4-5, March 2002. K. Fjeldsted and S. L. Chase, Trimming Embedded Passives: Cost of Ownership, CircuiTree, September 2002. P. A. Sandborn, An Assessment of the Applicability of Embedded Resistor Trimming and Rework, to be published. D. Becker and P. Sandborn, On the Use of Yielded Cost in Modeling Electronic Assembly Processes, IEEE Transactions on Electronics Packaging Manufacturing, 24, 3, 195202, 2001. Passive Components Technology Roadmap, National Electronics Manufacturing Technology Roadmaps, NEMI, Inc., 2002. J. Debardelaben, V. K., Madisetti, and A. J. Gadient, Incorporating Cost Modeling in

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Embedded-System Design, IEEE Design & Test of Computers, 14, 3, 2435, 1997. 21. W. R. Blischke and D. N. P. Murthy, Warranty Cost Analysis, Marcel Dekker, New York, 1993. 22. R. C. Stogdill, Dealing with Obsolete Parts, IEEE Design & Test of Computers, 16, 2, 1725, 1999. 23. P. Singh, P. Sandborn, T. Geiser, and D. Lorenson, Electronic Part Obsolescence Driven Design Refresh Optimization, In Proceedings of ISPE/CE2002 Conference and Exhibition, pp. 961970, July 2002.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

CHAPTER 14

THE FUTURE OF INTEGRATED PASSIVES

RICHARD K. ULRICH

This book started out with an introduction to integrated passives that covered their definitions, various configurations, and the motivations and problems associated with their implementation. The next twelve chapters provided an analysis of the extensive and diverse state of the art for the various aspects of the technology. This final chapter will seek to pull together some of this large amount of information in order to predict the future of integrated passives.

14.1 STATUS OF PASSIVE INTEGRATION Embedded passives in primary interconnect boards are not a new idea; they have been used in ceramic substrates for decades. Favored materials and processes for resistors, capacitors, and inductors in LTCC are well characterized with regard to manufacturing requirements, performance, and economics, and there is a large infrastructure supporting them. The main technical drawback with embedded passives in between ceramic layers is that tolerance is rarely better than around 10% due to variations in printing, firing, shrinkage, and the inability to trim component values. If passives are formed on the surface of the ceramic substrate (hybrids), they can be trimmed after firing. Ceramic substrates, though growing in use with the rest of the industry, will never approach organic boards in sales volume and, therefore, will continue to host only a small fraction of the overall passives produced, discrete or integrated. Integrated passives are also widely available as arrays or networks, usually fabricated on IC-sized Si using basic front-end technologies, that can be surface mounted onto ceramic or organic boards using the same sort of infrastructure used to install discretes. This technology is rapidly gaining market share due to the obvious economic advantages with a minimum of changes in board design or on the factory floor for implementation.
361

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THE FUTURE OF INTEGRATED PASSIVES

To date, integrated passives have not been utilized as embedded structures in organic substrates to a significant degree, particularly with FR4, which makes up the vast majority of boards sold today. This potentially very large market is the driving force for R&D in the area. The problems with this implementation are well understood; both academia and industry are doing their parts in their own ways to solve these issues. Literature, conferences, and workshops for integrated passives on organic substrates began to appear in the mid 1990s and the typical journal article or conference presentation since then is a demonstration of a material or a process to make resistor, capacitor, or inductor test structures, or else to make a simple multicomponent device such as a filter or terminator. The striking characteristic about the technical literature is the vast array of materials and processes that have been investigated for integrated resistors and for capacitor dielectrics. The list is very long and diverse, including metals, ceramics, and polymers as well as nano- and microcomposites of these materials that can be formed and patterned through many different processes. Methodology from the ceramic side is difficult to use with organics because these processes typically require much higher processing temperatures than can be tolerated by organic board materials and can only be applied if processed separately and laminated onto the board afterwards. A more manageable number of candidate processes, together with design software, costing models, and supply infrastructure, must be developed before embedded passives can move into organic boards.

14.2 ISSUES FOR IMPLEMENTATION ON ORGANIC SUBSTRATES A comprehensive evaluation of using an integrated passive technology versus a discrete passive technology must take into account the following factors: 1. Electrical Design Issuesschematic differences due to differences in component characteristics 2. Board Design Issuesfootprint, routing, number of layers 3. Fabrication Issuesmaterials, processes, tolerances, yield 4. Manufacturing Issuesimplementation and scale-up of fabrication technology to produce a volume process 5. Added Value to the Productincreased customer appeal resulting from smaller form factor, mass, performance The following is a summary of the status of these first four issues based on the earlier chapters and a brief description of the remaining challenges. 14.2.1 Electrical Design Issues The impact of passive integration on the electrical schematic of a system will be considerable for decoupling but fairly minimal for other applications. A single inte-

14.2 ISSUES FOR IMPLEMENTATION ON ORGANIC SUBSTRATES

363

grated capacitor has such a low parasitic inductance that it can replace dozens of discrete capacitors that have been wired in parallel for the purpose of decreasing their overall inductance. But for other uses of passives, the replacement of discretes will be much closer to one-to-one. In some cases it might be possible for a single integrated component to replace multiple discretes if the integrated version can be custom sized to replace more than one of the off-the-shelf discretes that are wired in series or in parallel to give a specific overall value but, for most filters, terminators, A/D converters, etc, the schematic will be the same. 14.2.2 Board Design Issues The impact of passive integration on board design will be profound. The main effect will be to increase the number of layers since some considerable area must now be created to accommodate the planar integrated components. This is based on the assumption that most integrated components will require more area per component than the discretes they replace, and this will be true for the most part. A secondary effect is the change in routing requirements since not all passives must be connected at the surface. The size gap is largest for capacitors. At the time of this writing, an 0402 can be purchased with 2.2 F, which, even with keep-away distance figured in, amounts to 230,000 nF/cm2. The highest values from the various processes becoming available for commercialization are much lower: up to about 1 nF/cm2 for unfilled polymers, maybe 30 for ferroelectric-filled polymers, 50 for fired ferroelectric-coated foils for lamination, and the low hundreds for sputtered or anodized paraelectrics. Ferroelectric thin films cured in place might reach over 1000 nF/cm2, but that technology seems the farthest away. Only the smallest-valued capacitors can be replaced on a size-competitive basis with embedded components. Somewhere above that range, the remaining driving forces include economy of manufacture, replacement of solder joints, and very low inductance for decoupling. It will rarely make sense to attempt to integrate the largest capacitors on the board, those over about a microfarad that are generally used for energy storage. Larger capacitor areas not only occupy more layer space, but also pose a higher reliability risk. Since a range of six decades or more of capacitance is required for many common systems, no one dielectric could provide the entire range with reasonable footprints regardless of its specific capacitance. Even if the lowest-valued capacitors can be fabricated, say, 10 mils across with acceptable tolerance, the highest-valued would then be unacceptably large at 10 inches. For this reason, it might be useful to employ the boards interlayer dielectric for the low-valued components and a more exotic high-k material for the large values. The low-valued capacitors generally require paraelectric-type performance, matching most common board dielectrics. The other technology should have as high a specific capacitance as possible in order to embed the most components. The size of integrated resistors is ruled by the number of squares and only indirectly by the specific resistance of the material. The lower limit of resistor linewidth is set by either thermal or tolerance issues. A large number of squares is to be avoid-

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THE FUTURE OF INTEGRATED PASSIVES

ed due to capacitive coupling between the meanders resulting in a decrease in impedance at high frequencies. Resistor materials need to span between about 100 and 10,000 /square to cover the entire range of values normally required in electronic systems. The available thin-film processes such as TaNx, CrSi, and NiP are limited to only a few hundred /square at most. There is some promise of achieving 10,000 /square with metal-deficient compounds or sputtered cermets, but more development is needed. Fired thick-film materials on foil, borrowed from LTCC technology, and polymer thick films can cover the entire range with no more than a few squares. If the fundamental problems of reliability and value drift can be solved, PTF will be hard to beat as a flexible, economical process. Integrated inductors can be designed as square or circular spirals, and can be on a single layer or distributed over multiple layers. Normal circuit board copper is used for the metal. Numerous programs exist that calculate the inductance and quality factor of these structures. The difficulty lies in keeping metal on other layers away from the inductor region, and in defining a keepout region around the inductor. For that reason, it is good practice to include a surrounding ground around the inductor, including an appropriate keepout, and to compute the inductance including this bounding structure. Then the entire structure is used as a keepout for layers above and below the inductor. Metal on other layers outside the keepout will not impact the inductor, since it is already bounded by ground metal on its own layer(s). The z-axis routing will be diminished by embedding since there is no need to route all passive connections to the surface. This would serve to reduce the number of vias and catch pads that have a limiting effect on wiring density. This beneficial consequence would probably never offset the increased layer requirements due to the area mismatch between discrete and embedded, so the number of layers would probably increase with passive integration. The number of extra board layers required for an embedded passive approach can be estimated. The total area requirements of proposed integrated passives from a schematic can be calculated for given set of integratable R, C, and L technologies. This can greatly exceed the interconnect area on the board in some applications. Dividing the total required area by the desired circuit board footprint will give a good estimate of the number of layers needed. Layout optimization may alter this number a bit, but this alone may indicate the worth of embedding for a specific application. 14.2.3 Fabrication and Manufacturing Issues This topic makes up most of the book due to the large number of candidate technologies reported in the literature. The materials and their processes are inextricably connected such that choosing one usually restricts options for the other. For instance, if Al2O3 is desired as the capacitor material, about the only way to deposit it is by sputtering or anodizing. It is possible to categorize these groups as follows: Processes Requiring VacuumSputtering and CVD are necessary for most thin-film processes. These tend to be subtractive techniques requiring photolithography and are capable of excellent tolerance. An extensive range of

14.3

PROGRESS ON BOARD-LEVEL IMPLEMENTATION

365

component values are enabled by this, particularly with thin-film dielectrics that make possible specific capacitances over the limit of about 30 nF/cm2 that is available with thick-film methods. Many tried-and-true materials are possible for resistors, but most are under a couple of hundred /square; considerable work remains to be done to achieve values over 1000 /square that are needed for the high end of resistor values. Inductor materials up to a few microns can be deposited in this way, but they may be too thin to achieve high Q at high inductance values, although at high frequencies the skin effect comes into play and thin inductors perform almost as well as thick ones. Complete integrated and interconnected R, C, and L systems have been demonstrated using thin-film methods and they are well suited to HDI and build-up technologies. However, vacuum processes are relatively expensive and it may not make economic sense to include them solely for the purpose of creating integrated passives on low-cost commodity boards. Old front-end lines work well for vacuum processing, using substrates of Si or glass. Polymer Thick FilmThese are additive processes using screen-printed preformulated inks. For capacitors, the maximum may be in the low tens of nF/cm2 with ferroelectric characteristics using high-k powders dispersed in curable polymers. This may not be high enough to replace the larger capacitors on the board or to provide sufficient decoupling in high-performance applications. For resistors, a very wide range of /square is available, enabling almost any practical resistor value to be fabricated with no more than 10 squares. Tolerances as printed are no better than about 10% and resistor inks tend to have unstable values with regard to humidity, temperature and time; extensive research is under way to improve this. The attractive feature of PTF is the low cost of capital equipment, inks, and processing. If value drift problems of PTF resistors can be solved, they will find widespread use for integration on almost any platform. Trimming has already been demonstrated to improve precision. Integrated Passives Formed Before Inclusion in the BoardSeparating the processing of capacitor dielectrics and resistor materials from the board enables the use of a host of materials that have been long used on ceramic substrates, such as BaTiO3 dielectrics and RuO2 and LaB6 resistors. Commercialized processes are soon to be released from DuPont that involve printing resistors and capacitors that are fired onto Cu foil and provided for lamination into FR4 or flex stacks. The metal is then photodefined to create the separated passive components. Ohmega-Ply has for some years provided plated NiP resistors on Cu foil that is postprocessed in much the same way. Costs are probably intermediate between PTF and vacuum processes. 14.3 PROGRESS ON BOARD-LEVEL IMPLEMENTATION For implementation into the primary interconnect board, the issues listed above are particularly suitable to be addressed by consortia since the subjects cover such a wide range of interrelated issues.

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THE FUTURE OF INTEGRATED PASSIVES

14.3.1 Advanced Embedded Passives Technology Consortium (AEPT) In October 1998, the National Center for Manufacturing Sciences (NCMS), the National Electronics Manufacturing Initiative (NEMI), the Interconnect Technology Research Institute (ITRI), and a dozen industry partners won a four year NIST Advanced Technology Program award for the purpose of developing the materials, design, and processing technology for embedding passive devices into circuit board substrates. The program ran through the end of January 2003. The team included a mix of OEMs, board fabricators, materials suppliers, and design tool developers in order to solve the simultaneous problems of implementation. The goal was to come up with marketable integrated passive technologies that include validated methodologies for design, materials, fabrication, trimming, reliability assessment, and economic evaluation. Manufacturing processes for large-format boards were targeted to improve the economics and the 110 GHz range was emphasized to accommodate future system requirements. The AEPT consortium developed a number of test structures and product emulators to be used in evaluating the entire spectrum of issues from design to reliability. 14.3.2 National Electronics Manufacturing Initiative (NEMI) NEMI is a consortium of 400 engineers and scientists from over 190 different organizations, including industry, academia, and national labs, with the mission of helping secure and maintain leadership of North American electronics manufacturing. They have published technology roadmaps every two years since 1994, concentrating on board and system issues and coordinating with SIA and other organizations that produce chip-level roadmaps. The reports utilize product emulators in five product sectors, along with predictions of technological and manufacturing progress, to identify upcoming gaps between technologies and needs. This roadmap series covers both the various forms of interconnect substrates and passives, both discrete and integrated. They concentrate more on performance trends, in terms of upcoming specific capacitance or sheet resistance, for example, and less on the technical details on how this might be achieved, making them complimentary to this book. Considerable effort is given to economic analysis for the product emulators (Table 14.1).

Table 14.1 Product Sector Low cost, high volume Hand-held Cost/performance High performance Harsh environment

Product sectors of the NEMI roadmaps

Characteristics Consumer products for which cost is the primary driver Hand-held, battery-powered products driven by size and weight reduction Products that seek maximum performance within a few thousand dollar cost limit High-end products for which performance is the primary driver Products that must operate in extreme environments

14.4 THREE WAYS IN FOR ORGANIC BOARDS

367

The 2000 NEMI Roadmap should be read not only for its predictions, but also to identify the important issues. A few of its more important points are summarized here. As mentioned earlier, lack of infrastructure is a major problem in the implementation of integrated passives, and this problem exists throughout the supply chain, from design, to materials and suppliers, to process technology. Yield and the lack of industry standards is also a major concern. Integrated passives are being driven more by the high-performance sector rather than the hand-held sector, because it requires better decoupling and EMI suppression, both due to the constant push for higher clock speeds. The roadmap also predicts the continued increase in surface-mount integrated arrays and networks. NEMI believes that the development and implementation of microvia HDI technology is essential for the implementation of integrated passives since they are both essential to high-speed design. Table 14.2 is taken, for the most part, from p. 6 of the Passives chapter of the 2000 NEMI Roadmap, with some updates by the authors of this book. 14.3.3 The Embedded Capacitance Project The National Center for Manufacturing Sciences (NCMS) organized more than a dozen partners consisting of materials suppliers, designers, board fabricators, and academia into a collaborative effort to advance the use of distributed embedded capacitance technology for power supply decoupling. The aim was primarily at FR4 circuit boards requiring a minimum of new process technology for implementation. Test vehicles were developed for electrical characterization, reliability assessment, and as proof-of-concept platforms for design software. High-speed measurements of power to ground voltage ripple were used to determine the effectiveness of various decoupling materials and configurations. The final report was issued in early 2000. Material from this project has been included in this book, as appropriate.

14.4 THREE WAYS IN FOR ORGANIC BOARDS If the high volume of organic board production is a target for passive integration, the entry strategies must be chosen for maximum effect. The following subsections describe three ways that this penetration can be brought about. 14.4.1 Decoupling As decoupling requirements become more stringent, surface-mount discretes will have an increasingly difficult time providing low-inductance capacitance. Embedded capacitance will always have less inductance than surface-mount units because they are planar and in-plane with the power and ground layers. Additionally, this will free valuable area on the surface near the chip being decoupled for use by other components such as memory. Specific capacitance levels of at least hundreds of nF/cm2 may be required, and this cannot be met with polymer-based films. Either thin paraelectrics or ferro-

368

THE FUTURE OF INTEGRATED PASSIVES

Table 14.2 Discretes Cost

Implementation issues for integrated passives Integrated Arrays and Networks Better when local densities have 48 devices close together Embedded Passives Better when the average component density is above 3/cm2, cost is panel-size dependent, number of layers is increased by integration. Pb-free technology. BestNo surface board area required since the devices are buried, but more total area required Bestvery high self-resonant frequencies due mainly to decreased lead length and avoidance of inductive current loops Besteliminates solder joints

Goodthe benchmark for all other technologies

Size

Goodboard area required for each and every device Goodbut self-resonates at low frequencies

Better50% and greater board area savings over discretes Betterhigher self-resonant frequency

Frequency range

Reliability

Goodheavy use of solder joints Bestmost flexible for both design and manufacturing Bestflexibility allows quick turns

Betterreduces the number of solder joints

Flexibility

Better than integrated, Good, but requires modeling not quite as good as and simulation up front, cannot discretes be reworked Bettersimple networks and arrays can be quickly designed and manufactured Betterstandard parts from multiple suppliers Goodmore work needed on high sheet resistance and high specific capacitance processes Fairmost board shops require 57 days to build an integrated passive board

Time to market

Availability Besthighly available from reliable sources Value range Bestall values available at commodity prices

Faironly a few suppliers, but more coming on board Goodmore work needed on high sheet resistance and high specific capacitance processes

Tolerances

Besttight Bettercan be Good10% achievable as tolerances available presorted like formed, and trimming possible at commodity prices discretes, with slightly more loss of parts

14.5

CONCLUSION

369

electrics formed at temperatures low enough for organic boards will be required. The limit for paraelectrics is probably around 5001000 nF/cm2 before leakage and breakdown become a problem in the low hundreds of angstroms. Lower operating voltages help this issue. Ferroelectrics are capable of much higher capacitances, depending on what can be achieved with tolerable processing temperatures. Rapid thermal annealing or firing before lamination may be effective approaches. The optimization of integrated decoupling with regard to the amount and distribution of the capacitance on the board is an important task yet to be completed and could easily be a book unto itself. This will require a concerted effort between modeling and measurement, taking into consideration the large number of possible permutations of current draw characteristics and distributions of the chips, as well as the materials and layout of the boards. 14.4.2 Component Replacement on FR4 Low-cost, everyday products require low-cost, everyday processing. To make headway in the massive FR4 board market in general, passive integration technologies must be inexpensive, robust, and capable of being dropped into existing board processes. The circuit board industry in the United States is largely outsourced and somewhat conservative compared to those of Asia and may require more incentive to change. PTF resistor materials are ideal for this, if some fundamental problems can be solved. PTF capacitors will be able to replace only the lowest-valued components, perhaps below 10 nF, so more development is needed in this area as well. 14.4.3 High-Density Interconnect As HDI technology evolves, it may be possible to include the development of passive integration, resulting in acceptable combined processes. Since HDI will be more expensive per square inch anyway, with the promise of higher performance, the initial higher cost of passive integration may be less of a problem. Vacuum processing could be applicable here.

14.5 CONCLUSION The implementation of integrated passives will be an evolution, not a revolution. Passive arrays and networks will continue to increase their market share as they replace terminators, filters, and other natural groups of passives. This should top out at some fraction of total passives, probably less than a quarter. The use of embedded capacitors for decoupling is a certainty since their parasitic inductance is lower than can be achieved with any surface-mount components. Upcoming high-current and high-speed microprocessors cannot be decoupled any other way. Penetration into commodity boards is an important goal that will be realized gradually as the interrelated issues are resolved. Once cost savings are demonstrated, market share should increase steadily.

370

THE FUTURE OF INTEGRATED PASSIVES

How far can this concept go? Figure 14.1 shows a hypothetical system with passives, chips, and other subsystems integrated together. In this format, all individual component packaging is discarded and the layers of the board become the mechanical and environmental protection for each part so that there is very little mass that does not have electrical function. The chips are thinned to fit within one layer of the stack, and the surface is left only for those components that require access to the outside world. The system could hardly be smaller or have shorter interconnects. On our way to this ideal, integrating passive components is essential. Between the current rapid development of integrated passive component technology and the increasing requirements of future electronic systems, significant commercial use appears assured, but when? For those of us in the business, this never happens fast enough. There is always a gap between what can be done technically and what is economically viable at a given time, which is always a challenge when drawing up roadmaps. For passive integration, this gap is especially large because of the vast number of materials and processes that have been demonstrated. Now, the infrastructure needs of design tools, costing models, and supply chains must be established and this will happen as a few tentative processes are commercialized in the coming years. Once at least some technologies are available for OEMs to consider, the first pieces of their associated infrastructure will provide nucleation for the simultaneous solution of the interrelated issues of passive integration. What year will more than 50% of passives be integrated? The microelectronics industry is full of cautionary tales; many of us remember other questions such as What year will more than 50% of ICs be made from GaAs instead of Si? or What year will more than 50% of chip connections be TAB instead of wirebond?

Figure 14.1

The complete integration of an electronic system.

14.5

CONCLUSION

371

But some technologies prove their economic viability and become industry standards, such as surface mounting. Is passive integration economically viable? Certainly for decoupling it is and, in fact, may be the only way to handle the future generations of high-power, high-frequency microprocessors. For discrete replacement in general, the best processes and materials are still being identified, and this is the most important task now. If we find suitable technologies, then passive integration will probably show a long, steady climb to dominance in a manner similar to surface mount as the infrastructure, supply chain, and industry acceptance grows simultaneously.

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

INDEX

AC impedance, 179 Accelerated testing capacitors, 89 resistors, 39 AEPT (Advanced Embedded Passives Technology Consortium), 27, 366 Al2O3 applied to integrated capacitors, 136 breakdown field, 90 capacitance from, 81, 102 dielectric properties, 80 size comparison, integrated and discrete, 17 thickness from anodization, 119 Anodization, 117 anodizable metals, table, 118 ferroelectrics, 124 film thickness, 119 formation voltage, 121 rectifying properties of oxides, 123 Anodized Ta, 120 applied to terminators, 296 leakage and breakdown, 86, 122 mechanism, 118 patterning, 123 rectifying properties, 123 technique, 120 Applications of integrated passives DC/DC conversion, 26 decoupling, 24, 177, 367 general, 23, 293, 367 filtering, 19 inductors, 224, 232 matched to dielectric properties, 93

termination, 96, 294, 315 Assembly methods, 21 AVX, 315 Bandpass filter, 233 BaTiO3. See also Ferroelectrics applied to integrated capacitors, 136 breakdown field, 90 capacitance from, 81 Curie temperature, 78, 82 dielectric properties, 80, 93 hydrothermal processing, 125 mechanism of capacitance, 78 powder mixed with polymer, 127 size of integrated capacitors from, 104 temperature, frequency and voltage effects, 82 BC2000 (Sanmina), 135 BCB 102, 108 Bedspring models, 184 Berry, Robert, 27 Bluetooth, 24, 306 Board design number of layers, 334, 363 size and routing, 332, 334 Breakdown voltage and field, 88, 90 Build-up applications, 313 processing, 13 Bypass capacitors, 178 C-Ply (3M) ,133 California Micro Devices, 313 Capacitance density, 79, 81 373

374

INDEX

Capacitance density (continued) maximum, 109 Capacitor(s). See also Integrated capacitors arrays, 314 in parallel, 181 range in cell phones, 4 Cell phones, passives in, 2 Ceramic substrates, see LTCC Cermets, 61 Characteristic impedance, 249 Class 1 dielectrics, 92 Computers, passives in, 3, 5 Conversion costs, 2 Corner squares, 34 Cost modeling, 22, 327 Coupled microstrip, odd-mode, 254, 255 even- mode, 254, 255 Couplers, 304 CrSi, 16, 58 in voltage dividers, 298 Curie temperature, 78, 82 CVD, 116 CV product, 108 DC/DC conversion, 26 Decoupling dielectrics for, 94 inductance issues, 25 overview, 24, 177 De-embedding, 259 Definitions of integrated passives, 7 Design issues, 362 Diamond-like carbon, 116 Dielectric constants, table, 80 Dielectric materials. See also Integrated capacitors breakdown, 109, 87 capacitance density, 79 class 1 dielectrics, 92 Curie temperature, 78, 82 CV product, 108 defects in, 145 diamond-like carbon, 116 dielectric constants, table, 80 dissipation factor, 89 ferroelectric-filled polymers, 127 films, 15 FR4, 129

leakage and breakdown, 86 matched to applications, 93 mechanisms, 76 paraelectrics and ferroelectrics, 77 polarizability and capacitance, 76 polymers, 126 processing, 113 silicon nitride, 318 specific capacitance, 79, 81, 95, 102 Ta2O5, 87 Ta2O5 /TiO2 composites, 115 temperature coefficient of capacitance, 82 Discrete passives 0201 surface mount components, 7, 22 capacitor areas, 101 comparison of areas with integrated, 101 density, 3, 102, 354, 363 in consumer electronics, 3, 5 maximum theoretical density, 22, 102 range of values in consumer equipment, 4 replacement with integrated, 18, 23, 27 sizes, 2 Dissipation factor, 80, 89, 166 Doping of semiconducting oxides, 41 Dow, 224 DuPont, 66, 132 Economics of integration, 327 cost of ownership, 338, 341 life cycle costs, 345 nonrecurring cost, 345 profit margin, 338, 340 recurring cost, 336 warranty cost, 346 yielded cost, 343 Eddy currents, 195 EIA dielectric classifications, 91 Embedded Capacitance Project, 367 Emulators, 352 Environmental considerations, 347, 357 Equivalent circuits capacitors, 154 ESR and ESL, 154, 166, 170 Ferroelectrics. See also BaTiO3 aging effects, 84, 90 anodization, 124 bottom plate materials, 131

INDEX

375

compared to paraelectrics, 77, 94 Curie temperature, 78, 82 dielectric constants, 80 dispersed in polymer, 127 dissipation factor, 80 frequency effects, 83 matched to applications, 93 mechanisms, 77 sol-gel and hydrothermal methods, 124 temperature effects, 82 thickness effects, 85 voltage effects, 84 Films processing in general, 14 thick and thin, 16 Filters bandpass, 302 general, 299 inductors in, 233 low-pass, 19 Flex substrates, 12 Footprints of passives, comparison, 17 Formation voltage, 121 FR4, 12, 369 replacement of passives in, 27 Gate oxide, 186 GPS, passives in, 4 Ground plane effects, 252 HDI, 27, 369 HF etchants, 124 HiDEC, 137 High-frequency noise, 178 Hybrids, 15 IMCE, 302306 Impedance analyzer, 167 limits of, 169 Impedance from S parameters, 171 Inductance. See also Parasitics calculation, 250 compared to discrete capacitors, 163 leads and contacts, 164 mutual, 185 parasitic in capacitors, 153 reduced in integrated capacitors,160 Insite (Shipley), 70 Intarsia, 15, 316

Integral Wave Technologies, 19, 299 Integrated active devices, comparison to, 10 Integrated capacitor(s). See also Dielectric materials application guide, 93 area compared to discretes, 101 capacitance density, 79, 81, 95, 109 commercialized processes, 132 CV product, 108 decoupling dielectrics for, 94 inductance issues, 25 overview, 24, 177 defects in, 145 dielectric materials for, 75, 80 electrical performance, 153 energy density, 81 ferroelectrics and paraelectrics, 77, 94 floating plate, 105 history of, 27 interdigitated, 130 layout options, 105, 107 leakage and breakdown, 86, 109 modeling, 153 overview, 15 parallel and floating plate, 105 plate materials, 131 size 101, chart, 103 specific capacitance, 79, 81, 95, 102 status, 28 summary table, 136 temperature coefficient of capacitance, 82 tolerance, 106 trimming, 132 yield issues, 145 Integrated inductor(s) application examples, 224, 232 circuit model, 250 current crowding effect, 253, 254 eddy currents, 195 equivalent circuit, 196 first self resonant frequency, 263 general191 ground plane effect, 252, 253 layout options, 192, 206 influence on performance, 213 LTCC, 230 MMIC, 224

376

INDEX

Integrated inductor(s) (continued) mutual inductance, 251 on silicon, 231, 265 options for high Q, 191 parasitic capacitance, 254-256 performance predictions, 216 Q factor, 200, 257 range in consumer electronics, 4 self and mutual inductance, 194 series resistance, 253 skin effect, 196, 289 effect on inductance, 199, 209 size comparison to discrete, 17 size reduction, 235 spiral inductors, 217 coupled, 237 substrate losses, 210 transmission line configuration, 217 Integrated passive(s) applications, 23 array, 7, 23 case studies, 348 compared to integrated actives, 10 cost modeling, 22, 327 definitions, 7 fabrication in general, 14, 28, 364 future of, 361 history of, 27 implementation issues, 20, 368 network, 8, 23 scaling down sizing, 21 status, 28, 362 substrates for, 11 subsystems, 9 Integrated resistor(s) See also Resistivity of materials commercialized processes, 66 CrSi, 16, 58 fabrication, 14, 55, 72 ink jet deposited, 66 Insite (Shipley), 70 Interra (DuPont) resistor process, 66 LaB6 (DuPont), 66 materials, 16, 35 network, 8, 23 NiCr, 16, 58 NiP, 38 M-Pass (MacDermid), 68

Ohmega-Ply, 66, 330 overview, 15 parasitic capacitance, 45, 49 performance equations, 33, 37 polymer thick film, 63, 70 problems with integration, 20 ranges required, 36 reasons for integration, 17 reworking, 341 sheet resistance, 16, 34 sizing, 45 stability, 38, 58 Ta, 57, 131 TaN, 16, 38, 59 TCR (Gould), 332 temperature coefficient of resistance, 37, 43 thermal issues, 46 trimming, 52, 341 value drift, 39, 58 polymer thick film, 64 Interdigitated capacitors, 130, 264 Interlayer dielectrics, 129 Interra (DuPont) capacitor process, 132 resistor process, 66 Jet Propulsion Laboratory, 26, 299 Kapton, 12 LaB6 Interra, 66 Langley Research Center, 19, 301 Layer count in boards, 363 Leakage and breakdown, 86, 109, 167 lead-free, 20 LICA, 163 Life cycle costs, 327 Low-pass filter, 19, 263 LTCC 14, 307, 321 inductors, 230 Lumped versus distributed performance capacitors, 173 inductors, 247 resistors, 52 MacDermid, 68 Magnetic fields, 194

INDEX

377

Maxwell's equations, solving for inductors, 221 M-Pass (MacDermid), 68 MCM, 15 MCM-D for inductors, 226 Mean time before failure (MTBF), 339 Mean time to repair (MTTR), 339 Meanders for resistors, 35 cause of parasitic capacitance, 50 Mezzanine capacitor (Motorola), 135 Micromachining for inductors, 192 Microstrip line, 284 characteristic impedance, 284 dispersion models, 286 effective dielectric constant, 284 losses, 288 lumped element model, 288 step discontinuity, 273,274 Microstrip loss, conductor loss, 288-290 dielectric loss, 291 Microwave integrated circuits (MIC), 247 measurements, 261-263 Miniature hybrid microwave integrated circuit (MHMIC), 248 Mixed dielectric strategies, 107 MMIC inductors, 224 Mobility of charge carriers, 40 MOCVD, 116 Modeling capacitors, 154 economics, 329 ideal passives, 154 inductors, 196, 249 performance prediction, 216 Q factor, 201 resistors, 271 temperature for integrated resistors, 47 Modules, functional, 305 Monolithic microwave integrated circuit (MMIC), 248 Motorola, 135 Mutual inductance, 185, 194, 251 nChip, 15, 135 NEMI (National Electronics Manufacturing Initiative), 352, 366 Network analyzer, 170

NiCr, 16, 58 NiP, 38 M-Pass (MacDermid), 68 Ohmega Ply, 66, 330 Nokia 6161 cell phone, 3 Number-up, 332, 336, 357 Ohmega-Ply, 66, 330 Paraelectric dielectrics compared to ferroelectrics, 77, 94 overview, 77 Parasitics, 18 capacitance in inductors, 212 capacitance in resistors, 45, 49, 51 discrete versus integrated capacitors, 159, 163 inductance in capacitors, 153 inductance in decoupling, 25, 177 inductance in leads and contacts, 164 Penetration depth, 196, 289 Picocell board, 348 Polarizability of dielectrics, 76 Polymer dielectrics, 127 Polymer thick film fabrication, 16 resistors, 63, 70 value drift, 65 Power distribution, 177 Propagation constant, 249 Q factor, 200 RC terminators, 96, 294, 315 Reliability test structures, 298 Resistivity of materials, 35. See also Integrated resistors alloys and metal-nonmetal compounds, 58 cermets, 61 definition, 34 films, 15 mechanisms of conduction, 40 NiP, 38 polymer thick film, 63 semiconducting oxides, 41 semiconductors, 61 single-component metals, 43, 56 Ta, forms of, 57

378

INDEX

Resistivity of materials (continued) table, 37, 71 TaN, 59 temperature coefficient of resistance, definition, 37 tunneling, 43 voltage coefficient of resistance, definition, 37 Resonance frequency capacitors, 155 in decoupling, 182 inductors, 193 resistors, 50 Reworking resistors, 341 Routing routing efficiency, 334 wiring blocked, 335 S parameters, 170 Sanmina, 135 Scheduled maintenance, 338 Self-inductance, 194, 251 Self-resonance frequency capacitors, 155 resistors, 50 Semiconducting oxides, 41, 61 Sheet resistance, 34 Shipley, 70 Siemens, 34, 40 Silicon substrates, 14 for inductors, 231 SiLK (Dow), 224 Skin effect, 196, 289 effect on inductance, 199, 209 Solder joints, 19 Solenoid inductors, 192 Specific capacitance, 79, 81, 95, 102 Spiral inductor, see Integrated inductor self-inductance, 251 synthesis, 258 Sputtering cermets, 62 dielectrics, 114 TaN, 59 Ti oxynitride, 60 Substrates for integrated passives effects of roughness, 45, 114 high resistivity, 197 issues for integration, 362

losses for inductors, 210 types, 11 Surface mount components, 2, 22 Surface roughness advantages of anodization, 118 effects on sputtering dielectrics, 114 effects on resistors, 45 Sustainment, 346 SyChip, 318 T junction, 303 Ta alpha and beta, resistivity of 57, 131, 296 first use in integrated passives, 27 TaN, 16, 38, 59 effects of surface roughness, 45 processing, 59 Ta2O5 anodized, 117, 120 applied to integrated capacitors, 136 leakage and breakdown, 87 MOCVD, 116 patterning, 123 sputtered, 114 Telephus, 320 Temperature coefficient of capacitance, 82 Temperature coefficient of resistance alloys, 58 definition, 37 pure metals, 43 Temperature effects on capacitance, 82 on resistance, 43 Termination, 96, 294, 315 Testing, 344 Thermal conductivity, 47 Thermal modeling, 48 effect of Cu cladding, 49 Thick and thin film processing, 16 Thin film polymer dielectrics, 126 Thin film resistor (TFR), 271 ABCD matrix, 274 experimental verification, 278 high sheet resistance microstrip model, 274 measurement calibration, 278-281 scattering parameter measurements, 278 self capacitance, 276, 277 sheet resistance, 274

INDEX

379

step discontinuity, 273 Throughput, 338 changeovers, 338 interdeparture time, 336, 340 Ti oxy-nitride, 16, 60 Tolerance capacitors, 106 resistors, 53, 342 Transmission line inductor, 217 Trimming integrated capacitors, 131 integrated resistors, 52, 341 specification limits, 342 Tunneling, 43 UL certification, 346 University of Arkansas, 137

Unscheduled maintenance, 338 Valve metals, 117 Voltage coefficient of resistance, definition, 37 Voltage-controlled oscillator, 9, 235 Voltage dividers, 297 WLAN receiver, 308 X7R, 91 Yield issues, 11, 22, 147 enhancement strategies for capacitors, 150 testing for, 343

Integrated Passive Component Technology. Edited by Richard K. Ulrich and Leonard W. Schaper Copyright 2003 Institute of Electrical and Electronics Engineers. ISBN: 0-471-24431-7

ABOUT THE EDITORS

Dr. Richard K. Ulrich has been a professor of Chemical Engineering at the University of Arkansas since 1987 and, prior to that, a packaging research engineer for Texas Instruments. He is a NEMI roadmap board member, a past chairman of the Dielectric Science and Technology Division of the Electrochemical Society, a guest editor for integrated passives at IEEE Transactions on Advanced Packaging, and a former member of editorial board of High Density Interconnect magazine. He is the author of numerous articles, presentations, book chapters, and short courses in the material science aspects of microelectronic fabrication, particularly integrated passives and reliability science. Dr. Leonard W. Schaper is professor of Electrical Engineering at the University of Arkansas, where he has led a research program at the High Density Electronics Center (HiDEC) in advanced interconnect technologies, including 3-D packaging, advanced heat removal, mesh plane power distribution, MCM-D/L process development, integral passives, ultra-low inductance decoupling capacitors, and throughsilicon interconnects. He has been active in electronic packaging since 1980, both at AT&T Bell Laboratories and at Alcoa Electronic Packaging, before joining the university in 1992. Dr. Schaper holds 10 patents and has authored or co-authored more than 250 talks and papers. He is a past president of the International Microelectronics and Packaging Society (IMAPS), and is a past member of the IEEE CPMT Board of Governors. Dr. Schaper is a Fellow of the IEEE and a Fellow and Life Member of IMAPS. He is a recipient of the IEEE CPMT Society Outstanding Sustained Technical Contributions Award and the IMAPS William D. Ashman Award.