MC LC

LI NI U ..................................................................................................................... 3 Chng 1: 1.1 Quy trnh thit k ASIC s dng b phn mm ca Synopsys ................... 4 S lc qu trnh pht trin ca mch thch hp IC ....................................... 4 Phn loi ASIC ................................................................................................ 4 Tng quan v cng ngh ASIC .............................................................................. 4

1.1.1 1.1.2 1.2 1.3

Quy trnh thit k ASIC ......................................................................................... 6 B cng c phn mm EDA ca Sysnopsys ........................................................ 10 S lc v cng ty Synopsys ........................................................................ 10 S khi tng qut ..................................................................................... 10 Leda ............................................................................................................... 11 VCS ............................................................................................................... 12 Design compiler ............................................................................................ 12 Prime time ..................................................................................................... 13 IC compiler .................................................................................................... 13 Fomality ........................................................................................................ 13 Thit k ng h s .................................................................................... 14

1.3.1 1.3.2 1.3.3 1.3.4 1.3.5 1.3.6 1.3.7 1.3.8 Chng 2 :

2.1. Miu t ng h s ................................................................................................. 14 2.2. Thit k ng h s ................................................................................................ 15 2.2.1 2.2.2 2.2.3 2.2.4 Khi Top Module .......................................................................................... 15 Khi Counter ................................................................................................. 18 Khi Extract_bits........................................................................................... 19 Khi Led_7_segment .................................................................................... 21

Chng 3 : Thc hin thit k vi b cng c phn mm Synopsys ................................ 24 3.1 Leda ......................................................................................................................... 24 3.2 VCS ...................................................................................................................... 28 1

3.2.1 3.2.2 3.2.3 3.3 3.4 3.5

Kim tra trc khi tng hp .......................................................................... 28 Kim tra sau khi tng hp ............................................................................. 29 Kim tra timming sau khi layout ................................................................... 30

Design Compiler .................................................................................................. 30 Formality .............................................................................................................. 42 Primetime ............................................................................................................. 46 Kim tra timing trc khi layout ................................................................... 46 Kim tra timing sau khi layout ...................................................................... 48 Ci t d liu ............................................................................................... 48 Floor Planning ............................................................................................... 54 Placement (Sp xp cell) va kim tra tc nghn ........................................... 58 To clock tree ................................................................................................ 60 Thc hin i dy ............................................................................................ 61 Xut cc file .sdc, .sdf, .v, .spef,.. ................................................................. 62 Xut ra cc file bo co ................................................................................. 62

3.5.1 3.5.2 3.6

IC Compiler.......................................................................................................... 48

3.6.1 3.6.2 3.6.3 3.6.4 3.6.5 3.6.6 3.6.7

KT LUN ....................................................................................................................... 64 TI LIU THAM KHO ................................................................................................. 65

LI NI U
Ngnh thit k IC l mt ngnh c yu t quyt nh s pht trin ca tt c cc ngnh khoa hc khc. Cng ngh ASIC c s dng rng khp cc thit b iu khin t ng iu khin cc chc nng ca cc phng tin truyn thng, xe c,cc h thng x l, dy chuyn cng nghip Nhn bit c tm quan trng ca ngnh thit k IC, thng qua mn hc Thit k VLSI ,chng em quyt nh thc hin ti Thit k ng h s s dng b cng c phn mm thit k IC chuyn nghip ca Synopsys. Chng em xin chn thnh cm n Ts. Nguyn V Thng v Ks. Nguyn Nam Phong tn tnh ch bo v hng dn, cung cp cho chng em nhng iu kin tt nht thc hin ti ny.

Chng 1: Quy trnh thit k ASIC s dng b phn mm ca Synopsys

1.1 Tng quan v cng ngh ASIC ASIC - Application Specific Integrated Circuit: mch thch hp ng dng chuyn bit. ASIC c xy dng bng vic kt ni cc mch c sn d c xy dgj theo cc phng php mi v vy ASIC thun tin v d dng hn. Asic l mt mch thch hp c sn xut cho mt ng dng c trng v thng c kch thc tng nh. Cng ngh ASIC c s dng rng khp trong cc thit b iu khin t ng iu khin cc chc nng ca cc phng tin truyn thng, xe c, cc h thng x l, dy chuyn cng nghip 1.1.1 S lc qu trnh pht trin ca mch thch hp IC SSI : Small Scale Intergation Mch tch hp c nh (<10 transistors) MSI: Medium Scale Integration Mch tch hp c trung bnh (10100 transistors) LSI: Large Scale Integration Mch tch hp c ln (1001000 transistors) VLSI: Very Large Scale Integration Mc tch hp c rt ln (103106 transistors)

1.1.2 Phn loi ASIC

ASIC

Gate Array

Full-Custom ASIC

Semi-custom ASIC

Programmable Logic Device (PLDs)

Channeled-gate array ASIC

Channelessgate array ASIC

SPLDs

CPLDs

FPGAs

Hnh 1: S phn loi ASIC Full-custom ASIC:

Mt phn hoc ton b logic cell v cc mch hoc nn (layout ) c thit k ring bit cho tng ASIC. Khng s dng th vin cell c sn cho ton b hoc mt phn thit k. u im: ti u v din tch, tng hiu sut lm vic ca IC Nhc im: gi thnh cao, chim nhiu thi gian thit k cng nh ch to Full-custom c dng trong cc trng hp i hi kht khe v tc , ti nguyn, din tch v hiu sut lm vic, hoc khi Asic qu c bit cn phi c thit k ty bin. Semi-custom ASIC: S dng cc th vin chun t bo logic. Th vin chun bao gm cc i tng , mi i tng l mt tp hp m t cc chc nng logic, thng s vt l (tr, in cm, in dung, in tr...) v cc c tnh hnh hc cn thit cho vic to ra mt n ca mt phn t c bn to thnh IC c gi l Standard Cell nh cc cng AND, OR, XOR, MUX, FF...Th vin ny c chun ha cho php cc cng c thit k c th c, ri bin dch bn thit k thnh mt file m t chi tit vic s dng cc phn t c bn trong th vic chun gi l file Netlist. Sau t file Netlist ngi thit k ch to ra cc mt n bng cch sp xp cc Standard cell v ni dy gia chng. C th s dng kt hp t bo chun vi t bo ln c th k sn nh vi iu khin, vi x l Ngi thit k ch cn n ngha v tr ca t bo chun v kt ni trong mt ASIC. Tt c cc mt n c ty bin v c thit k duy nht cho tng khch hng. u im: Tit kim thi gian, gim chi ph sn xut v gim ri ro do s dng t bo chun c thit k sn v kim tra trc . Nhc im : mt thi gian ch to cc lp mt n, khng ti u v din tch cng nh hiu sut. Gate array: L ASIC c c sn bng mng cc cng hoc cc cell ging ht nhau nhng cha tng c kt ni vi nhau. Cc cell ny c t ti cc v tr c xc nh trc. Channeled-gate aray ASIC: Cc kt ni v cc mng logic nm trn cng mt lp, cc kt ni to thnh cc knh nm gia cc mng cng logic. Channeless-gate aray ASIC: Cc kt ni nm lp, cn cc mng logic nm lp di. 5

Programmale Logic Device (PLDs): PLD l cc IC chun .Tuy nhin PLD c th cu hnh hay lp trnh to nn mt b phn ty bin cho cc ng dng ring bit nn chng cng thuc h ASIC. c im: logic cell v cc lp mt n khng c ty bin, thit k nhanh gi thnh r, mt khi n l ca kt ni c th lp trnh. CPLD: Complex Programmable Logic Device. SPLD: Simple Programmable Logic Device. FPGA: Field Promgrammable Gate Array. 1.2 Quy trnh thit k ASIC Quy trnh thit k ASIC c th c chia lm 2 phn vng chnh l front-end v back end. Qu trnh Front-end bao gm cc bc khng ph thuc vo cng ngh ch to. l qu trnh kim th thit k. Qu trnh back-end da trn cng ngh c s dng. do tnh s dng li rt hn ch. S khi tng qut:
Design specification FAB

Behavioral description

Layout verification and Implementation

RTL coding Physical layout

Functional verification and testing

Floor planning, place and route

Logic synthesis

Logic verification and testing Back end Gate level netlist

Front end

Hnh 2: S khi tng qut qu trnh thit k ASIC 1.2.1 Specification y l bc u tin ca lung thit k ASIC v l phn quan trng nht ca lung thit k ASIC. Trong bc ny, c tnh v chc nng ca ASIC c nh ngha, ng thi ngi thit k s lp k hoch thit k ca mnh(lin quan ti thi gian hon thnh d n, chi ph). T nhng i hi v chc nng v c tnh, ngi thit k s phc tho kin trc ca ASIC cn thit k. Vic ny ng vi tr c bit quan trng trong vic quyt nh kh nng v hiu sut ca thit k (bao gm mc tiu th cng sut, mc in p, nhng gii hn v timing). Do , khi phc tho kin trc phi xem xt tt c cc i hi v in p , tc v hiu sut ca thit k m bo rng n tha mn tt c nhng c t mong mun. Trong qu trnh m phng, kin trc s phi thay i nu kt qu m phng cho thy n khng p ng nhng yu cu ca Specification. Khi kin trc p ng c tt c cc yu cu, ngi thit k s chi thit ha cc thit k trong kin trc a ra cc vi kin trc cho tng module. Vi kin trc l cu ni gia kin trc v mch thc t, n nh x nhng nh ngha trong kin trc thnh nhng thit k c kh nng thc hin c trong thc t. 1.2.2 M ha RTL (RTL coding) M ha RTL l bc th hai trong lung thit k ASIC. Trong bc ny, cc vi kin trc c m t di dng m RTL theo mt ng ng m t phn cng nht nh. M RTL ny phi m bo c th tng hp logic v vt l thnh mch thc t c. Do , vic m ha RTL phi tun theo mt b cc quy tc, cc quy tc ny thng ph thuc vo kh nng h tr ca nh sn xut v phn cng c la chn thc thi thit k. v th, so vi vic m ha RTL cho FPGA, m ha RTL cho cng ngh ASIC c nhiu im khc bit.

1.2.3 Logic synthesis Bc tip theo trong lung thit k ASIC l tng hp. Trong bc ny, m RTL c tng hp. y l qu trnh m trong m RTL c bin i thnh cng logic. Cng logic c tng hp s c cng chc nng ging nh c m t trong RTL. Qu trnh tng hp cn hai tp tin u vo khc thc hin vic bin i RTL thnh cng logic. Tp tin u vo u tin m cng c tng hp phi c trc khi thc hin bin i l tp tin th vin cng ngh. l tp tin th vin cha nhng cell chun. Trong qu trnh tng hp chc nng logic ca m RTL c bin i thnh nhng cng logic s dng nhng cell sn c trong tp tin th vin cng ngh. Tp tin u vo th hai l tp tin gii hn (constraints file) gip quyt nh vic ti u mch logic tng hp tp tin ny thng cha nhng thng tin v nh th, yu cu ti v thut ton ti u m cng c tng hp cn ti u thit k thm ch c nhng nguyn tc thit k cng c xem xt trong qu trnh tng hp. Bc ny l mt bc rt quan trng trong lung thit k ASIC. Bc ny bo m vic tng hp c ty bin nhm c c kt qu ti u nht c th. Da vo bn ti u ha cui cng, nu nhng yu cu v hiu sut hay tn dng din tch vn khng nm trong khong cho php ngi thit k phi xem xt li t kin trc n vi kin trc ca thit k. Ngi thit k phi nh gi li kin trc cng nh vi kin trc p ng yu cu v din tch v hiu sut hay cha? Nu vn cha p ng c th vic nh ngha li kin trc hay vi kin trc l vic lm bt buc tuy nhin vic lm ny s dn n vic phi bt u li t u, mt hnh ng tt mt thi gian. Thm ch nu vic thay i kin trc hay vi kin trc vn khng mang li kt qu mong mun th vic phi ngh n l sa cha specification. 1.2.4 Logic verification and testing Bc tip theo trong qu trinh l kim tra qu trnh tng hp. bc ny , du ta ca qu trnh tng hp logic trn c a vo kim tra tnh ng n v chc nng so vi m t chc nng ca thit k ra bc th nht.

Ngoi vic kim tra v chc nng bc ny cn c th bao gm c qu trnh kim tra timing ca mch sau khi tng hp. Bt k vi phm no v mt thi gian nh setup time hay hold time u cn c ngi thit k sa cha. Trong mt s thit k ngi ta c th b qua vic kim tra timing ny do trong qu trnh Layout s cn c mt qu trnh kim tra timing na. 1.2.5 Physical layout Trong bc ny, nhng cng logic c tng hp s c sp xp v ni dy. a s thit k c nhng critical path rt cht v mt timing. Nhng ng ny c th c xc nh bi nhng ngi thit k bng ng c mc u tin cao. Cng c t ng sp xp v ni dy s ni nhng ng c mc u tin cao trc nhm t n vic nh tuyn ti u. APR cng l bc lin qua n vic tng hp clock tree. a s nhng cng c APR c th thc hin vic nh tuyn clock tree vi nhng thut ton c bit c xy dng sn. y l mt phn quan trng ca lung APR bi v vic xy dng clock tree l rt tin quyt bi nu c nh tuyn ng s trnh c hin tng sai lch clock. 1.2.6 Layout verification and implementation Bc ny kim tra chnh xc v chc nng ca mch layout so vi mch sau khi tng hp mc cng. Trong bc ny cn cn kim tra mt s lut ca nh sn xut ra trong th vin chun (DRC). Nu cha t yu cu th quay li cc bc trc kim tra v thc hin li 1.2.7 Fabication Qu trnh cui cng l em mch Layout i in. File sau khi layout l GDSII c gi n nh sn xut sn xut ra con chp.

1.3 B cng c phn mm EDA ca Sysnopsys 1.3.1 S lc v cng ty Synopsys Synopsys l mt trong nhng cng ty ln nht trong lnh vc sn xut EDA. Synopsys c thnh lp bi Dr. Aart J. de Geus, David Gregory v mt nhm k s n t General Electric's Microelectronics Center, Research Triangle Park (bc Carolina). Hng pht trin ban u ca Synopsys l tp trung vo pht trin cc sn phm thng mi phc v cho vic tng hp logic, bi vy, c th ni sn phm ni ting nht ca Synopsys l phn mm "Design compiler". Tuy nhin, Synopsys cng cung cp cc phn mm khc phc v hu ht cc cng on trong quy trnh thit k IC, tp hp thnh b Synopsys Tools. Ngy nay, Synopsys bao gm hn 60 vn phng bn hng, h tr v trung tm R&D trn khp th gii; s dng khong 6,800 lao ng c doanh thu t 1.54 t USD (nm 2011).

Hnh 3: Tr s ca Synopsys (Mountain View, California, US) 1.3.2 S khi tng qut

10

Hnh 4 : Cng c thit k Synopsys theo lung ASIC

1.3.3 Leda L cng c kim tra tnh kh thi ca m RTL cho vic tng hp mch, m phng, kim th, s dng li. Leda pht hin nhng li lin quan n ng b, cch ly v nng cao hiu nng ca cc cng c khc, nh VCS MX, DC, v Formality. 11

u vo: Cc file HDL c dng ui .v, .sv, .vhd . . . u ra: Cc cnh bo v li cho file HDL

Hnh 5: V tr ca Leda trong b Synopsys Tools 1.3.4 VCS L cng c kim th a chc nng, VCS cung cp cc c ch m phng (m phng ngu nhin hoc "vt cn" cc trng hp ca u vo), phn tch coverage (coverage chc nng, coverage code ...), sa li c trc v sau khi tng hp mch. u vo: cc tp HDL (.v, .sv, .vhd . . .), th vin ca nh sn xut IC, tp cha cc thng s tr (.sdf) (m phng mc logic gate), d liu m phng (file .txt) u ra: kt qu m phng (file u ra .txt, .doc; waveform ...), thng s coverage 1.3.5 Design compiler L cng c tng hp logic, s dng th vin c sn tng hp mch t m RTL; cho php thit k trong thi gian nhanh nht, vi din tch mch nh nht, cng sut tiu th thp nht v ph ln nht. u vo: cc tp m HDL (.v, .sv, .vhd . . .), th vin ca nh sn xut, cc thng s rng buc do ngi thit k t nh thi gian, din tch . . . u ra: file netlist (.v), file cha thng s tr (.sdf), file cha thng s rng buc (.sdc), file .ddc

12

1.3.6 Prime time L cng c phn tch cc thng s v mt thi gian mc logic gate. Cng c ny phn tch thi gian tnh, "bt" cc vi phm v thi gian nh setup time, hold time.. trc v sau khi layout. u vo : file netlist sau khi tng hp logic hoc vt l, file .sdc u ra : Cc vi phm v thi gian tnh

1.3.7 IC compiler L cng c thc hin tng hp mc vt l, bao gm layout (thc hin vic sp xp v ti u v tr cc khi, ni dy, b tr ng i ca xung clock) v gii nn RC. IC Compiler cho php ngi thit k lm vic c hiu qu cao khi thit k cc khi phc tp. u vo: netlist (.v) hoc file .ddc, .sdc, .def, .spef, .sbpf u ra: netlist (.v), .sdc, .def, .spef, .sbpf, .gdsii

1.3.8 Fomality L cng c kim tra tnh tng ng, s dng k thut thng k v hnh thc ha kim chng xem chc nng ca 2 bn thit k c tng ng nhau hay khng (2 bn thit k ny 2 mc k tip nhau, thng l u vo v u ra ca mt cng c tng hp). Formality cng h tr kim th cc trng thi nng lng, cc thit k c nhiu mc in p.

u vo : 2 file HDL cn kim chng, file .svf u ra: kt qu so snh 2 file HDL

13

Hnh 6: V tr ca Formality trong b Synopsys Tools

Chng 2 : Thit k ng h s
2.1. Miu t ng h s ng h s hot ng da trn tn hiu sn dng ca xung nhp thc hin cc b m gi, pht, giy vi chu k iu khin ca xung clock l 1s. Cc tn hiu gi pht giy c hin th ln LED 7 thanh . Module chnh gm 3 tn hiu u vo v 6 tn hiu u ra, mi u ra c 7 bit iu khin hin th ln LED 7 thanh. Cc tn hiu u iu khin u vo gm: Tn hiu clk l tn hiu xung clock, chu k xung l 1s. Tn hiu rst l tn hiu reset, khi rst = 0 gi tr cc thanh ghi trong cc module khi to v gi tr ban u. rst l tn hiu tch cc mc thp. Tn hiu en l tn hiu enable, khi en = 1 cho php hin th cc gi tr ca gi, pht, giy ln LED 7 thanh. en l tn hiu tch cc mc cao.

14

2.2. Thit k ng h s 2.2.1 Khi Top Module S khi:

tens_hour_o [6:0] units_hour_o [6:0] tens_min_o [6:0] units_min_o [6:0] tens_sec_o [6:0] units_sec_o [6:0]

clk rst_n en

Digital clock

Hnh 7: S khi tng qut Miu t cc tn hiu vo ra Tn hiu clk rst_n en tens_hour_o Kch thc 1 bit 1 bit 1 bit 7 bit I/O I I I O O O O O O Chc nng Xung clock u vo Tn hiu reset ng b tch cc mc thp Tn hiu cho php hin th ln LED 7 thanh tch cc mc cao Biu din tn hiu hng chc ca gi Biu din tn hiu hng n v ca gi Biu din tn hiu hng chc ca pht Biu din tn hiu hng n v ca pht Biu din tn hiu hng chc ca giy Biu din tn hiu hng n v ca giy

units_hour_o 7 bit 7 bit tens_min_o units_min_o tens_sec_o units_sec_o 7 bit 7 bit 7 bit

Bng 1: Miu t cc tn hiu vo ra ca khi Top module

15

en tens_sec_w Second_w Extract_bits sec units_sec_w Led_7_segment Tens_sec Led_7_segment Units_sec tens_Sec_o[6:0]

units_sec_o[6:0]

clk rst Counter Minute_w Extract_bits min

tens_min_w

Led_7_segment Tens_min Led_7_segment Units_min

tens_min_o[6:0]

units_min_w units_min_o[6:0]

tens_hour_w Extract_bits hour Led_7_segment Tens_hour units_hour_w Led_7_segment Units_hour Extracts_bits Extracts_bits Leg_7_Segment Leg_7_Segment units_hour_o[6:0] tens_hour_o[6:0]

Hour_w

Digital Clock

Hnh 8: S khi chi tit ca khi Top module

16

Miu t cc cc tham s Tham s Second_w Kch thc [5:0] Miu t Tn hiu ni gia u ra ca khi Counter sec vi khi Extract_bits sec Minute_w [5:0] Tn hiu ni gia u ra ca khi Counter min vi khi Extract_bits min Hour_w [5:0] Tn hiu ni gia u ra ca khi Counter hour vi khi Extract_bits hour tens_sec_w [3:0] u ra phn chc ca khi Extract_bits sec,u vo ca khi Led_7_segment Tens_sec units_sec_w [3:0] u ra phn n v ca khi Extract_bits sec,u Units_sec tens_min_w [3:0] u ra phn chc ca khi Extract_bits min,u vo ca khi Led_7_segment Tens_min units_min_w [3:0] u ra phn n v ca khi Extract_bits min,u Units_min tens_hour_w [3:0] u ra phn chc ca khi Extract_bits hour,u Tens_hour units_hour_w [3:0] u ra phn chc ca khi Extract_bits,u vo ca khi Led_7_segment Units_hour Bng 2: Miu t cc tham s tn hiu bn trong khi Top module 17 vo ca khi Led_7_segment vo ca khi Led_7_segment vo ca khi Led_7_segment

Chc nng khi Top module Khi Top Module c chc nng kt ni u vo v u ra gia cc khi con bng vic khai bo cc dy tn hiu v kt ni cc tn hiu u vo v u ra ca khi Top Module. 2.2.2 Khi Counter S khi:
Second_o clk Counter rst Hour_o Minute_o

Hnh 9: S khi b Counter Miu t cc tn hiu vo ra: Tn hiu clk rst Second_o Minute_o Hour_o Kch thc 1 bit 1 bit [5:0] [5:0] [5:0] I/O I I O O O Chc nng Xung clock u vo Tn hiu reset u ra tn hiu giy u ra tn hiu pht u ra tn hiu gi

Bng 3: Miu t cc tn hiu vo ra ca khi Counter Chc nng: Thc hin b m da vo sn dng ca xung nhp. u ra ca b Couter l cc tn hiu giy, pht, gi. S thut ton:

18

Clk, rst; Second_o = 0, Minute_0 =0, Hour_o = 0;

Minute_o = Minute_o +1;

S second = second +1; Minute = 59?

S second = 59 ? Hour_o = Hour_o +1;

S Hour_o = 23?

Hnh 10: S thut ton ca khi Counter 2.2.3 Khi Extract_bits S khi:
tens_o[3:0] number_i[5:0] Extract_bits units_o[3:0]

Hnh 11: S ca khi Extract_bits Miu t tn hiu vo ra: Tn hiu number_i tens_o Kch thc [5:0] [4:0] I/O I O Chc nng Tn hiu a vo Tn hiu hng chc ca tn hiu a vo

19

units_o

[4:0]

Tn hiu hng n v ca tn hiu a vo

Bng 4: Miu t tn hiu vo ra ca khi Extract_bits Chc nng: c nhim v bin i tn hiu u vo c 6 bt thnh 2 tn hiu u ra 4 bt mi tn hiu l s hng n v v s hng chc ca tn hiu u vo. S thut ton
start number_i [5:0]

d1 = {1'b0, number_i[5:3]}; d1

d1 > 4'd4

0 c1

c1 = d1 + 2'd3;

c1 = d1;

d2 d2 = {c1[2:0],number_i[2]};

c2 1 d2 > 4'd4 0

c2 = d2 + 2'd3;

c2 = d2; d3

d3 = {c2[2:0],number_i[1]};

c3

d3 > 4'd4

0 tens_o units_o

c3 = d3 + 2'd3;

c3 = d3;

number_i = 6'b111111

tens_o = 4'b1111; units_o = 4'b1111;

tens_o = {1'b0,c1[3],c2[3],c3[3]}; units_o = {c3[2:0],number_i[0]};

end

20

Hnh 12: S thut ton ca khi Extract_bits

2.2.4 Khi Led_7_segment S khi :

en Led_7_segment input_i[3:0] out_put [6:0]

Hnh 13: S khi Led 7 thanh Miu t tn hiu vo ra: Tn hiu En input_i out_put Kch thc 1 bit [3:0] [6:0] I/O I I O Chc nng Cho php hin th led 7 thanh Tn hiu vo Tn hiu u ra hin th led 7 thanh

Bng 5:Miu t tn hiu vo ra ca khi Led_7_segment Chc nng : Chc nng: c nhim v gii m s 4 bt hin th ln led 7 thanh vi s iu khin ca tn hiu enable en.

21

f g

Hnh 14: Led 7 thanh Bng gi tr u vo u ra u vo 4d0 4d1 4d2 4d3 4d4 4d5 4d6 4d7 4d8 4d9 u ra {a,b,c,d,e,f,g} 7b1111110 7b0110000 7b1101101 7b1111001 7b0110011 7b1011011 7b1011111 7b1110000 7b1111111 7b1111011

22

En

7b0000000

Bng 6: Miu t cc tn hiu vo ra ca Led 7 thanh Yu cu Timing: Do trong s khi chi tit ch c khi Couter mi c tn hiu xung clock lm nhim v iu khin b m. v vy ta ch quan tm ti timing ca khi Counter Khi giy m n gi tr ngng thit lp l 59 th giy v 0 v tip tc m, pht tng ln 1 Khi pht m n gi tr ngng c thit lp l 59 th pht c gi tr tr v 0 v tip tc m,gi tng ln 1 Khi gi m n gi tr ngng c thip lp sn l 23 th gi c gi tr v 0 v tip tc m

clk

...

rst 6'd0

S: set_number 6'd1 6'd2 6'd3

...

counter_o

6'd0 6'd1

flag_o

Hnh 15: Yu cu Timing

23

Chng 3 : Thc hin thit k vi b cng c phn mm Synopsys

3.1 Leda To th mc rtl cha code RTL v to thm th mc leda trong project. m ca s terminal,chn ng dn n th mc leda ri g lnh leda ca s giao din phn mm hin ra: Bc 1: Chn new project chn OK

Sau khi ca s hin ra trong mc Project Name c th thay tn project c ui m rng l .pro, sau chn next.

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Sau khi ca s mi hin ra, trong mc Verision chn 2001 (verilog 2001)

Chn Next. Ca s tip theo hin ra

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Chn Add ri chn ng dn n th mc cha code verilog

Chn OK chn Next ca s tip theo chn Finish

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Vo Check chn Load Configuration ri chon RTL. Chn biu tng ! xut hin ca s:

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sau khi xut hin ca s vo mc Test clock/reset thit lp clock v reset ri chn OK. ca s mi s hin th cc trng thi kim tra nh sau

Nu ca s hin th trng thi cc mu xanh th code c kim tra ng Nu hin th cc mu nu bo cc cnh bo nn c qua v c th iu chnh. Nu hin th cc mu phi c chi tit cc cnh bo vo sa li code tun theo cc lut mnh chn. Sau khi sa code chy li kim tra mt ln na cho n khi no trn ca s khng xu hin mu na. 3.2 VCS

3.2.1 Kim tra trc khi tng hp To th mc vcs trong project. Trong th mc vcs to th mc pre_syn cha cc file sinh ra tron qu trnh m phng code RTL trc khi tng hp bng design compiler. Vo th mc pre_syn m ca s lnh Terminal g lnh sau: vcs -debug +v2k ../../rtl/*.v 28

sau khi phn tch cc file .v xong n s to ra mt file simv trong th mc pre_syn. tip tc vo terminal g lnh sau thc hin m phng chc nng: ./simv -gui sau khi ca s hin ra chn file testbench click chut phi vo chn Add to Wave ri chn New Wave view. Ca s mi hin ra bm F5 hoc chn run (mi tn c chiu hng xung di) s xut hin ra timing cn kim tra. 3.2.2 Kim tra sau khi tng hp To th mc post_syn trong th mc vcs sau khi tng hp bng cng c Design Compiler s sinh ra mt file Netlist c ui m rng l .v bao gm cc cell c bn c ni dy vi nhau v file delay c ui m rng l .sdf. kim tra timming sau khi tng hp cn c 4 file cn thit l: file netlist .v file delay .sdf file th vin cell tcbn45gsbwp.v file testbench .v

Cc file kia cn phi copy vo trong th mc post_syn. vo terminal g cc lnh sau : vlogan -debug +v2k *.v vcs -debug tn file module ca testbench -sdf typ:tn modue top:file.sdf -l comp.log v d: vcs-debug tb_digital_clock_top -sdf typ:digital_clock_top:top.sdf -l comp.log Sau khi phn tch cc file trn trong th mc s to ra file simv. vo terminal g lnh sau: ./simv -gui

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Ri lm tng t nh cc bc trc khi trc khi tng hp. s xut hin cc timming vi c thm tr (mu vng). 3.2.3 Kim tra timming sau khi layout To th mc post_layout trong vcs. Trong qa trnh Layout c th lm sai timing v vy sau khi layout xong cn phi kim tra li timing xem c ng nh timming mnh kim tra sau khi tng hp hay khng. kim tra timming bc ny cn c cc file sau: file .v c to ra sau khi layout file delay .sdf c to ra sau khi layout file th vin cell tcbn45gsbwp.v file testbench .v

Thc hin cc bc tng t nh khi kim tra chc nng trc khi tng hp. 3.3 Design Compiler To th mc dc trong project, vo terminal g lnh: design_vision Giao din ngi dng hin ln:

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Bc 1: Ci t th vin File Setup

Search

path

chn

ng

dn

th

vin

milkyway

~Mikyways/tcbn45gsbwp/frame_only_HVH_0d5_0/tcbngsbwp/LM

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Target

library:

th

vin

cng

ngh

ca

nh

sn

xut

~Mikyways/tcbn45gsbwp/frame_only_HVH_0d5_0/tcbngsbwp/LM/tcbn45gsbwpbc .db Symbol library : th vin k hiu c sn trong th mc ci t ca synopsys

/usr/synopsys/dc/libraries/syn/generic.sdb Synthetic library : th vin tng hp c sn trong th vin ca synopsys

/usr/synopsys/dc/libraries/syn/dw_foundation.sldb Link library : ng dn n th vin bao gm 2 th vin Synthetic library v Target library Bc 2 : To file theo di qu trnh c ui m rng .svf. Vo terminal g lnh: set_svf top.svf Bc 3: c file *.v File Read c tt c cc file verilog trong th mc rtl tr cc file testbench

Bc 4 : Analyze File Analyze

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Chn Add: chn tt c cc file *.v tr file testbench

Bc 5: Elaborate File Elaborate Trong mc Design chn file top module

Bc 6: Kim tra thit k Design Check Design OK Bc ny s kim tra thit k. Trn ca s terminal s c cc cnh bo nn c k

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Bc 7: Set clock constraints Chn vo biu tng trn thanh menu s hin ln schematic

S dng cc phin I (zoom in) v O (zoom out) phng to hoc thu nh s Chn vo tn hiu clk trong s :

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Sau khi chn tn hiu clk vo Atributes trn thanh Menu chn Specify Clock

Ta c cc thit lp sau: Trong mc Clock name t tn l clk Trong mc Period : 1000000000 (ns)(do chu k thc hin ca ng h s l 1s ) Trong mc rising: 0 (ti 0 th xut hin sng ln ca xung nhp) 35

Trong mc falling: 500000000 (ti 500000000 ns th xut hin sn xung ca xung nhp) Chn Don't touch network : trong qu trnh tng hp th tn hiu clock c bo v Chn Fix hold : khc phc cc li hold time sau khi tng hp

Ngoi ra cn c cc rng buc khc bng cch s dng cu lnh nh set_clock_uncertainty 0.01 clk set_clock_latency 0.2 clk n FF set_clock_transition 0.1 clk // thit lp tr chuyn trng thi ca lock ( dc ca sn clock) Bc 8: Thit lp cc rng buc thit k (constrain) Tr u vo: Chn cc tn hiu u vo trn s (tr tn hiu clock) Trn thanh Menu vo Atributes chn Operating Environment Input delay // thit lp lch gia 2 FF k tip nhau

// thit lp tr ca xung clock t b to dao ng

Tr u ra : Chn cc tn hiu ra trn s Trn thanh Menu vo Atributes chn Operating Environment Output delay 36

iu kin hot ng (Operating condition) Trn thanh Menu vo Atributes chn Operating Environment Operating conditions

Wire load: Trn thanh Menu vo Atributes chn Operating Environment Wire load

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Design constraints Trn thanh Menu vo Atributes chn Operating Environment Design constraints

C th thit lp thm cc rng buc v cng sut ng, cng sut dng r, Max fanout, maxtransition.

Bc 9 : Compile Design Trn thanh Menu vo Design Compile Design OK Ngoi ra bn c thm cc la chn sao cho sau qu trnh tng hp thit k ca mnh ti u nht. 38

Bc 10: Compile Ultra Sau qu trnh tng hp thit k, bc ny s va tng hp va ti u ha thit k nhng cng no tha hoc khng cn thit trong qu trnh tng hp s b xa. Trn thanh Menu vo Design Compile Ultra OK

Sau qu trnh tng hp khi xem li s mch s tr nn phc tp hn rt nhiu.

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Bc 11 : Xut bo co Sau khi tng hp kim tra xem thit k ca mnh c p ng c cc yu cu v timing, cng sut, din tch,.. hay khng cn phi xem qua cc bo co m phn mm t ng to ra cho mnh. C mt s bo co in hnh nh sau: report_timing : Timing Report Timing Path report_constraints: Design Report Constraints report_power : Design Report Power report_Resource : Design Report resource

Bc 12 : To file Netlist File Netlist l file m t mc cng ca thit k bao gm cc cell c bn (AND, OR, MUX, FF) c ni dy vi nhau. File Save as

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Bc 13 : To file .ddc File .ddc c s dng cho phn mm ICC layout v kim tra chc nng trong Primetime File Save as

Bc 14 : To file .sdf File .sdf l file nh ngha tr tng cng, dy dn Vo terminal g lnh sau: write_sdf top.sdf

Bc 15 : To file .sdc

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File .sdc (synopsys design constraints) c s dng trong ICC a cc rng buc thit k ca mnh vo thc hin layout. Vo Terminal g lnh sau:

write_sdc top.sdc Bc 16 : Tt file theo di Vo terminal g cu lnh: set_svf -off File .svf c s dng trong qu trnh kim tra Formality

3.4 Formality To th mc fm trong project

thc hin phn mm cn c cc file sau: File theo doi top.svf Cc file code RTL *.v File Netlist top.v

Thc hin: Bc 1: M terminal go lnh hin th giao din ngi dng fm_shell gui

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Bc 2: Chn Guidance chn ng dn n file top.svf Chn Load Files

Bc 3: Chn Reference c tt c cac file verilog tr file testbench Chn Load File

Vo mc 3 chn Set Top Design chn file top module Set top Set reference 43

Bc 4 : Chn Implementation Chn Verilog chn ng dn m file top.v sau khi tng hp trong th mc dc. Chn Load File.

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Chn Read DB Libraries : chn file tcbn45gspbw.v trong th vin Milkyway chn Load Files Chn file top module Set top Set Implementation.

Bc 5: Match Chn Run Matching s co ca s thng bo c bao nhiu im so snh ging nhau va bao nhiu im so snh khc nhau.

Bc 6 : Verify Chn Verify : Trn ca s bo Verify Succeeded tc la kim tra thnh cng. Trong mc Debug s hin ra cac im so sanh gia 2 file code RTL va file netlist.

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3.5 3.5.1

Primetime Kim tra timing trc khi layout

Bc 1 : Ci t th vin To th mc pt trong project Vo th mc pt m ca s lnh g lnh: pt_shell Ci t Search Path:

set lib_path "~/milkyway/tcbn45gsbwp_120a/frame_only_HVH_0d5_0 /tcbn45gsbwp/LM"; set ADDITIONAL_SEARCH_PATH set TARGET_LIBRARY_FILES set_app_var search_path $ADDITIONAL_SEARCH_PATH" set_app_var target_library set_app_var link_library Bc 2 : c file .ddc c file .ddc s dng cu lnh sau: $TARGET_LIBRARY_FILES "* $target_library" "$lib_path";

"tcbn45gsbwpbc.db"; "$search_path

c/syn/ultra_compile.ddc Bc 3: Xut bo co M giao din ngi dng dng lnh : start_gui

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Xut bo co Coverage.txt: Vo timing Analysis Coverage Lu file bo co t tn file l coverage.txt Xut bo co trn ti a : Vo Timing Report Timing Lu tn file l maxdelay.txt

47

Xut bo co tr ti thiu: Report Timing Edit Trong th mc Data type chn min Lu tn file l mindelay.txt 3.5.2 Kim tra timing sau khi layout S dng file .ddc c to ra sau khi chy ICC. Cc bc thc hin tng t nh trc khi layout.

3.6 IC Compiler 3.6.1 Ci t d liu

M ca s giao din ngi dung bng cach go lnh sau: 48

icc_shell gui

Ci t th vin

File Setup Application Setup Thc hin tng t nh bc cai t th vin trong Design Compiler To th vin milkyway

File Creat Library

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C cc thit lp sau: New library path: Chn ng dn n th mc minh cn cha th vic Vi d: /home/TrungHoDuc/VLSI/icc_manual/ New library name : t ten th vin V d : my_library.mw Technology Files: Chn ng dn n file th vin cong ngh trong Milkyway V d: /home/TrungHoDuc/milkyway/tcbn45gsbwp_120a/techfiles/HVH_0d5_0

/tsmcn45_10lm7X2ZRDL.tf Trong mc input reference libraries Chn Add chn n th vin tcnbn45gspwb V d : /home/TrungHoDuc/milkyway/tc

bn45gsbwp_120a/frame_only_HVH_0d5_0 /tcbn45gsbwp 50

Chn Open library

c File top.ddc File Import Read DDC

c file top.sdc

File SDC l file rng buc thit k. N c a vao rng buc thit k sao cho thit k ca mnh ti u nht. File Import Read SDC

Sau khi c file top.sdc s xu hin ca s giao din hin th cc cell c xp chng ln nhau v khung hnh thit k. 51

To TLU+ File Set TLU+

C cc thit lp sau: Max TLU+ file : Chn n th vin cng ngh theo ng dn sau: /home/TrungHoDuc/milkyway/tcbn45gsbwp_120a/techfiles/tluplus/cln45gs_1p10m +alrdl_rcbest_top2.tluplus Min TLU+ file : Chn n th vin cong ngh theo ng dn sau: /home/TrungHoDuc/milkyway/tcbn45gsbwp_120a/techfiles/tluplus/cln45gs_1p10m+ 52

alrdl_rcworst_top2.tluplus Layer name : Chn n th vin cong ngh theo ng dn sau: /home/TrungHoDuc/milkyway/tcbn45gsbwp_120a/techfiles/tluplus/star.map_10M Lu : Trong th vin c nhiu la chn khc nhau ng vi bao nhiu lp kim loi. Nu trong mc Max/Min TLU+ file ch n 10 l p kim lo i thi trong mc Layer name cng lp kim loi. Kim tra th vin: kim tra th vin s dng cc lnh sau : check_library check_tlu_plus_files list_libs

Ngoi ra c th xut cc bo co kim tra xem trong qu trnh layout gp phi vn g khng qua cc lnh sau: check_timing report_timing_requirements report_disable_timing report_case_analysis report_clock report_clock -skew 53

Trong khi tng hp mnh xem cc cng c gian ra mc l tng nn khi layout cn phi xa c tnh ny, s dng cu lnh: remove_ideal_network

Lu ci t d liu Sau khi cai t xong d liu cn lu li bc ny c th d dng xem li cc thit lp ca mnh. s dng cau lnh sau: 3.6.2 save_mw_cel -as data_setup Hoc vao File Save Design Floor Planning

Thc hin khi to nn Floorplan Initialize Floorplan

sau khi khi to nn s c hnh nh sau: 54

Thc hin to chn ni ngun v ni t VDD v VSS PreRoute Derive PG Conection

To cc vng dy VDD v VSS Preroute Creat ring Net(chn VDD) 55

Tip theo chn VSS

Sau khi to c cc vng dy VDD v VSS trn hnh s xut hin nh sau

56

Thit lp rng cho dy ngun dy t cho tng lp kim loi Preroute Creat power strap VDD:

VSS:

57

To vng m: Preroute Creat Pad ring

Sau khi xong bc Floorp Planning ta cn lu li s dng cu lnh save_mw_cel -as floorplanned 3.6.3 Placement (Sp xp cell) va kim tra tc nghn Placement Core Placement and Optimization 58

Sau khi sp xp cc cell xong ta c:

kim tra tc nghn xut bo co sau: report_congestion -grc_based -by_layer -routing_stage global 59

Lu li qu trnh thc hin Placement: save_mw_cel -as placed 3.6.4 To clock tree Clock Core CTS and Optimization

Sau khi to c clock tree:

60

Lu li bc to clock tree save_mw_cel -as ctsed 3.6.5 Thc hin i dy Route Core Routing and Optimization

61

Lu li kt qu sau khi i dy t ng save_mw_cel -as routed

3.6.6 Xut cc file .sdc, .sdf, .v, .spef,.. write_parasitics -output ./rpt/icc.spef -format SPEF write_sdf ./rpt/icc.sdf write_sdc ./rpt/icc.sdc write_ddc ./rpt/icc.ddc write_verilog ./rpt/icc.v

3.6.7 Xut ra cc file bo co report_qor > ./rpt/rpt_icc_qor.txt report_area > ./rpt/rpt_icc_area.txt report_constraint -all_violators > ./rpt/rpt_icc_constraint.txt report_port > ./rpt/rpt_icc_port.txt report_power > ./rpt/rpt_icc_power.txt 62

report_timing > ./rpt/rpt_icc_timing.txt report_timing -nosplit > ./rpt/rpt_icc_timing_nosplit.txt report_timing -delay min > ./rpt/rpt_icc_timing_delay_min.txt report_design -physical > ./rpt/rpt_icc_design_physical.txt

63

KT LUN
Chng em hon thnh thit k ng h s vi cc chc nng c bn hin th gi, pht, giy ln LED 7 thanh. Cc kt qu m phng chc nng trc khi tng hp mch, sau khi tng hp v sau khi layout u chnh xc . Qua qu trnh lm ti ny, Chng em hiu thm v cng ngh thit k ASIC, lung thit k, cc bc thc hin, c tip xc vi b cng c phn mm chuyn nghip Synopsys, bit thm v ngn ng lp trnh m t phn cng verilog.

64

TI LIU THAM KHO

1. Verilog HDL by Samir Palnitkar. 2. ASIC Design Flow Uvision. 3. Asic Design Flow Tutorial Using Synopsys Tools by Hima Bindu Komoru Hamid Mahmoodi. 4. Ti liu hng dn ca synopsys.

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