UH30OSD

TARGET SPECIFICATION

OCTAL INTELLIGENT SQUIB DRIVER

EIGHT SQUIB DEPLOYMENT DRIVERS (1.2A/2ms AND 1.75A/4ms); DEPLOYMENT CURRENT AND TIME PROGRAMMABLE VIA SPI CAPABILITY TO DEPLOY WITH 1.47A (2.14A) UNDER 40V (21V) LOAD-DUMP CONDITION AND THE LOW SIDE FET SHORTED TO 1V. 5.5MHZ SPI INTERFACE WITH MESSAGE VALIDATION 4 CHANNELS OF DISCRETE/SERIAL LOGIC ARMING INTERFACE PROGRAMMABLE VIA SPI DEPLOYMENT DRIVER SELF-DIAGNOSTICS: - SHORT TO BATTERY/GROUND AND OPEN CIRCUIT - SQUIB RESISTANCE MEASUREMENT - SHORT BETWEEN CHANNELS DETECTIONS - HIGH AND LOW SIDE FET TESTS - GROUND LOSS DETECTION -40 C TO +85 C OPERATING AMBIENT TEMPERATURE 4KV ESD CAPABILITY ON ALL OUTPUT-DRIVER PINS AND 2KV ON ALL OTHERS

MULTIPOWER BCD4 TECHNOLOGY

TQFP44 10 x 10mm
deployment drivers. It provides short to battery and ground protection, open circuit protection, individual squib resistance measurement, capability to detect shorts between channels, tests for high and low side FETs and ground loss detection. The device has individual control pins for each of the drivers, including a separate ground pin. It also features arming inputs that act as a fail-safe mechanism to prevent inadvertent deployment.

DESCRIPTION
The UH30OSD is an Octal Intelligent Squib Driver ASIC in 44pin Thin Quad Flat Pack (TQFP) package designed using ST proprietary BCD4 technology. It is designed to deploy airbag squibs and provide diagnostics for each of the deployment drivers. Each of the eight drivers is sized to deliver 1.2A or 1.75A min for 2ms or 4ms. The deployment current and time are programmable via SPI. The device has full diagnostic capability via SPI on the

BLOCK DIAGRAM VRM VDD

IREF
x = 0 to 7 (8 modules)

VRx TEST / DEN

RESET
HSD
ISENSE

SHx MISO MOSI SCLK CS DIAGNOSTICS SLx

SPI

LSD
ISENSE

GNDx

For x = 1 to 7
GND0

FSxx

FSxx / FSyy

20-May-03 Rev. 1.1

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UH30OSD PIN CONNECTIONS (top view)

39 VRMEAS 44 VRES0 43 VRES1 35 VRES2 38 GND2 37 SQL2 40 GND1 42 SQH1 36 SQH2 41 SQL1 34 VRES3

SQH0 1 SQL0 2 GND0 3 ARMCLK/ARM45 4 ARMOUT/ARM67 5 ARMEN/ARM23 6 ARMIN/ARM01 7 TEST/DEPEN 8 GND7 9 SQL7 10 SQH7 11

33 SHLH3 32 SQL3 31 GND3 30 SCLK 29 MOSI 28 MISO 27 VDD 26 IREF 25 GND4 24 SQL4 23 SQH4

12 VRES7

13 VRES6

14 SQH6

15 SQL6

16 GND6

17 CS

18 GND5

19 SQL5

20 SQH5

21 VRES5

22 VRES4

ABSOLUTE MAXIMUM RATINGS Symbol VDD VIN VRM VRx SHx, SLx Tj Tstg Supply Voltage Discrete Input Voltage Supply Voltage for Resistance Measurement Reserve Voltage for Loop Channels (x = 0 to 7) Squib High Side and Low Side Drivers output (x = 0 to 7) Junction Temperature Storage Temperature -40 Parameter min -0.3 -0.3 -0.3 -0.3 -1 Value max +6.5 +6.5 +40 +40 +40 +150 +150 Unit V V V V V C C

20-May-03 Rev. 1.1

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UH30OSD DEVICE PIN OUT Pin Nbr 1 42 36 33 23 20 14 11 2 41 37 32 24 19 15 10 44 43 35 34 22 21 13 12 7 Pin Name SH0 SH1 SH2 SH3 SH4 SH5 SH6 SH7 SL0 SL1 SL2 SL3 SL4 SL5 SL6 SL7 VR0 VR1 VR2 VR3 VR4 VR5 VR6 VR7 FSIN FS01 FSEN FS23 FSCLK FS45 FSOUT FS67 GND0 GND1 GND2 Description High Side Driver Output for Channel 0 High Side Driver Output for Channel 1 High Side Driver Output for Channel 2 High Side Driver Output for Channel 3 High Side Driver Output for Channel 4 High Side Driver Output for Channel 5 High Side Driver Output for Channel 6 High Side Driver Output for Channel 7 Low Side Driver Output for Channel 0 Low Side Driver Output for Channel 1 Low Side Driver Output for Channel 2 Low Side Driver Output for Channel 3 Low Side Driver Output for Channel 4 Low Side Driver Output for Channel 5 Low Side Driver Output for Channel 6 Low Side Driver Output for Channel 7 Reserve Voltage for Loop Channel 0 Reserve Voltage for Loop Channel 1 Reserve Voltage for Loop Channel 2 Reserve Voltage for Loop Channel 3 Reserve Voltage for Loop Channel 4 Reserve Voltage for Loop Channel 5 Reserve Voltage for Loop Channel 6 Reserve Voltage for Loop Channel 7 Fail Safe Serial Mode Data Input Fail Safe Input Signal for Channels 0 and 1 Fail Safe Serial Mode Data Enable Fail Safe Input Signal for Channels 2 and 3 Fail Safe Serial Mode Clock Input Fail Safe Input Signal for Channels 4 and 5 Fail Safe Serial Mode Data Output Fail Safe Input Signal for Channels 6 and 7 Power Ground 0 Power Ground 1 Power Ground 2 I/O type Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Input Input Input Input Input Input Input Input Input Input Input Input Input Input Output Input -

5 3 40 38

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UH30OSD Device Pin Out (continued) Pin Nbr 31 25 18 16 9 8 17 30 29 28 26 27 39 Pin Name GND3 GND4 GND5 GND6 GND7 TEST DPEN CS SCLK MOSI MISO IREF VDD VRM Power Ground 3 Power Ground 4 Power Ground 5 Power Ground 6 Power Ground 7 Test Input Pin Deployment Enable SPI Chip Select SPI Clock SPI Data In SPI Data Out External Current Reference Resistor VDD Supply Voltage Supply Voltage for Resistance Measurement Description I/O type Input Input Input Input Input Output Output Input Input

DC ELECTRICAL CHARACTERISTICS(-40C < Tj < 95C, 4.9V < VDD < 5.1V, 6.5V < VRES < 40V, 7.0V < VRMEAS < 26.5V unless otherwise specified) General IC Parameters Symbol VRST IDD IDD VIH VIL ILKG ILKG VTEST H VTEST L IPD VOH VOL Iz Parameter VDD Internal Reset voltage VDD Supply current VDD Supply current Input threshold voltage
MOSI, SCLK, CS, ARMx, DEPEN

Test Condition Lower VDD Voltage until deployment drivers are disabled Normal or shorted SQL or SQH (Shorted to -1V) Deployment Input Logic 1 Input Logic 0 VIN = VDD 0V < VIN < VIH Logic 1 Logic 0 VIL < VIN < VDD IOH < 800A (out of the part) IOL < 1.6mA (into the part) 0V < MISO < VDD

Min. 4.2

Typ.

Max. 4.7 5

Unit V mA mA

TBD 2.0 0.8 1 -1 TBD TBD 10 VDD0.8 0.4 -10 10 50

V V A A V V A V V A

Input threshold voltage

MOSI, SCLK, CS, ARMx, DEPEN

Input leakage current MOSI, SCLK Input leakage current MOSI, SCLK TEST Input threshold Voltage TEST Input threshold Voltage Input pull down current ARMx, CS, DEPEN Output high Voltage MISO Output Low Voltage Tristate Current MISO

20-May-03 Rev. 1.1

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UH30OSD DC ELECTRICAL CHARACTERISTICS(-40C < Tj < 95C, 4.9V < VDD < 5.1V, 6.5V < VRES < 40V, 7.0V < VRMEAS < 26.5V unless otherwise specified) Deployment Drivers DC Parameters Symbol ISQH_LKG ISQH_STG ISQL_LKG ISQL_STG ISQL_STB IPD IRES VSGth VSBth VOCth VLDth ID_SRC ID_SNK RDS(on) RDS(on) RDS(on) IDEP IDEP ILIM IBIAS VBIAS RIREF_O RIREF_S RL_RNGE1 ADCacc ADCacc ADCRES IPEAK1
20-May-03 Rev. 1.1
1 design information only

Parameter SQH Leakage current SQH Leakage current SQL Leakage current SQL Leakage current SQL Leakage current SQL Pulldown current VRESx Bias current Short to GND threshold Short to B+ threshold Open Circuit threshold FET Test load detect Resistance meas. current source Resistance meas. current sink Total High + Low side on resistance High Side FET on resistance Low Side FET on resistance Deployment current Deployment current Low side FET current limit Diagnostic Bias current Diagnostic Bias voltage IREF open circuit resistance threshold IREF short circuit resistance threshold Load Resistance range ADC Accuracy ADC Accuracy ADC Resolution FET transient response

Test Condition VRMEAS=VDD=VSQH=0V, VRESx=36V VRMEAS=18V, VDD=5V, VSQH= -1V VRMEAS=VDD= 0V, VSQL=18V (not during diagnostic) VRMEAS=18V, VDD=5V, VSQL= -1V VRMEAS=18V, VDD=5V, VSQL= 18V VSQLx = 1.8V - VDD VRMEAS=18V, VDD=5V, SQH shorted to SQL, VRESx=36V VDD=5.0V VDD=5.0V VDD=5.0V

Min.

Typ.

Max. 50

Unit A MA

-5 -10 -5 5 500 700 10 1.9 3.9 1.9 100 2.1 4.1 2.1 300 42 55 1.5 TBD TBD 1.2 1.75 1.75 -6 2.7 1.47 2.14 2.14 -3 3.3 62.5 6.25 0.0 10 5 5 8 10

A A A A A V V V MV mA mA A A

VDD=5V, 7.0V<VRMEAS<26.5V

38 45

High side FET + Low side FET Vres=6.9V, I=1.2A@95C VRES=40V, IVRES=1.1A, TA=150C VRES=40V, IVRES=1.1A, TA=150C MOSI: command mode D11=0, RLOAD=5.3, 12V<VRES<21V MOSI: command mode D11=1, RLOAD=5.3, VSQH=18V MOSI: command mode D11=1/0, RLOAD=5.3, 12V<VRES<21V VSQH=0V, device configured to run in diagnostic mode via SPI ISQH=-1.5mA Open circuit Short circuit %0000 0000=0 %1111 1111=10 4.0<RL<10 0.0<RL<4.0

IPD V K K % counts bits

(peak current)See fig.

2.0

IFINAL
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UH30OSD DC ELECTRICAL CHARACTERISTICS(-40C < Tj < 95C, 4.9V < VDD < 5.1V, 6.5V < VRES < 40V, 7.0V < VRMEAS < 26.5V unless otherwise specified) Deployment Drivers AC Characteristics Symbol tPOR tON Parameter POR De-glitch timer FET turn on time tSETTLE FET settling time tPULSE tP_ACC tGLITCH tDEPLOY tDEPLOY tTIMEOUT tFLT_DLY ISLEW tRES TFET_ON tDETECT tPROP_DLY tDIAG1 Pulse Stretch Timer Puse Stretch Timer Accuracy Pulse Stretch De-glitch timer Deployment time Deployment time Diagnostic Bias current time Fault detection Filter RMEAS Current di/dt Resistance Measurement time FET test turn on time FET test detection window FET turn off propogation delay Diagnostic time ARMx & DEPEN pins asserted. time from CS falling edge to 90% of IFINAL. ARMx & DEPEN pins asserted. time from CS falling edge to 90% to 110% of IFINAL. See table Test Condition Min. 5 Typ. Max. 20 150 Unit s s s ms % s ms ms

300 0 -20 5 60 20 25 2.5 4.5

6.9V<VRES<40V, Deployment Period bit = 0 12V<VRES<21V, Deployment Period bit = 1 Duration required to bias SQHx &SQLx above SGth & OCth

2 4

10 From falling edge od CS to end of resistance measurements On time of LS and HS drivers during a FET test LS & HS FET fault detection window LS/HS FET fault to LS/HS turn-off duration Falling edge of CS to SPI diag. complete duration Single loop, FET test disabled Falling edge of CS to SPI diag. complete duration Multiple loops, FET tests disabled

50 40 2

s mA /s ms ms ms s ms

2.5 4 10 4

ms 32

tDIAG_MULT

Diagnostic time

FET Turn-on and settling times

20-May-03 Rev. 1.1
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UH30OSD DC ELECTRICAL CHARACTERISTICS(-40C < Tj < 95C, 4.9V < VDD < 5.1V, 6.5V < VRES < 40V, 7.0V < VRMEAS < 26.5V unless otherwise specified) SPI Port AC characteristics Symbol fOP Parameter Operating Frequency SCLK period Enable Lead Time Enable Lag Time SCLK High Time SCLK low Time MOSI Input Set-up time MOSI Input Hold time MISO Access time MISO disable time MISO Output valid time MISO Output Hold time Rise time Fall time CN Negated time Measured with minimal capacitance Design information only Design information only 100 0 30 30 Measured with minimal capacitance (see fig. Xxx) Test Condition Min. DC 181 62 50 65 65 20 20 66 100 45 Typ. Max. 5.5 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns

tSCK tLEAD tLAG tSLCKHS tSLCKLS tSUS tHS tA tDIS tVS tHO tRO tFO
tCSN

SPI Timing diagram

MISO Disable Time Measurement loading

20-May-03 Rev. 1.1
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UH30OSD

DC ELECTRICAL CHARACTERISTICS(-40C < Tj < 95C, 4.9V < VDD < 5.1V, 6.5V < VRES < 40V, 7.0V < VRMEAS < 26.5V unless otherwise specified) Arming Serial Mode AC characteristics Symbol fOP Parameter Operating Frequency ARMCLK Period Enable Lead Time Enable Lag Time ARMCLK high time ARMCLK low time ARMIN Input Set-up time ARMIN Input Hold time ARMOUT Access time ARMOUT Output valid time ARMOUT Output Hold time Rise time Fall time ARMEN Negated time Design information only Design information only 200 10 30 30 Test Condition Min. DC 500 250 100 220 220 30 10 125 190 Typ. Max. 2.0 Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns

tARMCLK tLEAD tLAG tARMCLK_HS tARMCLK_LS tSUS tHS tA tVS tHO tRO tFO
tARMEN_N

Arming Serial Mode timing diagram

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UH30OSD

Package Outline

20-May-03 Rev. 1.1

This copyrighted document is property of STMicroelectronics and is disclosed in confidence. It may not be copied, disclosed to others or used for manufacturing without the prior written consent of STMicroelectronics

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