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MDLOGIC SOLUTIONS - #4 Arcot Road, Kodambakkam, Chenna !4 "!##$##"4# % #4444##"4# md&o' c(o&)t on(*'ma &+com operation even in small supply voltages. !ithout complicating the design and by adding few transistors, the positive feedbac" during the regeneration is strengthened, which results in remar"ably reduced delay time. #ost-layout simulation results in a $.%&-m '()* technology confirm the analysis results. It is shown that in the implemented dynamic comparator both the power consumption and delay time are significantly reduced. 0RO0OS3D S5ST3M In the proposed system a digitally controlled dual tail comparator is designed with tunable threshold is designed. 6sing the auto tunable threshold a comparator is capable of generating the digital signal from analog input through a systematic manner which achieve tolerance and efficiency SO6T7AR3 R38UIR3M3NT Design 7nvironment8 9ILI:9 I*7 Language8 20DL *imulation8 ()D7L*I( ; 9ILI:9 I*7 *imulator 9ARD7AR3 R38UIR3M3NT 9ILI:9 *#<=+<: Development Device8 9'4*.$$7 oard