EDK Overview

This material exempt per Department of Commerce license exception TSU

2010 Xilinx, Inc. All Rights Reserved

Objectives
After completing this module, you will be able to:

Describe the embedded systems development flow Describe the components in the hardware design Specify ways to create a hardware design Identify the tools included in the Embedded Development Kit (EDK)

12- 2

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Outline
Introduction EDK
Overview of EDK Embedded Development Design Flow Embedded Project Management

Supported Platforms Appendix: Project Files and Structure

12- 3

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Embedded System
An embedded system is nearly any computing system (other than
a general-purpose computer) with the following characteristics:
Single function
Typically designed to perform a predefined function

Tightly constrained

Tuned for low cost Single-to-fewer component based Performs functions fast enough Consumes minimum power

Reactive and real-time

Must continually monitor the desired environment and react to changes

Hardware and software coexistence

12- 4

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Embedded Systems
Examples:
Mobile phone systems
Customer handsets and base stations

Automotive applications
Braking systems, traction control, airbag release systems, and cruise-control applications

Aerospace applications
Flight-control systems, engine controllers, auto-piloting systems, and passenger in-flight entertainment systems

Defense systems
Radar systems, fighter aircraft flight-control systems, radio systems, and missile guidance systems

12- 5

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Current Technologies

Microcontroller-based systems DSP processor-based systems ASIC technology FPGA technology

12- 6

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Integration in System Design

Embedded Software Tools

Integration of Functions

CPU CPU
Embedded Software Tools Embedded Software Tools

Logic + Memory + IP + Processors + RocketIO (Virtex-II Pro)

Logic Design Tools

FPGA

FPGA + Memory + IP + High Speed IO (4K & Virtex )

Logic Design Tools

I/O Memory
Logic Design Tools

Programmable systems usher in a new era of system design integration possibilities

Time
12- 7 EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Embedded Design in an FPGA

Embedded design in an FPGA consists of the following:
Develop FPGA hardware design Generate drivers and libraries Create the software application
Software routines Interrupt service routines (optional) Operating System (OS) or Real Time Operating System (RTOS) (optional)

12- 8

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

MicroBlaze Processor-Based Embedded Design

BRAM Local Memory Bus I-Cache BRAM

MicroBlaze
32-Bit RISC Core

Configurable Sizes D-Cache BRAM

Another segment of PLB necessary when slow devices to be operated at slower bus speed enabling higher-performance system Arbiter required only when a peripheral is master capable and wants to write to peripheral on the other segment

Arbiter

0,1.15
Custom Functions Custom Functions

Processor Local Bus

Bus Bridge

Processor Local Bus

CacheLink

10/100 E-Net

Memory Controller

UART

GPIO

On-Chip Peripheral

SDRAM

Off-Chip FLASH/SRAM Memory

Hardware Design
2010 Xilinx, Inc. All Rights Reserved

This is a v7.3 architecture. Versions 7.0, 7.1, and 7.2 supported OPB bus off the core if PLB interface was disabled Versions 6.0 or earlier did not support PLB bus off the processor. Instead they had OPB bus
13- 9

For Academic Use Only

PowerPC Processor-Based Embedded Design

RocketIO DSOCM BRAM

Dedicated Hard IP

PowerPC 405 Core

Data

ISOCM BRAM

Flexible Soft IP
IBM CoreConnect on-chip bus standard PLB, OPB, and DCR

Instruction

DCR Bus OPB

Arbiter

PLB
Processor Local Bus

Bus On-Chip Peripheral Bus Bridge

Hi-Speed Peripheral

e.g. Memory Controller

GB E-Net

UART

GPIO

On-Chip Peripheral

Off-Chip Memory

ZBT SSRAM

DDR SDRAM

SDRAM
EDK Overview

Full system customization to meet performance, functionality, and cost goals

12- 10

2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Arbiter

Fast Simplex Link

PLB

PLB

Arbiter

Outline
Introduction EDK
Overview of EDK Embedded Development Design Flow Embedded Project Management

Supported Platforms Appendix: Project Files and Structure

12- 11

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Embedded Development Kit

What is Embedded Development Kit (EDK)?
The Embedded Development Kit is the Xilinx software suite for
designing complete embedded programmable systems The kit includes all the tools, documentation, and IP that you require for designing systems with embedded IBM PowerPC hard processor cores, and/or Xilinx MicroBlaze soft processor cores It enables the integration of both hardware and software components of an embedded system

12- 12

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Embedded Development
Tool Flow Overview
C Code VHDL or Verilog Standard Embedded SW Development Flow Embedded Development Kit Standard FPGA HW Development Flow

Code Entry Include the BSP C/C++ Cross Compiler and Compile the Software Image Linker

Board Support Package Data2MEM

HDL Entry System Netlist Instantiate the Simulation/Synthesis System Netlist and Implement Implementation the FPGA

?
Load Software Into FLASH Debugger

Compiled ELF

Compiled BIT

Download Combined Image to FPGA

Download Bitstream Into FPGA Chipscope

RTOS, Board Support Package

12- 13

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Embedded Design Flow

A. Develop the embedded hardware
Quickly create a system targeting a board using Base System Builder Wizard Extend the hardware system, if necessary, by adding peripherals from the IP Catalog Generate HDL netlists using PlatGen

B. Develop the embedded software

Generate libraries and drivers with LibGen Create and debug the software application using Software Development Kit (SDK) Optionally, debug the application using Xilinx Microprocessor Debug (XMD) and the GNU
debugger (gdb)

C. Operate in hardware
Generate the bitstream and configure the FPGA using iMPACT

D. Deploy
Initialize external flash memory using the Flash Writer utility or boot from an external compact
flash configuration file generated using the System ACE File generator (GenACE) script

12- 14

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

EDK Tool Flow Do it in SDK

Library Generation
MSS MHS

Hardware Platform Generation

IP Models

CompXLib

ISE Models

IP Library or User Repository EDK SW Libraries Drivers, MDD Libraries, OS, MLD MPD, PAO Pcore HDL PlatGen

LibGen

SimGen

.a

System and Wrapper VHD ISE Synthesis (XST) Tools NGC

system.bmm

Behavioral VHD Model

Embedded Software Development

Application Source .c, .h, .s Compiler (GCC) UCF

NGDBuild NGD MAP, PAR

SimGen

Structural VHD Model

.o, .a NCD Linker Script Linker (GCC) system_bd.bmm BitGen SimGen ELF BITINIT system.bit Timing VHD Model Simulation download.cmd iMPACT

XMD, GDB

download.bit

Simulation Generator

JTAG Cable FPGA

12- 15

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Xilinx Platform Studio (XPS)

use the Filter pane to create filters for bus interfaces or ports

Access project files

Develop software applications

Access design overview information, reports, and messages View a block diagram of the system
For Academic Use Only

Select cores from the IP catalog

12- 16

Connect the hardware system

EDK Overview

2010 Xilinx, Inc. All Rights Reserved

XPS Functions
Project management
Creation of Microprocessor Hardware Specification (MHS) or Microprocessor Software Specification (MSS) file Xilinx Microprocessor Project (XMP) file

Platform management

Tool flow settings Software platform settings Tool invocation Debug and simulation

12- 17

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Outline
Introduction EDK
Overview of EDK Embedded Development Design
Flow Embedded Project Management

Supported Platforms Appendix: Project Files and Structure

12- 18 EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Create/Open a Project
Create a new project
Using File New Project or
toolbar button

Select Base System Builder option

The Base System Builder (BSB) wizard helps you quickly build a working
system targeted at a specific development board

Select Blank XPS Project option Open an existing project

Using File Open Project or
toolbar button

Browse to a pre-created project directory and selecting

an xmp file
Using File New Project or
toolbar button
Select Open a Recent Project option and selecting a project

Project information is saved in the Xilinx Microprocessor

Project (XMP) file
12- 19 EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Create a Project
Automatically with Base System Builder
1. 2. 3. 4. 5. 6. 7.
Select a target board Configure your system Configure the processor Select and configure the peripherals Configure the cache Configure the applications Generate the design
Generated files:

system.mhs System.xmp etc/fast_runtime.opt pcore directory (empty) system.mss data/system.ucf etc/download.cmd system.bsb (optional, if selected) TestApp_Memory_LinkScr.ld TestApp_Periperal_LinkScr.ld
EDK Overview
2010 Xilinx, Inc. All Rights Reserved

TestApp_Memory_microblaze_0/src directory containing

TestApp_Memory.c TestApp_Peripheral.c
12- 20

TestApp_Peripheral_microblaze_0/src directory containing

For Academic Use Only

10

Create a Project
For a Custom Board with BSB
1. Select a custom board creation option Select architecture, device, package, and speed grade Select board reset polarity
2. Configure your system

3. Configure the processor(s) and peripheral(s) 4. Configure the cache if enabled 5. Configure the applications 6. Generate the design 7. Create UCF file and update the download.cmd file to specify the FPGA position in the JTAG chain 8. Generate Bitstream
12- 21 EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Create a Project
From Scratch
1. Identify a New XPS Project location

Select target FPGA, and optionally import an MHS file and/or user repository directory

2. Using IP Catalog, add processor(s) and peripheral(s) 3. Configure the processor(s) and peripherals 4. Create UCF file 5. Specify Software Configuration for the hardware components 6. Develop application software 7. Generate Bitstream 8. Download Bitstream and Execute
12- 22 EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

11

Hardware Creation Flow

Library Generation
MSS MHS

Hardware Platform Generation

IP Models

CompXLib

ISE Models

IP Library or User Repository EDK SW Libraries Drivers, MDD Libraries, OS, MLD MPD, PAO Pcore HDL PlatGen

LibGen

SimGen

.a

System and Wrapper VHD ISE Synthesis (XST) Tools NGC

system.bmm

Behavioral VHD Model

Embedded Software Development

Application Source .c, .h, .s Compiler (GCC) UCF

NGDBuild NGD MAP, PAR

SimGen

Structural VHD Model

.o, .a NCD Linker Script Linker (GCC) system_bd.bmm BitGen SimGen ELF BITINIT system.bit Timing VHD Model Simulation download.cmd iMPACT

XMD, GDB

download.bit

Simulation Generator

JTAG Cable FPGA

12- 23

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Hardware Creation Flow

Platform Generator PlatGen
Input file MHS and MPD
MHS file defines the configuration of the embedded processor system including bus
architecture, peripherals and processor(s), interrupt request priorities, and address space

MPD file defines the configurable parameters with their default values and available ports
for a peripheral

Output files system netlist, peripheral netlists, and BMM file Creates the synthesis, HDL, and implementation directories Generates the HDL wrapper files for the peripherals Generates the top-level system HDL file Extracts the peripheral netlists from the EDK install directory Generates the BMM file Calls XST to synthesize the top-level wrapper file

12- 24

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

12

Hardware Implementation Flow

Library Generation
MSS MHS

Hardware Platform Generation

IP Models

CompXLib

ISE Models

IP Library or User Repository EDK SW Libraries Drivers, MDD Libraries, OS, MLD MPD, PAO Pcore HDL PlatGen

LibGen

SimGen

.a

System and Wrapper VHD ISE Synthesis (XST) Tools NGC

system.bmm

Behavioral VHD Model

Embedded Software Development

Application Source .c, .h, .s Compiler (GCC) UCF

NGDBuild NGD MAP, PAR

SimGen

Structural VHD Model

.o, .a NCD Linker Script Linker (GCC) system_bd.bmm BitGen SimGen ELF BITINIT system.bit Timing VHD Model Simulation download.cmd iMPACT

XMD, GDB

download.bit

Simulation Generator

JTAG Cable FPGA

12- 25

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Hardware Implementation Flow

Hardware netlists must be implemented with the Xilinx
implementation tools Either the manual approach (ISE Project Navigator) or automatic approach (Xflow batch tool) can be used to implement the design
The ISE Project Navigator GUI gives you access to the whole suite of Xilinx design entry and physical implementation point tools Xflow is a non-graphical tool that encapsulates the Xilinx implementation and simulation flows
Device independent and has a simple interface to the Xilinx tools that is flexible, extensible, and user customizable Using this batch tool enables an abbreviated and simplified flow

12- 26

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

13

Library Generation Flow

Library Generation
MSS MHS

Hardware Platform Generation

IP Models

CompXLib

ISE Models

IP Library or User Repository EDK SW Libraries Drivers, MDD Libraries, OS, MLD MPD, PAO Pcore HDL PlatGen

LibGen

SimGen

.a

System and Wrapper VHD ISE Synthesis (XST) Tools NGC

system.bmm

Behavioral VHD Model

Embedded Software Development

Application Source .c, .h, .s Compiler (GCC) UCF

NGDBuild NGD MAP, PAR

SimGen

Structural VHD Model

.o, .a NCD Linker Script Linker (GCC) system_bd.bmm BitGen SimGen ELF BITINIT system.bit Timing VHD Model Simulation download.cmd iMPACT

XMD, GDB

download.bit

Simulation Generator

JTAG Cable FPGA

12- 27

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Library Generation Flow

Library Generator LibGen
Input files MSS Output files libc.a, libXil.a, libm.a LibGen is generally the first tool run to configure libraries and device drivers
The MSS file defines the drivers associated with peripherals, standard input/output devices, and other related software features

LibGen configures libraries and drivers with this information and produces an archive of object files:
libc.a - Standard C library libXil.a - Xilinx library libm.a - Math functions library

12- 28

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

14

Software Application Flow

Library Generation
MSS MHS

Hardware Platform Generation

IP Models

CompXLib

ISE Models

IP Library or User Repository EDK SW Libraries Drivers, MDD Libraries, OS, MLD MPD, PAO Pcore HDL PlatGen

LibGen

SimGen

.a

System and Wrapper VHD ISE Synthesis (XST) Tools NGC

system.bmm

Behavioral VHD Model

Embedded Software Development

Application Source .c, .h, .s Compiler (GCC) UCF

NGDBuild NGD MAP, PAR

SimGen

Structural VHD Model

.o, .a NCD Linker Script Linker (GCC) system_bd.bmm BitGen SimGen ELF BITINIT system.bit Timing VHD Model Simulation download.cmd iMPACT

XMD, GDB

download.bit

Simulation Generator

JTAG Cable FPGA

12- 29

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Software Application Flow

Compile program sources
Input files *.c, *.c++, *.h, libc.a, libXil.a, libm.a Output files executable.elf This invokes the compiler for each software application and builds the executable files for each processor Four stages:
Pre-processor: Replaces all macros with definitions as defined in the .c or .h files Machine-specific and language-specific compiler: Compiles C/C++ code Assembler: Converts code to machine language and generates the object file Linker: Links all the object files using user-defined or default linker script

12- 30

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

15

Merging Hardware and Software Flow

Library Generation
MSS MHS

Hardware Platform Generation

IP Models

CompXLib

ISE Models

IP Library or User Repository EDK SW Libraries Drivers, MDD Libraries, OS, MLD MPD, PAO Pcore HDL PlatGen

LibGen

SimGen

.a

System and Wrapper VHD ISE Synthesis (XST) Tools NGC

system.bmm

Behavioral VHD Model

Embedded Software Development

Application Source .c, .h, .s Compiler (GCC) UCF

NGDBuild NGD MAP, PAR

SimGen

Structural VHD Model

.o, .a NCD Linker Script Linker (GCC) system_bd.bmm BitGen SimGen ELF BITINIT system.bit Timing VHD Model Simulation download.cmd iMPACT

XMD, GDB

download.bit

Simulation Generator

JTAG Cable FPGA

12- 31

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Merging Hardware and Software Flows

BitInit Update the bitstream
Input files system_bd.bmm, system.bit, executable.elf Output file download.bit This invokes the data2MEM tool, which initializes the instruction memory of the processor The instruction memory may be initialized with a bootloop, bootloader, or an actual application This is the stage where the hardware and the software flows come together. This stage also calls the hardware and software flow tools if required

12- 32

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

16

Configuring the FPGA

Download the bitstream
Input file download.bit This downloads the download.bit file onto the target board using the Xilinx iMPACT tool in batch mode XPS uses the etc/download.cmd file for downloading the bitstream
The download.cmd file contains information such as the type of cable is used and the position of the FPGA in a JTAG chain

12- 33

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Outline
Introduction EDK
Overview of EDK Embedded Development Design Flow Embedded Project Management

Supported Platforms Appendix: Project Files and Structure

12- 34

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

17

XPS Platform Management

Platform management tasks of XPS include:

Hardware Generation (PlatGen) Library and device driver configuration (LibGen) Simulation model generation (SimGen) Implementation (Xflow or ISE) Compilation (GNU Compiler) Bitstream initialization (Data2MEM)

For changing the system specification and software settings, XPS

supports the following features and processes:
Add cores, edit core parameters, and make bus and port connections through System Assembly view Generate and modify MSS file through Software Platform Settings Tool Flow Settings Tool Invocation

12- 35

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Modifying the Hardware

Add cores, edit core parameters, and make bus and port
connections through System Assembly view
Select IP Catalog tab to add peripherals 1
Select a core and drop it in
the system view or doubleclick on it to add

In the System View select an 2 instance, right click, and then select Delete Instance Change settings using 3 appropriate filters and select an instance
Base and end addresses Parameters Ports
12- 36 EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

18

Setting Project Options

XPS supports project options settings for:
General tab Design Flow tab

12- 37

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Project Options
General Tab
Set/Change Target Device

Architecture Device Size Package Speed Grade

Show dialog for evaluation cores Project Peripheral Repository

Specify the user repositories containing custom pcores, drivers, Board Support Packages (BSPs), and Software Services

Custom Makefile Directory

Specify a custom make file to be used instead of the make file generated by XPS. The custom make file cannot have the same name as XPS-generated make files: <system>.make or <system>_incl.make.

12- 38

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

19

Project Options
Design Flow Tab
HDL selection Testbench generation option Simulation Models
Choice of simulator and simulation
libraries search path settings are done in XPS preference settings (Edit Preferences)

12- 39

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Outline
Introduction EDK
Overview of EDK Embedded Development Design Flow XPS Platform Management

Supported Platforms Appendix: Project Files and Structure

12- 40

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

20

Supported Platforms
Operating systems

Windows XP 32/64-bit SP2 Professional Windows Vista Business 32-bit Linux Red Hat Enterprise (4.0 and 5.0 32-bit/64-bit) SUSE Linux Enterprise 11, 32/64-bit

FPGA families
Spartan-3E/3A/AN (MicroBlaze processor) Spartan-3A DSP (MicroBlaze processor) Spartan-6 (MicroBlaze processor) Virtex-4 FX (MicroBlaze and PowerPC processors) and LX/SX (MicroBlaze processor) Virtex-5 FXT (MicroBlaze and PowerPC processors) and LX/LXT/SXT (MicroBlaze processor) Virtex-6 FPGAs (MicroBlaze processor)
12- 41 EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

BSB-Supported Platforms
A list of supported Xilinx hardware boards:

Spartan-3A/3AN Starter Kits Spartan-3E Starter Kit Spartan-3E 1600E MicroBlaze Development Kit Spartan-3A DSP 1800A Starter Kit Spartan-3A DSP 3400A Spartan-6 SP601, SP605 Virtex-4 ML402, ML403, ML405, ML410 Virtex-5 ML505, ML506,ML507,ML510 Virtex-6 ML605 Custom board

Board definition (.xbd) files for third party boards can be

downloaded from the board vendor web site
Links from the BSB wizard and Xilinx embedded Web page
12- 42 EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

21

Outline
Introduction EDK
Overview of EDK Embedded Development Design Flow XPS Platform Management

Supported Platforms Appendix: Project Files and Structure

12- 43

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Project Directory Structure

project_directory data - created by default upon project creation etc - created by default upon project creation pcores - created by default upon project creation __xps - created by default upon project creation ppc445_0/ppc405_0/microblaze_0 - created by default upon project creation implementation - created during PlatGen synthesis - created during PlatGen hdl - created during PlatGen

12- 44

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

22

Project Files and Structure

ppc445_0/ppc405_0 / microblaze_0
include

*.h header files

libsrc

BSP, drivers, etc.

lib libc.a file libm.a file libxil.a file boot.o file Code (default repository if user application is not defined)
executable.elf file
12- 45 EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Project Files and Structure

pcores
Peripheral IP files

data
system.ucf file

Code or user-defined software application

*.c / *.cpp, *.h files

etc
download.cmd file fast_runtime.opt file BSDL files

12- 46

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

23

Project Files and Structure

__xps
makefile

synthesis
system.scr file

HDL
system.[vhd|v], system_stub.[vhd|v]* file Peripheral_wrapper.[vhd|v] files

implementation
peripheral_wrapper.ngc files system.ngc, system_stub.ngc* file system.bmm file

* files created if system is a submodule

12- 47 EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Project Structure
Project Directory

MAKE

PBD

MHS

MSS

mblaze/ppc405_i

etc

__xps

code

data

pcores

implementation

hdl

synthesis

CMD BSDL

OPT

OPT

.C

.H

UCF <ip_name>

NGC

BMM

VHD

SCR

code

include

lib

libsrc OS/BSP/DRIVER

data

hdl verilog vhdl

devl

ELF

.H

.A

.O

MPD PAO

BBD

ipwiz.l og

12- 48

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

24

Glossary of Tools and Files

Some of the EDK tools:
LibGen = Library Generator. Uses MSS file, copies device drivers source files and generates software libraries for the defined system PlatGen = Platform Generator. Uses the MHS and MPD files to create an implementation netlist of a bus-based sub-system SimGen = Simulation Generator. Uses MHS file to configure and generate a simulation netlist pointing to various simulation model types, such as SWIFT, BFM, netlist, RTL, etc.

12- 49

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

Glossary of Tools and Files

A few of the files the EDK tools generate:

MDD = Microprocessor Driver Description MHS = Microprocessor Hardware Specification MPD = Microprocessor Peripheral Description MSS = Microprocessor Software Specification PAO = Peripheral Analyze Order BBD = Black Box Definition BMM = Block RAM Memory Map

12- 50

EDK Overview
2010 Xilinx, Inc. All Rights Reserved

For Academic Use Only

25