Table of Contents

Introduction....................................................................................................... 3 A. Oscillator Fundamentals ................................................................................. 3 II. VCO Topologies ............................................................................................... 4 A. Current Starved Ring Oscillator ....................................................................... 4 B. Ring Oscillator Phase Noise Analysis ................................................................ 5 C. Symmetric Load Differential Feedback Oscillator ................................................ 6 D. High Frequency Varactor LC Oscillator.............................................................. 7 III. ADS Design................................................................................................... 11 IV. Analysis and Simulations ................................................................................ 12 A. Current Starved Ring Oscillator ..................................................................... 12 B. Symmetric Load Differential Oscillator............................................................ 14 C. High Frequency Varactor LC Oscillator............................................................ 18 V. Conclusions .................................................................................................. 19 VI. Bibliography.................................................................................................. 20 Table of Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1: Oscillator Feedback System and Transfer Function .......................................... 3 2: Barkhausen Criteria .................................................................................... 3 3: Ideal VCO Frequency Transfer Characteristic .................................................. 4 4: Three Stage Current Starved VCO Schematic.................................................. 5 5: Basic CMOS Inverter Ring Oscillator .............................................................. 5 6: Differential Buffer Symmetric ....................................................................... 6 7: Differential VCO Feedback System ................................................................ 7 8: LC oscillator Schematic and Symbol Description .............................................. 7 9: LC Varactor VCO Schematic ......................................................................... 8 10: LC Tank model of VCO............................................................................... 8 11: LC oscillator noise model ........................................................................ 10 12: Current Starved Inverter Final Schematic ................................................... 11 13: Symmetric Load VCO Final Schematic ........................................................ 11 14: LC VCO Final Schematic........................................................................... 12 15: Unbuffered Current Starved VCO............................................................... 13 16: Buffered Current Starved VCO. ................................................................. 13 17: Differential VCO Transient Signal .............................................................. 14 18: Differential VCO Voltage vs. Frequency transfer curve .................................. 15 19: Differential VCO Harmonic Balance results .................................................. 16 20: Noise source description and legend .......................................................... 16 21: Differential VCO Noise Results .................................................................. 17 22: Differential VCO Power Flatness ................................................................ 18 23: Time domain response of LC oscillator ....................................................... 19

I.

I. Introduction
Oscillators are among the most important building blocks in modern electronic systems. Oscillators can be found anywhere from clock generators in computers, carrier synthesizers in cell phones to simple AM radios. Their need in very different arrays of applications has required oscillators to have very different topologies and performance parameters. This project studies some of the topologies and design requirements of tunable oscillators, or voltage controlled oscillators (VCO). For the case of the VCO, the circuit has the ability to control the output frequency as a function of a control input.

A. Oscillator Fundamentals
Oscillators are feedback systems that produce periodic outputs in this case in the form of a voltage. These circuits have the ability and characteristic of being able to sustain an output without and any applied input. Oscillation occurs after the feedback system contributes enough phase shift that the overall feedback becomes positive. This concept is illustrated in the figure bellow:

+
X

Forward Network: a(s)

Feedback Network: f(s)

H (s) =

a( s) 1 a( s) f ( s)

Figure 1: Oscillator Feedback System and Transfer Function

While deriving a set of conditions that guarantees oscillations is difficult to assemble. The Backhausen criterion establishes a set of conditions necessary, although not sufficient, for oscillation to occur. It states that the loop gain of an oscillating system must be greater than unity while the loop phase shift must be zero, namely, constructive interference of the system waves.

T (s ) = a (s ) f (s ) > 1 T ( j ) = 0

Figure 2: Barkhausen Criteria

VCOs are usually characterized by their frequency vs. control transfer characteristic and its gain [/v]. This relationship states how sensitive, the range, the bandwidth, and the control

details of the VCO.

Figure 3: Ideal VCO Frequency Transfer Characteristic

In addition to these parameters, VCO center frequency, power dissipation, supply and common mode rejections ratios, and noise performance are the figures of merit that accurately describe the performance of the VCO. This project will visit and design several VCO topologies and analyze their applications, design procedures, and figures or merit, as discussed above. These RF CMOS topologies encompass some of the most important VCO requirements and uses. For one of these VCOs, this report will outline detailed results and design techniques using ADS simulation software. These are the current starved ring oscillator, symmetric load differential feedback oscillator, and a high frequency varactor LC oscillator.

II. VCO Topologies

The following VCO topologies were implemented using the Jazz Semiconductor SiGe BiCMOS 0.35m ADS PDK. However, due to project requirements no bipolar devices were used, even though they are the highest performance devices in the design kit.

A. Current Starved Ring Oscillator

Ring oscillators are found both in analog RF and digital applications due to their versatility and easy implementation. They consist of a series of gain stages in a feedback loop. In the case of the current starved ring oscillator, the top and bottom current mirrors limit the amount of pull up and pull down current available to the core CMOS inverter. The total oscillation frequency will depend on the delay time and number of stages:

f osc =

1 2 n d
1 ID

In turn the adjustment of this current will affect the propagation delay generating a tunable frequency control process

d =

It due to the wide tuning range of the ID current it is expected that the frequency range will be broad and have a high slope. These strengths make it an ideal candidate for clock generation and clock recovery applications. As part of the design applications of this VCO, it

is required that the output swing vary from rail to rail. In addition, some of the non-linearity that affects this feedback loop might be solved with a low pass stage. Therefore, a buffer stage will be necessary at the output of the VCO so that the system can reach the appropriate logic levels and also generate a more clock like waveform. At 0.35m gate lengths, the delay offset introduced by this buffer is negligible.

Figure 4: Three Stage Current Starved VCO Schematic

B. Ring Oscillator Phase Noise Analysis

Phase noise is defined as the frequency domain uncertainty of an oscillator signal. The output of an oscillator can be written as Vout (t ) = A(t ) f [ 0 t + (t )] , where (t ) represents the phase-shift due to the internal and external noise sources. Consider the single-ended ring oscillator with a single current source on one of the nodes as shown in the figure bellow, suppose that the current source consists of an impulse of current with area g (in coulombs) occurring at time t = . This will cause an instantaneous change in the voltage of that node, given by V = q / C node , where Cnode is the effective capacitance on that node at the time of charge injection.

Figure 5: Basic CMOS Inverter Ring Oscillator

This produces a shift in the transition time. For small the change in the phase is proportional to the injected charge:

Where

q max = C nodeVswing and Vswing is the voltage swing across the capacitor. In most of the

cases the large phase shift occurs when the impulse is injected during an output transition. Since the small amount of change in the voltage due to the current impulse, the resultant phase shift is linearly proportional to the injected charge, therefore the transfer function from current to phase is linear. The time dependent impulse response is given:

By using the impulse response we can obtain the using the superposition integral:

(t )

in response to any injected current

Where i(t) represents the noise current injected into the node. The single sideband phase noise spectrum for a ring oscillator with N identical then is given by the equation:

C. Symmetric Load Differential Feedback Oscillator

Most ring oscillators present a tuning range that rarely surpasses 3:1. There exist many applications where broad tuning flexibility is required. The following ring VCO block has several key features that satisfy wide tuning range necessities. Based on a differential buffer ring oscillator topology, with the current sourced by a saturated NFET acting as controlling element. Different from standard differential buffers, the additional PFET connected in parallel with the inner diode connected load devices are able to pull the output note to VDD. This feature creates a fairly constant output swing even at large variations of the control current. These strengths make it an ideal candidate for PLL applications, which are available at a variety of frequency ranges. Figure 6: Differential Buffer Symmetric In addition, this differential arquitecture will also display better common mode rejection thn the current starved topology while still consuming the same amount of branch power.

Figure 7: Differential VCO Feedback System

D. High Frequency Varactor LC Oscillator

LC oscillators are very popular due to their high frequency operation. The key advantage of LC oscillator over the ring oscillator is its low power consumption and low phase noise. However, the large on-chip inductors usually need larger layout area and it usually has small frequency tuning range. The basic schematic and block diagram of the LC oscillator used in this project is shown in figures bellow:

Figure 8: LC oscillator Schematic and Symbol Description

Figure 9: LC Varactor VCO Schematic

Figure 10: LC Tank model of VCO

Tuning of LC Oscillator: The oscillation frequency of LC topologies is equal to

f osc = 1 / 2 LC , which the inductor and capacitor values are given by the tank inductance
and tank capacitance values of the equivalent small signal differential model in the figure above where,

Since the varactor capacitance C v =

C0 depends on the reverse bias voltage V R , (1 + VR B ) m

2

it is clear that the oscillating frequency is also voltage dependent. The tuning range is given by Ltan k C tan k ,max 1 / min , and Ltan k C tan k ,min 1 / max , which we can rewrite it as
2

2 2 min C tan k ,max max C tan k ,min .

Now we let

2 2 , the tuning range of the LC oscillator r = max / min

is given:

If loop gain condition of the complementary LC oscillator is given by ( g m,n + g m , p ) / 2 g g tan k , in this case, g m ,n = g m , p , then the loop gain condition becomes

g m ,n g g tan k . For the varactors tuning range, since the maximum tuning ratio is limited
by v = C v , max / C v ,min , we impose a maximum

with monomial constraint C v ,max C v , min v .

Phase Noise: In most of the cases, the LC oscillator is used in RF-IC design because of its good phase noise characteristics. In the 1 f
2

region of the phase noise spectrum, the

single sideband phase noise at the offset frequency is given by

Which for the differential noise sources, rms 1 / 2 , and the total charge swing of the tank
2
2 q max is given by C tan k Vamp .

Figure 11: LC oscillator noise model

2 n

/ f Stands for the total current noise for the LC oscillator, which is the sum of the
2 2 f ), the transistor gate noise ( i M , gT f ), the
2

transistor channel thermal noise ( i M , dT

2

inductor noise ( i RL f ) and the varactor noise ( iCV

f ). Please refer to the noise source

calculations bellow for a better understanding of the magnitudes and elements that generate noise:

,
Transistor channel thermal noise

,
Transistor gate noise

Inductor noise

Varactor noise

III. ADS Design

The following schematics outline the design and simulations of the three VCOs.
SiGe Models

H AR MON IC BALANC E
TR AN SIEN T

s bc 35x _model X Ver=default fet=N OM npn=NOM pnp=NOM c ap=NOM ind=NOM res =N OM

Tran Tran1 StopTime=20 ns ec Max TimeStep=0.07 ns ec

Harmonic Balanc e HB1 Freq[1]=1.0 GH z Order[1]=3 Status Lev el=2 Sw eepVar="Vtune" Start=0 Stop=3.3 Step=

Current Starved VCO

VD D

VD D

V_D C SR C1 Vdc =3.3 V

s bc 35x _pfet3 M5 w f=9 u lf=0.35 u nf=1 s lic es =1 c ount=1

No d e Se t

s bc 35x _pfet3 M4

s bc 35x _pfet3 M10 wf=9 u lf=0.35 u

s bc 35x _pfet3 M14 w f=9 u lf=0.35 u

s bc 35x _pfet3 M18 w f=9 u lf=0.35 u

s bc 35x _pfet3 M22 w f=9 u lf=0.35 u

N odeSet N odeSet2 V=3.3 V Vfb

s bc 35x _pfet3 M3

s bc 35x _pfet3 M9 wf=9 u lf=0.35 u

s bc 35x _pfet3 M13 w f=9 u lf=0.35 u

s bc 35x _pfet3 M17 w f=9 u lf=0.35 u

s bc 35x _pfet3 M21 w f=9 u lf=0.35 u Vfb

s bc 35x _pfet3 M24 w f=1.5 u lf=0.35 u

s bc 35x _pfet3 M26 w f=1.5 u lf=0.35 u

Vout
s bc 35x _nfet M2

Va r Eq n

VAR VAR 1 Vtune=1.5

s bc 35x _nfet M7 wf=3 u lf=0.35 u

s bc 35x _nfet M11 w f=3 u nf=1

s bc 35x _nfet M15 w f=3 u lf=0.35 u

s bc 35x _nfet M19 w f=3 u lf=0.35 u

s bc 35x _nfet M23 wf=0.5 u lf=0.35 u

s bc 35x _nfet M25 w f=0.5 u lf=0.35 u

V_D C Vin Vdc =Vtune V

s bc 35x _nfet M6 w f=3 u lf=0.35 u nf=1 s lic es =1 c ount=1

s bc 35x _nfet M1

s bc 35x _nfet M8 wf=3 u lf=0.35 u

s bc 35x _nfet M12 w f=3 u nf=1

s bc 35x _nfet M16 w f=3 u lf=0.35 u

s bc 35x _nfet M20 w f=3 u lf=0.35 u

Figure 12: Current Starved Inverter Final Schematic

Sy mmetric Load Positiv e Feedback VCO

VDD

s b c 3 5 x _ p fe t3 M1

s b c 3 5 x _ p fe t3 M2

s b c 3 5 x _ p fe t3 M4

s b c 3 5 x _ p fe t3 M3

s b c 3 5 x _ p fe t3 M9

s b c 3 5 x _ p fe t3 M8

s b c 3 5 x _ p fe t3 M 12

s b c 3 5 x _ p fe t3 M 13

s b c 3 5 x _ p fe t3 M 16

s b c 3 5 x _ p fe t3 M 15

s b c 3 5 x _ p fe t3 M 19

s b c 3 5 x _ p fe t3 M20

s b c 3 5 x _ p fe t3 M 23

s b c 3 5 x _ p fe t3 M 22

s b c 3 5 x _ p fe t3 M 26

s b c 3 5 x _ p fe t3 M 27

s b c 3 5 x _ p fe t3 M 30

s b c 3 5 x _ p fe t3 M 29

s b c 3 5 x _ p fe t3 M 33

s b c 3 5 x _ p fe t3 M 34

Vd 1

Vd 2

Os c Po rt2 Os c P1 V=

v out

Vd 1

Vd 2

Z=1 .1 Oh m Nu m Oc ta v e s =2 Ste p s =1 0
s b c 3 5 x _ n fe t M 10

s b c 3 5 x _ n fe t M5

s b c 3 5 x _ n fe t M6

s b c 3 5 x _ n fe t M 14

s b c 3 5 x _ n fe t M 17

s b c 3 5 x _ n fe t M 21

s b c 3 5 x _ n fe t M 24

s b c 3 5 x _ n fe t M 28

Fu n d In d e x =1 M a x L o o p Ga i n Ste p =

s b c 3 5 x _ n fe t M 31

s b c 3 5 x _ n fe t M 35

V_ DC Vi n Vd c =v tu n e V

s b c 3 5 x _ n fe t M7

s b c 3 5 x _ n fe t M 11

s b c 3 5 x _ n fe t M 18

s b c 3 5 x _ n fe t M 37

s b c 3 5 x _ n fe t M36

Figure 13: Symmetric Load VCO Final Schematic

LC Oscillator with Varactor Tunning

VDD
SiGe Models

TRANSIENT
T ran T ran1 StopT ime=25.0 nsec MaxT imeStep=0.03 nsec

sbc35x_model X Ver=default fet=NOM npn=NOM pnp=NOM cap=NOM ind=NOM res=NOM

sbc35x_pfet3 M4 wf=52.7 u lf=0.35 u nf=1 slices=1 count=1

sbc35x_pfet3 M3 wf=52.7 u lf=0.35 u nf=1 slices=1 count=1

Var E qn

VAR Vc ontrol X=1.0

L L1 L=Y nH R=

L L2 L=Y nH R=

VDD

Vcontrol

Vcontrol
sbc 35x_varactor_bl X1
sbc35x_varactor_bl X2

V2

Var E qn

VAR Ls Y=3.9
VAR varac Z=20
VAR VAR1 W=1

Var E qn

V_DC SRC1 Vdc=3.3 V

V_DC SRC2 Vdc=X V

Var E qn

sbc35x_nfet M2 wf=17 u lf=0.35 u nf=1 slices=1 count=1

s bc35x_nfet M1 wf=17 u lf=0.35 u nf=1 s lices=1 c ount=1

V_DC SRC3 Vdc=W V

sbc 35x_nfet M5 wf=10 u lf=0.35 u nf=1 slic es=1 count=1

Figure 14: LC VCO Final Schematic

IV. Analysis and Simulations

A. Current Starved Ring Oscillator
After several simulation trails it is easy to see that at least 5 to 9 stages are necessary to satisfy the Barkhausen criteria. This number of stages happens to be consistent with the specified frequency range. Too many stages lower the high frequency end points of the system, while too few create non-linear transfer curves and sometimes drive the system out of oscillation. The following two figures illustrate the time domain response of this oscillator without and with an output buffer. It can be easily seen buffers are highly required and prove their worth in power dissipation, delay, and chip area increases. Figure 16 illustrates a buffered output with highly rectangular characteristics and a full rail to rail voltage performance.

dep Delta=0.135 delta mode ON

4 3

time=6.652nsec Vout=3.242 V

m2 m1

Vout, V

2 1 0 -1

10

12

14

16

18

20

time, nsec
Figure 15: Unbuffered Current Starved VCO

time=4.676nsec Vout=3.343 V
4 3

dep Delta=0.006 delta mode ON

m1 m2

Vout, V

2 1 0 -1

10

12

14

16

18

20

time, nsec
Figure 16: Buffered Current Starved VCO.

B. Symmetric Load Differential Oscillator

This VCO will be analyzed with great detail through the ADS process flow. The following subsections will deal with maybe of the aspects required for a full parameters extraction of the VCO figures of merit. Transient analysis: After finishing the schematic capture of the devices and adding five stages to the circuit to obtain oscillation, a simple transient analysis was performed. The following time domain figure illustrates the transient curve of the oscillator differential output. The output was taken by subtracting each of the differential signals. Notice that it is centered around 0V and has peak to peak amplitude of almost 4V. In a practical application a differential to single ended converter would be required. Figure 17 was obtained by biasing the control voltage close to power supply levels.

Figure 17: Differential VCO Transient Signal

Frequency Response Analysis: Following the transient analysis, we made use of the ADS harmonic balance simulator. This frequency domain tool allow designers to use power design aids to better understand frequency, noise, and the small signal parameters of a circuit. In this case a voltage sweep was performed by varying the VCO control voltage across its valid range of oscillation. The following figure outlines the linear portion of the VCO transfer characteristic, including VCO gain. It is clear that the VCO is very linear and displays excellent performance up to 1GHz. After which the gain profile drops; even though the VCO can still be used in these regions it is not suitable for linear applications such as PLLs. It has a VCO gain of about half a GHz per volt, with a linearity that is better than 95%, which would make the design of a PLL of a phase frequency detector very simple.

Figure 18: Differential VCO Voltage vs. Frequency transfer curve

Harmonic Balance Analysis: The last two analyses outline the main, first order performance parameters of the VCO. Nevertheless, these figures of merit do not contain any information regarding the VCOs signal purity, noise or power efficiency. From the harmonic balance noise analysis we are able to plot several key second order effects such as harmonic power distribution as illustrated in the following figure.

Figure 19: Differential VCO Harmonic Balance results

Figure 19 displays the harmonic content of the VCO. The large 19.94dBm harmonic at 0 GHz is due to the DC offset experienced by this differential configuration. A differential to single ended converter is necessary to alleviate this problem. The main harmonic is at 7.874dBm, while the next higher power harmonic is a 7.556dBm, which shows substantial signal purity, with an attenuation of over 15dBm. Phase Noise Analysis: The noise performance of the oscillator will be determined by its Noise frequency and phase noise parameters. These parameters are described in Figure 20, where pm = phase margin; an = amplitude noise.

Figure 20: Noise source description and legend

As expected from this all MOSFET ring oscillator, the noise frequency, performing like quadratic function of frequency. Nonetheless, this factor only becomes alarming when it is coupled by a high phase noise factor. From the following figure it is clearly seen that the pnmx and pnfm of the amplifier are lower than 70dBc. As expected it will increase aggressively as it closes in to the oscillation frequency. These phase noise results are very good for ring oscillators which classically display bad noise performance.

Figure 21: Differential VCO Noise Results

Ideally, the VCO would consume power equal to the bias current times supply voltage times the number of stages used in the design. However, in this situation the harmonic balance simulation is able to discern the power consumed as a function of frequency. It is seen that the oscillator will consume anywhere from 12 top 15mw.

Figure 22: Differential VCO Power Flatness

C. High Frequency Varactor LC Oscillator

The following figure outlines the oscillating pattern of the LC VCO. It a very high frequency sinusoid which we tuned to be in the Bluetooth range of 5GHz. Even though it possesses high frequency and high spectral purity, it has a very limited range of oscillation, mainly due to the tuning limitations imposed by the varactors.

dep Delta=-0.001 delta mode ON m1 3.5 m2

3.0 2.5

time=7.827nsec plot_vs(V2, time)=3.184

V2

2.0 1.5 1.0 0.5

10

15

20

25

time, nsec

Figure 23: Time domain response of LC oscillator

V. Conclusions
The objective of this project was to become familiar with the tools available in the ADS circuit design environment. To meet this objects we explored three different VCO oscillator alternatives, performing detailed ADS analysis on one of these: the symmetric load differential VCO. From our experimentation with ADS, it is clear that it offers several powerful aids, especially in the frequency domain, that other time domain tools such as PSPICE do not have. The harmonic balance toolbox provides a pre-programmed interface that shortens design time dramatically and provides many templates that allow designers to concentrate on designing and not on playing with the tool. Through this VCO design we have acquired ADS experience as well as learned, in detail, the operation, design, figures of merit that make up voltage controlled oscillators.

VI. Bibliography
Betancourt, Rafael; Lee, Thomas. Ring Oscillator VCOs for Frequency Synthesis. Stanford Microwave Integrated Circuits Laboratory, July 1998. Razavi, Behzad. Design of Analog CMOS Integreted Circuits, Teta McGraw Hill, New Delhi, 2001. Hajimiri, Ali; Betancourt, Rafael; Lee, Thomas. A 1.5mW, 200MHz CMOS VCO for Wireless Bioletemetry, Stanford Microwave Integrated Circuits Laboratory, July 1998, Hajimiri, Ali; Lee, Thomas. A General Theory for Phase Noise in Electrical Oscillators. IEEE Journal of Solid State Circuits vol 33, n2, pp 179-194. Hajimiri, Ali; Lee, Thomas; Sohernson, Maria. Design and Optimization of LC Oscillators. IEEE Journal of Solid State Circuits, http://www.stanford.edu/~boyd/reports/opt_LC_oscil.pdf. Lee, Thomas. The Design of CMOS Radio-Frequency Integrated Circuits. Cambridge University Press, 1998.