IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO.

3, MARCH 2009

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Voltage Balancing Control for a Three-Level Diode-Clamped Converter in a Medium-Voltage Transformerless Hybrid Active Filter
Hirofumi Akagi, Fellow, IEEE, and Takaaki Hatada
AbstractThis paper discusses a transformerless hybrid active lter integrated into the 6.6-kV, 1-MW adjustable-speed motor drive having a three-phase diode rectier at the front end. The hybrid lter consists of an active lter using a three-level diodeclamped pulsewidth modulator converter rated at 60 kVA, and a 250-kVA passive lter tuned to the seventh harmonic frequency. They are directly connected in series without a transformer. This circuit conguration enables one to use 1.2-kV insulated gate bipolar transistors because the dc voltage of the three-level converter is 1.32 kV (20% of 6.6 kV). Voltage balancing control characterized by superimposing a sixth harmonic zero-sequence voltage on the active lter voltage reference in each phase is introduced to the three-level converter with triangle carrier modulation. Experimental waveforms obtained from a 400-V, 15-kW downscaled system verify the viability and effectiveness of the proposed hybrid lter, keeping the two dc capacitor voltages well-balanced. Index TermsActive lters, diode rectiers, harmonics, hybrid lters, passive lters, three-level converters.

I. INTRODUCTION A. Background ITH the emergence of high-voltage insulated gate bipolar transistors (IGBTs) rated at 3.3, 4.5, and 6.5 kV, attention has been paid to medium-voltage adjustable-speed motor drives without transformers. Generally, their nominal motor voltages are in a range of 2.3, 3.3, 4.16, and 6.6 kV [1]. Mediumvoltage adjustable-speed motor drives for energy savings require neither fast speed response nor regenerative braking, particularly in applications to fans, blowers, and pumps. As a result, a three-phase diode rectier can be used as the front-end converter of such a motor drive, instead of a three-phase pulsewidth modulator (PWM) rectier. The diode rectier is much more efcient and reliable as well as less expensive than the PWM rectier. However, the diode rectier produces a large amount of harmonic current, and therefore, it does not comply with the harmonic guidelines. Hybrid active lters consist of single or multiple voltage source PWM converters and passive components such as ca-

pacitors, inductors, and/or resistors. They are more attractive in harmonic ltering than pure active lters from both viability and economical points of view, particularly for medium-voltage applications [2][12]. The authors have proposed a transformerless hybrid active lter for harmonic compensation of a three-phase diode rectier with a capacitive load [13][16]. This hybrid lter is formed by a three-phase passive lter tuned to the seventh harmonic frequency and a small-rated active lter using a three-phase two-level PWM converter. They are directly connected in series without a transformer. This paper follows the previously published papers [13][16], with focus on a hybrid active lter using a three-level diode-clamped or neutral-point-clamped PWM converter. This hybrid lter is well-suited to a 6.6-kV motor drive having a three-phase diode rectier at the front end, because the hybrid lter can use 1.2-kV IGBTs that are currently available from the market at a reasonable cost. A concern resulting from using the three-level converter in the hybrid lter is voltage imbalance of the two split dc capacitors. B. Three-Level Diode-Clamped Converter Since the three-level diode-clamped or neutral-point-clamped PWM inverter was invented in 1979 [17], comprehensive research has been achieved on voltage balancing control of the two split dc capacitors [18][27]. However, the research has been conned to the three-level converters and inverters with sinusoidal current inputs or outputs because they have been applied to static synchronous compensators (STATCOMs) and motor drives. A three-phase pure active lter has the same power circuit as a three-phase PWM rectier. However, the active lter is controlled to draw a three-phase nonsinusoidal current from the point of installation, unlike the PWM rectier drawing a three-phase sinusoidal current. This makes more complicated and/or difcult voltage balancing control for the three-level converter used as the active lter than that for the three-level converter used as the PWM rectier. As a result, no literature has addressed voltage balancing control for the three-level converter in pure and hybrid active lters, including experimental verication of its validity and effectiveness, although a few papers have dealt with a pure active lter using the three-level converter [28], [29]. C. Triangle Carrier and Space Vector Modulations The three-level PWM converter can be classied into triangle carrier modulation and space vector modulation by pulsewidth

Manuscript received July 22, 2007; revised November 21, 2007. Current version published April 8, 2009. Recommended for publication by Associate Editor D. Xu. H. Akagi is with the Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Tokyo 152-8552, Japan (e-mail: akagi@ee.titech.ac.jp). T. Hatada was with the Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Tokyo 152-8552, Japan. He is now with Toyo Electric Manufacturing Company, Ltd., Tokyo 104-0031 Japan (e-mail: hatada@akg.ee.titech.ac.jp). Digital Object Identier 10.1109/TPEL.2009.2012528

0885-8993/$25.00 2009 IEEE

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Fig. 1.

6.6-kV, 1-MW transformerless adjustable-speed drive equipped with the hybrid lter.

modulation. The authors of this paper prefer triangle carrier modulation to space vector modulation in terms of simple and easy implementation of voltage balancing control when the three-level converter is used as an active lter. The main reason is that the three-level converter in the active lter requires a higher switching frequency than that in a motor drive, which lies usually around 10 kHz to provide satisfactory ltering performance. This paper lays emphasis on voltage balancing control for the three-level converter with triangle carrier modulation. A downscaled laboratory system rated at 400 V and 15 kW is designed, constructed, and tested to verify the viability and effectiveness of the hybrid lter. Experimental waveforms obtained from the laboratory system show that the hybrid lter provides satisfactory ltering performance in steady and transient states, maintaining the two dc capacitor voltages well-balanced, even in transient states.

active lter represents a single 1.2-kV IGBT. This makes the active lter inexpensive because the 1.2-kV IGBT is available on the market at reasonable cost. Although the active lter has a carrier frequency of 10 kHz, the actual switching frequency of each IGBT is 5 kHz, i.e., half of the carrier frequency. This leads to less switching loss. Generally, the ac inductor Lac of the 6.6-kV diode rectier ranges from 5% to 10%. Fig. 1 assigned it to 5%, thus resulting in cost and size reductions. Note that LS (=1.8%) is not an intentionally connected inductor for the hybrid lter, but an equivalent background system inductor seen upstream of the point of installation of the hybrid lter. B. 400-V System Conguration Fig. 2 shows the circuit conguration of a 400-V, 15-kW downscaled system that was designed, constructed, and tested to conrm the validity of Fig. 1. Table I summarizes the circuit and control parameters of the downscaled system. The active lter in Fig. 2 has a carrier frequency of 10 kHz, which is the same as that in Fig. 1. The passive lter is tuned, not to the most dominant fth harmonic frequency, but to the second most dominant seventh harmonic frequency, thus bringing cost and size reductions to the passive lter. As a result, the passive lter sinks the seventh harmonic current from the diode rectier, while the active lter compensates for the other harmonic currents produced by the diode rectier [13]. The hybrid lter is directly connected to the 400-V system. The active lter consists of a three-phase three-level diodeclamped PWM converter using 12 100-V MOSFETs, and two split dc capacitors CD P and CD N . The active lter controller described in the next section regulates the total dc voltage vD (= vD P + vD N ) at 80 V (=400 V 0.2) and keeps the two dc capacitor voltages vD P and vD N well-balanced. Neither the

II. SYSTEM CONFIGURATIONS AND CONTROL A. 6.6-kV System Conguration Fig. 1 shows the circuit conguration of a 6.6-kV, 1-MW transformerless adjustable-speed motor drive integrated with a hybrid active lter. The hybrid lter consists of the 250-kVA passive lter tuned to the seventh harmonic frequency and the 60-kVA active lter using a three-phase three-level diodeclamped PWM converter. Note that each IGBT symbol in the 6.6-kV, 1-MW three-level inverter represents either a string of two 4.5-kV IGBTs connected in series or a string of three 3.3-kV IGBTs connected in series. The dc voltage of the 60-kVA active lter is designed as 1.32 kV (=6.6 kV 0.2) so that a dc voltage of 660 V is applied across each split dc capacitor. Therefore, each IGBT symbol in the three-level converter of the 60-kVA

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Fig. 2.

400-V, 15-kW downscaled system. Fig. 3. Control block diagram of the active lter, where 6 is a constant value of 1.4 rad in the voltage balancing control. TABLE I SPECIFICATIONS AND PARAMETERS OF THE 400-V, 15-kW DOWNSCALED SYSTEM

Fig. 4. Common triangle carrier signals and the active lter voltage reference vA F in one phase.

C. Control of the Active Filter Fig. 3 shows the control block diagram of the active lter [31]. It can be divided into feedback control, feedforward control, dc voltage control, and voltage balancing control. The whole signal processing is achieved by a fully digital controller based on a DSP and eld-programmable gate arrays (FPGAs). The control system of the hybrid active lter has already been described in [13][16] using a traditional two-level PWM converter with triangle carrier modulation. A main difference in the control system between the three-level converter and the two-level converter is that the three-level converter requires the voltage balancing control of the two split dc capacitors whereas the two-level converter does not. Fig. 4 shows two triangle carrier signals with the same fre in quency as 10 kHz and the active lter voltage reference vAF one phase. The sampling time for digital signal processing is 50 s. Note that the actual switching frequency of the threelevel converter becomes 5 kHz, i.e., a half of the carrier frequency, whereas the actual switching frequency of the twolevel converter is the same as the carrier frequency, i.e., 10 kHz.

auxiliary circuit nor the component exists on the dc side except for two voltage sensors. The ac inductor Lac (=5%) should be designed to be larger than the background system inductance LS (=1.8%). Note that LS includes the leakage inductance of the 15-kW transformer with a primary voltage of 200 V and a secondary voltage of 400 V in Fig. 2. The dc inductor Ldc (=1%) is connected to the dc side of the diode rectier. A starting procedure of the hybrid lter is described in [16] by replacing the three-level converter with a traditional two-level converter, along with experimental waveforms during starting. This starting procedure using two three-phase magnetic contactors MC1 and MC2, and a current-limiting resistor in each phase is also applicable to Figs. 1 and 2.

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Fig. 5. Active lter voltage reference v A F on the horizontal axis and the duty factor D on the vertical axis.

III. VOLTAGE BALANCING CONTROL OF THE TWO SPLIT DC CAPACITORS This section discusses voltage balancing control for the active lter playing an important role in the hybrid lter, thus providing a graphic description of the operating principle. A. Duty Factor A duty factor in one phase is dened by the ratio of a time interval, during which the lter current iF ows into, or out of, the midpoint M through a clamping diode, with respect to one-line cycle (20 ms at 50 Hz). The product of the duty factor D and the lter current iF yields the midpoint current iM , i.e., iM = DiF in one phase. Fig. 5 shows a relation between the voltage reference vAF and the duty factor D, where the duty factor is a function of vAF as follows [18]: VD vAF <0 1 + 2vAF /VD , 2 D= (1) VD 1 2vAF /VD , 0 vAF . 2 B. Midpoint Current When No Voltage Balancing Control is Applied The following assumptions in one phase are made for the sake of simplicity. 1) The line-to-neutral voltage vS O is purely sinusoidal: vS O = VS O sin(1 t). 2) The lter current iF consists of only the fundamental component: iF 1 = IF 1 cos(1 t). 3) The active lter voltage vAF consists of only the fth harmonic component: vAF5 = VAF5 cos(51 t 5 ). Fig. 6 shows some waveforms to draw the waveform of iM when no voltage balancing control is applied in an ideal condition, where 5 is the initial phase difference at t = 0 between the fundamental component of the lter current iF 1 and the fth harmonic component of the active lter voltage vAF5 . Careful observation and analysis of the waveforms of iF and vAF M in Fig. 9 give the initial phase 5 as 1.4 rad (= 80 ). Note that the waveforms in Fig. 6 are not drawn by using circuit simulators such as a software of power systems computer-aided design (PSCAD)/electromagnetic transient in dc systems (EMTDC) but calculated by using the software of Excel.
Fig. 6. Waveforms of v A F 5 , D , and iM (= DiF 1 ) when no voltage balancing control is applied in an ideal condition.

The dc mean current of iM over a period of 20 ms, which is equal to the average value of iM over a one-line cycle, becomes zero so that no voltage imbalance occurs in ideal systems. However, component tolerances including unequal conducting and switching losses produced by power switching devices, along with signal imbalance and resolution issues inherent in the digital control circuit including voltage/current sensors, may bring a voltage imbalance to the two dc capacitors in actual systems. In fact, it was observed in Fig. 2 that a voltage imbalance of 4 V (10% of 40 V) occurred when no voltage balancing control was applied. In other words, the positive dc voltage vD P was higher by 4 V than the negative dc voltage vD N . C. Operating Principle of Voltage Balancing Control The basic idea of the voltage balancing control proposed in this paper is to superimpose a sixth harmonic zero-sequence voltage with an appropriate amplitude and initial phase on the active lter voltage reference in each phase. The frequency of the superimposed zero-sequence voltage should be an evenorder harmonic frequency to make the voltage balancing control effective. Moreover, a triple-line frequency is desirable because its component disappears from three-phase line-to-line voltages. Thus, the sixth harmonic frequency is the lowest one that meets the two requirements. Fig. 7 depicts waveforms in one phase when the voltage balancing control is applied. These waveforms are drawn by using the software of Excel, like those in Fig. 6. Fig. 7 makes the following assumptions. 1) The line-to-neutral voltage vS O is purely sinusoidal: vS O = VS O sin(1 t). 2) The lter current consists of the fundamental and fth harmonic components: iF = IF 1 cos(1 t) + IF 5 cos(5 t 5 ). 3) The fth harmonic active lter voltage is given by vAF5 = VAF5 cos(51 t 5 ), where 5 = 1.40 rad.

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TABLE II MEASURED HARMONIC COMPONENTS OF v A F AND iF , AND THE CALCULATED DC MEAN CURRENT OF DiF n (n = 1 , 5, 7, 11, AND 13)

Numerical analysis concludes that the dc component of iM gets maximal when 5 = 6 . The reason can be explained in the following. The fth and sixth harmonic voltages have the same phase at t = 0, and they have the opposite phase at t = 10 ms, when 5 = 6 . The reason is that the waveform of the fth harmonic voltage has two and a half cycle periods for 10 ms, whereas that of the sixth harmonic voltage has three cycle periods for 10 ms. As a result, the sum of the fth and sixth harmonic voltages (vAF5 + vAF6 ) becomes small so that the duty factor D gets large around t = 10 ms. The lter current iF 1 in Fig. 7 reaches the negative maximum of IF at t = 10 ms. As a result, the dc mean current of DiF 1 over a period of 20 ms, which is equal to the average value of DiF 1 over one-line cycle, becomes negative. The amplitude of the fth harmonic lter current IF 5 is larger by 25% than that of the fundamental lter current IF 1 , as shown in Table II. However, the dc mean current of DiF 5 is much smaller than that of DiF 1 , because some differences exist between the waveforms of DiF 1 and DiF 5 in Fig. 7. The average value of D over a period of iF 1 > 0 is different from that of iF 1 < 0. This means that a dc mean current of DiF 1 over a period of 20 ms is not equal to zero. On the other hand, when attention is paid to the waveforms of iF 5 and D, iF 5 has a period of 4 ms, whereas D has an average period of 2 ms. Roughly speaking, the average value of D over the period of 2 ms is independent of whether iF 5 is positive or negative. Thus, such a small dc component appears in DiF 5 .
Fig. 7. Waveform of v A F 5 + v A F 6 and the midpoint current iM (= DiF 1 + DiF 5 ), when the sixth harmonic zero-sequence voltage is superimposed on each voltage reference.

4) The sixth harmonic superimposed voltage1 is given as: vAF6 = VAF6 cos(61 t 6 ). The amplitude IF 5 and the initial phase 5 of iF 5 are obtained from the experimental waveform of iF in Fig. 9. The waveforms of DiF 1 and DiF 5 are described under an assumption of vAF = vAF5 + vAF6 . As a result, the dc component of DiF 1 over a period of 20 ms in Fig. 7 becomes negative. Therefore, the positive dc capacitor CD P is charged, whereas the negative dc capacitor CD N is discharged. In other words, the midpoint voltage falls down. Hence, Fig. 7 means that the voltage balancing control is effective.

D. Effects of Harmonic Components Contained in vAF and iF on Voltage-Balancing-Control Performance Table II summarizes the fundamental, 5th, 7th, 11th, and 13th harmonic components of vAF and iF , along with the dc mean currents of DiF n . Note that VAF5 , IF 1 , and the dc mean current of DiF 1 , respectively, are set to 100%. Individual harmonic components of vAF and iF are calculated from the experimental waveforms of Fig. 9. The dc mean currents of DiF n (n = 1, 5, 7, 11, and 13) are obtained by numerical analysis, where the value of VAF6 /VAF5 is assumed as 0.02. Table II concludes that the fundamental lter current iF 1 produces the most dominant effect (100%) on the performance of the voltage balancing control. The fth harmonic lter current iF 5 produces an effect as low as 20%. The seventh harmonic lter current iF 7 , 11th harmonic lter current iF 11 , and 13th harmonic lter current iF 13 are negligible, as shown in Table II.

1 The value of V A F 6 /V A F 5 is assumed as 0.6 in Fig. 7 to explain the operating principle of the voltage balancing control. However, it is as small as 0.02 in the experimental result of Fig. 9.

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Fig. 8. Experimental waveforms with a dc load rated at 15 kW when the stand-alone passive lter is connected.

IV. EXPERIMENTAL RESULTS A. Performance of the Stand-Alone Passive Filter Fig. 8 shows experimental waveforms with a dc load rated at 15 kW when the stand-alone passive lter was connected. The total harmonic distortion (THD) of iL was 28%, whereas that of iS became 32%. The reason why the THD of iS is higher than that of iL is that a weak resonance at 325 Hz (=1/2 (LF + LS )CF ) occurred between the background system inductance and the passive lter tuned to the seventh harmonic frequency.

Fig. 9. Experimental waveforms with a dc load rated at 15 kW, where K = = 80 V. 2 .0 per unit (p.u.) and V D

B. Performance of the Hybrid Filter Fig. 9 shows experimental waveforms when the diode rectier has a dc load rated at 15 kW. The proportional gain and integral time constant of the voltage balancing control in Fig. 3 were assigned as 1 V/V and 20 ms, and the initial phase of the sixth harmonic zero-sequence voltage superimposed on the active lter voltage reference was set as a constant value of 6 = 1.4 rad (= 80 ) throughout all the experiments in this paper. Note that the initial phase of 5 = 1.40 rad was obtained from the waveforms of iF and vAF M in Fig. 9 under a rated load condition of 15 kW. The waveform of vAF M was observed as the ac voltage of the three-level converter with respect to the midpoint M , while the waveform of v AF M was observed through a rst-order low-pass lter with a cutoff frequency of 4 kHz, to make the waveform of vAF M clear. The switching ripples contained in the line-to-neutral voltage and the supply current are hardly visible from the waveforms of vS O and iS in Fig. 9, because a voltage step change in the threelevel converter is as low as 40 V (= 10% of 400 V). When a traditional two-level converter with the same carrier frequency as 10 kHz was introduced to the active lter, the switching ripples would get double theoretically because a voltage step change in the two-level converter is as high as 80 V (= 20% of 400 V) [16].

Fig. 10.

Time-expanded waveforms of v A F M and v A F M in Fig. 9.

Fig. 10 shows time-expanded waveforms2 of vAF M and v AF M in Fig. 9. The waveform of vAF M veried that the three-level converter worked properly as expected, because PWM switching was achieved either between 40 and 0 V or between 0 and 40 V, and no switching occurred between 40 and 40 V. This PWM switching voltage as low as 40 V results in a good side effect that almost no switching ripple voltage appears in vS O without switching-ripple lter. Table III summarizes the THD and each harmonic current of iS . The THD was calculated up to the 37th harmonic current.3
2 A digital recorder, WE7000, manufactured by Yokogawa, was used for observing the waveform of the active lter voltage v A F M . The sampling frequency was 1 million samples per second. 3 The Japanese harmonic guideline prescribes that the THD of supply current must take into account up to the 40th harmonic current. Even 38th and 40th harmonic, and triple 39th harmonic currents were low enough to be eliminated from Table III.

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TABLE III CURRENT THD AND HARMONICS OF THE EXPERIMENTAL RESULTS, EXPRESSED AS THE HARMONIC-TO-FUNDAMENTAL CURRENT RATIO [%]

Fig. 11. Experimental waveforms when a step change occurred in a dc load = 80 V. from 15 to 10 kW, where K = 2 .0 p.u. and V D

The passive lter absorbed the seventh harmonic current, and the active lter compensated for the 5th, 11th, and other higher harmonic currents. When the 15-kW load was applied, each harmonic current contained in iS was reduced below 2%. The THD of iS was as low as 4.5%, whereas that of iL was as high as 32%. Fig. 9 also shows that the dc voltage of vD was regulated at 80 V and the two dc capacitor voltages vD P and vD N were well-balanced. Fig. 11 shows experimental waveforms in a step load change from 15 to 10 kW. After the load change occurred, the supply current iS was slightly distorted for about half a cycle (about 10 ms). The dc capacitor voltage reached 82 V during the step load change and this overvoltage was only 2.8% of 80 V. These waveforms veried that the hybrid lter provided much better transient performance than stand-alone passive lters suffering from undesirable harmonic resonances.

Fig. 12. Experimental waveforms with a dc load rated at 15 kW before and after the voltage balancing control was enabled, where a 250- resistor was intentionally connected across C D N .

C. Effectiveness of the Voltage Balancing Control Fig. 12 shows experimental waveforms to verify the effectiveness of the voltage balancing control. A 250- resistor was intentionally connected across the negative dc capacitor CD N . This brought a forced voltage imbalance to the two split dc capacitors. Before the voltage balancing control was applied, the positive dc voltage vD P (=46 V) got higher by 12 V than the negative dc voltage vD N (=34 V). However, the total dc voltage vD (= vD P + vD N ) was kept constant at 80 V because the dc voltage control was enabled through this experiment. Note that the negative dc capacitor was producing a power loss of 4.6 W (=342 /250), i.e. only 0.5% of 900 VA. As soon as the voltage balancing control was enabled, the two dc capacitor voltages started converging, and nally reached the

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same value as 40 V in 80 ms. An amplitude ratio of the sixth harmonic voltage with respect to the fth harmonic voltage contained in vAF M was 8% when the two dc capacitor voltages were balanced. On the other hand, the ratio was as small as 2% when the 250- resistor was eliminated from Fig. 12. This means that the adoption of the voltage balancing control has no bad effect on the ltering performance of the hybrid lter because the sixth harmonic zero-sequence voltage superimposed by the voltage balancing control is much smaller than the most dominant fth harmonic voltage produced by the active lter. The initial phase of 6 was assigned as a constant value of 6 = 5 = 1.4 rad through the experiments, where the initial phase of 5 was obtained by experiment at a rated load condition of 15 kW. It would be challenging to obtain the initial phase from theoretical analysis although it would be easy by simulation. Note that the hybrid lter is installed for harmonic compensation of the three-phase diode rectier or the so-called passive frond end in the adjustable-speed motor drive, as shown in Fig. 1. Strictly speaking, the initial phase 5 is not a constant value but a weak function of a dc load (current) of the diode rectier. However, it is veried by experiment and simulation that assigning 6 as the constant value would produce little effect on voltage balancing performance in a full dc load range from 0 to 15 kW. This means that assignment of 6 does not require any ne-tuning, which is of great advantage in the implementation of the voltage balancing control proposed in this paper. If the hybrid lter is intended for harmonic compensation of a three-phase thyristor rectier with an inductive dc load, the initial phase 6 should be adjusted in such a way as to constitute an additional feedback or feedforward control loop because the ring angle of the thyristor rectier is controllable. V. CONCLUSION This paper has addressed voltage balancing control for a three-level diode-clamped converter with triangle carrier modulation in a transformerless hybrid active lter. This hybrid lter is intended for integration into the 6.6-kV motor drive having a three-phase diode rectier at the front end. The 400-V, 15-kW downscaled system has been designed, constructed, and tested, with focus on voltage balancing of the two split dc capacitors. A sixth harmonic zero-sequence voltage with an appropriate and constant initial phase is superimposed on the active lter voltage reference in each phase. Experimental results in steady and transient states have veried the effectiveness and viability of voltage balancing control. However, theoretical analysis aimed at designing the voltage balancing control and providing a more theoretical insight into the effectiveness of the voltage balancing control is left as a future study to encourage wide acceptance of the hybrid active lter. REFERENCES
[1] B. Wu, High-Power Converters and AC Drives. Piscataway, NJ: IEEE Press, 2006. [2] H. Akagi, E. H. Watanabe, and M Aredes, Instantaneous Power Theory and Applications to Power Conditioning. Piscataway, NJ: IEEE Press, 2007.

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Takaaki Hatada was born in Tokyo, Japan, on April 20, 1982. He received the B.S. degree in electrical engineering from Tokyo Metropolitan University, Hachioji, Japan, in 2005, and the M.S. degree in electrical engineering from Tokyo Institute of Technology, Tokyo, Japan, in 2007. He is currently with Toyo Electric Manufacturing Company, Ltd., Tokyo.

Hirofumi Akagi (M87SM94F96) was born in Okayama, Japan, on August 19, 1951. He received the B.S. degree from Nagoya Institute of Technology, Nagoya, Japan, in 1974, and the M.S. and Ph.D. degrees from Tokyo Institute of Technology, Tokyo, Japan, in 1976 and 1979, respectively, all in electrical engineering. In 1979, he was an Assistant and then Associate Professor in the Department of Electrical Engineering, Nagaoka University of Technology, Nagaoka, Japan. In 1987, he was a Visiting Scientist at Massachusetts Institute of Technology (MIT), Cambridge, for ten months. From 1991 to 1999, he was a Professor in the Department of Electrical Engineering, Okayama University, Okayama, Japan. From March 1996 to August 1996, he was a Visiting Professor at the University of Wisconsin, Madison, and then MIT. Since January 2000, he has been a Professor in the Department of Electrical and Electronic Engineering, Tokyo Institute of Technology, Tokyo, Japan. His current research interests include power conversion systems, ac motor drives, active and passive EMI lters, high-frequency resonant inverters for induction heating and corona discharge treatment processes, and utility applications of power electronics such as active lters, self-commutated back-to-back (BTB) systems, and exible ac transmission system (FACTS) devices. He has made presentations many times as a keynote or invited speaker internationally. He has authored or coauthored more than 80 IEEE journal/transactions papers, including two invited papers published in Proceedings of the IEEE in 2001 and 2005, respectively. According to Google Scholar, the total citation index for all his papers is more than 7000. Prof. Akagi served as the President of the IEEE Power Electronics Society for 20072008. He was elected as a Distinguished Lecturer of the IEEE Power Electronics and Industry Applications Societies from 1998 to 1999. He received two IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS Prize Paper Awards in 1991 and 2004, two IEEE TRANSACTIONS ON POWER ELECTRONICS Prize Paper Awards in 1999 and in 2003, nine IEEE Industry Applications Society Committee Prize Paper Awards, the 2001 IEEE William E. Newell Power Electronics Award, the 2004 IEEE Industry Applications Society Outstanding Achievement Award, and the 2008 IEEE Richard H. Kaufmann Technical Field Award.