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PEMP VSD531
Session objective
After completing this session students will be able to: Clock Tree General Concepts Impact of clock skew Clock Skew Types CTS in design flow and basic steps CTS in real P&G flow Set up the design for clock tree synthesis Perform clock tree synthesis Perform post CTS optimizations Analyze timing and clock specifications post CTS
PEMP VSD531
Session Topics
Clock Tree Synthesis (CTS) goals Clock tree attribute Clock Distribution schemes Clock Skew Clock Tree Optimization Techniques Effect of clock tree synthesis
Identify settings of key timing parameters for pre-CTS and post-CTS stages
PEMP VSD531
Placement - completed Power and ground nets prerouted Estimated congestion acceptable Estimated timing acceptable (~0ns slack) Estimated max cap/transition no violations High fanout nets: Reset, Scan Enable synthesized with buffers Clocks are still not buffered
PEMP VSD531
Before CTS
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Clock
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All Allclock clockpins pinsare aredriven drivenby bya asingle singleclock clocksource. source.
M.S.Ramaiah School Of Advanced Studies
PEMP VSD531
CTS Goals