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School of Engineering and Technology (E&T)

Microelectronics & VLSI

TEXTIO
Finite State Machines

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Last Time

Sequential design using VHDL

o Flip Flops
o Counters o Memories RAMs ROMs

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This Time

TEXTIO package
o TEXTIO and testbenches

o TEXTIO procedures and functions

o STD_LOGIC_TEXTIO package

Finite State Machine (FSM)

o Moore and Mealy machines o An implementation example

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TEXTIO and Testbenches

A VHDL testbench can read test cases from a file and write outputs to a file

Files can be opened, closed, appended or read during simulation

VHDL supports the reading and writing of text files during simulation using a predefined package STD.TEXTIO

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TEXTIO

Text files are portable

o They can be reused with simulation tools from any vendor

Procedures and functions for reading and writing text files are included in the package TEXTIO TEXTIO considers files to be files of lines, where a line is text string terminated by a carriage return The package defines a number of types that can be used with text files
o FILE is defined to hold a text file
o LINE is defined to hold a line of text To read a set of values from a file, the line is first read, and then the individual elements of the line

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TEXTIO procedures and functions

Most commonly used procedures and functions

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File declaration

A file declaration opens a file for input or output, depending on the mode
o A file can only be read and written. It cannot be assigned

Input file declaration

file file_name: text open read_mode is "input_file_name.txt";

Output file declaration

file file_name: text open write_mode is "output_file_name.txt";

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TEXTIO output

Steps to write to a text file:

use std.textio.all;

file example: text open write_mode is "output_example.txt";

variable L: line;

signal A: bit_vector(2 downto 0) :=010; --------------------------------------------write(L, now, left, 8 ); write(L, A); writeline(example, L)

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TEXTIO input

Steps to read from a text file:

use std.textio.all;

file example: text open read_mode is "input_example.txt";

variable L: line;

Signal A,B: bit_vector(2 downto 0); variable A_var, B_var: bit_vector(2 downto 0); --------------------------------------------readline(example, L); read(L, A_var); read(L, B_var); A <= A_var; B <= B_var;

A = 000 B = 111

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Procedure READ

READ skips over white spaces and starts reading at the first non-space character, except for types Characters and Strings
o Space is a valid value of Character and String types
variable A: time; variable B: integer; variable C: character; variable D: string(1 to 4); -----------------------------------------readline (example, L); read(L, A); -- A = 10 NS read(L, B); -- B = 5 read(L, C); -- C = read(L, D); -- D = IS read(L, B); -- error !

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Package STD_LOGIC_TEXTIO

The package TEXTIO which is part of the VHDL standard does not support the STD_LOGIC data type Many private packages have been proposed to do the job of TEXTIO for the data type STD_LOGIC

One such package is STD_LOGIC_TEXTIO

o Developed by Synopsys o For most simulators, this package is provided in their IEEE library

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Use of STD_LOGIC_TEXTIO

Both packages, STD.TEXTIO and IEEE.STD_LOGIC_TEXTIO, must be used in order to be able to use all the types and functions library ieee;
use std.textio.all; use ieee.std_logic_textio.all; ---------------------------Signal A,B: std_logic_vector(2 downto 0); --------------------------Stimulus: process file example: text open read_mode is "input_example.txt"; variable L: line; variable A_var, B_var: std_logic_vector(2 downto 0); begin while not endfile(example) loop

A = 000 B = 111

readline(example, L); read(L, A_var); read(L, B_var); A <= A_var; B <= B_var; end loop; end process stimulus;

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Input / Output files example

library ieee; use ieee.std_logic_1164.all; entity or_gate is port ( A, B : in std_logic; C : out std_logic ); end entity; architecture behavior of or_gate is begin C <= A or B; end behavior;

Use Use

IEEE.std_logic_textio.all; STD.textio.all;

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Input / Output files example

Library IEEE; Use IEEE.std_logic_1164.all; Use IEEE.std_logic_textio.all; Use STD.textio.all; entity Testor_gate is end Testor_gate; architecture stimulus of Testor_gate is -- UUT component declaration here -- Signals declaration here begin -- UUT component instantiation here STIMULUS0:process file in_file : text open read_mode is "in_values.txt"; file out_file : text open write_mode is "out_values.txt"; variable out_line, in_line : line; variable X,Y,Z : std_logic;

begin while not endfile(in_file) loop --do this till out of data readline(in_file, in_line); --get line from input file read(in_line, X); --get first operand from the line A <= X; read(in_line, Y); --get second operand B <= Y; wait for 2ns; Z := C; write(out_line, Z); --save results to line writeline(out_file, out_line); --write line to file End loop; assert false report "Simulation done" severity note; wait; --allows the simulation to halt! end process; end architecture;

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Finite State Machine (FSM)

A Finite State Machine (FSM) is a model of behaviour composed of a finite number of states, transitions between those states, and actions
o Used as a controller in digital circuits
o Consists of a storage element and logic to generate next state
Transition

Designing of FSMs involves:

o Defining states
Transition condition 2

State 1
Transition condition 1

o Defining transition between states

State 2

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Present State and Next State

For any given state there is a finite number of possible next states
o On each clock cycle, the state machine branches to the next state if the transition condition is true
o One of the possible next states is the new present state
State 1

State 2

If the present state is state 2, then the previous was either state 1 or 2 and the next state must be either 2, 3 or 4
State 4

State 3

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Moore and Mealy Machines

Mealy Machine
o A state machine that determines its outputs from the present state and from the inputs

Moore Machine

o A state machine that determines its outputs from the present state only
(Mealy only) Inputs

Next State Logic

Next State

State Memory

Output Logic

Outputs

clock Current State

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FSM: An Implementation Example

After 1 min After 1 min After 1 min After 1 min

After initialized

T=1

T=2

T=3

T=4

Reset = 1 Reset = 1 Reset = 1

Reset = 1

S_R
T=1

S_RY
T=2

S_G
T=3

S_Y

T=4

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FSM: An Implementation Example

Reset T

LG

Next State Logic

Next State

State Memory

Output Logic

LY LR

clock Current State

entity FSM_for_Traffic_Lights is port ( Reset, CLK : in std_logic; T: in integer range 4 downto 0; LG, LY, LR : out std_logic ); end entity FSM_for_Traffic_Lights ;

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FSM: An Implementation Example

Reset T LG

Next State Logic

Next State

State Memory

Output Logic

LY LR

clock Current State

Architecture behaviour of FSM_for_Traffic_Lights is Type statetype is (s_r, s_ry, s_g, s_y); Signal CurState, NxtState: statetype:= s_r; NSL: process process (CurState, (CurState, T) T) NSL: begin begin --Next Next State State Logic Logic -end process process;; end

SM: SM: process process(CLK, (CLK,Reset) Reset) begin begin --- State State Memory Memory end process ;; end process

OL: OL: process process(CurState) (CurState) begin begin --- Output OutputLogic Logic end ;; end process process end behaviour;

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FSM: An Implementation Example

Reset = 1 Reset = 1 Reset = 1

Reset = 1

S_R
T=1

S_RY
T=2

S_G
T=3

S_Y

Reset T

LG

T=4

Next State Logic

Next State

State Memory

Output Logic

LY LR

clock Current State

NSL: process (CurState, T) begin case CurState is when s_r => if (T = 1) then NxtState <= s_ry; end if; when s_ry => if (T = 2) then NxtState <= s_g; end if;
when s_g => if (T = 3) then NxtState <= s_y; end if; when s_y => if ( T = 4) then NxtState <= s_r; end if; end case; end process;

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FSM: An Implementation Example

Reset = 1 Reset = 1 Reset = 1

Reset T

LG

Reset = 1

Next State Logic

Next State

S_R
T=1

S_RY
T=2

S_G
T=3

S_Y

State Memory

Output Logic

LY LR

T=4
clock

Current State

OL: process (CurState) begin if CurState = s_r then LG <= 0; LY <= 0; LR <= 1; elsif CurState = s_yr then LG <= 0; LY <= 1; LR <= 1; elsif CurState = s_g then LG <= 1; LY <= 0; LR <= 0; elsif CurState = s_y then LG <= 0; LY <= 1; LR <= 0; end if; end process;

SM: process (CLK, Reset) begin if Reset=1 then CurState <= s_r; elsif rising_edge (CLK) then CurState <= NxtState; end if; end process;

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Exercise: FSM for a Washing Machine

T=2 T=1

Wash

Rinse

Reset

Stop
T=5 T=4

T=3

Dry

Spin

Current State Stop Wash Rinse Spin Dry

Next State Wash Rinse Spin Dry Stop

T (every 10 mins) T=1 T=2 T=3 T=4 T=5

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Solution: FSM for a Washing Machine

T=2 T=1

Wash

Rinse
T=2

Reset

Stop
T=5

Dry

T=4

Spin

Reset T

Next State Logic

Next State

State Memory

Output Logic

R Sp D

clock Current State

entity FSM_for_Washing_Machine is port ( Reset, CLK : in std_logic; T: in integer range 5 downto 0; S, W, R, Sp, D : out std_logic ); end FSM_for_Washing_Machine ;

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Solution: FSM for a Washing Machine

Reset T
S

Next State Logic

Next State

State Memory

Output Logic

R Sp D

clock Current State

Architecture behaviour of FSM_for_Washing_Machine is Type statetype is (stop, wash, rinse, spin, dry); Signal CurState, NxtState: statetype:= stop;

NSL: process process (CurState, (CurState,T) T) begin -- Next State State Logic Logic end process ; process;

SM: SM: process process(CLK, (CLK,Reset) Reset) begin begin --- State State Memory Memory end process ;; end process

OL: OL: process process(CurState) (CurState) begin begin --- Output OutputLogic Logic end ;; end process process end behaviour;

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Solution: FSM for a Washing Machine

T=2

T=1 Reset

Wash

Rinse
T=3

Stop
T=5

Dry

T=4

Spin
Reset
S

NSL: process (CurState, T) begin case CurState is when stop => if (T = 1 ) then NxtState <= wash; else NxtState <= NxtState; end if; when wash => if (T = 2) then NxtState <= rinse; end if; when rinse => if (T = 3) then NxtState <= spin; end if;

Next State Logic

Next State

State Memory

Output Logic

R Sp D

clock Current State

when spin => if (T = 4) then NxtState <= dry; end if; when dry => if (T = 5) then NxtState <= stop; end if; end case; end process;

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Solution: FSM for a Washing Machine

S

T=2 T=1 Reset

Reset T

Next State Logic

Next State

Wash

Rinse
T=3

State Memory

Output Logic

R Sp D

Stop
T=5

clock Current State

Dry

T=4

Spin

OL: process (CurState) begin

SM: process (CLK, Reset) begin if Reset=1 then CurState <= stop; elseif rising_edge (CLK) then CurState <= NxtState; end if; end process;

if CurState = stop then S <= 1; W <= 0; R <= 0; Sp <= 0; D <= 0; elsif CurState = wash then S <= 0; W <= 1; R <= 0; Sp <= 0; D <= 0; elsif CurState = rinse then S <= 0; W <= 0; R <= 1; Sp <= 0; D <= 0; elsif CurState = spin then S <= 0; W <= 0; R <= 0; Sp <= 1; D <= 0; elsif CurState = dry then S <= 0; W <= 0; R <= 0; Sp <= 0; D <= 1; end if; end process;

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Exercise

Different inputs and outputs (Entity declaration)? VHDL code to implement the circuit modelled using the above state diagram?

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Solution

entity FSM_ent is port ( RESET, A, B: in std_logic; CLK: in std_logic; C: out std_logic_vector (1 downto 0)); end FSM_ent;

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Solution

architecture FSM_arch of FSM_ent is -- creation of a new type Type statetype is (S0, S1, S2, S3); -- declaration and initialisation of signals: signal CurState, NxtState: statetype:= S0; begin -- Next state logic process NSL: process (CurState, A) begin case CurState is when S0 => if (A='0') then NxtState <= S0; else NxtState <= S1; end if; when S1 => if (A='0') then NxtState <= S1; else NxtState <= S2; end if; when S2 => if (A='0') then NxtState <= S2; else NxtState <= S3; end if; when S3 => if (A='0') then NxtState <= S3; else NxtState <= S0; end if; end case; end process;

-- State memory process SM: process (CLK, RESET) begin if (RESET='1') then CurState <= S0; elsif rising_edge(CLK) then CurState <= NxtState; end if; end process;

-- Output logic process OL: process (CurState) begin if (CurState=S0) then C<= "00"; elsif (CurState=S1) then C<= "01"; elsif (CurState=S2) then C<= "10"; elsif (CurState=S3) then C<= "11"; end if; end process; end FSM_arch;