Microprocessor Instruction Set © Er. A.

N Mishra

Data Transfer Croup

The data transfer instructions move data between registers or between memory
and registers.

Op code operand Description

MOV Rd,Rs Move
MVI R,Data(8-bit) Move Immediate
LDA Address (16-bit) Load Accumulator Directly from Memory
STA Address(16-bit) Store Accumulator Directly in Memory
LHLD Address( 16-bit ) Load H & L Registers Directly from Memory
SHLD Address ( 16-bit) Store H & L Registers Directly in Memory
LXI Rp,16 bit data Load Register Pair with Immediate data
LDAX B pair or D pair Load Accumulator from Address in Register Pair
STAX B pair or D pair Store Accumulator in Address in Register Pair
XCHG - Exchange H & L with D & E
XTHL Exchange Top of Stack with H & L
IN 8 bit(port Adress) Load accumulator from Input port
Out 8 bit(port Adress) Send data byte from accumulator to output device
X: the name of a data transfer instruction implies that it deals with a
register pair (16-bits)
R: 8085-8 bit register (A, B, c, D, E, H, L)
M: memory registers (location)
Rs: Register source (A, B, c, D, E, H, L)
Rd: Register Destination (A, B, c, D, E, H, L)
Rp: register Pair (B->BC,D->DE,H->HL,SP)
Note: Data Transfer Instruction Instruction not affect flags.

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 Microprocessor Instruction Set © Er. A.N Mishra

Arithmetic Group
The arithmetic instructions add, subtract, increment, or decrement data in
registers or memory.
Op code operand Description Flag
operation
ADD R Add to Accumulator ALL
ADI 8 bit data Add Immediate Data to Accumulator All
ADC R Add to Accumulator Using Carry Flag ALL
ACI 8 bit data Add Immediate data to Accumulator Using ALL
Carry
SUB R Subtract from Accumulator ALL
SUI 8 bit data Subtract Immediate Data from Accumulator ALL
SBB R Subtract from Accumulator Using Borrow ALL
(Carry) Flag
SBI 8 bit data Subtract Immediate from Accumulator Using ALL
Borrow (Carry)Flag
INR R Increment Specified Byte by One ALL except
carry
DCR R Decrement Specified Byte by One ALL except
carry
INX Rp Increment Register Pair by One Affect no
flag
DCX Rp Decrement Register Pair by One Affect no
flag
DAD Rp Double Register Add; Add Content of Only carry
Register Pair to H & L Register Pair flag
DAA Adjust the accumulator content in BCD Affect all
this is only instr which use AC flag. flag
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 Microprocessor Instruction Set © Er. A.N Mishra

Logical Group
This group performs logical (Boolean) operations on data in registers and
memory and on condition flags.

The logical AND, OR, and Exclusive OR instructions enable you to set specific
bits in the accumulator ON or OFF.
Op code operand Description Flag
ANA R/M Logical AND with Accumulator Affect all but
set AC and Clear
Carry flag
ANI 8 bit data Logical AND with Accumulator Using Immediate Data ””

ORA R/M Logical OR with Accumulator Affect all but

clear AC and
Carry flag
ORI 8 bit data Logical OR with Accumulator Using Immediate Data ””

XRA R/M Exclusive Logical OR with Accumulator ””

XRI 8 bit data Exclusive OR with Accumulator Using Immediate Data ””
CMP R/M Compare with Accumulator ””
CPI 8 bit data Compare with Accumulator Using Immediate Data ””
RLC - Rotate Accumulator Left Only carry
RRC - Rotate Accumulator Right Only Carry
RAL - Rotate Left Through Carry Only carry
RAR - Rotate Right Through Carry Only carry
CMA - Complement Accumulator No Afft flag
CMC - Complement Carry Flag Only carry
STC - Set Carry Flag Only carry

Q.N. Write a program to test D4 bit of memory 2056H is either 1 or 0.

Q.N. Write a program to complement D5 bit of the memory 3057 and store the result to the
3058.

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 Microprocessor Instruction Set © Er. A.N Mishra

Compare Operation.

If (A)<(Reg/Mem/Data): Carry flag is set and Zero flag is reset.

If (A)=(Reg/Mem/Data): Carry flag is reset and Zero flag is set.
If (A)>(Reg/Mem/Data): Carry flag is reset and Zero flag is reset.

S Z X AC X P X CY

Branch Group:

The branching instructions alter normal sequential program flow, either unconditionally
or conditionally. The unconditional branching instructions are as follows:

JMP Jump
CALL Call
RET Return

Conditional branching instructions examine the status of one of four condition flags to
determine whether the specified branch is to be executed. The conditions that may be
specified are as follows:

NZ Not Zero (Z = 0)
Z Zero (Z = 1)
NC No Carry (C = 0)
C Carry (C = 1)
PO Parity Odd (P = 0)
PE Parity Even (P = 1)
P Plus (S = 0)
M Minus (S = 1)

Thus, the conditional branching instructions are specified as follows:

Jumps Calls Returns

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 Microprocessor Instruction Set © Er. A.N Mishra

C CC RC (Carry)

INC CNC RNC (No Carry)

JZ CZ RZ (Zero)
JNZ CNZ RNZ (Not Zero)
JP CP RP (Plus)
JM CM RM (Minus)
JPE CPE RPE (Parity Even)
JP0 CPO RPO (Parity Odd)

Two other instructions can affect a branch by replacing the contents or the program
counter:

PCHL Move H & L to Program Counter

RST Special Restart Instruction Used
With Interrupts

These Branching instructions not affect the flag.

Stack I/O, and Machine Control Instructions:

The following instructions affect the Stack and/or Stack Pointer:

PUSH Push Two bytes of Data onto the Stack

POP Pop Two Bytes of Data off the Stack
XTHL Exchange Top of Stack with H & L
SPHL Move content of H & L to Stack Pointer

The Machine Control instructions are as follows:

EI Enable Interrupt System
DI Disable Interrupt System
RIM
SIM
HLT Halt
NOP No Operation