There are a lotal of four players and four nlsslles.

The fout
nisstles n0aybe grouped together and used as a 5rh player, These
objects are posltloned horlzontally by 8 horizonral posltlon regtslers
([PoS (X)). These reglsrers nay be reloaded at any rlne by rhe proces-
sor, allowlng an object to be repllcated nany tiioes across a horizontal
TV 1ine.

The shape of a player-nlsslle is deterElned by lhe data tn lts

graphics reglster (GMF (X)). Players have independent 8 blt graphtcs
reglsters. The four lllsslles have 2 blt regtsters (located wlthln olre
address). These reglsters oay also be reloaded at afly ttne by the
processor, although they ale usually changed during horlzontal bLank
tlme. The data ln each giaphics reglster is placed on the display
rhenever the horizontal sync couflter equaLs the corresponding horlzon-
ta1 posltion tegister. The same data \1111 be displayed every line unless
the graphlc reglsters are reloaded vrith Ire data.

The player-ntssile graphlc registers rnay be reloaded by the mlclo-

processor (CRAF (X)), or arlonattcally fron nenory with dlrect meDory
access (Dl4A) (see figure II.3). The prograr0ner lrusr place rhe objecr
graphics ln Demory, I1'rlte the player-miss1le base address (PMBASE), and
enable player-Eissile DI'A (DMACTL, GRACTL). The transfer of object
graphlcs from rneuory to dlsplay ls then fully autornaric.

PMBASEspeciftes the nost slgnificanr byte (MSB) of the address of

the player-nissile graphics. The locatlon of rhe graphics for each
oblect is deternined by addtng an offset to PMBASE*256 (decimal). The
bytes betrseen the base address aod the ntsslle dara are not used by
Antic, so they are available to rhe progranner.

Only the five nost stgnificant bits oI PMBASEare used lrirh

strgle-line resolutlon and the slx nost stgnlftcant blts are useil
wlth two-line resolutior. This !0eans thar the location of the graphlcs
1n nenory 1s restllcted !o certaln page boundartes. Two-llne reso-Lu-
tion neans that each byte of data ls repealed for lqlo Ilnes. (see
DI.{ACTL,blt 4). 540 (decinal) bytes (5X128) are requlred for rwo-ltne
resolutlon and l28O byres (5x256) tor one-tine resoiur'ion,

Each byte tn rhe player graphics area represenls elght ptxels whtch
are to be displayed on the correspondtng llne(s) of rhe TV screen. A
I indlcates that the player's color-lun ts to be dtsplayed in that ptxel.
The graphics nay be anyrhtng, not Just rectangles like the ones in ftgure
II.3. The player graphlcs may f111 the enttre hetght of rhe screen or
they may be only a couple of lines high if the rest of the dlsplay dara ts
al1 0's. Each byte 1n rhe rolssile dlsplay also represenrs etgi.rt plxels,
trro pixels for each missile. Each ptxel nay be 1, 2, or 4 color clocks,
and is deternined by the SIZE registers.

Plavfleld: Playfle1d ts always generaled by DMA. There axe four

piayfields, each ldenrtfled by its own color-1um reglster and colllstott
detection. Playfleld ls generated by lwo dlfferen! DMA technioues:
neloory nap and character. Both methods provtde llsts of insE;ctlons 1n
menory, independent of the player-r0issile generatlon.
player-Mlsslle Sase Address (PMBASE)= ),ISBof address.
Resolutlon ls controlled by bit 4 of DI4ACTL,

(hex)
PMBASE*100

A.DDRESS OFFSET
Tvo-l1ne One-line
resolutlon resolutlon
(hex) (hex)

Mlss lle TV SCREEN

+180 +300 2 I Nunber
.21 I
M P0l
i i ; i
r l
r42 It l
+200 +400 l t MO -
I i I Pl
PO P2 |.'i
+280 +400 rP3t
I' MI
M3 I
i-T--
PI I r l
f300 +600 t l
t l
P2 | | Horlzonral Dosirlon
I ior each objec! 1s s e t
+380 +700 l t lndependently by 8

P3
t l horlzontal positlon
l l regasrers.
I
+400 +800

E a c h s e c t l o n o f m e m o r yn a p s d l r e c t l y
Player-Mtssile onlo total height of TV screen.
Ver!1ca1 screen Object vertical posltion is deternined
only by lts Iocatlon In lts section
of deDory. one byre of oenory equals
I or 2 television lines vertlcally,

Figure II.2 P L A Y E R - M I S S I L E D M A

II.6
 Unl1ke players and Elssiles, there are oo horlzontal posltlon regtsrers
for playfleld. Each player can only have one byte of display per llne.
Playfteld, on lhe othet hand, nay requlre up to 48 bytes per line because
1t can fll1 the entire wldth of the screen.

T'here are three dlfferent playfield lrldths: narrow (128 color

clocks), standard (160 color clocks), and wide (192 coLor clocks),
The ddth 1s selected by stortng lnto DMACTL. The advantage of a rarrolrer
nldlh ls that less R.A.lills reql.rlred and fener nachine cycles are stolen for
DMA. The 0S graphlcs modes use the standald screen wldth.

g!9If3I-!19!: The dlsplay list is a sequence of display instructlons

stored fir rnemory. These lnstructlons are eithe! one (1) byte or rhree (3)
bytes 1ong. The dlsplay llst can be considered a dlsplay progran, and the
Dlsplav Llst Counter that fetches lhese lnstluctlors can be thought of as
a dlsplay progran counler. (10 bit counter plus 6 bit base reglster.)

The dlsplay 1lst counter can be inirlalized by wrirtng ro DLISTIT and

DIISTL. (or OS shadow registers SDLSTEard SDLSTL). once tnltlaltzed
thls counler value ls used to address the dlsplay llst, fetch the lnstruc-
!ton, dlsplay one (l) to slxteen (16) lines of data on lhe TV screen,
lncrenent the Dlsplay l,1st CounLei, fetch the next dlsplay lnstruction,
and so on &.ltonatlcally irlthout Elcroprocessor control (see DLISTI and
DIISTII). DLISTI and DLISTH should be aLtered only during vertlcal blank
or when DMA 1s disabled (see DI,IACTL).

Each lnstructlon deftnes the type (alpha character or nemory map) and
the resolutlon (s1ze of blts on screen) and the locatlon of data ln nerory
to be dlsplayed for a group (I to 16) of l1nes. Each group of lines ts
ca11ed a dlsplay b1ock.
TITE DISPI-AY I-IST CANNOTCROSSA lK BYTE MEMORYBOIINDARYUNLESS
A JUMP INSTRUCTION IS USED.

DI,ISTI,

Flxed (6 btrs) counter ( 1 0 b l t s )

DISPLAYLIST COUNTER

tr.7
 Dlsplav Inslructlon Fornat: Each lnstruction conslsts of either an
opcode only, or of an opcode followed by tiro (2) bytes of operadd.

lopcodel ------Slngle Byte Display Instructlon

-.t
l6'..d.-l \
l o p e r a n d| ) - - - - T r l p l e EyLe DIspIdy Instructlon
-_-t
lOperand I.,

The opcode ls al{ays fetched flrst and placed ln the leqlggllgg

Reelster. This opcode deflnes the type of lnslructlon (1 o! 3 bytes)
and wll1 cause t\ro 'Iore bytes to be fetched if needed. If fetched,
these next rwo (2) bytes rrill be placed ln lhe l4gggTI-.gSeg-9993!CI,
or ln the Dlsplay I-1st Counter (if the instructlon ts a Jump).

Dlsplay Instructton Reglster (IR)r This register is loaded wlth the

opcode of the current dtsplay 1lst lnstructlon. It cannot be accessed
dlrectly by the prograomer. There axe three bastc lypes oi display lts!
inslruc!1ons: blank, ju!0p, and dlsplay.

Blank
( t-byte) 6lD5lD4

This lnslnrctlon is used to create I to 8 blank llnes on the

dlsplay (blackground color).

D7 I - display llsr InsLrucclon inEerrupt

t5 - D4 0-7 = r-8 blank lines
D3-D0 0 = blank

(3-bytes ) D 7 l D 6 lX l X l 0 l 0 l 0

Thls lnslructlon is used to reload the Dlsplay List Counter.

The next two bytes speclfy lhe address to be loaded (LsB first).

D7 I = d t s p l a y . I . L s cl n s c r u c t l o n i n t e r r u p t
D6 0 = junp (creates one blank ltne on dlsplay)
"_i' _:t.I end of nexl vertlcal blank
D5-D4 X = don't care
D3_D0 I = junp

Dlsplay
(1 or 3 bytes) D 2 I D lI D O

Thls lnstructlon specifles the type of dlsplay for the next

display block.

D7 I = dlsplay list inEtructlon inteErupt

n6 n=l hvts.i^cfr,r.rlon
I - 3 b y L e I n s c r u c c l o n ( r e l o a d M e m o r ys c a n C o u n t e r
uslng address ln next lwo bytes, LSB ftrst).
D5 I = verttcal scroll enable
D4 I - horlzontal scroll enable
D3-D0 2-F = dlsplay node (memory or character map -
see following pages).

II.8
.rr x

F H

ts.o6<raoatsl
r & t s ] t 4l & h t 4 I ' r E t s t r h E r E l
F @ 6 < l q ( J A l n

F c o 6 < f q { J A [ r ]

r @ 6 < 1 4 ( ) a F r

N.o6<FqL)crrIr

r o 6 < i 0 < J A p l ;

Fco6<rcrJoFt

( c o 6 < F ( J A d

N c o 6 < F q ( j , a

Fco6<laL)FIIr

F@6<rC(JAtst

ts@6<lqc)A14

F@6<rO(,)OEl

tsco6<roooFl

t s @ 6 < l a O A F . l

6 t s @ o < F O O t s l

t t l
--! | |
-----1 I I
I
,
 Btt 7 of a dtsplay 1lst tnstructlon can be set to create a dlsplay
list tnterrupt 1f btt 7 of NMIEN 1s set. The dlsplay 11s! lnternrpt coile
can change the colors or graphics durtng the nlddle of the TV dlsptay.
The lype of lnterrlpt ls derernlned by checklng NMIST. NMIRES clears
NMIST, The current 0S will vecror through VDSLST(Itex 200 and 2Ol) to
lhe user's dlsplay 1lst lnterrupt rourine. See the OS nanual for proarau-
.olng detatls.

Blts 5 and 4 of a dlsplsy type of dtsplay llst inshuctlons are used

to enable vertlcal and horlzoflta1 scro111[g. The amount of scro1llng
depends on the values ln the VSCRoI and I{SCRO],reglsters (to be descrtbed
later).

Meoorv Scan Counter! Thls counter is not dlrecrly accesslble by the

progtaEner. It 1s loaded wlth the value in rhe last 2 bytes of a 3 byre
(non-Junp) 1Tlstruction.

Thls counter pohts to the locarlon (address) ln mernoryof data ro be

directly displayed (Eemory nap dtsplay) or ro the locatlon of characrei
rane strlngs to be tndtrectly displayed (chalacter dlsplay).

A single byEe lnstructlon does not reload thts counter. Thls lnp11es
a contimratlon In rremory of data to be dlsplayed frorn that displayed by
the previous instructlon. Stnce thls counter really conslsts of 4 btts of
reglster and 12 of actual counter, a conttnuous menory block cannot cross
4K bvte rnenorv boulldarles. unless the counter ls reposltloned wlth a 3
byte Load Meinory Scan Counter instrucllon.

l,lSB thlrd byte of 3 byte LSB Second byte of 3

hwrc lnorh!.r l^n byte lltstrucllon

t t t l
1 1 0 2

t t t l t t t t l
15l 14l 13l r2 3 ' 2 t 1
Flxed (4 btts) Counter ( l2 bits)

Menorv Map Dlsplav Instructlons: Data 1n nenory (addressed by the

Memory Scan Counter) is dlsplayed dtrectly $hen executlng a nenory (btt)
nap dlspfay lnstruction. As data is betng displayed 1t ls also stored 1n
a shlft reglster so that it can be redlsplayed for as nany TV 1lnes as
required bY the lnslructlon.

1 r .l 0
 Menory Scan Counter
Addresses each byte
Mernory

one l1ne worth of rdenory 1s

loaded tnto the shlft reglster

Shlft reglster data 1s dlsplayed for four Tv scan 11nes ln thls exarnple.

In Instructlon Regtster (IR) dtsplay nodes 8 through tr', one or two

blts of nemory are used to spectfy lrhal 1s to be dlsplayed on each plxel
of the screen. Plxel slzes range froE l/2 clock by I TV llne to 4 cLocks
by 8 TV ltnes. The 0S and BASIC support nost of these grephlcs nodes
(BASIC GRAPITICS comand). Tvo nodes, C and E, are not supporled by the
OS. Ttese nodes have rectanguLat plxels, lrhlch are approxlmately tlrlce as
wide as they are hlgh,

In IR Eode F, only one color (CoIPI2) can be dlsplayed. T\ro dlfferent

luElnances are avatlable. If a blt 1s a zero. then the lunlnance of the
correspoodlng plxel cones fron COLPI'2. If the btt 1s a one, them the
lunlnance ts deterntned by the contents of CoLPFI (abbrevlated to Pf'l).

In lR modes 9,8, and C, two different colors can be displayed. A

zero lndlcales background color and a one hdlcates ?f0 color. T1le
dlfference between the varlous modes 1s ln the slze of the plxels.

In IR modes 8,A,D, and E, two btts are used to speclfy the color
of each ptxel, This al1ows four dlfferent colors ro be dlsplayed.
l{olrever, only four plxels can be packed llrto each byte, lnstead of elght
aB in the prevlous Ecdes. The bi! asslgnnents are shoqrnbelor.

SHIFT RECISTER 7 6 t 5 4 1 3 2 t t 0 | 7 6 t 5 4 2 t t 0

2 blts foro
one plxel

II. I1
 l4eoorv }lap Dlsplay ltlodes

oS I lcolors Plxels lBytes Iscen lColor I I Blt I

and l1nst. I per per I per lLlnes I clocks I Btts lvalueslcotor
BASICIRes. I uode srd. lstd. I per I per lper I tn I Rec.
odeslHEx | | Line I ritre lPtxel lPlxel lPlxellPixel lselect
| | I | | I | 100 | BAK
40 l0 8 1 4 OI PFO
I 10 PT'I

ro | 4
I

s l A l 4 l 8 0 101 l?30
l t l lr0 lPrl

I 160 0 BAK
I I ?r0
00 BAK
2 I 0l PTO
I r0 ?r1

I 160 0l
I 10

320 40
I Prl
t t t t l IGIIM)

rt. t2
 Character Dlsplav Instructlonst The flrst step 1n ushg the character
map dode 1s to cxeate a character set ln neEory (or the bu1lt-tn OS
character set at hex E000 nay be used). The character set contalns elgh!
bytes of !g!g for the graphlcs for each character. The neantng of the
data depends on the hode. The charecter set can contaln 64 or 128 characters,
also depending on the oode. The USB (l,losr Slgntftcant !yte) of rhe
address of the character set ls stored ln CHBASE(or the OS Shadon CHBAS).
Only the most slgntftcant s1x or seven blts of CHBASare used (see CIIBASE
descrlptlon ln sectlo[ III). The other one or two blts and the LSB of the
addless are assuued to be zero, so lhe character set fitst start aE an
acceptable page boundary.

Tte dext step ls to set up the dtsplay 11st for the destred node.
Then the actual dtsplay 1s set up. Thls constsrs of a strlflg of chatacter
lgggg or codes. Each nane takes one byte. The last 6 or 7 bits of the
nene selects a character. For a 64 charactet set, the naEe would range
froE 0 through 63 (decloal). For a 128 characrer ser, rhe range \rould be
0 through 127 (declnal). The upper one or rwo blts of rhe nane byle are
used to speclfy the color or orher speclal tnfornatlon, dependtng on the

Character nanes (codes) are fetched by the neroory scan counter, and
are placed ln a shtf! reglster. On any glven ltne of dlsplay the shifr
reglster rotates, changing only the nane portlon of the character address,
as shol'n belon.

After a full 1lne of character data has been dlsplayed the line
counter v111 lncrenent. The next l1ne agaln addresses all characrers by
na.oe for lhat ftne rnrmber.

In 20 character f'er ltne modes the seven nost slgrlflcant birs of

CIBASE are used. Th{s requlres that the charactet set !o statt upon a 512
byte Eenory boundary. The set Inlst conratn 64 charcters, 8 bytes each,
glvlng a rotal of 512 bytes for the

The 40 character per ltne aodes use the slx most slgnlficant blts
of CEBASE,forclng the character set to start on a lK byte rnemory boundary.
The aet rrust have 128 charactels of 8 bytes each. Thls gives a total of
1024 bytes for the set.

I ltex Graphlcs I chars. Nunber laytes lNunbe. lnytes

lCode Mode of l l n
L tne Char Set

f 4 l I28

II.I3
 Character Dlsplay Internal
codes for
(20 Characrer per llne mode exarnple)

Codes (naines)
Stored ln
Shlft Register

shlft
Resls!er

Color Addr:ess portlon of

Reglster Character nane
Select

Llne

Character Data Address

Char:acter Set
1n llemory

Addresses data in

and displays on the

TV 0
I TV
2 Scan
3 Lines
Color assigned 4
by color reglsEer 5
sefected 6
7

r1.14
 There are slx charcter inap modes, IR rnodes 2 through 7. Modes 2,6
and 7 are supported by the OS and BASIC (GRAPHICS0,f and 2).

In IR dodes 6 and 7, the upper two bits of each character Iraoe selec!
one of four playfleld colors, For each 3e!g bit that contains a one, tfre
selected playfleld color is dlsplayed. For each zero data btr, the
background color ts dtsplayed. The four characler colors plus the background
color glves a total of flve dlfferent colors. the loode 6 characters are
elght lines htgh and the dode 7 characters are slxteen lines htgh (each
data byte ls dlsplayed for two ltnes).

In IR nodes 4 and 5, each character ls only four plxels i{de lnstead

of elght (as ln the olher nodes). Two btts per pixel of data are used to
select one of three p1ayf1eld colors, or background. Seven eqEg bits are
used to select lhe character. If the most signlftcant nane blt ls a zero
the[ data of 10 (binary) selects P]I. If the nane blt 7 1s one, rhen data
blts of l0 select PF2. Thls nakes it possible to dlsplay l\no chalaclers
wlth dlfferert colors, uslng the same data but differenr nane bytes.

.- In IR roodes 2 and 3, each plxel is half of a color clock tn width.

This makes lc posslble to have forty etght-pixe1-wtde characters in a
standard \ddth 11ne. These nodes are slnllar to r0enory loode F h that two
lur0inances can be dlsplayed, but only one color 1s available a! a tllle.
In IR mode 3, each character ls l0 Unes high. This nakes lt posslble to
deflne loner case characters w_ith descender€. Tlle las! fourlh of the
characte! set (naEe blts 5 and 6 equal to one) is lowered. The hardware
takes the flrs! !!r0 dala bytes and noves then to the botron of the characte!,
displaylng two blank l1nes at the rop of the character (see next page).

\- In IR oodes 2 and 3. blt 7 of the characler narne ls uaed for inverse

vldeo or blanklng. This is controlled by CHACTL(character co$tro1). If
blt 2 of CHACTLls a one then all of the characlers will be dlsplayed
upslde dolrn, reeardless of node, If CEACTLbil I is set, lhen each
character \.rhich has blt 7 of 1ts nane set l{lll be displayed in inverse
vtdeo (the luBlnances will be reversed). If CHACTI- blt 0 is set, then
each character whlch has blt 7 set w'l1l be btanked (on1y background wil be
dlsplayed). Characters can be blinked on and off by settlng nane bil 7 to
I and loggltng CEACTI-bit 0. Inverse vldeo and blank apply only to IR
modes 2 ard 3. If both inverse vldeo and blank are set then the character
w111 appear as an lnverse vldeo blank character (solid sqrare).

Ilardware collislon Delectlonr 60 bils of colllslon register are

provlded to delect and store overlap (hits) belreen players, misslles and
playfleld. These collislons can be read by the Dicroprocessol fton
addresses D000 thlough D00I. There are no btts for nisslle to nlssile
co11islons.

16 bits for ulssile to Playfield

16 btts for Player to Playfield
16 blts for }Ilssile to PlaYer
12 bits for Player to Player (P0 io PO allr'ays leads as zelo, e!c.)

The l/2 clock lleDory nap node (1R code llll) and lhe l/2 clock chalacter
node (IR codes 0011 and 0010) are both playfleld type 2 coLltsions and w111
be slored in btl 2 of the playfietd colltsion registers.

T1.15
 IR l,lode 3-Upper and l,ower Case

Upper Case

Data

Act\ra1
Dlsplay
E

II.I6
 Chalacter Map Displav Modes

I os I I l c h a r s . l s c a nl c o l o r l D a t a l c o l o r I B i t I
I and lrnst.loolors I per lllneslclockslBtrs lselect lvalueslcolor
l B A s r c l R e lsp. e r Ista. lper lper lper lattsrnl 1Il lRec.
lModeslttEx I Mode lLine lchar.l?txel lPlxell Naroe lDara lselect
r r r r t t t -
t l l
o t 2 I4 4 0 l 8 l : l l | o I PF2
l r l P r l

0
I I PFT

lB{t 7 01 ?FO
l ' o l0 PTI
I 1I PF2
I
lBlt 7 11 PF3

00 BAK
lBtt 7 01 PFO
l = 0 l0 PFI
I ll PF2
I
lBit 7 II PF3

0 BAK
00 I PFO
OI I PT'I
IO I PF2
! PF3
o BAK
00 Pr'0
0I ?FI
10 PE2
| | | | | | | 1l I I L Pr'3

rr.17
 Vertlcal and llorlzontal Flne Scrolllna: ?layfleld objects are dlfflcult
to Eove srnoothly. Me.oory nap playfield can be rnoved by rewrttlog secrlons
of nenory. llowever, thls 1s extreEely tlne-consunlng if large secrlons
of the screen rfils! be noved snoothly. Character playfleld oblects can be
6oved easlly ln a jerky fashlon by chaoglng the nenory scan counter.
Ilorever, thls results 1n a large posltlon junp fro.n one character posttion
to another, not a smooth Dotlon. For thls teason hardnare reglsters
(VSCRoLand HSCROI,)and counters are provtded ro a1low snooth horlzonlal
or vertlcal notlon, up to one character wldth horlzonrally and up to one
character helgh! vertlcally. After this ouch snooth xnotion has been
done by lrrcreaslng the value in these reglsters, nenory 1s reErltten or
the nenory scan counter ts nodlfled and sDooth .0otlon 1s resuned for
another characrer distance,

Vertlcal ScrolllnA: A zone of playfleld on the screen can be scrolled

upward by uslng VSCRoLand bir 5 of rhe dtsplay llst lnslructlon, The
dtsplay blocks at the upper and lower boundarles of rhe zo[e Eu6t have a
varlable verElcal slze. In particular, the flrst dlsplay block rrithln lhat
zone trlist be shortened froid the top, and the last dtsplay block ftrst be
ehortened fron the botton (t.e. not all of the top and botton blocks dll
be dlsplayed).

The vertlcal dinenston of each dtsplay block 1s controlled by a 4 btt

counter wlthtn the ANTIC, called the 'De1ta Counter' (DCTR), Wlrhour
vertlcal scro1l1ng, lt starts at 0 on the firsr line, and counts up to a
standard va1ue, detelnlned by the current dlsplay lnsrruction. (Ex:
for upper and lolrer case text display, the end value is 9. Ior 5 color
character dlsplays, it 1s 7 or 15,)

If btt 5 of the lnstructlon renalns unchanged between consecutlve

display blocks, then lhe second block 1s displayed 1n the normal fashlon.
If blt 5 of the lnstructlon goes fror0 I to 0 between two consecutlve
display blocks, the second block \'111 start tu{th Delta = 0, as usual, but
r'llf coun! up until delta=VSCROL, lnstesd of lhe standard value. Ihls
shortens that dtsplay block fron the botton.

To deftne a vertlcally scrolled zone, the most dlrect melhod ls to

sel blt 5 to I ln the first dtsplay instnrctlon for that zone, and 1n all
consecutlve blocks but the lasr one. If rhe VSCROLregisrer is no!
reFrlttren on the f1y, thls results ln a rotal scrolled zone that has a
conslan! IujDber of 11nes (provtded that the VSCROTvalue does not exceed
the standard lndlvidual block stze). If N 1s lhe standard block size, che
rop block will be N-VSCROLl1nes (N > VSCROI ), and the lasr block wtll be
VSCROL + I 11nes: (N-VSCROL)+ (VSCROL+ 1) = 111. Shown on the
followtng page 1s an exanple of a scrolled zone, top block, for 8 VSCROI-
valuesforN=8.

Horlzonlal scrolllns is descrlbed under HSCROLln sectton IIt,

II. T8
 o

2
I 2 T1 I 3
t: T 5
7
'7

l i 5
7
J I
2
5 7 I z J
1 l z 3
-l 2 5 5
I z 3 5
I
I z 5 5 7
2 l 5 7
2 T
5 I
5 7 I 2
5 I 2 J

F
7 I
2 3 4
-t z 2 3 5
I
I fz 3 5
- 2 I 1 3 7

S+np19 Dlsplav Llst Exanpte: BASIC starls out in os graphlcs

. _ . node O
whlch dlsplays 40 characters across by 24 ro\rs, Thls 1s IR
node 2 nlth a
slandard screen ntdth. OS sets up the allsplay lts! near the top of
.The
R-Al1nlth room for the character nanes at the top of UU. On a 32 K_byte
nachtne, the dlsplay l1st would start at hex 7CiO. The flext three bytes
are hex 70's !o create 24 blank 1i[e6. The next byte 1s a hex 42, The
4 teUs the hardware to reload the Bernory scan cou;ter wlth
the follor,lng
address (7C40). Thts ls rhe aildress of ih. d.t. to be dlsptayed.
The 2
te1ls the hardware to dlsplay one line of IR noale 2 characters.
The
next 23 bytes specify 23 nore ltnes of rooile 2 characters.
Eex 4t is rhe
code for Junplng and walttng until the end of the nex! verllcat btank,
The address to Junp to ts 7C20, rhe start of the alisplay
-, llst. The flext
960 bytes are the 11st of characlers to be dlsplayed,
40 bytes per l1ne.
The oS lErst set up the dlsplay 1lsr pornter (oirsiu
;nd DLISTL) to the
atattlng address of the dlsplay 11st (7C20). It also
sets CIBASE to the
MSB of the address of rhe character ser (EO).

Thls ls a slEple exardple because orlly one node ls used and

the roenory
scan counter 1s only loaded at one point. It ls posslble
to have different
n o d e s o n d t f f e r e n t l t n e s , c h a n g e c h i r a c r e r e e t s and colors,
etc., as shor,rn
10 the example tn Sectlon IV.

II.19
 0S Mode 0 Dtsplav Ltst (40 chars x 24 1lnes)

Ad.i raee ahav\ Data (hex)

7C20 70'\
7 0 1 24 blatrk l1nes
70)
4 2 ) reload meroory acan counter r.Ith 7C40,
4 0 I IR roode 2
7C)

i)
; l
t
' . ( 23 nore IR mode 2 tnstructions

2 l
i -))
4l Junp back to 7C20 and
20 1 walt for end of vertlcal b1ank.
1C)
7C40
l
)
960 bytes of dtsplay
(character naoes)
data

cvcle countlns: As explatned prevtously, the ATARI 800 5502 ndcropro-

cessor runs at a rate of 114 machine cycles per Tv ltne (1.79 MHZ). There
ate 262 Ilnes per TV frane and 60 frames per second on the NTSC (tls) Bysren.
(The PAL (Europeor) systen ls dtfferent. See the sectlon on NTSCvs. ?AL.)

Each nachlne cycle ls equlvalert 1n length to 2 color clocks. There

are 228 color clocks on a TV 1lne. The highest resolutlon graphtcs nodes
have a ptxel slze of Il2 color clock by I TV Une. Ilorlzontal blank takes
40 nachlne cycles. Thls 1s !,'hen the bean returns to the left edge of the
screen 1! preparatlon for dtsplaytng the next TV 1lne. A walt for Sync
(WSYNC)lnstructlon stops the 6502. The processor ts restarled exactly 7
uachlne cycles betore the beglnnlng of the next Tv 11ne. lhe prograo can
thus change graphlcs or colors durlng horlzontal blallk lfl preparatlon for
the next 1ine,

The ANTIC chlp steaLs cycles fron the 6502 tr order to do memory
xefresh and fetch graphtcs data ehen needed. The general rule to r:emenber
ls that each byte fetched fron nernory re$lres one Dachine cyc1e. If a
dlsplay Ilst BeEory nap inslruction extends over several llnes then the data
ls only fetched on the flrst 1lne. MeEory refresh takes 9 cycles out of
every l1ne, unless pre-enpted by a htgh-resolutlon graphlcs mode. Menory
refresh conllnuea durtng vertlcal b1ank.

l,rsstle Dl4A takes one cycle per l1ne ln the one-1lne resolutlon Bode
and one cycle every'other 11ne ln the tlro 1lne resolution node. l,Ilsslle
DMA can be enabled rlthou! dolng playex DMA. l{owever, lf player DMA ts
enabled lhen olsslle DMAn111 also be done (see Dl4AcTL, GMCTL blls).
Player DMA iequlres 4 cycles every one or tlro llnes, dependlng on the
resolution used.

II.20
 Each fetch of a dtsplay ltst byte takes one cycle, so three cycles
are required for a three byte tnstructlon.

Player/mlsslle and display list lnstructton fetch DMA take place

during horlzontal b1ank, tf they are required for the next llne.

In nemory nap modes, the graphlcs dara ls fetched as needed rhroughout

the first l1ne of the display hst instruc!1on, lhen saved by ANTIC for
use ln succeedlng l1nes, In character nodes, the character codes are
fetched durlng the first ltne of each ron of characters, along rrtth the
graphics data needed for that llne. Or the next ltnes, only ihe graphlcs
dala iB fetched, slnce ANTIC renembers the character codes.

In lhe 40 x 24 character rdode, &{th a standard screen wtdth. nost of

the cycles durlng the top ltne of each row of chalacrers ale requrleal to
fetch the character codes and data, so rhere ls only rlne for one oenory
refresh cycle lnstead of the usual [1ne. ]-ess DltA ts requlred wlth a narro,
screen wldth so two Denory refresh cycles I'ould occur in thls case.

The menory refresh ls done fast enough !o nake up for the lost cycLes
tn the hlgh resolutlon rnodes. Once rnenory refresh slarts or a 1lne, lt
occurs every four cyclea unless pre-enpted by Dl4A,

A11 lntelrupts reach the 6502 near rhe end of horizontal btank.
Wlth standard o! narrow screen lrldths, refresh DMA starts after the end of
horlzontal b1ank.

The time at which ANIIC does cycle stealing ls deterndnlstlc, but

depends on the graphics node, screen {1dth and nhether or not horlzontal
scrolling 1s enabled. Horizontal scrolling reqrtres extra graphtcs data:
see I{SCRoL.

ANTIC does horlzontal scrolllng of an even rllnber of color clocks by

delaylng the tlne at which 1t DMA'S the data. To do an odd nunber of color
clocks (which lnvolves half of a nachtne cycle), ANTIC has a one color clock
inlernal delay.

Theoretlcally, it ls possible to write a program vhlch changes graphlcs

or colors rron the flyi, t.e. during the nlddle of a TV llne. Iiowever,
I'lth all the DMA going on, rhe cycle counting gets to be qulte conpltcateal,
ard ls beyond the scope of thls roanual.

There are a mlnber of delays assoclated with the display of graphtcs.

These occur in the ANTIC and the CTIA, The ANTIC sends data to the CITA
which adds in lhe color infornatlon. Thus the rlnlng for changing colors on
the fly is dlfferenr fron that for changtng graphlcs on the f1y.

II.2I
 Itortzontal Blank DUA Tlntne

When DMA ts enabled, cycles are slolen at the tiEes shown belol'.
End of
Lprevrous+l Horlzontal BIank_____J
ll,lne | |
20 nachtne cycles (40 color clocks)

-_
.r - v^ tr e r-r e s n
cycres.
char, and graphlcs
I,ISYNC dara DMA (depends on
orr.hl. m-,{ c )

Interrupt
Address DMA (3-byte dlsplay llst
lnstrucrion)
Player
Dlsplay 1ls t lnstruction fetch DMA
Mlsslle Dl,{A

Cycle Countlnq Exanple: fhis exar0ple uses the 40 char:acter by 24 l1ne

dlsplay l1st given on page II.24. This dlsplay lisr 1s 32 byres long so
dlsplay list DI,IAtakes 32 nachlne cycles. It takes 960 cycles to Dl'lA rhe
characters and 8*960 to DMA the characrer da!a. The refresh DMA takes 9
cycles for each of 262 1ines, except for the 24 tines wnere the characters
are read, where only I refresh cycle occurs.

DMA descrlptlon Machine cvcles

dtsptay llst 32
chalac!ers 40x24 = 960
character data 950x8 =7680
refresh 262xe-24x8 =!!!!
!ota1 1 0 8 38

Thus tbe total DMA per frane ls 10838 nachine cycles. one fraroe
1s 262 llr\8 with 114 machlne cycles per ltne for a total of 29868 nachtne
cycles per fraDe. Thus 362 of each frarne is required for DMA tn 0S graphlcs
node 0.

NTSCvs. ?Al, Svstens: There axe tr^roverslons of the ATARI 800: the NTSC
(Untted States T,V. slandard) and PAI- (one of the European T.V. standards).
The PAL systeu has been destgned so that mosl programs wlll lun wlthout
belng modlfled. Ilowever, sone dlfferences nay be notlceable. There 1s a
hardtrare reglscer (PAL) vhich a progran can read to deternlne which type of
system lt Is runnins on and adjult;ccordlngly.
 The PAL T.V. has a slo\rer frame rate (50 Hz. instead of 60 t{2.) so
gaues lflll be slot'er irnless an adlustneflt is oade. pAL has roore T.V.
..__ 1lnes per frax0e (312 lnstead of 262r. T\e Arart 800 harilr,rare cordpensates
-
fot thts by adding extra 11nes at the beglnnlng of vertlcal blank. Display
llsts do not have to be altered. llor,rever, thelr actual vertlcal heisht \1111
be shorter. PAL ATARI 800 colors are simtlar to NTSCbecause of a hardware
nodlflcetlon.

B. POIGY

Audlol Ttere are 4 seni-tndependent audlo channels, each lrith its o\rn
frequency, nolse, arld volune control. Each has an 8 b1t "dlvtde by Ni,
frequency dlvider, controlled by an 8 blt regtster (AUDFX). (See andlo-serlal
port block dlagran.) Each channel also has an 8 btt conrrol regtster (AUDCX)
\rhlch selects the tlolse (poly counler) conrent, and the volune.

Irequetcy Dlvlders: A11 4 frequency dlvlders can be clocked slmrltane-

ously fron 54 KHZ or 15 KHZ. (AUDCTLbtt O). Ire$ency dividers I and 3
can alternately be clocked from 1.79 MHZ (AUDCTLbits 6 and 5). Dlvlders 2
and 4 can alternately be clocked \di!h the output of dividers I and 3 (AUDCTL
blts 4 and 3). Thls a11on6 rhe followlng oprlons: 4 channels of 8 bits
resolutlon, 2 chanrels of 16 btt resolutlon, or I channel of 16 btt and 2
channels of 8 blt.

Poly Nolse Cou[ters: There ale 3 polynoEial counters (17 b1t, 5 btt
and 4 blt) used !o generate random nolse. The 17 btt poly counter can be
reduced to 9 bils (AUDCTLblr 7), These counlers are ;11 clocked by 1.79
MEZ. Thel! outputs, however, can be sampled tndependently by the four
audlo chamels at a rate detelnlned by each channel,s frequency dlvlder.
Thus eech channel appears ro contatn separate poly counters (3 types)
clocked at lts olrn frequency. Thls poly counter noise saopllng is controlled
by blts 5,6 and 7 of each A1IDCXregtster. Because the poly counters are
senpled by the 'rdlvtde by N[ frequeocy dtvldet, lhe output obvlously cannot
change faster than the saopllng !ate. IIr these nodes (poly noise outputted)
the dlvlders are therefore acting asirlow pass,'filrer clocks, allo\rlng only
the low freqrency noise to pass.

The output of the notse control circult descrtbed above conststs of

pure tones (sqrare rrave type), or polynonlal counter noise at a rnaxlurE
frequency set by the ridtvide by Nri countet (1o\r pass clock). This output
can be routed through a high pass ftller 1f desired (ALIDCTLblts 1 and

rr.23
Audio Nolse tr1lters:

trreqrelrcy
Notse

Frequency

Any chanflel nolse output (vtthout htgh pass fllter)

voL

chennel ,) fctaonet t
- b y N o' "
lL-
I
v

f!equency

Chendef I output (wLth high pass f11ter)

(or3&
-bvN
,J
channel ;\

Freqtrency

Chamel 2 output (!?-lth blgh pass filter)

Clock
 Elah Pass Fllters: The htgh pass filter conststs of a "D'r fllp flop
attd an elcluslve-OR Gate. Ihe noise control clrcult outpu! ls sanpled by
thls fltp flop dt a rate set by the "Aigh Pass" c1ock. The input and output
of the lllp Flop pass through the excluslve-oR Gate. If the fllp flop lnput
ls changing mrch faster than the clock rate, the stgnal !1111 pas8 easlly
through the excluslve-OR Gate. l{owever, lf lt is Lower tha[ the clock ra!e,
the f11p flop outpul w111 tend to foUow the loput and the two excluslve-oR
Gate lnputs lll1l nostly be tdenttcal (ll or 00) gtvtng very 11!t1e drtput.
Thls glves the effect of a crude hlgh pass fllter, passhg nolse whose
olnftolid frequency 1s set by the htgh pas8 clock rate. Only channels
I and 2 have such a htgh pass ftlter, The hlgh pass clock fo! chatlnel I
cones fro.n the chanfle] 3 dlvlder. The hlgh pass clock for channel 2 cones
froo the channel 4 dlvider. Thls filter 1s lncluded ooly if bit I or 2 of
AIIDCTL ls true.

J9Jtg9_994!gf: A volune control clrcult ls placed at the output of

each chennel. Thls ts a crude 4 blt dlgltal to analog coDverter that
allons selectlon of one of 16 possible oltput current 1evels for a loglc
true audlo lnFrt. A loglc zero audlo ltlput !o thls volune clrcul! al\rays
glves an open clrcult (zero current) outputt The volulle selecllon 16
codtrolled by bits 0 thru 3 of AUDCX. "voluxoe control on1y" node can be
lnvoked by forcing thls clrcult's arrdlo input true l.lth blt 4 of ALTDCX. In
thla mode the dlvldels, nolse counters, aod fllter clrcults are all dlscoo-
nected fron lhe chaIlnel outpu!. Olrly the volune control blts (0 to 8 of
AUDCX) determlne the channel output current.

The ardlo output of any chennel can be conpletely turned off by wrltlng
zero to the volude control blts of AUDCX. A11 ones slves rnaxfid]n volur0e.

c. SERIA]- PORT

The serlal port coflslsts of a serlal data output (transolsslon)

1lne, a ser1a1 data lnput (recetver) 1tne, a serial output clock 1lne, a
bl-directlonal serlal data clock 1lne, arld other rolscellaneous control lines
descrlbed ln the operatlng Systen Manual. Data ls transDltted and recelved
as 8 btts of serlal data preceded by a logic zero start bit, and succeeded
by a logtc true stop btt. Irput and outpu! clocks are g$g! to lhe baud
(blt) ra!e, not 16 tines baud rate. Transnltted data changes qrhe[ the
oulput clock goea true. Recelved data ls sanpled rhen the lnpu! clock goes

Sg4e1_9.g!!g9: Ttre transElsslon sequence beglns lrtlen the processor

\alrltes 8 blts of peralle1 dara into rhe serial output register (sERoUT)(see
audto and sertal port block diagran). vhen any previous data byte trens-
nisston 1s flnlshed the hardware a'111 artonatically transfer new data from
(SERoUT) to the oltput shlft reglster, lnterrupt the processor to lndicate
an empty (SERoUT) reglster (ready to be reloaded wtlh the next byte of
data), and auto!0attcally serlally transnl! lhe shlft reglster contenls ltrlth
start-stop b1!s attached. If the processor responds to lhe interrupt, and
reloads SERoUTbefore the shlft reglster 1s conpletely transnltted, the
serlal transnlssion w111 be soooth and contlnuous.

r1.25
 Output data ts nornally transnitted as loglc leveLs (t4v=lrue ov=Fatse).
Data can also be transmirred as two lone lnforDatlon. Thls rdode ls selected
by bit 3 of SKCTI-. In rhls node andlo chanoel I 1s transroitled 1n place of
loglc true, and audlo channel 2 1r place of togic zero. channel 2 mlst be
the lower tone of the tone Pair.

The processor can force the data outpu! ltre to zero (or to audlo
channel 2, lf 1n two rone node) by settlng btt 7 of sKcTL. Thls 1s requlred
lo force a break (I0 zeros) code tlansolsslon.

Serial Output Clock: The serial output data always changes when the
serlal output clock goes true. Tte clock then returns to zero 1n the cente!
of the output dara blr tlne.

The baud (bil) rale of the data and clock i3 deternined by audlo
channel 4 audio channel 2, or by the lnput cLock' dependtng on the serlal
dode selected by btts 4, 5, and 6 of SKCTL. (see charl at end of thls

SSJjg!_!.!!g.!.: The recelvlng sequence beglns vhen the hard\rare has

received a conplete 8 blt serlal data i^rord plus start and stop blts. This
data ls autoroatically transferred !o the 8 bit paraLlel input teglster
(SERIN), and the processor ls lnterrupted to indlcate an input data byle
ready to read ln SERIN. The processor nust respond to thls lnterrupt' and
read SERIN, before the next lnput dala vord receplion is coaplete, olherwise
an input data nill occur. This over-run wtll be tndtcated by btt
5 of SKSTAT(if bit 5 of IRQST is not RESET (true) before next lnput conplete) '
and neans input data has been lost. Thls blt should be lested whenever
SERIN ls read. Blt 7 of SKSTATshould also be rested to detec! frame errors
caused by extra (or nlsstng) data bits.

Direct Serlal Input: The serial data lnput line can be read directly
by the rnlcroprocessor 1f deslred, ignoring lhe shlft reglster, by readtng
b1I 4 of SKSTAT.

Bt-Direclional Clock: This clock ltne is used lo elther recelve a

clock fron an external clock source for clocking iransnitted or recelved
dala, or is used to supply a clock lo e).texnal devlces indlcatlng the
transnit or receptlon rate. This clock llne d1lectlon is deternined
by the serial rnode selected by bils 4, 5, and 6 of SKCTL. (See node chart
at the end of this section.) Transaitted dala changes on the rislng edge of
thls clock. Recelved data 1s sadpled on the lfalling edge of thts clock.

Asvnchronous Serlal Input: Unclocked serial dala (at an approxlllately

known (+5%) rate) can be received 1n the asynchronots modes. The recelve
(input) shift reglster is clocked by audio channel 4. channeLs 3 and
4 should be used togelher (AUDCTLbit 3 = l) for lncreased resolutton.
In asynchronous nodes, channels 3 and 4 are teset by each start blt at the
beglnning of each serial data byte. This allows the serial dala rale to be
sl lghtly different from the rate set by channels I and 4.
 Serlal Mode Control: Thete ate 6 useful rnodes ( o f t h e p o s s i b l e 8 )
cortrolled by bits 4, 5, and 6 of SKCTL. These are described on the next
page.

Note that two lone output (bit 3 of SKCTL) Eay be used 1n any
. of these
nodes except for the bortoE pair. Thts is because channel 2 is
cne output lransntt rate and 1s therefore nor available for
one

Note that the output clock rate is tdentlcal !o lhe outpur dara rare.

Mode Control

Force Break

p 7l p 6l p sL D 4
l D 3l D 2l D rI D O S(CTL REGISTER

Pot scan and keyboard CTRL

Two Tone Control

Mode Control Blrs A-asynchronous

Q"t I o"t I r n l B1-Dir

D4 R a t c1o
trrans. & R.".in; ;;i;;-;;ali
linput lexternal clock. Also lnrernal
lock phase reser to zero.

I chan Trans. rale set by external

lext I l 4 I lnput lcfock, Receive asynch. (ch. 4)

t l lTrans. & Recetve b v l

l c h a nI 4 lChan. 4. chan. on 81- I
4 Direc clonal clock ttne.

cr{4 | CII4 cI{4 Not Useful

lTrars. R a t e S e t by Chan. 4
1 4 l4 lnpu t lRecelve Rate by External
C1ock.

lr lcn4 | cH4 CH4 lNot UsefuI

lcran I ctran Chan Chan lTrans. rate set by chan.

1 2 | 2 2 lRecleve rate se! by chan.
0rrI 4 out on B1-Dlrect. CIo

Input lTrans. Rate set by Chan. 2. Re-

Chan Chan lceive async. (chan 3&4) Bi-Dir.
2 4 lClock nor used (Tri-srare

ft'o lone (bit3) not useable ln these nodes

11,27
D. INTERRUPTSYSTEU

There are t\ro baslc types of lnterrupts deflned on the r0lcroprocessori

NMl (non naskable lnterrupt) and IRQ (lnterrupt request). It is recoomended
rhar a rhorough understanding of these inter.rpt types be acqulxed by
reading all chapters concernlng lnterrupls in the 6502 microprocessor
progranmi ng and hardware manuals.

In this systern NMI interrupls are used for video dlsplay and reset.
IRQ lnterrupts are used for serlal porl com'rnlcatlon, peripheral devlces,
tlners, and keyboard inputs.

NMI Interrupts.: Even though NMI lnterrupts are "unrnaskable" on

lhe nicrptocessor, this systeE has interrupt enabLe (:nask) bits for NHI
function. (Blts 6 and 7 of NMIEN) t{hen lhe€e blts are zero NMI lnterrupts
are dlsabled (nasked) and prevented fro![ causlng a xoicroprocessor NUI
interrupt. (see NMIEN reglster descrlptlon) The 3 types of NMI lnterlupts

1. D7 - lnstruction lnterrupt (ftrrlng dlsplay ttrtre any dlsplay

lnstructlon wlth blt 7=1 w111 cause thls lnterlupt to occur
(if enabled) at lhe star! of the last video line dtsplayed by
that instructlon. )

2. D6 - Vertical Blank Interrupt (lnterrupt occurs (if enabled) at

rhe beginning of the vertical blank rime interval.)

3, D5 = Reset Butron Interrupt (pushtng rhe SYSTEMRESETbutton lfi11

cause thls interruDt to occur,)

Slnce any of these lnterrupls rtrlIl cause the processor lo Jurnp to lhe
same NMI address, lhe syslen also has NMI status blts rrtich nay be exantned
by the processor to deterrnlne whlch source caused the NMI lnterrupt, Blts
5, 6, and 7 of NMIST serve this functlon (see NI1IST register descrtptlon).
These status blts are set by the correspondlng lnterrupt funcllon (even tf
the loterrupt 1s Easked fron the processor by NMIEN). The status bits toay
be reset logether by wriling to the address NMIRES.

Tno of the lntelnrpt enabLe blts (blts 6 and 7 of NMIEN) are cleared
autornatlcally durlng sysren po!/er turr oo and therefore these NMI internrpts
aie inilially dlsabled (nasked), preventing any pover turn on servlce routlne
fron being lnte.rupted before proper lnltiallzatlorl of reglsters and polnlers.*
They can then be enabled by the processor nheneve! deslred, by wrltlng lnro
blts 6 and 7 of NMIEN. Except for the reset button lnterrupt, they can also
be dlsabled by the processor by writing a zero lnlo bits 6 or 7 or NMIEN.
The reset button cannot be dlsabledj allowing an unstoppable escape from any
posslble "hangup" conditlon.

These NMI lnterrupt functlons are each separaled ln tlne (to prevent
ovetlaps) and converted to pulses by the systeo hardware, in order to supply
N M Tt r a n s l r l o n s r e q u i r e d b y t h e n t c r o p r o c e s s o r I o g t c ,

* - NOTE: Blt 5 1s never dtsabled and therefore the Reset Button

should not be pressed durlng pover turn on.

r1.28
 _ -
IRQ Tnterrupts: IRQ lnterrupts are a1l "naskabte,' together by one blt
of rhe sratus teglster on the mictoprocessor. This blt is se! ro the
dtsable condltton autonatlcally by power turn on !o prevent tnlerrupt of
power Eurn on service rortines.*r. In addltlon to thts processor IRQ mask
bit, there are separate systenr IRQ lnrerrupt enable blts for each IRQ
lnterrupr functton (blts 0 thrll 7 of IRQEN). These btts are not tnltlalized
by porrer turn on, and rorsr be inttlalized by rhe progran befoie-enabling the
processot IRQ. The I rypes of tRQ tnterrupts are:

D7 = BREAKKXy (depression of rhe br€ak kev)

D b = O T H E RK e y { d e p r e s s i o n o f a n y o t h e r k e i )
D5 = SERIAL INPUT RXADy (Byte of serial data has been recelved and is
ready !o be read by the processor tn SERIN leglsrer).
D4 = SERIAL OUTPUTNEEDED(Byte of serial data is being rransnlrrect and
SERoUTis ready to be lrritten to agatn by the processor).
D3 = TR-ANSMISSION FINTSEED(serlal data transnission 1s flnlshed,
Ourput shift register is enpry).
D2 = TIMER #4 (audio dlvider /14 has counred dol''n to zero)
Dl = TIMf,R /12 (audto divider 12 has counted dol',n to zero)
D 0 = T t M f , R/ i t ( a u d i o d i v i d e r 4 t h a s c o u n r e d d o & n t o z e r o )

In addition ro the above IRQ inrerrupts (enabled by blrs 0 through 7 of

IRQENand ldenrtfied by stalus btls O rhru 7 of IRQST) ih"re u.. cwo *o.e
syslen IRQ lnterruprs lrhlch are generated over the serlal bus proceed and
Interrupr lines.

D7 of ?ACTL = peripheral "A" tnte(rupt

status bit
D0 of PACTL = pertpheral 'tA" tnrerruDt
enable blt
D7 of P B C - L- Dertpherat ',S', internrpt
srarus bit
D0 of ?BCTL = peripheral ',B" lnrerrupr
enabte blr

These last tvo interruprs g!9 auronatically dtsabled by powet Eurn on,
.
and thelr starus blts are reset by readtng fron porr e reglster and port B
register. (See PORTA,PACTL, P0RTB, and PBCTLRegister descrlptions,)

The IRQEN reglster, like rhe NMIEN regtsrer, enables lnterruprs

when lts birs are I (logic rrue). The IRQST horever (unllke rhe NMIST) has
inlerrupt status bits thar are normally logic rrue, and go !o zero ro
lndicale an interrupr reqresr, The IRQST status bits ar; reEurned to logic
true only by llrlring a zero into rhe corresponding rRQENblr. This I't1l
dlsable the interrrlrpr and simrltaneously set the intetrupt sratus bi! to
one, Bit 3 of IRQST ls nor a tatch and does nor ger rese! by interrupr
disable. It is zero "hen rhe serlat out rs empty (our ftnt;hed) and true
\rhen it is not.

*x - NoTE: An NMI also disables the I bit.

II.29
 INTERRUPT SI]MMARY

STATUS
NAME TUNCTIONS ENAB]-E STATUS RESEl
I
I ulsPray NMIST Address
NMI llnstructlon (Bits 6 rhru 7) (Blrs 5 thru 7) NMIRES
INTERRUPTS
IJ9!9: g]3gL NorEally Zeio NornaUy Zero (Resets all NMI
lReset Button (Dtsabled) | (no lnlerruot) lstatus toeether)

KEYS IRQEN rRQST Reset (to rme)

Serlal (Blts 0 rhru 7) (Bits 0 thru 7)
.P.g.!!e Noroally True Correspondlng
Tlners (Dlsabled) 't (no interrupl) Bit of IRQEN
I | | (except Blt 3)*
IRQ I
INTERRU?TS Perlpheral I D0 of PACTL I D7 of PACTL I Reset by
A lNormally Zero lNorrnally zero I Reading PoRT A
| (Dlsabled) l(no interrupt) | Restster

Perlpheral I D0 of ?BCTL I D7 of PBCTL

B lNornally Zero lNornalLy zero Reading PoRT B
| (Disabled) l(no lnterruDt) | Resister

E. CONTRO1LERS

A varlety of controllers can be plugged into the four jacks on the

front of the console. Thts includes joysttcks, paddle (pot), twelve-key
keyboard, and ltght pen (when avallable).

T h e c o n t r o t L e r p o r t s a r e r e a d L h r o u g h t h e P O R T Aa r d P O R T Br e g i s e r s
and the PoT a{d mIG regtsters. The OS reads these registers doring
vertlcal blank and slores lnto its own RAM locatlons. These are STIC(,
PADD1othrough PADDLT, PTRIG'S and STRIG'S. The OS sets up PORTAAND
PoRTBfor inpur. Thts is done by settlng PACTI-or PORTB(Port Control)
blr 2 ro a 0 (to seleci the dlrectlon control register), then lJrlrlng all
0's to the destred port. PACTL (PBCTL) b1r 21s then changed back to
a I, allo$.'1ng the progrard to read fron the porl. The ports can aLso be
set up for outpu! by \rrirlng 1's instead of 0's whtle the direcrion control
mode is selected.

.I9J9!f9E9: The joysttcks have four s\rltches, one each for righl (R),
left (L), back (B) and foruard (F).

These swltches are read thlough PORTAand PORTB.A fifrh swltch is

actlvated by presslng the red t!1gger button. The trigger buttons are
read fron TRIC0 through TRIG3. A value of 0 indicates that a button has
been pressed and a I indicares rhat it has not been pressed.

II.30
 The IRIG reglsters are trorroally read directLy, bul they can be used
ln a latcheil oode. wrltlng a zero to btt 2 of GItAcTl- dlsables the latches
and sets them to 1. Wrltlng a I to bit 2 enables the latches' If a joy_
stlck trlgger button ls pushed al any ttne Ithlle bit 2 of GMCTL is I
the latch value r'l1L change to zero and stay that qay. A Progran can
use th13 to deterrdne whether the joystlck trlgge! buttons have ever been
pressed durlng a certain perlod of tiEe.

?addles: The paildles cone ln palrs, so elght paddles can-be connected

to th;=;I jacks. The paddles are read bv storlng lnto PoTGO' then
readlng lhe tOT registers at least 228 llnes later. The values range fron 0
(wrth;he paddle turned Lo the rlght) lo 228 (Paddle turned counter-clockrlse) '
The value lnallcates how dany TV llnes 1l takes to charge up the capacllor
rhlch ls the serles \.ith the potentioneter. Turnlng lhe knob to Lhe righl
lo\.ers the reslstance, so the capacitor charges up qllckly' l\rnlng the
knob to the lef! lncreases the reslstance and the charging tlme' The
capacltor ilunp translstors are used to discharge lhe capacltors so !ha! a
nev readlng can be rnode. The POTCOcommand clears the counters and lurns
off the du;p translstols to allow the capacitors to charge up' The ALLPOT
reglster contalns ofle blt for each paddle. l]hen the capacltor has charged
up to lhe threshold value the AJ,LPOTblt changes fron one to zero and the
tOt reglster conlains the corlect readings. Blt 2 of SKCTL (Serial Port
Cootrol) enables fast pot scan. In thls node, lt takes only lwo scan llnes
to charge up the capacltors to the maxllffln 1eve1 lnstead of 228 lines' Btt
21s flrst set !o O lo durop lhe capacitors. Then Bit 2 is set to I to start
the pot
-2 scan' The fas! pol scan is not as accurale as the nornal scan t0ode'
Btt of SKCTLrfirst be set to O to use nornal scan mode' 0ther\tlse' the
capacltors wlll flever dunP. Note !ha! soue paddles have a range srnallel
rh;d O to 228 due to illfferences ln the pots. The left and rlght paddle
trlggers for each paalille palr are read fron the left and right bits for the
correspondhg joystlck (PORTAor PORTB).

Kevboard Co[trol1ers: Each keyboard controller has a lwelve-key pad

and pLugs lnlo a joystlck controller pott. The flrst slep tn using the
teytoara ts to select a ron by settlng the port dlrectlon to output and
tn itrng . 0 to the blt tn the PORTA or ?ORTB reglster iThlch selects lhe
deslred low (see PORTA, SECTION III). The other rots should have l's
are read lhrough lhe POT and TRIG registers (see
wrltten !o then. Colur0ns
controlLer PORTPlNoIn ahart ln sectlon rll). Appendlx fl of the BASIC
Reference Manual contalns a Baslc plograro uhich reads the controllers' The
flrst and seconil colunns of the keyboard use the sane plns as the pots for
lhe padtlle conlro1lers, so they are read by readlng the PoT (or PADDI-)
reglsters. Whe[ a bultofl is prished' the pot line is grounded' so lhe po!
capacltors never charge up !o lhe threshold Level and lhe reading ls 228
(tire rnaxiurn). When the button 1n lhe selected lolr and coluEn is not pushed
the capacltor ls connected to +5V through a relatively sBall reslstor'
glvlng a POT value of about 2 (thls rnay vary). Since the readlng 1s not
crltlcal, the fast pot scan mode can be used, 3o that only a 2 Une wait 1s
reqrired between selectlng the rol' and reading the POT reglster' The
co;ventton has beefl adopled of cor0parlng the POT readlog wlth l0 (declnar)'
If ls lt greater lhan 10 then the bullon has been pressed' The thtrd
colunn ls read through lhe loysttck trigger ltne, so i! \torks just ltke a
( 0 = b u t ! o n ls pressed, I=not Pressed) .
loysrick trlgger

II.31
 Llahr PerI: A llght pen ts a device rhat can detect the electron beaD
as lt sweeps across the TV screen. It 1s irsed to polnt dlrectly at an irnage
on the TV display. Appltcatlons hclude selecting memr ltens and drawlng
l1nes. Tte ATARI 400/800 hardware was deslgned so that a light pen can be
pfugged lnto any of the joystlck controller porte (see ena if sectron
III).

m:" any one of the joystick rrlgger lines (pln 6) rs pul1ed 1or, the
.---
ANTIC chlp takes rhe current VCOI]NTvalue and st;res tt in PENV. The
horlzofltal color clock value (0-227 declnal) is storect 1n pENt{.
The teast
slgnificant blt ls inaccurate and should be lgnored. Slnce there are a
nuober of delays lnvotved 1n dtsplaytng the alata and changing the ltghr
per! register, eech systeE mrst be cal brated. Softr"rare irhtch uses the
l1ght pen should contaln a user-tBteractlve caltblatlon routlne. For
exanple, the user could pol[t the Ught pen at a crosshalt tn the center
of-the screen and the progran could coruFnrrethe requtreil horlzontal
offset.
PENHwt1l wrap around fton 227 ro O near the rlght halld edge of a
statdard
width dlsplay because of lhe delay. fhe pen rd11 not l'ork lf 1t 1s polnted
at a black area of the screen, slnce the elecrron besn is turneal
oif. It ls
a good ldea to read t\ro (or nore) values anal average then, slnce
the user
rsll1 probably not hold the pen perfecrty sready.

TI.32
 I1I. HAR)WAREREOISTERS

Thls sectlon 1lsts the hardware registers and operatlng Systen (OS)
shadow reglsters.

In the fo1lo\"dng descrtptions, tme ahrays refers to a btt \'rhose value

1s l.

A. PAL (D014)

Not I D3 | D2 | DI lNor
U s e d l l l l u s e d

D3 D2 D]

I I I NTSC (US TV)

0 0 0 PAI- (European TV)

Thls byte can be read by a prograrn to deternlne edlch lype of systeE

the progran ls runnlng ofl.

\-- B. INTERRIJPTCONTROL

NMIEN (Non Maskable Interrupt tnable)(D408): Thls address wrltes data

to the NMI lnlerrupt enable blts.

0 = dlsabled (dasked)
I - enab led

I Nor
Used

D7 Dtsplay l,tst Instrucllon Interrupt Enable. This blr is

cleared by Power Reset, and nay be set or cleared by lhe
plocessor,

D6 Vertlcal Blank lnterrupt Enable. This blt 1s cleared by Po\rer

Reeet, and roay be set or cleared by lhe processor.

SYSTEMRESETBulton lnterrupt

This lnterrup! ls always eflab1ed. The SYSTEI{RESET button should

no! be pressed alurlng power turn on.

(ser ro hex 40 by os IRQ code.)

1r1.1
 NUIST (Non Maskable Interrupr Status)(D40F)! Thls address read the NMI
Status Reglsrer (Read by OS NMI code).

0 - no intelrupt
I = lnterrupt

I Not
D7 D6

D7 This btt ldenttfies an Nl,Il lnrerrup! caused by btt 7 of a

Dlsplay List hstructton.

D6 Thts blt ldentlfies an NMI inrerrupt caused by the beglnnl'tg

of vertlcal blank-

D5 This blt ldenttfles arl NMI lntetruDt caused b\/ the SYSTn1
RESETbutron.

NMIRES (NMI Status Reqtster Reset)(D40F): Thls wrtte address resets

the Non Maskable Interrupr Status Regtster (MIST).

Not
Used

( Wrttten by OS NMI code.)

IRQST (IRQ lnrerrupt Status)(D20E): This address reads the dala fron
the IRq Interrupt Status Reglster.

0 = Interrupt
I - No Inlerrupt

D5 D4 D3 D2

D7 = 0 Sreak Key Inlerrupt

D6 = 0 Other Key Intertupt
D5 = 0 Serial lnput Data Ready Tnterrupt
D4 = 0 Serial Ortput Data Needed Interrupt
D3 = 0 Serlal Outpur (By!e) Transntssion Finlshed fnterrupt *
D2=0 Tiner 4Interrupt
Dl-0 Tlner 2 Inrerr:upt
Dn=n Tlnor I T^ra?r,,-r

* - NoTE: Used for generation of 2 stop blts, See IRQ descrlptlon

ln sectlon II (no dlrect reset on btt 3).

IAI.2
 IROEN lqcerrupt EnabIe D20E): Thls address wriles
Interrupt data to the IRQ
Enable

0 = dlsable, correspondtng IRQST blt is se! ro I

\7 Break Key Interrup! Enable

D6 other (ey Interrupt Enable
D5 Serlal Input Data Ready Inlerrupt Enable
D4 Serlal 0utput Data NeedealInterruDt Enable
D3 SerlaI 0ut TransElsslon Elnlshed interrupr Enable
D2 Tlner 4 Inrerrupt Enable
DI Tlner 2 Interrupt Enable
DO TlEer I Interrupt Enable

OS SIADOW: PoXMSK (hex lO)

U€e AND'S and OR's to change one bit tn pOre,ISK

. wilhqr! affec(ang
-
the olhers. Store the ilesired ialue tn both IRQEN and pOruSK:

c, TV LINE COMROL

Vertical Cqunter) (D4OB): Th{s address reads

the Vertlcal TV
Llne Counter nost slgDlflcanr btts).

V0 not read.
v8 17 v6 v3 \2 vl V0 Tlro llne
resolutlon
supplted.

1 "a".a "f

Thls address sets a latch rhat pu1ls down on lhe

Rny llne to the
Dlcroplocessor' caislnS 1t to nalr until thrs latch is autordaticafly
by the beglnntng of horlzontal b1ank. Dlsplay reset
fr"t i"t.r*ptr'."v U.
delayed by 1]lne 1f wSyNCts used. ([sed by OS t"yt"".i .ii"t-ro"ti"..t

II1.3
D. GRAPHICSCONTROI.

Dl.tAcTL(Dlrect Medorv Access Control) (D400): This address nrites data

lnto the DMA Control Register.

Not I
Used D5 D4

D5 = I Enable lnstruction fetch DMA

D4 = I I Llne P/!l resolutlon

D4 - 0 2 ltne P/M resolutlon

D3 = 1 Enable Player DMA

D2 = t Enable Mtsslle DI,IA

D1,D0 = 0 0 No Playfteld DI'IA

= 0 I Narror Playfteld DI,IA

(128 Color clocks)

= 1 0 standard ?layfleld n4A

(160 color clocks)

= I I Wlde ?layfteld Dl4A

( 192 Color clocks)

See GRACTL. 0S Shadow: SDMCTL(22F) default value hex 22

GMCTL (Graphlcs Control) (D01D): Ttls address \trites dats to the

craphlc Corllrol Reglster.

N o t l l l
Used D

D2 = | Enable latches on 1'RIG0 - TR1G3 tnprts (latches are

cleared and TRIG0 - TR1G3 act as normal lnputs a'hen
control b1t 1s zero).

Dl = I Enable ?1ayer DMA to Player Graphlcs Reglsters.

D0 = I Enable Misslle DMA to MlBslle Graphlca Reglsters.

DMA ls enabled by setthg blts in bolh DMACTLand GRACTL. settlng

DMACTI-only wtll xe'sult ln cycles betng stolen but ro displsy k{11 be
eenerated.
 cflAcTl (character control) (D401): This address \rrltes data lnto the
Character Control Reelster.

Not I
Used D2 DI DO

D2 Character Vertlcal Reflect Blt. Thls blt ls sanpled at the

bepinninp of each line of characters. If true l! causes the
line of characters to reflect (inverr) vertically (for upstde
dofir chalacters).

Dl Character Video Inverr llae (used for 40 Character Mode

only). If bit 7 of character code is true thls flag causes
that character to be blue on lrhlte (lf nornal colors are
white on blue).

D0 Character Blank (Blink) Flag (used for 40 Characrer Mode

o$ly). If bit 7 of charecler code ls true this flag causes
lhal character !o b1ank. Blinklng characters are produced by
setting bit 7 of the characters to I, then perlodlcally
changing D0 of CMCTL.

OS SfiADO : CHACT (2F3)

DLISTL( Displav List Low )(D402): This address writes data lnto thc
1o!, byie of the Dlsplay Llsl CounEer.

I 0 ,List
\ counter
lBtt
oS SHADOW: SDr,sTL (hex 230) (Posrtlon,

DLISTH (Displav List Hish) (D403): This address wrltes data into the
high byte of the Dlsplay List Counler.

D TI D 6 I D D 4I D 3 I D 2

15 t4 t3 t2 TI 10 9 8 f?lserav
\ co'lnrer
lBit
\?os1t1on.
OS SHADOW: SDLSTH (}TEX231)

The Dlsplay l-1st ls a llst of display lnstructlons in memory. These

lnstructlons are addr essed by the Display List Counter, Loadtng these
regisrers deflnes the address of the beginnlng of the Display List. (See
sec!1ons I and Il, )

Not€: The top 6 birs are latches only and have no count capabll1ty, therefore
lhe displav llst can not cross a lK bvte nenorv boundarv unless a lunD
instructlon ls used.
 DLISTL and DLISTIi should be changed only during vettlcal blank or arllh
Dl4A dtsabled. Other:rlse, the screen nay ro11. Bit 7 of NMIENr(rs! be set
in order to recelve dlsplay list lnterrupts.

@: Thls address writes

data lnto the Character Address Base Register. The data specifies lhe nost
slgnlflcant byte (MSB) of the address of the deslred character set (see
sectlon l1), Note lhat the last I or 2 btts are assuroedto be 0.

40 characrer Modes

CI{BASE

Base Address Char Nane

20 Character Modes

CIIBASE

12 |lt [0

Base Address Char Nane Llne Counter

oS SHADoI,J: CHBAS (2F4)

PIfBASE(?1aver-Mlsstle Address Base Reeisler) (D407): Thls address

l'rltes dala into lhe Player-Mlss1le Address Base Reglster. The data
spectftes the l,tSBof the address of lhe player and .0iss11e DMA dala (see
sectton II).

One Llne Resofution

PMBASE

Base Address Player-Mlsstfe Player-Missile scan

Select Counters

Tl'o Llne Resolution

PI{BASE

Base Address Player-Mlsslle Player-Misstle Scan

Select

II I.6
 HSCROL(florizontal Scrolt Reelste!) (D404): This address L.rltes data
lnto lhe llorlzofltal Sclol1 Reglster. Only playfteld ls scrolled, not
Dlavers and Elss1les.

not used | | | |
D3 D2 DI DO

0 to 15 color
clo.k 'iqht Fhl fl c

The dtsplay ts shlfted lo the rlght by the mrnber of color clocks

speclfted by IISCRoLfor each dlsplay llst lnstruction that contalns a 1 ir
Its ITSCROLFlag blt (blt 4 of lnsrruction byte).

When horizontal scrol1lng ls enabled, nole bytes of data are needed.

For a narro\r playfleld (see DI,IACTL blts I and 0) there should be the sane
nunber of bytes per llne as for standard playfleld \rlth no scrol11ng.
Stun11arly, for standard playfleld use the sane mnber of bytes as for the
wtde playfleld. ror wlde playfleld, there ls no change 1n the nunber of
bytes and background color 1s shlfted ln.

VSCRoL (Vertlcal Scro1l Reslster) (D405): Thls address {rrltes dara lnro
the Vertical Scroll Reslster.

not used I
D2 D1 DO

8 lloe display Eodes

not used I
I

16 llne dlsplay nodes

The dlsplay ts scrolled upward by the rnrroberof lines specified 1r

the VSCRoLreglster for each display l1st lnstruction that coflta1ns a I ln
1ts VSCROLllag btt (bt! 5 of lrlslrucllon byte), The scrolled area rilf
termlnate lrlth the flrst lnstrucllon havlng a zero tn btt 5. (see sectlon
II for Dore detalls).

PRIoR (Prtorirv) (D0lB): This address writes data into the Prlorltv
Control Reglster.

D7 D6 D2 DI DO

D7-D6 = 0 D5
l4rltlple Color Player Enable.
Thls blt causes the toglcal "or" function of the bits of
the colors of Player 0 wlth Player I, and also of Player 2
sith Player 3. Thls perrlts overlapping the poslrlon of 2
pLayers wilh a choice of 3 colors in lhe overlapped reglon.

III. 7
 D4 Flfth Plaver Enable.
This bit causes all mtsstles to assune rhe coLor of playfleld
Type 3. (CoLPI3). thls allovs alsstles ro be posttloned
together with a coomon color fot use as a flfth player.

D3, D2, D1, Prlorltv Select (}tutua1ly Exclustve).

& D0 These blts select one of 4 types of prlorlty. Objects wtth
hlgher prlorlty !,1111appear to nove tn front of objects
n'lth fol'er Drlorltv.

D3=l D0=l

?F 0 Pc.l
t ?F T
PFO
PF] PI J Pr I

l
PO PF2
f PFo P2 l
P 1l i
P I + P5 PFr P3 _l
I
P 2 2l
P l P0-l pF0
P3.J I PI I - i-s
l"o:- Pr'l
a ?F2 | P2 | Pzf PF2
1P1'
* +3 P5 | P3-,1 P3,J + 5
rAr I

!9:g: The use of Prlority blts tn a ',not-exclustve" mode (nore than 1

blt rrue) \rl1l result in objecrs (lrhose prtorlttes are ln confltct)
turnlng B]-ACK ln lhe overlap regton.
EXA],IPI,E:PRIOR code = 1010 Thrs w111 black p0 or pl lf rhey are over
PlO or PFl. It will also black P2 or p3 if they are over ?F2 or
PF3. In the one-color 40 character oodes, the lunlnance of a
plxel in a character Is determined by col,pFt, rQaii'ili! or che
priority. If a hlgher priority player or misslle overlaps the
character then the color ls deterdtned by the player's color.

OS SHADOITI: GPRIOR(26I)

C o L P F O- C 0 1 P F 3( P l a v f i e l d C o l o r ) ( D 0 1 6 . p o l 7 . D 0 1 8 . D 0 t 9 ) : T h e s e
addtesses $.rlte data to the Playfield Color-t-ur0 Reglsters,

D 6I D 5 I D 2 t D l t D 0
(see CoLBK for b l t asslgnnent)

OS SHADOWS: COLORO- 3 ( 2 C 4 - 2 C 7 )

III.8
 Co],BK (Backeround Color)(D01A): This address wrltes data ro rhe
Background Color-Lum Reglster.

Co
Not
D7 D6 D5 D4 D3 D2 DI Used

X x x x 0 0 0 Zero Lunlnance (black)

0 0 I
ETC.
I I Max. Luninance (white)

0 0 0 0 Grey
0 0 0 1 Gold
0 0 r 0
0 0 1 1 Red-Orange
0 1 0 0
0 I 0 1 Purple
0 1 1 0 Purple-Blue
0 r 1 t Blue
1 0 0 0 Bfue
I 0 0 l 1-igh!-Blue
1 0 r 0 Tu r quoise
l 0 r 1 Green-Blue
1 1 0 0
l l 0 1 Ye11ow-creen
I 1 l 0 Orange-Green
l l l l Llght-Orange

- OS SHADOI.I:CoLORa(2C8)

E. PLAYERSAND MISSII,ES

DMACTL, GRACTL, PMBASEand PRIOR also affecr players and nissl1es,

C o L P M o- C O L P M 3( P l a v e r - M i s s i l e C o l o r ) ( D 0 1 2 , D 0 1 3 , p 0 1 4 , p 0 l 5 ) : These
addresses rr.rlte to the Player-Mlssile Color-Lun Registers. Missiles have
.- the salle color-lun as thelr player unless rnissiles are used as a 5th player
(see bit 4 of PRIoR). A 5th player missile gets irs color frorn CoLPI3.

D D3 D2 D1 DO
(see CoLBK for bit assignnents)

OS SHADoWS: PCoLRo- 3 (2C0-2C3)

GRAFPO- CMFP3 (Plaver craphlcs Reslsters): (PO D00p, ?1 p00E, p2 p00I,

P3 D0l0): These addresses r".rlte dara dlrectly into rhe player craphtcs
Reglsters, independent of DMA. If DMA ls enabled then the graptllcs reglsters
I{iU be loaded autonatlcally fron the nenory area specified by PMBASE(see
page II.3).

D7 D6 D D3 D2 DI DO
Lefl R l g hr
Playe! on TV Screen

r11.9
 GRAFM(Mlsslle Graphlcs Reqlsters)O01I): Thls address r^'rltes data
dllectly lllto the Mlsslle Graphlcs Reglster, lndependent of Dl,tA.

I I I
D7ID6 D5 ID4 D3 D2 D 1I D O
L R L R ] - R ] - R

M3 M2 Ml l{0

SIZEP0 - SIZEP3 (Plaver stze)(?0 D008. ?1 D009, P2 D00A, ?3 D00B):

These addresses write data lnto the ?laver Stze Control Reeisters.

N o t l l liorlzontal Slze
used lDrlD0 Register (Player)

0 0 Nornal stze
(8 color clocks vide)
0 1 Twtce Noroal Size
(16 color clocks h{de)
I 0 Nornal slze

I 1 4 Tines Nornal size

(32 color cLocks wide)

Wlth nornal size objecls, each blt in the graphlcs register corresponds
to one color c1ock. Ior laxger objects, each bit ts extended over nore than
one color clock.

SIZEM (Mlsslle Slze)(D00c): Thls address I'rltes data into the ll1sslle
Slze Control Register.

Eorizontal Slze
D7 D6 D5 D4 D3 D2 D1 DO Register (Misstle)
\__\r.--l
M3 M2 Ml MO

0 0 Normal Slze
(2 color clocks \r'Ide)
0 I Twice Nornal Slze
(4 color clocks dde)

I I 4 Tlnes NorEal Slze

(8 color clocks \rrde)

ttPOS?0- H?0SP3 (Player Eorlzontal Posltlon)(P0 D000. ?1 D001. P2 D002,

?3 D003)r These addresses wrlte data lnto the Player Horlzontal Posltlon
Reglster (see display dlagran ln sectlon IV). fhe horizontal positon value
deternlnes the color clock locatton of the left edge of the object. Hex 30
is the lefl edge of a standerd wldth screen. Ilex D0 ls the rlght edge of a
standard screen.

I
7 D6 D5 D4 D D2 D1 DO

III,IO
 .u,- _
swwer
t, ur ouo:.
uj uuu/r; Inese addresses rN.rlte data into the Misslle itorlzontal
Positlon Reglsrers (see ItpOSpO descrlDtion).

D7 I D D 5I D D 3l D 2 l D l

mpL4Y -(yc4LE-!-Uq!4dQ9.!O: rhls a.lclress t'rites dara irto

-- the
v e r t l.c a l D e l a y R e g l s r e r .

I ! | i t - - - - - - _ l
p7tp6 lp5 lp4 lp3 D2
| lDrlDO
P3 P2 ?l PO M3 M2 l,1l MO

VDELAYls used to glve one-Ilne resolutton 1n rhe vertlcal

- po_
sltlonlng of an object when lhe 2-1ine resolutlon dtsplay ts enabled.
Settlng s blt tn VDELAy to I noves the corresponcltng otllct
aown ty one
TV flne.

If player-nlsslle Dl4Ais enabled then chang{ng the vertlcai tocation

of ar oblect by nore thar one line 1s acconpllsied by ,."i"g tii" ._""a
1n the nenory nap. If Dl,tA is dlsabled rhen rhe vertical loiatlon can Ue
set.up by assenbly language code whlch stores data tnto ttre grafhics
reglsters at the deslred line,

M g t E ! - Y I P L - l - \ a 2 P F r . l , 1 3(PMPi s s l ] e . r o p t a v f t e t d c o l r i s r o n s ) ( p O o O , p O O r ,
h
, v^u^ z, . u u u r r : Inese addresses read l,tisstte to playfietd Cotlisions.
A I blt neans that a colllslon has been detected since the last HITCLR.

Not used | | | I
o forced) J p3 L D2 | Dt I DO

Playfleld Type

P O P F .P l P F . P 2 P 3PF (Player t o P 1 efd Colltslons) (D00

p 0 0 5 . p 0 0 6 . p 0 0 7 ) : These addtesses
Player to Playfield Collisions.
Not used | | I
zero torced) | p3 | D2 J Dt I DO

Playfteld Type

MIPI,. M2P1,.M3PL sl1e to r Cofl on) (D008

D00A. p00B): These addresses read Mlsslle lo Player Coltislons.

Not Used I
D 2 D1 0

Player ltunber

POPI. PI P'IPL. P to Plaver ollislons 00c DOOD

D00F): These addresses read Playe r to Player C o l l l s i o n s

Not osed I I I
rorced) lD3 lD2 lDI lD

I 0 Player Nunber
(Player 0 against player O ts always a zero). Erc.

III.lI
 (co1llslon "HlT" clesr) D OI E
IM!B-

Ttls wrlte address clears all colllslon btts descrlbed

Not

I. AUDIO

AUDCTL(Audio Control) (D208): Thls address wrltes data lnto the Audlo
r'roa! C"trt.of r"gr"t.t. {Ll*-"i" SKCTL tro-tone blt 3

7 D6 D5 D D D2 DI DO

D1 Change 17 btt poly inlo a 9 blt below poly'

D6 clock chan$el 1 r'tth 1.79 MHZ, lnstead of 64 relz.
D5 clock Channel 3 with 1.79 }l1lz, instead of 64 Klz.
D4 Clock Channel 2 with Channel 1, lnstead of 64 ].J lZ (f6 BlT).
D3 clock Chamel 4 nilh channeL 3, lnstead of 64 xllz (16 BIT)'
D2 Inser! Ill Pass lllter in Channel I, clocked by chanflel 3.
(See sectlon 11. )
D] Insext l{i Pass llLter 1n Chan$el 2, clocked by Channel 4.
DO Chaflge Normal 64 ICIZ frequeocy, tnto 15 KlZ.

Ee9!-lEgSg!g1es: Tne frequencles glven above are apProxinate. The

Elact Frequency (f1[) that clocks the dlvtde by N counters ls glve[ below
(NTSCorly, ?AL differert).

FIN FIN

t . 7 9 MItZ t.789'19 Use modifled forldrla for fout

6 4 KtZ 6 3 ,9 2 1 0
- Use norDal forlerla for fout
15 15.6999

The Nornal Tornula for output frequency is:

Iour = Fin/2N

where N = The blnary nudber 1r) the frequency reglster (AUDF), plus I (N=AUDF+1).
The MODIFIED FORMUI.Ashould be ssed when I1rI = r.t9 ttltL and a rlore
ls desired:

2 (AIIDF + M)

lihere: M 8 b 1 t counter (AUDCTI-blt 3 o r 4 = 0 )

M 1 6 b 1 t counlex (AIJDCTLblt 3 o r 4 = l )

rll.12
 AUpII. AUpr2. AUpF3.AUpr4 (Audlo Freouencv) (p200. p202. t204. D206)
These addresses lrrlte data lnlo each of lhe four Audlo Freqrency Control
Reglsters. Each reglster controls a dlvtde by "N" counter.

Note: "Nt' ls one gleater

than the blnary nunber
1n Ardlo Irequency
0 0 0 0 0 0 0 0 Reglster AUDF(x).

0 0 0 0 0 0 0 1

AUDCl. AUDC2, AUDC3. AUDC4(Audlo Channel Co$tro1)(D201. D203.

D205. D207): These addresses wrlte data into each of the four Ardlo Control'
Reglsters. Each Reglster controls lhe no13e content and volurne of the
correspondlng Audio channel.

olse Cofltent or Dlstorlion volune

Dlvlsor "N" set
HEX D7 D6 D5 D4 D2 DI DO by audlo frequency
!egister.
0 0 0 0 0 - 17 BIT poly - 5 BIT
poly - N
2 0 0 l 0 - 5 B I T p o l y - N - 2

0 I 0 0 - 4 BIT poly ' 5 BIT

poly - N
6 0 I 1 0 - 5 B I T p o l y - N - 2

I I 0 0 0 - 17 BIT poly - N

I X 1 0 -PureIone-N-r

c I I 0 0 -4BtTpoly-N

I x X - Force Output
(Volune onlY)

0 0 0 0 0 - I-olrest voluroe (off)

8 1 0 0 0 - Ealf Volume

F t l l l - Eighest Volune

Itr. l3
 PITCIT VALUBST'ORTIIE I.IUSICALNoTXS-AUDCTL=0. AUDC = hex AX

AI'DF
t{ex Dec
ItrGtt c ID 29
NOTES B 3l
Atl or Bb 2l 33
23 35
e# or Ab 25
G 28 40
l# or Gb 42
! 2D 45
E 2l 41
D# or Eb 32 50
D 35
C# o! Db 39 57
c 3C 60
B 4A 64
AtAor Bb 68
48 72
G# or Ab 4C 76
G 5I 81
F# or cb 55 85
F 5B 9I
E 60 96
D/l or Eb 66 102
D 6c 108
C# or Db 72 II4
I1IDDLE C c 79 t2\
B 80 r28
A# or Bb 88 I36
90 r44
C# or Ab 99 153
G r62
F# or Gb A)D r73
I 182
E CI 193
D# or Eb cc 204
D D9 2t7
L0w c# or Db E6 230
NOTES c 243

STIUER (Start Tirne!)(D209): This ts'rite address resets all audto

frequency divtders !q thelr I'AUDF|| value. These dtviders generate tlrtrer
internrpts $hen lhey coun! dolr'n to zero (if enabled by IRQTN). (also see
lRQST)

R-ANDOM (Randon Nunber Generator) (D20A): This eddress reads the hlgh
order 8 blts of a 17 bit Dolvnonial counter (9 bit, 1f blt 7 of AlrDcTL=t).

D7 D6 D5 D4 D 2

III.I4
 G. KEYAOARDAND SPEAKNR

CoNSoL (Console Sr,'itch Port)(D0lF)r Thls address reads or \,Iriles itata

fro.0 the console snltches and lndlcarors. (Set to 8 by OS Vertlcal Blank
c o d e .)

Not used I I I I
ero forced) | D3 | D2 | DI I D0

Eex 08 should be wtlrten to this address before readlng the slrltches.

Ones !.ritten w111 pul1 down on the sl'itch llne.

CONSOI,Btt Assignnent:

I - 0 neans snitch
DI CaroeSelecr \ pressed,
upElon serecE I
D3 Loudspeake! .,,, - should be held at I
except when r.rltlng 0
noEenlarlly. OS nrlles a
I durtng verttc al blank.

KBCODE(Kevboard Code)(D209): This address reads the Keyboard Code,

and ls usually tead 1n response to a Keyboard Interrupt (IRQ and blts 6 or 7
of IRQST). See TRQENfor lnfornarlon on enabling keyboard inrerruprs. See
SKCTLbits I and 0 for key scan and debounce enable.

D7 D6 D4 D3 D2 DI

D7 = Control Key
D6 - Shifr Key

Read by 0S lnto shadoo CH trhen key ls hlt. The OS has a get character
-
functton whtch converts the keycode to ATASCII (Ararl ASCII).

III.15
 KEYCODETO ATASCII CON\,"ERSION

KNY KEY KEY KEY

CODE CAP L .C . u,c. CTRL CA? I-.C. u.c. TRL

00 L 6C 4C 0c 20 2C 5B 00
OI J OA 2\ SPACE 2 0 20 20
02 ;. 3B 3A 7B 2Z 2R 5D 60
03 23 N 6E 4E OE
04 24
05 K 6B 4B 03 25 M 6D 4D OD
06 + 2R 5C ]E 26 3I
o7 27 ,|\
08 0 6F OI 28 R 12 52 T2
09 29
OA P 70 50 r0 2L E 05
OB U 75 55 15 2R Y 79 59 I9
0c RET 98 9R 9B 2C TAB 9I 9E
OD 69 49 09 2D T 74 54 l4
OE : 2D lc 2E w 77 I7
OF 3D 7C 1D a 7l 5I ll
10 76 56 l6 30 9 39 28
tl 3I
I2 c 63 03 32 0 30 29
I3 33 7 37 27
t4 34 BAC(S 7E 9C FE
15 B 62 42 02 35 8 38 40
16 x 18 58 l8 36 3C 7D 7D
I7 Z 1A 37 3E 9D FT
l8 34 24 38 T 66 46 06
I9 39 H 68 48 08
1A 3 33 23 3A D 64 04
IB 6 36 26 3B
lc ESC IB IB 3C CAPS
ID 5 35 25 3D G 67 4'l 07
IE 2 32 22 FD s 73 53 I3
IF I 3I 2l 3F 4l 01

* = speclal handling

III.I6
H. SERIAL PORT (see perlpheral conoeclor on consofe)

sKcTI- (Serial Port control)(D20F): This address vrltes data lnlo lhe
reglsler that controls the conflguatlon of the serial port' and also the
Fast Pot scan and Keyboald Enable.

(Bits are nordally zero

and perforn the functlons
D6 D5 D4 D3 D2 DI sholrn belolr lrhen true. )

D7 Force Break (force serial output to zero (space))*

D6)
D5 ) sertal Port Mode Control (see mode chalt at end of
D4) set]-a! port description, paee I1.34).

D3 Tno Tone (Serial output transnltted as two tone slgnal lnsEead of

loetc true/false.)

DZ Iast Po! (Fast ?ol Scar. The ?ot Scan Coonler coBPletes its
seqrence tn tlro TV 1lne tlEes instead of one ftane tlne. The
capacltor dunp transislors are completely disabled.)

DI Eoable Key Scan (Enables Keyboard Scanrlng circuit)

D0 Enable Debounce (Enables Keyboard Debounce circrils)

D0-Dl (Borh Zero) Inltialize (State used for lestlng and inltializing
chiP) *rt

OS SHADOW: SSKCTI- (hex 232)

The oS enables key scan and debounce and may change the other blts for
dlfferent I/O operattons. In particular, an aborled cassette operatlofl nay
leave the two tone b1t 1n ihe true state, causlng undesirable audto signals.
Thts i0ay be corrected by \{rltlng hex 13 lo both SKCTL and SSKCTL after dotng
I/0 and/or before nodlfylng the audlo reglslers.

* NOTE: n'hen powered on, serial port output nay stay low even if this blt
ls cleared. To get S.?. hlgh (nark)' send a byte out (reconnend
00 or FF).

**NOTE: Thele 1s no original polrer on state. Pokey has no reset pln.

III.I7
 SKSTAT(Serial Port-Keyboard Slarus)(D20I): This address reads rhe
status reglster glving inforBation about the sellal Dor! and kevboard.

(Blts are nornally true

D7 D5 D4 D and provlde the following
lnformatior vhen zero.)
D 7 = 0 = Serlal Data Input Frane Error

D6 0 = Serlal Data hput Over-nrn

D5 0 = Keyboard Over-run
( SKRES)
D4 0 - Direct from Serlal Input port
(D5 and D6 are se! to
D3 0 = Shtft Key Depressed zero when new data
and sane blt of IRQST
D2 0 = Last Key is Stlll Depressed

DI 0 = Sertal Input Shlft Register Busy

DO I Not Used (Log1c Tnre)

SKRES(Reset above Status Reqister) (D20A): This wrile address resets

bits 7, 6, and 5 of the Serlal por!-Keyboard Stalus Register to 1.

SERIN (Sertal Input Dara)(D20D): Thls address reads rhe 8 bit parallel
holdlng register that ls loaded I,hen a fult byte of serlal input dara has
beeo recelved. Thls address ls usually read in response to a serial data ln
inlerrup! (IRQ and bit 5 of IRQST). Also see IRQEN.

D7 D D4 D

Serial lrlo Porr Connector plnout;

6 8 10 t2

l. Clock In 2. Clock Out

3. Data In to computer GND
5. Data Out of Coopurer CND
7. Comand Moror Control
9. 10. +5 / Ready
11. Ardio In 12. +t2

See serlal p o r t d e s c r t p r i o n t n 0 S Eanual for Eore deta1ls.

III. t8
 SERoUT(Se!la1 output Data)(D2oD): This address rffites to the 8 blt
parallel holdlng reglsler tha! ls transferred to Ehe output serlal shlft
reglsier when a fu11 byte of serlal ortpul data has been transmitted. This
address ts usually \rritlen in response to a serial data out inlerrupt (IRQ
and btt 4 of IROST).

D7 D6 D4 D

I. PORTS (front
CONTRoI-LER of console)

PoRTA (Port A)(D300): Thls address reads or lrrltes data from Player 0
and Player I cortroller jacks if blt 2 of PACTL is true. Thls address
wrltes to the dlrectlon conlrol register lf bit 2 of PACTLls zeto. I/o for
both ports (A and B) goes through a 6520/6820

Dara Reslster-Addressed lf blt 2 of PACTL is l.

stlck 0Deration
0=Swilch pressed
l=Switch not pressed
Rlght Back Rlght Back
Left . l-eft ftrd.

srick0
(Jack 2) (Jack r)

Paddle
o=Str'itch pressed
l=Sirltch not pressed

board controller 0

ToP Rol.' )
2nd Row \ Jack I
3rd Rowr
4rd
Top Row .\
2nd Rol' Jack 2
3rd Row ,
4rh Ro\t )

Dlrectlon Control Re -Ad if blt 2 of PBCTL ts 0

Each blt corresponds to a jack ptn

0-tnput
l=output

os ssADowS: STICKo(hex 278), STICKI (279), PTRIGO-3(27c-27I

III. 19
 PACTL (Port A ControL) (D302) | This addless \"'rites or reads data froro
the Port A Control Reglsler.

Port A Conrrol
D6 D4 D3 D2 DI Reglster
x X x Set up register as shown
(x - descrlbed below)

(Read ggLI) Peripheral A Interrupt Status Bit. Serial

bus Proceed line. (Reset by readtng Port A Register.
Set by Pertpheral A lncermpt.)
D3 - Peripheral Moto! Control line on serlal bus (trite).
(0=0n I -off)
D2 - Controls Porl A addressing described above (wrlte).
{I = Port A Reglsrer 0 = Directlon Control Register).
D0 - Perlpheral A Interrupt Enable Blt. (wrlte) I = Enable.
Reset by poi.'er turn-on ox processor. Se! by Processor.

PORTB(Port B)(D301): This address reads or wriles data fron Player 2

and Player 3 controller jacks tf bil 2 of PBCTL ls true. Thls address
lrrltes to the dilectlon control register lf bll 2 of PBCTL ts zero. I/O for
borh ports (A and B) soes throush a 5520/6820.

Data Resiste!-Addressed if bil 2 of PBCTI-ls I

0=Swltch pressed
l=Switch not pressed
Right Back Rtght Back

srick2
(Jack 4) (Jack 3)

o=Swltch pressed
1=Swltch not pressed

PTRIG6 PTRIG4
?TRIG7 PTRlG5

board C tr

Top row )
2nd Rov \ Jack 3
3 r d Ror' I
4rd
Top Ro\,r)
znd Ror' \ Jack 4
3rd Rol.' f
4th

r1r.20
Dlrectlon Contlo1 Reeister-Addressed if blt 2 of PBCTL is 0
m
l p 7 l p 6 l p 5 l p 4 l p 3 l p 2 l p 1 l p 0 I

t a c h b l t c o r r e s p o n d st o a J a c k p i n

0-tnput

os SI1ADoI\IS:STICK2 (hex 27A), sTIcK3 (278), PTRIG4-7 (280-283)

PBCTI (Port B Control) (D303): This address \rrltes ol reads data fron
the Port B Control Register.

Port B Conlrol
Reglster
Sel up .egister as
sholrn (X=Described
bero!')

D7 (Read 94I) Peripheral B Interrupt Srarus Blt. Serlal

bus Interrupl line. Re8et by Readlng Port B Reglster.
Set by Perlpheral B Inrernrpt.
D3 Peripheral CommandIdentlflcation. Serial bus CoEnand
L1ne.
D2 Controls ?or! B addresslng descrlbed above.
(l= Port B Regisrer 0 = Dlrection Control Register)
DO Perlphetal B lnterrupt Enable Bit. I = Enable.
Reset by power turn-on or processor. Set by processor.
(Set to he). 3c br os IRQ code)

POT0 - P0T7 (Pol Va1ues) (D200-D207): These addresses read the value (0
to 228) ot 8 pots (paddLe controllers) connected to the 8 lines por port.
The paddle controllers are nuobered from left to right nhen facing the
console keyboard. Turning the paddle knob clockirise results in decreasing
pot values. The values are valld only after 228 TV lines follor1ng the
"POTGO"connaod described beloi.' or after AJ-LPOT
chanees.

D7 D6 D5 D

Each ?or Value (0-228)

?ADDLO- 7 (}],ex 270-211)

0S SHADOWS:

III.2I
 ALIPOT (A11 Pot Lines Siw-rltaneouslv) (D208): This address reads the
present state of the 81ine pot port!

Capacitor dunp transitors ftrst be turned off by elthe! golng to fast

pot scan node (blt 2 of SKCTL) or starting pot scan (PoTCO).

Pot runber: 0 - Pot register value ls val1d.

7 6 5 4 3 2 I 0 I = Pot register value ls not valld,

8 ?ot Lilre States

ryL9gl!le:t-.3.e1--gse4 :
No
Data Birs Used

Thls write address atarts the pot scan sequence. The pot values
(POT0 - POTT) should be read first. Thls sr1!e strobe ls then used causlog
the follo!,rlng sequellce,

l. Scan Counter cleared to zero.

2. Capacitor dullp translslors turned off.
3. Scan Counter beglns counring.
4. Counter value captured in each of 8 registers (POTO-
P0TT) as each pot line crosses trigger voltage.
5. Counler reaches 228, capacitor dunp transistors turned

(Wrillen to by OS ver!1cal blank code)

TRIGo, TRIcl, TRIG2, TRIG3 (Trisqex Ports)(0 D0I0, I D0I1. 2 D012.

3 D013): These addresses read por! plns nordally connected to the loystick
controller trlgger buttons.

Not Used I 0 = burton pressed

ed DO I = butto[ not pressed

OS SHADOWS:STRIGo-3 (hex 284-287)

NOTE: 1TIIGOlhru TRIG3 are nornally read dlrectly by rhe nlcroprocessor.

Ilowever, lf bil 2 of GRACTI,ls I, rhese inputs are latched wheoever
they go to loglc zero. These latches are rese! (true) when bl! 2
of GRACTLls set to 0.

trl.22
 PENIT(Llqht Pen Horlzontal Color Clock Posltlon) (D40C) : Thts address
reads the llorlzontal l,lght Pen Register (based on the horlzontal color clock
counter 1n hardnare). The values range fron 0 !o declnal 227. Wraparound
occurs $hen the pel! lf near the right edge of a standard-!,/ldth screen. pENtt
and PENVare nodllled when any of the loystick trlgger llnes ts pulled loir.

t r t l
4 l D

t\7 H6 tr5 E4 n3 H2 r{1 l{0

0S SHADOW: LPENH (hex 234)

PENV (L1eht Pen Vertlcal TV Llne Posltton) (D40D) : Thls address reads
the Vertlcal Light ?en Register (8 most slgnlflcant bits, sane as VCOUNT).

D7 D6 D5

L P 8 7 5
resolutlon supplied.

OS SltADoW: LPENV (hex 23s)

Front PaneI (Conlrolfer) Jacks as T/O Parrs:

PrA (6s2016820)
Out: TIL tevels, I load
Io : ml levels, 1 load

?olt A Circuit (lyp1cal):

Jack

Port B Circult (typical):

ot5
4.7K
6520 (B) 220 Jack
.00r

"Trlgger" PorL Circult ( typl cal ) :

Jack

arl.23
 ge.!!!.9.1f9r-39:!-3.99s! :
Male lemale
(console) (connector)

I 2 3 5 5 4 3 2 1

8 1 6

Controllers HARDI{ARE os
PIN JOYSTICK I PADDI,E (POT) I KEYBOA.R,D VARIASLES

I Iorward Top Blt 0 or 4** Btt 0***

2 Back 2nd B1t I or 5** Blt 1:t,t*

3 Left A(Left)rrisser 3rd Rc,l.'* Blt 2 0r 5*:t P T R I G O2, , 4 , 6

| Blr 2***
Rlght B(Risht)Trtsser I BottonoRow,t Blt 3 or 7** ?TRTGI,3,5,7
Blt 3***
5 PoT B (Rlght) 1st Colunn POl r,3,5,7 PADDLl,3,5,7

6 Trigger Button 3rd colunn T R 1 G 0 , 1 , 2 , 3 sTRrGo

1, 2 , 3

7 +5 +5

8 GND GND

9 PoTA (Left) 2nd coluBn P o T0 , 2 , 4 , 6 PA.DDLO,2,4,6

* Wrlte
** ?oRTA or PORTB
* * * S T I C K0 , 1 , 2 o r 3

lat.24