Mux select 0 selects the first configutation

Fig. 3. ModelSim post place and route simulation showing the test patterns generated by NEXT 2-D LFSR circuit.

Subsequent 8 patterns are generated Reset every clock cycle loads Mux select the first First pattern is 1 selects generated at vector the second the next clock 41 configutation edge (seed)

Subsequent 8 patterns are generated every clock cycle First pattern Reset loads the is generated first vector at the next clock 35 (seed)

Config. 1 41 - 101001 28 - 011100 63 - 111111 15 - 001111 23 - 010111 01 - 000001 18 - 010010 58 - 111010 52 - 110100

Config. 2 35 - 100011 9 - 001001 15 - 001111 55 - 110111 3 - 000011 32 - 100000 41 - 101001 38 - 100110 17 - 010001

Latency

Data corresponding to address 0

Fig. 4. ModelSim post place and route simulation showing the test patterns generated by 6b single port ROM circuit implemented using Core Generator feature of Xilinx
Reset loads the first vector 0 (seed) Reset loads the first vector 255 (seed)

(a)

00 24 88 167 231 255 231 167 88 24

00000000 00011000 01011000 10100111 11100111 11111111 11100111 10100111 01011000 00011000

Mux select 0 selects the first configutation

First pattern is generated at the next clock edge

Subsequent 4 patterns are generated every clock cycle Mux select 1 selects the first configutation

First pattern is generated at the next clock edge

(b)

Subsequent 4 patterns are generated every clock cycle

Fig. 5. a) The sampled 250 MHz analog waveform; b) ModelSim post place and route simulation plot
255 - 11111111 241 - 11110001 203 - 11001011 154 - 10011010 110 - 01101110 83 - 01010011 80 - 01010000 96 - 01100000 .. ... 110 - 01101110 154 - 10011010 203 - 11001011 241 - 11110001
Reset loads the first vector 255 (seed) Reset loads the first vector 83 (seed) Mux select 0001 selects the second configuration

Mux select 0000 selects the first configuration

First pattern is generated at the next clock edge

Subsequent 4 patterns are generated every clock cycle

First pattern is generated at the next clock edge

Subsequent 4 patterns are generated every clock cycle

Fig. 6. The sampled (105 MHz + 250MHz) analog waveform and patterns to be embedded

utilized to convert the phase word to a sinusoidal amplitude word in [12]. The length of the amplitude word was limited by the finite number of input bits of the DAC. An analog stimulus generator based on the pre-calculated Delta-Sigma modulated bit-stream stored in ROM was presented in [4][5]. The BIST architecture proposed in [5] utilizes an on-chip ROM to store the digitally sampled test signals. A 320 8 b ROM in conjunction with the 8-b segmented current steering DAC was used to generate ten cycles of test signals of 125, 250, combined 125 and 250, 312.5, and 416.67 MHz at 8-b resolution. Utilization of NEXT 2D-LFSR in lieu of traditional used ROM is discussed next. ROMs are generally used to store and retrieve binary data. In general applications, the data is retrieved from random locations in the ROM. However, when ROMs are used to store analog stimulus, the data representing samples of the waveform is retrieved from consecutive locations. This forms the basis for utilizing the hardware efficient NEXT 2D-LFSR for storing analog stimuli for mixed-signal BIST designs. The hardware utilization and time taken to generate two waveforms using both 8-b ROM and NEXT 2D-LFSR was compared.

Two waveforms used in this study were generated and sampled using an ideal ADC in Matlab programming environment. The number of points was carefully selected so that only minimum number of points is stored. The stored patterns are then repeated continuously by triggering the reset and mux select signals of the NEXT 2-D LFSR circuit. The first waveform is a sinusoidal signal with a frequency of 250 MHz that was sampled and digitized at a rate of 2500 MHz (Fig. 5(a)). Only 10 points was used for storing as the data can be repeated continuously by triggering the reset and mux select signals. The BIST hardware for 8-b binary equivalent of the 10 sampled points was synthesized using the HPC based highly optimized NEXT 2-D LFSR algorithm described in section III. C. Two configurations were required for the implementation where both the first and the second configuration embedded 5 patterns each. The post place and route simulation plot generated using Modelsim for the design is shown in Fig. 5(b). The performance and gate count comparison of ROM generated using Xilinx Core Generator and NEXT 2-D LFSR for the 250 MHz sampled waveform is given in Table 3.