Ocb

Chapter –1
General Architecture of Digital Switching System
A digital switching system uses the S.P.C. concept and a digital switch.
The following diagram indicates the basic building blocks of any digital switching
system. (Fig.1)
N x 2 Mbps
links
Subs access inter face

DIGITAL
SWITCH
Trunks or V 5.2 access
Trunks/PCM
interface

Remote CONTROLLERS
Subs & access
Other auxiliary inter Operation & Mtce. system with

faces
Dialogue peripherals
(a) Tone generator
(b) Frequency receives
(c) Conference call facility
(d) CCS# 7 Protocol Manager
(e) V 5.2 access manager
Fig. 1
A brief description of the components is given below:-
1.1 Subs access interface:

Analogue or digital subscribers make entry to the exchange at this interface.
Analogue to digital conversion or ISDN protocol translation is done at this
interface. Number of digital links (2 Mbps) are extended from this interface
to switch. Allotment of T/S on one digital link is done by the subs interface
logic. The information is carried digitally on allotted time slot and then
switched to called side by a digital switch.
1.2 PCM interface:
Any digital exchange can only accept intelligence in PCM decoded form and
hence trunks from other exchange or links from remote subscriber units or
other access systems e.g. V 5.2 will be inform of PCMs. These PCMs are
terminated in a PCM interface. The basic function of the PCM interface
would be HDB3/ Binary code conversion, CAS handling and forwarding
CCS# 7 signals to suitable protocol handler. PCM interface on the other hand
are connected to switch and other controllers.
1.3 Auxiliary interface :

The auxiliary interface is again a service peripheral which take care of one or
more of the following functions:-
(a) Tone generation e.g. DT, BT, RBT NU etc.

(b) MF Signalling dual tone
(c) Conference call facility
(d) CCS #7 protocol management
(e) Access Network (V 5.2) protocol management
1.4 Controllers :
Various controllers are required to control switching based on the digital
informations received from subscribers or over the trunks.
The main control function are :-
1.4.1. Call handler (Register) : This is the control function which processes a call
right from the point of seizure to called party connection.
1.4.2 Translator : This control function basically maintains all data base of subs &
trunks and provides necessary information to call handler enabling the same to
establish connection between calling links T/S to called link T/S.
1.4.3 Charger : Computation of charge based on set principles is carried out by this
control function.
Other control functions could be controllers for connection, message

distribution and formatting and defence for connections and CCS # 7 protocol
management functions etc.
The various control processes may be centralised or distributed depending upon

type of system.
2. The Switch : A digital switch of different configuration e.g. a pure Time

Switch or a combination of time and space switches are used in different type
of exchanges and various service peripheral like subs access/trunk access etc.
are connected to this by n X 2 Mbps link as shown, Switch connections are
established by controllers like call handlers.
3. OM functions : A general purpose computer is generally used with dedicated

software to dialogue with the system in order to carryout various operation
and mtce. activities like data base creation, fault/alarm message output
diagnostics, creation of new equipments etc.
4. Additional Features in new Switches:

New switches are capable of providing ISDN where in i.e. the subs loop is
also digital. The ISDN feature necessiates CCS# 7 signalling also.
Chapter - 2
FUNCTIONAL ARCHITECTURE OF OCB – 283 SWITCH
1. The functional architecture : The main functional blocks of a OCB-283 switch

are :-
- Subscriber access sub system which carries out connection of different types
of analogue and digital subscriber.
- “Connection & Control” Sub system which carries out connections and
processing of calls including PCM connections.
- Operation and mtce. sub function which does the management of database and
helps in carrying out various maintenance procedures in built in the systems.
Figure 1 shows general functional breakdown and figure 2 shows the detailed
functional architecture of OCB-283 switch.
V 5.2 access
CCS # 7 Network
Telephone Network
Connection
Subs
access
System
and
Control
Data Network
Analogue
or digital
subs (Single or Value added Network
Group)
Operator & Mtce

Operation Network
&
Maintenanc
Disk
Streamer
Mag tape
Fig. 1
BTT
(N)
CSNL Switch
Matrix ETA
System
(MCX) (N)+1
URM
(duplicate) PU/PE
Com
s
PCM From
CSND
CSED
Commmunications multiplex (MAS)
V 5.2
access
Circuits
(CAS & CCS # 7)
Recorded
Announcement
n=7
MQ GS TX GX CC PC MR
TR
Control
functions
Communications multiplex (MIS)
O&M
O&M functions
Fig. 2 (OCB 283 Functional Architecture)
The various connection and control functions in OCB-283 system are distributed
with appropriate redundancy as indicated in the diagram.
2. Brief description of the functional components :-
2.1 BT (Time base) : Time pulses are generated in triplicate and distributed to
LRs at Switching unit. The time base is usually synchronised with the network by
a synch. interface. Synchronisation interface gets the clock from PCMs which
carry traffic also and synchronises the local clock with the PCM clock and thus
network synchronisation is achieved.
2.2 Host switching Matrix (MCX)/Switch Control Function “COM”

This is a pure time switch of maximum 2048 LRs connectivity capability. The
switching of LR time shots are controlled by the function COM which in turn
obtains the connection particulars from call handler known as Multiregister.
LRs are 2 Mbps binary coded PCM links with 32 time slots.
2.3 Auxiliaries : Following auxiliary functions are available
- Auxiliary Equipment Manager (ETA) :
The ETA supports the following function:
- Tone generation (GT) e.g. dial tone, busy tone etc.
- Frequency generation & reception (RGF) for R2 MF signal, tone dial
reception etc.
- Conference call facility (CCF).
- Exchange clock.
2.3.2 CCS # 7 Protocol Manager (PU/PE)

64 kbps signalling channels are connected to this by semipermanent link and
carries out level 2 and level 3 of the signalling message transfer.
The defence and signalling link resource allocation is done by a control function
PC.
2.3.3 V 5.2 Protocol Handler : The signalling protocol between an access

network an d local exchange is processed and managed by this function.
2.4 Call Handler “MR”

This obtains necessary data from subs and circuits and process for connection and
disconnection of call with the help of a database manager TR. In addition this
helps in carrying out circuit tests and some observations.
Besides MR function there is one CC (Call Contorl) function which again

contains register to handle CCS # 7 calls in conjunction with MR registers.
2.5 Data Manager TR:

This function is responsible for managing and storing various subscriber and
trunks related data base. The data is returned by the call handler “MR” as and
when required during call processing.
2.6 Charging function (TX):
This function is responsible for charge computation on the basis of certain
charging parameters supplied by the translator during analysis of digits received
from a source (Subs or Circuit). This also prepares detailed billing messages and
forwarding the same to the operation & maintenance function for further
processing. Besides the charge related function the TX also is responsible for
carrying out some traffic observation on subscriber and trunks.
2.7 Matrix handler (GX)

This function is responsible for processing and for defence of connections on
receipt of :-
(a) request for connection and disconnection from MR or MQ (marker).

(b) fault in connection signalled by the switching controller function (COM).
GX also carrier out monitoring of connections and checks data links periodically..
2.8 Message Distribution function (MQ) marker:

Its function is to format if required and distribute messages
- It also supervises semipermanent links .
- Interchange of messages between different communication multiplexes.
2.9 PCM controller (URM) :

PCM interface receives PCM from other exchanges remote subs access
units, access networks and digital recorded announcement systems and the URM
function carrier out the following:
- HDB3/Binary code conversion

- Injection / extraction of TS 16 for CAS.
2.10 OM Function:
This function enables to create all data required for subs/circuits and their
testing.
This also enables spontaneously issuing fault and alarm messages in case
of indications coming from OCB units.
OM function further provides features for saving detail billing/ bulk

billing messages on mag tape (cartridge) .
The OM function possess a two way communication path with the

exchange system.
2.11 Subscriber access function :

This functional component is implemented in CSNL/CSND or CSED and is
responsible to forward new call connection & disconnection requests to control
functions.
Chapter – 3
Hardware architecture of OCB-283 Switching Systems

1. Various functional components discussed in the previous chapter are required to
be implemented in some hardware unit.
For this purpose functions are classified as under:-
1. Subs access functions

2. PCM connection interface
3. Auxiliary functions interface
4. Control functions
5. OM function
OCB – 283 system does not include the subs access systems but can support
different type of subs access systems.
2. There are different type of subs access units like CSNL/CSND i.e. local and
distant digital (Numerique) subs connection unit and CSED i.e. (Distant analogue
subs connection unit).
A detail description of subs interface provided in OCB shall be discussed

in yet another chapter.
3. Control functions – Concept of station

For all control function or functions OCB-283 uses concept of a station.
Following type of stations are available:

3.1 SMT: Trunk multiprocessor station – This implements the URM function for
PCMs i.e. responsible to handle CAS and be transparent to CCS# 7 signalling.
3.2 SMA : Auxiliary multiprocessor station. These stations implement one or more
auxiliary functions like ETA, PU/PE or V 5.2 functions. However, while ETA &
PU/PE functions can be implemented in one station, V 5.2 function is
implemented in SMA without any other auxiliary function.
3.3 SMX: Switch multiprocessor station This implements the switching function
(COM) and contains the switch matrix system also.
3.4 SMC : Command or control multiprocessor station.
This type of station implements one or more control functions like MQ,
TR, TX, MR, GX, PC etc.
3.5 SMM: Maintenance multiprocessor station implementing all OM functions. This
supports process for, dialogue with OCB, data base management and handling
spontaneous message generated by OCB units.
3.6 STS : Synchronisation and time base station. This station is responsible for
generating exchange clock and synchronise the same with the network.
4. GENERAL CONCEPT OF A STATION
A station in OCB is a hardware unit consisting of number of processors and

couplers connected on a common bus referred to as BSM i.e. Multiprocessor
Station Bus as shown below. Each processors or couplers is a Motorola 60830
processor with sufficient on board RAM and known as an agent on the BSM.
Each agent is loaded with one or more application e.g. MR. TR, TX etc.
depending upon memory space required and traffic. The couplers besides
supporting applications may supports other functions also e.g. couplers to connect
token rings used for communication between different stations, couplers to
support GT/RF/CCF and CCS#7 functions etc.
The diagram shows structure of a SMC type of station Fig. 1
MIS
BL
C P P P P P
M U U U U
M U
S S S S
P P C 4
1 2 3
BSM BUS
C C C C
M M M M
S S S S
1 2 3 4
MAS - 1 MAS - 4
Fig. 1
CMP : Principal Multiplex coupler for coupling to MIS token.

CMS – 1 to CMS 4 : Secondary multiplex couplers coupling to 1 to 4 MAS
tokens.
PUP : Principal processing unit.
PUS 1 – PUS 4 : Secondary processing unit
BL : Local bus
MC : Common memory.
Functional architecture of different station are described in little more detail in
subsequent chapters.
5. Inter Station Communication : The control stations communicate among
themselves on a token ring called MIS i.e. Inter Station Multiplex, while the
other stations are connected on 1 to 4 MAS i.e. station Access Multiplexes.
The concept of token ring is similar to the connection of computers in a
LAN.
The MAS are connected to control stations also, so that the MAS domain units
can communicate with control stations. Most of the time cross over from MAS
to MIS domain or vice verse may require a gateway function and this is provided
in the SMC with marker function.
The application softwares are referred to as logical machines (ML) and are
loaded as per some standard configurations in various agents of a station.
The various logical machines are :

{MLMR, MLTR MLTX, MLMQ, M,LGX, MLPC, MLCC} SMC
MLPU/PE, MLETA, MLAN } SMA

MLURM } SMT
MLOC, MLOM } SMM
MLCOM } SMX
Little more elaborate description of individual stations shall be discussed

in the following chapters.
6. Redundancy Principles:
For reliability reasons the provisioning of hardware is more than what is required
as per traffic, so that either load may be shared or transferred. The redundancy
criterion is different in different station.
(a) Station: SMC N +1 (N+1)th taking load on failure of any

SMC.
SMA (PU/PE) (N+1) (N+1) th reconfiguring on failure
of any of the N PU/PEs.
SMA (ETA) N (load sharing)
SMA (V 5.2) 2 N (Pilot/Reserve)
SMX 2 N (Parallel)
SMT 2 N (Pilot stand by)
(b) Logical Machines : MR – 1 to 7 , MQ, TX, TR, GX, PC are

duplicate but PC works on Pilot/Reserve mode &
all others on load sharing/mode. Number of MR
depends or capacity and traffic.
Chapter – 4
MAIN CONTROLS TATION – SMC
1. Role of SMC:
All the control functions are supported in SMC and one or more of these
functions can be used during call processing.
The main control functions are MR, TR, TX, MQ, GX, PC, CC etc.
S S
SMT M M
A X
MAS (1 to 4
(OTHER STATIONS)
SMC SMC
MIS (1)
MAL
SMM
Fig. 1 SMC Environment
2. Environment of SMC : Relative position of SMC in OCB exchange is

shown in the diagram fig.1. Control functions in SMC communicate on MIS.
s s
While other function (ML ) communicate with SMC on MAS. CSN
communication with PU/PE over CCS# 7 link. The PU/PE forwards the
messages to SMC (MR).
3. Hardware architecture of SMC :

SMC station consists of following functional hardware components
connected on a common bus known as BSM as shown in the diagram below :-
MIS BL
CMP PUP MC PUS 1 PUS 2 PUS 3 PUS 4
CMS 1 CMS 2 CMS 3 CMS 4
MAS 1
MAS 2 MAS41
MAS 3
Fig. 2 FUNCTIONAL ARCHITECTURE OF SMC STATION
- One Principal Multiplex Coupler (CMP) for connections to MIS token

ring – implemented in ACAJA/ACAJB
- One to four Secondary Multiplex Coupler for Connection to 1 to 4 MAS
token ring implemented in ACAJA/ACAJB
- One Principal Processing Unit – PUP/ implemented in (ACTUR 5)
- 1 to 4 Secondary Processing Unit - (PUS) – also implemented in
ACTUR5
- One common memory – ACMCS
- Secondary alarm coupler (CSAL) implemented in ACALA
- Power supply convertors (DC to DC) – 5 V 40A – AE 5 V 40
4. Functional architecture of SMC

The functional architecture and the physical architecture of SMC is shown
below diagrammatically.
CSAL
MAL
ACALA
CMP
PUP PUS (1<4)
MC A A
MISA C C
MISB V V
5 5
A A A A A A V V
C C C C C C 5V 40 40
A A U M U U
J J T C T T
B A R 5 R R
5 5 5
A A A A
C C C C
A A A A
J J J J
A B A B
5 5 5 5
MAS 1
MASA 4
MASB 1 MASB 4
CMS (1 < 4)
Fig. 3
THE PHYSICAL ARCHITECTURE OF SMC
4.1 Function of various agents on BSM

4.1.1 ACAJA 5 / ACAJB 5 as CMP
ACAJA 5 is a Motorolla 68020 processor based coupler with a 128 Kb EPROM
and 4 Mb DRAM required for booting. This board is connected as an agent or
BSM bus and connected to MISA ring. ACAJB 5 is similar to ACAJA 5 but
there is no direct connector with BSM. It gets connected to BSM through
ACAJA via a daughter board ADAJ and connects MISB.
This also supports registers ICMAT and ICLOG for storing hard and soft fault
conditions.
The CMP :
- Enables communication between different SMCs & SMM on MIS token
ring
- Enables loading of telephone application data
NB : A station gets inserted on MIS right on powering up but on MAS after

getting initialised i.e. after application software are loaded.
4.1.2 ACAJA / ACAJB as CMS

- This control the exchange of messages with MAS domain units e.g. SMT,
SMA, SMX etc. The informations are concerning channel associated
signalling from SMA/SMT or messages related to
connection/disconnection etc. with SMX.
- A SMC with marker function (MLMQ) does the job of linking messages
between MIS & MAS domain. The messages may be like status
setting/operational/and security – defence related message.
4.1.3 ACTUR 5 AB as PUP

The PUP i.e. main processing unit also referred to as station processor routes the
exchanged informations between different entities present in the station. Each
executable function e.g. TR, TX, MR, MQ, PC etc. have their own exchange
function requiring practically all the storage capacity of PUP.
The PCB presently in use is ACUTR 5 AB. This has Motorola 68030
processor with modularly expendable on board RAM in steps of 64 Mb. The PUP
is connected to the common memory ACMCS over a 32 bit local bus.
4.1.4 ACTUR 5 AB as PUS :

The secondary processors hardware wise are similar to PUP but connected only
to BSM.
The PUS generally support MR (MACRO) TX (macro) MQ exchanger etc.
TR and PC functions are essentially supported on PUP.

The processors ACTUR 5 AB consists of MOTOROLLA 68030 40 MHz
processor with 128 Kb EPROM, 4 Mb DRAM registers ICMAT & ICLOG for
storing hardware and software faults respectively and a local bus interface, and a
BSM interface.
4.1.5 ACALA board :

This is used as a secondary alarm coupler and do the preliminary processing of
converter alarms for onward transmission to SMM over a MAL ring.
5. External Interfaces to the station :
(a) MIS and MAS rings : There are two rings referred to as A & B operating
on loads sharing basis. The rings are connected at the back of the
ACAJA/ACAJB on add on boards AIISM. There are two cables for each
ring i.e. one coming from up stream station and other going to down
stream station.
(b) MAL ring : There are two rings A & B in one cable connecting ACALA
in different stations and finally to ACRAL board of SMM.
6. Internal Interfaces :
The BSM and the BL are the internal interface. While all agents are
connected or BSM bus, PUP is connected to memory on local Bus. The station
processor PUP use 32 bit BL for certain transactions.
BOARDS ORGANISATION IN SHELF FOR SMC STATION

s
The PCB with their relative slot positions in shelf are indicated in the
figure below:-
Location and rack assembly
Location
FRONT VIEW
SLOT
AE5V40
138
ACUTR
132
ACUTR
126 ACUTR
120 ACUTR
114
108
102 ACMCS
96 ACUTR
90 ACAJA
82 ACAJB
78 ACAJA
70 ACAJB
66 ACAJA
58 ACAJB
54 ACAJA
46 ACAJB
42 ACAJA
34 ACAJB
30 ACALA
24 AE5V40 FIG. 4
15
CA CB CC UA UB UC
SMC SMC SMC SMC SMC SMC
SMC SMC SMC SMT1G SMA

SMT1G
SMC SMC SMA
SMM SMA
SMA SMC SMA
SMT1G
SMA
SMA SMC SMA
Fig. 5 Standard Racks with SMC

SOFTWARE ARCHITECTURE OF SMC
The software orgainsation is as under :=
The application Software which are supported by :-
A basic Software Hypervisor.
MLSM for communication, loading and defence.
Hypervisor Functions:
This is the software enabling more than one application e.g. MQ, TR, TX
etc. to be supported on same agent and it performs:
- Communications within the station

- Management of time delays
- Time allotment for various applications.
The elemental tasks corresponding to an application is taken care of by a
software SUPERVISOR which in case of MR & TX is known as sequences.
Thus Hypervisor is one per agent but supervisor is one per application on
the agent.
General Software Architecture

This is explained in the schematic below :-
SOFTWARE ARCITECTURE OF A STATION
Fig. 6
Main coupler (CMP) Secondary coupler (CMS)
ML ML
SM/P ML SM/S
SUPERVISOR SUPERVISOR
HYPERVISOR HYPERVISOR
SUPERVISOR SUPERVISOR
HYPERVISOR HYPERVISOR
SEO
ML MLj/E
MLi ML
SM/S ou
MLj/M MLk/S SM/S
MLk/P
Main processor (PUP) Secondary processor (PUS)
SEQ : sequencer (SMR or TX)

ML SM/P : main component of MLSM
ML SM/S : secondary component of MLSM
MLi : MLi (Single component)
MLj/E : interchange unit software module of Mlj (multi-component)
MLj/M : macro component MLj(multi-component)
MLk/P : main component (new structure multi-component)
MLk/S : secondary conponent (new structure multi-component)
5.2 Examples of location of software machines
5.2.1 Small configuration P (Subscribers applications)
CMP CMS 1 CMS 2 CMS 3
M M M M M M
M M
L L L L L L
L L
S S S S T M
M G
M M M M R R
Q X
/ / / / /
P S S S E
SUPERVISOR SUPERVISOR SUPERVISOR SUPERVISOR
HYPERVISOR HYPERVISOR HYPERVISSIOR HYPERVISOR
BSM
HYPERVISOR HYPERVISOR HYPERVISOR HYPERVISOR
M M M M M M M M
M
L L L L L L L L
L
S S M S T S T P
M
M M R M X M X C
R
/ / / / / / /
/
S S M S E S E
M
PUS 1 PUS 2 PUS 3 PUS 4
NOTE : ML _ _ /M are managed by a sequencer (SEQ)
Fig. 7
5.2.2 Medium configuration (Subscribers application)
(a) SMC = TR + TX + MQ + GX + PC
CMP CMS 1 CMS 2 PUP
M M M M M
L L L L L
S S S S T
M M M M X
/ / / / /
P S S S E
BSM
M M M M M M M M M M
L L L L L L L L L L
S T G S T S T S M P
M R X M X M X M Q C
/ / / / / /
S S M S E S
Fig. 8
(B) SMC = MR
CMP CMS 1 CMS 2 PUP
M M M M M
L L L L L
S S S S M
M M M M R
/ / / / /
P S S S E
BSM
M M M M M M M M
L L L L L L L L
S M S M S M S M
M R M R M R M R
/ / / / / / / /
M S S S M
S M M
Fig. 9
(C) SMC = TX + MQ + PC
M M M M M
L L L L L
S S S S T
M M M M X
/ / / / /
P S S S E
BSM
M M M M M M M M M
L L L L L L L L L
S T S T S T S P P
M X M X M X M Q C
/ / / / / / /
S M S M S E S
Fig. 10
5.2.3 Configuration TM (SSP application)
(a) Station SMC = PC + TR + GX + MQ + TX
(B)
M M M M M
L L L L L
S S S S T
M M M M R
/ / / /
P S S S
BSM
M M M M M M M M M M
L L L L L L L L L L
S G P S P S M T S T
M X C M C M Q X M X
/ / / / / / / /
S N S I S E S M
Fig. 11
(B) Station SMC = CC + GS + MR (SSP application)
CMP CMS 1 CMS 2 PUP
M M M M M
M
L L L L L
L
S S S C M
S
M M M C R
M
/ / / / /
/
S S S P E
P
BSM
M M M M M M M M M M
L L L L L L L L L L
S C G S C G S M S M
M C S M C S M R M R
/ / / / / / / / / /
S S S S S S S M S M
Fig. 12
5.2.4 Multi-component software machine : MLMR
EXCHAN MACRO MACRO MACRO MACRO

GER
MR MR MR MR
MR
- Each MR MACROPROGRAM BLOCK can generate up to 256 “MR

REGISTERS” simultaneously.
- An MR REGISTER is a software unit which controls and supervises the

establishment pr breaking off of a communication.
- The EXCHANGER BLOCK carries out interface between all the MR registers
(256, 512, 758 or 1024) and the other software machines.
- Two of the registers in a macro program are reserved for exchange

administration.
Fig. 13
5.2.5 Multi-component software machine ML IX
EXCHAN MACRO MACRO MACRO MACRO

GER
TX TX TX TX
TX
BSM
- Each STX MACROPROGRAM BLOCK can manage up to 1500 TX

REGISTERS simultaneously.
- The TX REGISTERS is a software above to charge a communication.
- The EXCHANGER BLOCK ensure interface between all the TX REGISTERS

(1500, 3000, 4500 or 6000) and the other software machines.
Fig. 14
5.2.6 Multi-component machine : MLCC (SSP application)
Main Secondary Secondary Secondary Secondary
CC CC CC CC CC
BSM
- Each secondary MLCC can manage up to 3000 process of communication

command (or calls) simultaneously.
- A process is a software in charge of the treatment of a communication

(setting-up or breaking down)
- The main component MLCC assume the function of exchanger (routing of

messages received at the MLCC level to the correspondent process (cc)).
Fig. 15
5.2.7 ML multicomponents : ML GS (SSP application)
Main Secondary Secondary Secondary Secondary
GS GS GS GS GS
BSM
- Each component of the secondary MLGS can manage up to 3000 service

management task (or servers calls) simultaneously.
- A task is a software in charge of checking the calls to the server at the LEG level
(SSP application).
- The MLGS main component have the exchanger function (send back) the
received messages at the MLGS level to the correspondent task manager).
Fig. 16
The distribution of various application on various agents basically depends
upon the traffic and certain standard configurations have been fixed for small,
medium and large systems. There can not be any choice for a different
combination of applications in different agents than those specified by
ALCATEL.
DEFENCE:
In case of any problems encountered e.g. watch dog time out or a hard
fault etc. the agent supporting the related application initiates a defence function
and communicates to the SMM via CMP. SMM then issues appropriate fault or
alarm messages and also initiates testing of faulty station for detecting any hard
fault. The stations while extending malfunction message conveys the content of
ICMAT & ICLOG registers for the connivance of SMM to issue appropriate
message for maintenance personnel.
Generally an isolated message may not give useful informations but

number of messages related to a function may give sufficient clue to fault.
POWER REQUIREMENT :
ACUTR 6.5 W at 5 V - 5 such boards total 32.5 W
ACMCS 3 board X 4.5 W per board – 13.5 V
ACAJA 5 boards X 1 UW per board – 50 W
ACAJB 5 boards X 3.5 W per board – 17.5 W
Total 113.5 W
Hardware addressing :
Every station on token ring has a unique hardware address. The address is
programmed by setting of a pair of dip switches provided on a daughter board
AARCH at the back panel of the station as follows.
T
OFF = 1 Y
C
ON = O P
DOCP TYOR APSM (MSB)

APSM (LSB
For 65% convertor efficiency consumption = 173.5

---------
.65
= 175 W at – 48 V
Add 4 W at – 48 V for ACALA
Thus total = 179 W
APSM Physical address of SM (in a bits)
DOCP Domain of coupler
TYCP Type of coupler
TYOR Type of organ
NOTE : Refer commissioning guide document for switch positions and value of
the various fields set in the Switch.
Chapter 5
SWITCHING MULTIPROCESSOR STATION (SMX)
1. ROLE : A SMX is one module of the entire switch matrix system with
independent control. The station is responsible for carrying out connection of an
incoming LR time slot to an out going LR Time slot.
1.1 FUNCTIONS :Switching may effect connection between subscribers, subscriber

to junction, junction to junction subs to tone or RF, junction to tone or RF etc. or
there may be a semi permanent connection for certain data link.
Besides the connection function, the SMX performs following other

functions:-
• Clock reception from STS and distribution.

• Fault and alarm processing
• Defence of the station etc.
2. SMX Environment - This is shown diagramatically in Fig. 1
LCXE FROM CLOCK FROM STS
OTHERS
SMXs
M
LREA I A I
T L SAB
L
SAB R
R A
R
CSN LAE A I
LCXS A CSN
A LCXE X
LRSA
SMT A A SMT
A
OR OR
SMA M I LAS SMA
SAB I A RSB
L L
B T SAB
R R R
LREA LCXS LCXS B
B
I B
B X B
B
LCXE FROM CLOCK

OTHER SMXs FROM STS
MAS
TO CONTROL
UNITS eg.MR
FIG. 1 (SMX ENVIRONMENT)

LCXE Links
From other STS
SMXS
LRS
(A)
S I S SMT
CSN A L I A SMA
SMT LA B R B CSN
A
L A
A
5 R 5
SMA B LA
A A
B B
B B
LRS (B)
MAS
CONTROL
UNITS
FIG. 1 SMX ENVIRONMENT

The SMX is connected on 4 Mbs links (LR) to units like CSN, SMT and
SMA referred to as service peripherals.
On the other hand SMX is also connected to control units over MAS
token rings which provide particulars of connections to be effected.
The Network synchronised clock from STS is supplied to SMX. Switching

is done on the strobe of clock and also this clock is supplied to the service
peripherals i.e. CSN, SMT & SMA on LR links.
The inlets from other SMXs also make an entry to SMX as LCXE links.
3. BASIC FEATURES OF SMX
- The switch in OCB-283 is a pure time switch.

- Ultimate capacity of switch matrix is 2048 X 2048 LR.
- Modularity 256 X 256 LR in 8 SMX Module
64 X 64 LR matrix by adding PCBs
• Each module of SMX is duplicated and Switching takes place in
either branch parallaly .
• 2 Mbps access links LA issuing from CSN, SMT or SMA are
converted into 4 Mbps LR links by a SAB interface card. The
SAB is a functional component of SMX but the hardware is put in
service peripherals. Branch is selected by receiving SAB
functional unit.
- Switching is done at 16 MBps rate but reception &
issue of LR links is at 4 Mbps rate.
4. CONCEPT OF PURE TIME SWITCH – A REMINDER
A pure time switch consists of a speech buffer a control buffer and a Read/Write
controller. Digital Samples of data carried by TS of LRs are written sequentially
in consecutive locations of the speech memory.
The control buffer contains the addresses of a location of speech memory

to be read at a defined TS i.e. write operation on speech memory is sequential
while read operation is controlled, by the contents of control memory
The contents of the control memory are based on the connection

particulars decided by the MR by going through the call processing sequence.
Based on above mentioned logics, the functional architecture of a switch
shall be as shown in diagram below:
SPECH BUFFER
LRE 1
4 LRS
Sl to parallel 20
conversion Parallel to serial
conversion
CONTROL MEMORY
MATRIX
4 20
Controller
20
4
Fig. 2 Functional Architecture of a Time Switch
Note: Control memory contents indicate a connection between TS 4 and RS 20.

Here speech and control memory constitutes the switch matrix. The
digital samples of T/S of LRE are as it is reproduced in the speech memory e.g.
location 4 contains the speech sample of TS 4. If TS 4 is to be connected to T/S
20 then location 4 of control memory should point to address of location 20 of
speech memory and location 20 of control memory should point to address of
location 4 of speech memory as shown. These contents are written by matrix
controller by getting the connection particulars from MR.
5.1 Functional Architecture of a SMX module in OCB –283

A SMX station uses the concept of digital pure time switch as discussed
above and further provides a coupling to the MAS token ring for communication
with control units for obtaining connection particulars. Also the station should
have interface for receiving time links and the inlets from other SMX station for
realising full availability of inlets in each station. Accordingly functional diagram
shall be as shown below :
LCXE from other SMXs
LCXE
S LCXs
To
A LRS 4 Receiving
B 4 Mb 4 Mb Mb SAB in
A Paral- paral Serial CSN SMT
lel -lel or SMA
LA S
From A
CSN Fig. B ILR
ILR
Control MATRIX System
SMT B
consisting of
SMA
speech & control
From
STS { MATRIX
COUPLER
memory
BTT
BSM
MUX
coupler
MAS
SMC
Fig. 3 Functional diagram of SMX
5.2 PHYSICAL IMPLEMENTATION AND PURPOSE OF PCBs OF SMX .
• The MATRIX is constituted of RCMT and RCSM boards.

• One RCMT board is capable of providing a square matrix of 64
LRs i.e. 64 X 64 Switchings are possible. Thus for one SMX
module 4 RCMTs are required to cater to 256 LRs. Since we need
to have the capability of switching any incoming LR time slot to
any O/G LR T/S the LRs of other SMXs as LCXE links are
multipled by providing RCMT boards. Thus in a SMX module
256 LRs are connected through LR interface (ILR) to 4 RCMT
boards and there can be a max of 28 more RCMT boards
provided in each SMX to receive inlet LCXE links from other
(max 7) SMXs. Whereas number of outlets derivable are 256 only.
Each SMX module therefore can be said to serve a max ,of 2048
inlets and 256 unique outlets. Of course the size of the rectangular
matrix supported in each SMX will depend upon actual number of
LRs and hence number of SMXs equipped.
5.2.1 The connection of RCMTs/RCSM in a SMX branch are as shown below:

256 LRE
CSN
SMT
or
{ SAB
MAX 256 X 7 LCXE LINKS
Multiplied from other MAX 7 SMXs
SMA
16 RCID
Serial
to 256 LCXE
parallel
4 RCMT + 28 RCMTs
4 RCSMs (Main)
4 RCSMs (Extn.) 256 LCXS 256 LRS

to SAB of
16 RCID receiving
unit
Fig. 4 Connection of RCMTs/RCSM in SMX
As shown in diagram – max no of RCMT boards required is (4 + 28) i.e. 32, of

which 4 belong to SMX itself catering to 256 inlets of its own and other 28 are
referred to as receptors for the I/C (2048-256) LRs served by other SMXs. No of
SMXs required will be as per traffic & no. of connector units.
Writing takes place on all RCMT boards corresponding to inlet in all

SMXs and buffered in a RCSM boards corresponding to outlet in particular SMX
to which the outlet belongs.
The ultimate capacity of switch 2048 X 2048 is realised in two group of

1024 X 1024.
The RCSM boards are provided for buffering the read output of RCMT (at
16 MHz), but set out at 4 MBPs in 4 groups of 16 LCSM links. The final readout
is at 4 Mbps rate from RCSM board giving 64 LCXS links at 4 MBps . One
RCSM can accommodate 64 LRs and hence 4 RCSMs are required. However for
more than 1024 LR capacity each SMX
module needs extension shelf to accommodate RCMT boards. Inlets
corresponding to the RCMTs in extension shelf when required to be switched to a
outlet of SMX, the buffering is done in RCSM provided in extension shelf only
i.e. max number of RCSM required for ultimate capacity of 2048 X 2048 will be
8 per SMX.
5.2.2 The interface for LRs (ILR) is differential interface implemented by PCB RCID.
Each RCID is capable of supporting 2 GLRs (or 16 LRs) and hence one SMX
will have 16 RCID boards to cater to the 256 LRs. The RCID boards receive the
LREs in serial format and convert the same to parallel 4 Mbps format known as
LCXE links. Similarly the output from RCSM board is in parallel format
(LCXS) Parallel to serial convertion again taken place in appropriate RCIDs
board and LR s is derived.
5.2.3 Read/write operations on the MATRIX System (Speech & control memory) is
done by a MATRIX coupler implemented by a PCB RCMP. The RCMP carries
out read and write operations at strobe of Network clock, which it receives in
triplicate from STS. RCMP board has a majority logic decision interface for
choosing the best clock out of the three received.
Read and write controls are independently carried out in the main and
extension shelves. For this RCMP is provided both in main & extension shelves.
The speech buffer is duplicated & Read & write are done in alternate
frames.
5.2.4 SAB function is performed by different PCBs in CSN, SMT & SMA e.g. TCBTL
(CSN) ICIDS (SMT 2 G) & ICID (SMA). This hardware units are a part of SMX
but physically mounted in CSN, SMT or SMA.
6.0 What is SAB Function & How implemented

SAB stands for selection & amplification of branch. The logic used for selection
of a branch is :-
(1) Sending unit calculates the parity in the data sent and sends the parity to
receiving unit. Receiving SAB also calculates parity on data received and
compares with parity received. If there is difference in parity or branch A
and branch B then the one which matches with sent parity is chosen.
(2) A bit by bit comparison of data on branch A & B is carried out to check
whether there is any change because this is likely even with parity
tallying.
There should be a method to send parity bit from source to destination or
an error indication either in parity received on bit by bit Comparision
made. For this purpose three additional bits are required. Actually 8 bits
are added in every time slot making 16 bits per slot i.e. the rate on LR link
becomes 4 Mbps. This addition is done by SAB function.
CSN S I
SMT
2 Mbps 4 Mbps MATRIX
A L
OR LA
B LR R
SMA
8bits
8 bit 8<12 131415
Fig. 5 Position in SMX

There are two types of checks on connections in the two branches of
switch.
(1) Permanent Check : This is done whenever a connection is made
by calculating the parity and comparing the same with sent parity
and also by making a bit by bit comparison of samples coming on
two branches.
(2) Multiframe check : This type of check is initiated by GX when

SAB defects a fault of switching and conveys the same to GX via
COM.
Use of additional bits
In Permanent mode:
Bit 13 is O (Zero)
Bit 14 Value is Zero on O/P and I/P line and is 1 or input line if an
error is detected in comparison.
Bit 15 Parity bit is sent

In Multiframe mode:
Bit 13 is use for marking multiframe of 32 frames. This bit will
be 31 times 1 and 32nd time “O”. Thus a change from 1 to O marks
end of multiframe.
Bit 14 on output lines it is control bit for multiframe and or input line is
the status bit of the SAB.
Bit 15 reception of One bit of CRC every frame and after 32 frames
32 bit CRC is received.
Functions of various PCBs in SMX.

7.0 Modular expansion from 64 X 64 LR matrix to 256 X 256 LRs by
RCMT boards
(a) 64 X 64 LR
16 LRE R
From SAB C
I
D
R
C
I
D
R
C
I
D
R
C
I 64 LCXE link
D 64LCXS
RCMT Board
16 LCSM 0
64 X 64 64 X 64
16 LCSM 1
64
LCXE R
at 16 16 LCSM 2
C
Mbps S
64 X 64
M
64 X 64 16 LCSM 3
LXE
LXS
FIG. 6 64 X 64 LR Matrix system with one RCMT and one RCSM board
There are 4 64 X 64 LR matrices in a RCMT board as shown.

64 LREs enter the 4 RCID boards in groups of 16 and 64 LCXE links are
derived . Four LCXE link at 4 Mbs/parallel are multiplexed to derive a 16 Mbps
parallel link and at 16 Mbps the contents of Time slots are written sequentially in
the speech memory of RCMT board. After switching in RCMT 64 LCSM links
are received in four groups. The output is buffered in RCSM boards from RCSM
64 LCXS links are read out at 4 Mbps and by parallel to serial conversion again at
the RCID board corresponding to the output GLRs LRs links are obtained.
As shown in the diagram for 64 LRs only one chip of 64 X 64 matrix out
of 4 in the board is used. Others are used when the size of matrix grows. This is
discussed case of 128 X 128 LR Matric (refer figure)
64 LCXE RCMT 0
16
16
16 to RCSM 0
16
16
128 LCSM
16
16
to RCSM 1
16
RCMT –1
64 LCXE
FIG. 7 (128 X 128) LR MATRIX
For 128 X 128 two RCMT boards will be required 64 LCXE will enter RCMT
No. 1 & another 64 LCXE in RCMT No. 2 . By interaid connector the
multiplexed LCXE link (L X S) 1t 16 Mbps from one RCMT is connected the 64
X 64 LR matrix chips in the second column n of second RCMT. Switching
among the 128 LRs are thus possible in the 4 chips of 64 X 64 LR in first RCMT
card only as shown. 2nd card in this case is used only to receive the 64 LCXE
links and multiplexing these in to 16 Mbps LSX link. The interaid is done by a
front connector between two adjacent RCMT board.
Case of 256 X 256 LR Matrix (Refer fig. 8)

The above concept is extended 4 RCMT cards are used and each pair of
cards is connected in such a way that 2 X 128 X 256 LR connection is realised
from two pairs of RCMT.
The same principal is further extended to realise bigger switch sizes.
64 LCXE 64 LCXE RCMT 2

RCMT0
64
64 LCSM
LCSM
64
LCSM 64
LCSM
To 4
RCSM boards
Inter aid
RCMT 1 RCMT 3
64
64
LCSM
LCSM
64
LCSM 64
LCSM
64 LCXE 64 LCXE
Fig. 8 (256 X 256) LR Matrix

Standard Racks
XA00 XA01
ILR (A) ILR (B) ILR (A1) ILR (A2) ILR (A) ILR (B)
SM X A1
SMX A1 SMX (A1)
SMX B1 SMX A2 SMX (A2)
SMX (Ext.)
SMX (Ext.)
For 256 LRs For upto 1024 LR For beyond 102 4 LRs
both branches Each rack will have Requires extension
shelves
in same rack 2 SMXs of one branch to accommodate
additional
So two racks required RCMTs i.e. beyond
for two branches for upto 16 RCMTs
512 LR and 4 racks will
be required for more than
512 LRs
Fig. 9 Standard SMX Racks
Maximum No of rack required for ultimate capacity i.e. all 8 SMXs will be four
per branch..
8. Function of PCBs of SMX

8.1 RCMP:
There can be two RCMP boards in a SMX, viz one in min. shelf and other in
extension shelf. The min, shelf RCMP carries out following function.
(a) Performs majority logic decision on BTT from STS.
(b) Clock distribution to RCID boards, main switch and extension with BSM bus.
(c) Interface with BSM bus.
(d) Serial transmission and reception of information with differential interface
(RCID), main and extension switch.
(e) Generator of alarms towards ACALA board
The extension shelf RCMP carries out :
(a) Ensures retransmission to the boards of its shelf, the serial control link
clock and signals received from main RCMP board
and
(b) ensures retransmission tot he main RCMP board of the serial link
signals received from the boards of its shelf.
8.2 RCID board :
(a) Provides interface between connection units and switch matrix.
(b) Connection security.
(c) Help in fault location for locavar..
(d) Serial to parallel and parallel to serial conversion.
(e) Clock reception and distribution.
8.3 RCMT board :
(a) Time switching of 128 LCXE links to yield 128 LCSM links. (64 LCXE
belonging to itself and 64 received from counterpart through inter aid).
(b) RCMT consists of two 128 X 64 buffer memory blocks. One of the blocks
switches LCXE (0 to 127) lines towards LCSM (0/63) lines and other
switches LCXE (0 to 127) lines towards LCSM (64 to 127) lines.
8.4 RCMS board :

(a) Receives 64 LCSM links at 4 Mbps in four sets of 16.
(b) Sending of 64 LCXS differentially at 4 Mbps to boards of different interface
with sifting at high impedance control for configuration above 1024 LR
(c) Sending of time signals accompanying the LCXS lines to the differential
interface boards if installed in the main switch.
8.5 & 6 ACAJA / ACAJB and ACALA :
boards have their usual function like coupling to token ring and secondary
processing of converter and time base related alarms respectively.
9. Layout of Cards in racks

LOCATION AND RACK ASSEMBLY
(1) Differential interface subrack
(2) Min subrack
(3) Extension subrack
C R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R C
O C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C O
(1) N I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I N
V D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D D V
E 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 E
R 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 R
0 0 1 1 1 2 2 3 3 3 4 4 5 5 5 6 6 7 7 7 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1
0T 5 0 4 8 2 6 0 4 5 2 6 0 4 8 2 6 0 3 7 8 8 9 9 9 0 0 1 1 1 2 2 3 3 3 4 4 5T
2 6 0 4 8 2 6 0 4 8 2 6 0 4 8 2 6 1
C C
O A A A R R R R R R R R R R R R R R R R R R R R R O
(2)
N C C C C C C C C C C C C C C C C C C C C C C C C N
V A A A M M M S M M M M S M M M M S M M M M S M M V
E L J J P T T M T T T T M T T T T M T T T T M T T E
R A B A 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
0T 0 0 1 2 2 2 30 31 40 84 95 26 36 17 0 7 81 48 95 02 02 1 3 61 27 23 43 3 5 T
4
0 6 9 6 0 4 8 2 8 4 8 4 0 6 2 6 2 8 4 0 4 8 6 2 8 2 8 6
C C
O A R R R R R R R R R R R R R R R R R R R R R O
N C C C C C C C C C C C C C C C C C C C C C C N
(3)
V A M M M S M M M M S M M M M S M M M M S M M V
E L P T T M T T T T M T T T T M T T T T M T T E
R A 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 0 1 1 R
T 0 1 0 8 9 2 3 1 0 1 4 5 2 2 3 6 7 3 4 5 T
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1
0 0 0 2 3 3 4 4 5 6 6 7 7 8 8 9 0 0 0 1 2 2 3 3 4
0 6 9 8 2 8 4 8 4 0 6 2 6 2 8 4 0 4 8 6 2 8 2 8 6
Wiring of GLRs and LCXE as viewed from Rear of rack
PARTIAL REAR VIEW OF A SMX RACK

(indicating wiring for GLRs & LCXE Cables)

PARTIAL REAR VIEW OF A SMX RACK

(indicating wiring for GLRs & LCXE Cables)

GLRS
2 0
30
RCID Boards on front side
31
3 1
ILR
SHELF
L L L L L L L L L L L
C C C C C C C C C C C
X X X X X X X X X X X
E S E S E S E S E S E
SMX
SHELF
LCXC TO
OTHER
RAX
R R R R R
C C C C C
M M M M M
T T T T T
9 8 0 1 0
Fig. 11 : PARTIAL REAR VIEW OF A SMX RACK

(Indicating wiring for GLRs & LCXE Cables)
CHAPTER – 6
Auxilary Multiprocessor Station (SMA)
1. Function of SMA
- Tone generation (GT)
- Conference call (CCF)
- Frequency generation & reception for R2 MF signalling or for receiving
DTMF frequencies (RGF)
- Clock
- CCITT 7 signalling management (PU/PE)
- Access network management (AN)
2. SMA Environment
8 LR
SMA
1 GLR
SMX
MAS
to other stations
The SMA is connected to the switch by one GLR (i.e. 8 LR links), On the other
side it is connected to MAS token ring over which it communicates with control
units. A MAL ring collects converter alarms of the station. The time base is
obtained by the SMA from STS via the switch over GLR cable.
3. Functional Architecture of SMA :

A SMA station can provide following functions (O) combination.
- ETA & PU/PE
- PU/PE alone
- ETA alone
- AN (access network) alone.
First two SMAs essentially have GT functions and clock function besides other
ETA or PU/PE functions.
For the above functions and to adapt on token ring different type of
couplers and processors are provided. The functional name and PCB names are
listed below:
- CMP - implemented by ACAJA5/ACAJB5 or ACAJAG ACASB4

- PUP - ACJTR5 AB
- PUS - ACUTR5 AB – Only one PUS
- MC (Common memory) – ACMCS
- Coupler CTSV – i.e. coupler Traitement Signal Vocal or Voice signal
processing couplers.
These couplers are used as GT, RGF, CCF and as psophometer.
- Coupler CSMP - Coupler signalling Multiprotocol for

CCS#7 or V 5.2 signalling implemented by ACHIL 2 & ACHIL 3 PCBs.
The functional architecture is indicated diagramatically below:-
MAS
BL
C P P
C
M U U
M
P P S
BSM
C
C C C L
T T S O
S S M C
V V P K
Max – 12 Couplers
4. Board Functions:
4.1 ICTSH/ICTSS
These cards can perform following functions
(a) Conference call facility - 8 numbers of 4 party conferencing is possible
with following features:-
(i) Add on conferencing with discreet listen in

(ii) Call hold indication
(iii) Making operator call
One ICTSH board can implement 8 such facilities.

(b) Tone generator function : (GT)
This function is for generation of tones like dial tone, busy tone etc. The
frequencies may be single or combination of one two three & four
frequencies with different pauses.
One ICTSH board generates 32 voice frequency signals.
(c) Frequency reception & generation function (RGF).
This function takes care of generation and reception of dual frequencies

used for R2 MF signalling One ICTSH board can implement 8 RGF
terminals and one ICTSS board 16 RGF terminals.
(d) Modulation detection function:

This function carries out supervision of modulation on recorded
announcement time slots. This is processed as a particular RGF code
defined.
4.2 ACHIL 2 Board :

This board carries out HDLC level – 2 functions for 16 channels. There
are two servers carrying out following functions:-
HDLC direction:
Sending - Sending flag, CRC Calculation and “O” insertion
Receiving - Elimination of “O” inserted, flag framing, CRC
verification.
CCITT – 7 direction
Send - Automatic sending of filler frames
Receive - Automatic elimination of filter frames which do not
carry useful information.
4.3 ICHOR Board
This board ensures generation of accurate exchange clock required for
correctly labelling various messages flowing between various units.
4.4 ACAJA/ACAJB card:

This board provides coupling of SMA station with token ring over which
communications is made with control units.
Following type of informations are exchanged:-

- CAS R2 MF signalling
- Status messages and CCS# 7 related messages
4.5 ICID Board (One for each branch of SMX)

- Receptor of 8 LRs and associated time base from RCID board of SMX
and convertion to LA to give to SMA and similarly converting LA link to
LRE toward RCID of SMX.
- Mutual help to extend LR link to counterpart ICID for the purpose of bit
by bit check
- Processing of additional bits on LR
- Selection of time base (4 MHZ)
Distribution of 8 access links (LA)
Case : 1 SMA 1 or SMA 2 with clock, GT, RGF and ACHIL function.
LA 1 - CCF
LA 2 - GT
LA 3 - ACHIL 11 Couplers + 1 Clock (1 CHOR) Coupler
LA 4 - ACHIL
LA 5 - 2 RGFS
LA 6 - 2 RGFS
LA 7 - 2 RGFS
LA 8 - 1 RGF
Case : 2 Where GT & clock are not there i.e. SMA 3 onward.
LA 1 & LA 2 to Two CCF (ICTSH)

LA 3 & LA 4 TO Two ACHIL
LA 5, LA 6, LA 7, LA 8 each to pair of RGFs (Total 8 RGFs)
Total 12 Couplers
SMA Rack card layout:

A A A A A A I I A A I I I I I I I I A I I A
E C C C C C C C C C C C C C C C C C C C C E
5 A A A U M T T H H T T T T T T T T U I I 5
V L J J T C S S I I S S S S S S S S T D D V
L L
4 A B A R S H H 2 2 H H H H H H H H R A B 40
0
1 2 2 3 4 4 5 5 6 7 7 8 8 8 9 9 10 10 11 11 12 14
4 3 9 3 1 7 3 9 5 1 7 1 5 9 3 7 1 5 3 9 5 2
Slot 41 -ACUTR 5 AB - PUP

Slot 53 -ICTSH for CCF
Slot 59 ICTSH for GT in SMA 1 & SMA 2 and
for CCF in other SMA
Slot 71, 77, 81, 85, 89, 93, 97, 101 ICTSH or ICTSS for RGF
Slot 105 either ICTSH/ICTSS for RGF or ICHOR (SMA 1 and SMA 2)
Slot 119 & 125 are ICIDs for SABA & SABB function
TYPE OFRACKS MOUNTING SMA :

UC UE
SMC SMC
SMA SMT
SMA SMT
SMA SMA
& MA SMA
SOFTWARE ARCHITECTURE
Following Software machines in different combination are loaded in SMA depending
upon requirement:
MLSM (P) in CMP

MLSM (ACHIL) in ACHIL board (for level 2 function of CCS # 7)
MLSM (S) + ML PU/PE in PUP for CCS # 7 protocol management
MLSM (S) + MLETA in PUS for ETA function
Firmware for GT, CCF, RGF, etc. or various

CTSV (ICTSH or ICTSS) depending upon
Slot locations as indicated earlier.
CHAPTER – 7
TRUNK MULTIPROCESSORS STATION (SMT)
1. GENERAL :
s
The SMT is a interface for PCM coming from RSU, RLU (E-10 B CSED) and as
junctions from other exchanges.
With the initial supply of OCB-283 exchanges first Generation SMT

(SMT – 1G) was supplied and subsequently SMT-2 G replaced them since no
more SMT – 1 G are existent in the field only SMT – 2 G is included in the
handout. The functions of SMT are same whether it is SMT 1 G or SMT 2 G.
SMT – 2 G is more powerful and intelligence is extended at the PCM terminal
level.
2. Function of SMT:
s
(i) Provide terminations of a maximum of 128 PCM from trunks, CSED
s
and CSND .
(ii) Carrying out URM (Multiplex connection unit function) consisting of :
(a) HDB 3/ Binary code conversion.

(b) Injection and extraction of CAS on time slot 16 and making over to
another functional unit called CLTH for processing.
(iii) Transforming the intelligence in PCM TS to LR T/S for switching to

destinations TS and transforming the switched LR time slot into PCM TS.
3. Specific features of SMT – 2 G :

Beside above mentioned general functions of SMT following special features are
available in SMT – 2 G.
(i) Digital Access cross connect (DACS) where the additionals bits (bit 8 to 12)
s
can be used to carry channel associated signalling for PABX with linked
numbering scheme.
(ii) Can support higher order PCM multiplexes e.g. 34 M bit /S.
(iii) Can support ISDN PRA (30 B + D) links.
(iv) Reduction of load on MIS/MAS by introducing decentralised processes in a
software way.
4. SMT Environment :
s
SMT on one end receives the external PCM which are HDB 3 coded and after
decoding in Binary extends LR links to Switch matrix. For the purpose of
communication with the control stations SMT is connected to MAS token ring.
For reliability reasons SMT logic part is duplicated and there is a link for inter
communication between two logic parts. The timing links for synchronisation
are also derived from some dedicated PCM terminals of SMT. Accordingly the
environment of SMT shall be as shown diagramatically below:
Synch PCM STS

Link LISM
(Receive)
to other
2 Mb HDB 3 logic
LR
Coded PCM
from and to
Logic SWITCH Clock
circuits MAL to
CSND or CSED -------- MATRIX
SMT other stations
MAS
CONTROL
UNITS
Fig. 1 SMT Environment
5. General Architecture of SMT 2 G

The SMT 2 G Comprises following three functional components.
(a) Exchange termination (PCM termination) which is not duplicated.
(b) Control system for processing the CAS, Comprising two processing sub
systems known as SMTA and SMTB.
(c) SAB function one each for issuing LRC links Switch matrix systems
branch A and branch B.
6. Internal Architecture of SMT – 2 G

The internal architecture is as shown in the diagram below. (Fig. 2)
BETP 1 (A)
C S E E E E E E E E
M M T T T T T T T T
BETP 2 (A) 64 PCM
M P T U U U U U U U U
& A 1 2 3 4 25 26 27 28
V
B
A 64 LA
S
A
B
ILSM
S
64 LA S
C S
A
M M BETP 1 (A) B
P T E E E E E E E E
& B T T T T T T T T
V 64 PCM
U U U U U U U U
B
5 6 7 8 29 30 31 32
BETP 2 (B)
(ETU)
CMP A&B, LOGICS AND ETU ALONGW
SAB INTERFACE ALL EQUIPPED IN
ET 1 ETP
TWO SHELVES – REFD. TO AS SMTA S
ET 2 ETP
ET 3 ETP
ET 4 ETP
MULTIPLEX : CONTROLL LOGIC BETP BUS EXCHANGE TERMINAL UNIT SAB INTERFACE
A&B LAPD PROTOCOL (ETU) SUPPORTED BY ICTRQ SUPPORTED BY ICID
ICTSM BOARD 750 Kb/S BOARD EACH ICIDS SUPPOR
S
(DUPLICATED) EACH ETU SUPPORTS 4 ET (PCM) 2 GLR
INTERCHANGE WITH ALONG WITH CORRESPONDING
CONTROL UNITS OVER PROCESSOR (ETP)
MAS THROUGH
PRINCIPAL COUPLER
AND CONTAINS A
COMMN. MEMORY
INTER COMMON BTN. LOGICS
ON LISM LINK IN HDLC
(LAPD at 250 Kbls)
FIG. 2
GENERAL INTERNAL ARCHITECTURE OF SMT – 2 G
-82-
As already mentioned before, the SMT consists of three parts viz. logic part
(duplicate) PCM terminator part (not duplicate) and the SAB part.
Interconnection of the three components are indicated in the diagram.
6.1 The PCM part is implemented on a functional unit known as ETU (Exchange
termination unit) which consists of 4 ET (exchange termination for 2 Mb/s PCM)
s
and 4 ETP i.e. ET processor. Partial processing of PCM & CAS signals is
s
carried out by ETP .
6.2 The logic part is duplicated which on one side is connected to ETU by BETP bus
and on the other side is connected on MAS ring via coupler for communication
with control units.
There are signalling links, Switch over links and PRS (Pilot/Reserve) links
between the two parts of logic.
The information on the PCM Time Slots are subject to a code conversion
i.e. HDB 3 to binary for incoming junction and Binary to HDB 3 for O/G
junctions at the ETU level. The binary coded access links (LA) are connected to
SAB unit which issue a 16 bit LR link toward the Switch matrix.
6.2.1 Processing Subsystem architecture :

As already mentioned before there are two processing system which can
work in pilot/standby mode, normal/back up mode or load sharing mode. Usually
– Pilot/Standby mode is used. The active subsystem is chosen by a

hardwired device supported by the first CLTH (HDLC Trans link coupler)
out of two.
The processing system architecture is as indicated below: (Fig.3)

BETP 1 s
To ETU
MAS BL BETP 2
CMP PUP MC CLTH 1 CLTH2
BSM LISM to
counter part SMT
NB: PUP is optional
CLTH means HDLC Transmission Link Coupler.
(Fig. 3)
6.3 SAB Function Part Organisation

For selection and amplification of branch there are couple of cards for
issue and receipt of LR links for branch A and B towards SMX. The SAB
functional unit is a part of SMX and implemented by hardware housed in SMT.
Entire SMT is broken up into 8 modules referred to as a URM supporting 16
PCMs or 2 GLRs (PCM on external side and GLR towards the switch). A pair of
PCB ICIDS is associated with each UR performing SAB function for branch A
and branch B.
s
2 GLR (E &S)
SA From to SMXA
B i.e. 8 LRE + 8 LRS
2 Mb/S 16 LAE + 16 LAS “A” + timing
4 ETU
per UR at 4 Mbps
i.e. s
16 PCM
s s SA 2 GLR (E & S)
16 ET +
HDB3 B
16 ETP Fig. 4 SAB function
Coded “B”
from & to SMXB
s
There is an inter aid link between branch “A” and branch “B” SAB function card
8 LRE + 8 LR +
for the purpose of receiving the sample of TS on counter part branch so that a
timing
comparision may be possible.
7. Functions of the hardware components of SMT :

7.1 ETU : The ETU i.e. exchange termination unit is implemented on a PCB ICTRQ
and this consists of 4 ET (exchange termination for PCM) and 4 ETP (exchange
termination processor)
This card carries out following functions:
(a) HDB3 – Binary conversion for 120 Ω PCM
s
(b) Looping of PCM viz. external, internal, both side and through
connection. This is done by a connector (4 connectors are provided per
ICTRQ PCB). There is a arrow mark on the connector and type of loop
depends on the direction of arrow as shown below: (Fig. 5)
External Exchange Loop or both Through

loop side loop exchange and connector
external side
Fig. 5 Hardware link for PCM looping
(c) Synchronisation on local call
The time slot contents are received and buffered at the clock rate coming
from other station but are read and switched at local clock rate. The local
clock itself is synchronised with the network by extracting clock from
s
some defined PCM .
(d) CRC 4 :
This cyclic redundancy check is an optional feature and is performed for
s
measuring the transmission quality of 2 Mb/s PCM .
(e) Alarm Processing:

The ICTRQ board has a alarm processing sub function for handling
following type of alarms:-
- F I i.e. fault indication alarm
- Failure of clock by code convertor part
- Frame loss
- Faulty ICIDS etc.
Alarm conditions are conveyed to CLTH for onward relaying to CMP and then to
central defence i.e. SMM for editing and message output on appropriate terminal.
(f) Processing of positioning messages sent by CLTH. The position messages

are:-
- Disabling recognition of signalling transition on PCM link.

- Loop on TS 0 for LA continuity check (refer GLRCT command)
- For CAS looping I/C trunk on O/G trunk
- Trunk assignment control
- Micro controller reset control etc. etc.
(g) PCM – LA Switching
There is no cross connection between PCM T/S and LA T/S. These are
one is to one. A 8 bit to 16 bit conversion is also done at ICTRQ card
level so as to make use of DACS, unlike 8 bit/16 bit conversion by SAB
in other cases.
All T/S except TS 16 and TS 0 are switched through between PCM end to
LA end.
(h) Signal processing:

In case of CAS TS 16 is injected (for O/G calls) and extracted for I/C
calls. The signalling information for I/C calls is made over to CLTH for
forwarding to MR for handling the call. For O/G calls signalling
conditions are conveyed by MR to CLTH via CMP of SMT. CLTH in
turn makes it over to ICTRQ which injects appropriate bits in TS 16 for
onward transmission over PCM. For CCS#7 signalling the ICTRQ card
remains transparent.
The ICTRQ also processes the CAS and semaphore signalling

from CSED of E-10 B.
(i) Synchronisation link for STS

There are defined ETU – ET for deriving timing clock from receive part of
PCM to drive the synchroniser part of STS.
(j) BETP bus management:
BETP is a full duplex point to multipoint bus connecting one CLTH to 64

ETP. In order to ensure communication between only one ETP and one
CLTH a contention system is designed. A ET wanting to send a message
has to claim the BETP bus acquire this and then send the message.
7.2 Processing System :

This consists of principle coupler implemented by ACAJA 4/ACAJB 4 or
ACAJA 5/ACAJB 5,
- CLTH function implemented by two ICTSM boards

- Common Memory implemented by ACMGS board.
The multiplex coupler and memory board functions are already covered
elsewhere.
7.2.1 Function of CLTH (ICTSM board) :
MAS
I/C OCB Messsage

CLTH (ISTSM)
CONFLICT RESOL
PCLTH C
PCLTH 2
MC 68030
68030
CMP ETU
ACAJA /
&B ETP
BETP
SERVES BANK OF ETPS

WITH MULTIDROP MULTIL
Standard OCB Bus
LISM DISREGARDING EACH OTH
COUNTER PART CLTH
TRANSMISSION ARCHITECTURE
• CMP RECEIVES MESSAGE OVER MAS AND ACCORDING TO DESTINATION TRANSFERS IT TO MC.
• PROCESSOR PCLTH EXTRACTS THE MESSAGE FROM MC AND LOADS IN ITS PRIVATE MEMORY.
• PCLTH CHECKS DEST ADDRESS AND TRANSFERS MESSAGE TO PHDLC
• PHDLC THEN CHECKS THE DESTINATION, IF IT IS ETU THEN COLLECTS FROM BUFFER AND TRANSFERS TO E
• ETP INJECTS SIGNALLING (CAS) ON TS 16 OF APPROPRIATE FRAME
NOTE : THE EXCHANGE CAN BE EFFECTED ON CLTH COUNTERPART ON LISM LINK e.g. a MODIFICATION COMMAND LIKE ETUM
FIG. 6 CLTH : HDLC TRANSMISSION GISSION LINE COUPLER (ICTSM B
-88-
GENERAL ORGANISATION OF ETU ( IET + IETP) – ICTRQ
HDB 3 BINARY * RESYN RECPCMON * SYNCH MUL. FR.
CALCULN. OF CRC 4 LOCAL TIMER * SIGN. INJ/EXTRN.
AND INJN. ON TRANS * RETRIEVAL OF ALM * DETN/CONFN OF STATUS TRANSITION
AND CRC 4 * TRANSFER OF DACS SIG ON LA
* FR. & MF ATRANS.
* LINE QUALITY MONTR. TO
LOOPS
PCMR LRE
:: MTRB
TRANS-
MSJB
RESYNCH
SIGNAL
PROCESS-
SAB
INTER
PCME
:: CODING ING -FACE DT
:: LRS
(ET PART)
OSCILLATOR
µ BUS
128 Kb
REFROM
BETPEDA I TO
BETPECA H C L MAS
ETP D T L VIA
128 Kb MICRO BETPEDA L S T CMP
RAM CONTR- CONT. C M H
OLLER BLKG
BCA
16 bit LISM
µ CONT. CONTAINS – ADD RESET
PRS
• 3 HDLC CONTROLLER BCB
• 3 TIMER I
8 bit CONT. H C C TO
(WATCHDOG/PROGMBL DATA MAS
BLKG D T L
REAL TIME INTRPT. BETPRDB VIA
• INTERRUPT CONTROLER L S T CMP
68302 BETPRDB C M H
• PORTS/ADD DECODING
BETPECB
GENERATES TIMER FOR
MTRB
REC. TIME SIG FROM SAB (ETP PART)
REL TIME SIG FAB
BETP FROM CLTH
& EXTL PCM TIMER FROM
REC PCM
BLOCKING /REINSTATEMENT FUNCTION

• TO RECOGNISE BLOCKING/REINST FRAME AND ACCORDINGLY BLOCK OR REINSTATE TR
AMP AND RESET µCONTLR WHEN A BLOCKING FRAME COMES FROM CONLLOG
MANAGEMENT OF CONTAINMENT BUS
• DETN. OF FREE STATUS ON CONT. BUS

• PUTS A CLAIM TO ACQUIRE BETP BUS ON RECEIPT RES (FROM HDLC (CONTLR)
• ON ACQUIRING BUS ENABLES BETPRO AMPLIFIER
• SENDS A CTS SIG. TO HDLC CONTRLR TO ENABLE TRANSMISSION OF HDLC FRAME.
WHEN A ET WANTS TO COMMUNICATE WITH LOGIC CORRESPONDING ETP FIRST LOOKS FOR P/R
STATUS, THEN LOOKS FOR STATUS ON CONFLICT RESOLVING BUS. IF BUS IS FREE THEN ACQUIRES
IT AND SENDS THE HDLC FRAME.
FIG. 7 CLTH – ETP COMMUNICATION

This board is organised around a 68030 CLTH microprocessor (PCLTH)
having a 4 Mb DRAM and BSM interface. There is a second microprocessor in
this board known as HDLC microprocessor for supporting ETP interfacing over
BETP bus.
Messages related to signalling from MR are received by PCLTH through

common memory.
PCLTH after checking address of destination transfer this to PHDLC.
PHDLC checks the address. If the address is for a ETU then transfers the
message in HDLC format to the ETU.
The other functions supported by CLTH are:-
- Inter SMe dialogue : For this the first ICTSM board is

linked to its counterpart by a HDLC link known as LISM
link.
- SMe switch over management device implemented only on
the first ICTSM.
Transmission architecture in CLTH is shown diagrammatically in Fig. 6. Fig. 7

explains the communication between CLTH & ETP
MESSAGE FLOW FOR NEW CALL
(THROUGH VARIOUS LOGICAL MACHINES)
MLMR MAS CMP MLURM (P) MLURM (S) ETP
IN LAPD
Cct. NO. &

New call ON status
Cct.. or CIC NO.
MSGE PREPARED
TRANSITION
FROM
PHDLC
TO
PCLTH
NB : ACCORDING TO TTC TABLES (information related to tele call set up

THE MLURM (S) DECIDES THE on the basis of int/ext. past events
NATURE OF MESSAGE e.g. OFF/ON HOOK call status at any point of time is
OR DIGITS etc. in TTC and transactions are
decided accordingly)
• JOB OF MLURM (S)
FIG. 8
7.3 Functions of ICIDS board :
- Interface for LAS sending to ET and LAE receiving from ET.
- Receipt of timing distribution signals H 4 M and SBT from the RCID
boards of the host switching matrix (MCX).
- Interface for timing distribution signals DH 4 M and DSBT between the
boards of the SMT and MCX.
- Branch selection on LRS channels, based on parity fault with choice of
branch dictated by MCX.
- Resynchronization on 16 LRS (in groups of 8) originating from the two
MCX branches and transmit mode amplification of the 16 LRE (in groups
of 8) to an MCX branch.
- Backup links on 16 LRS between the two branches of the MCX.
- Processing of the three control bits crossing the LRE and LRS.
Recognition of parity faults and check multiframes on request.
- Implementation of the LR link loop back function for LOCAVAR
purposes.
- Implementation of the LA link loop back for LOCABAR purposes with
regard to TMIC (LAE to LAS loop). Loop back controlled by a
positioning signal from the TMIC and operates in the space domain
(looping the entire link). To minimize the equipment needed for the loop
back function, it is initiated with timeslots rearranged (offset).
NOTE: The ICIDS boards are entirely independent of the ACTIVE/STANDBY

concept, which remains an operating mode affecting only the control
system, if adopted.
8. Physical form of SMT – 2 G: (The physical connection of components of

SMT on BSM is shown in the diagram.
PCM
ICTRQ
A A BETP
I I I
C C Buses
C C LA C to
A A T T I SMX
J J S S D LR
B A S
M M
BSM
Fig. 9 (Physical architecture of SMT – 2 G)
9. SMe Switch over :

There are two switch over modes :
(a) Forced switch over – Calls being set up are lost.
(b) Controlled switch over – No calls are lost.
The switch over is always activated by Active SM.

Forced switch over is controlled by CMP in response to serious hardware fault in
the station controlled switch over is always activated by program.
10. Software Organisation :

Just like other stations the application ML are supported on a basic
software (Hypervisor) and on the system software.
The hypervisor allows cohabitation of more than one ML on same

agent, and carries out following:
- Communication within the station

- Management of time lags
s
- Processor sharing by different ML .
Supervisor in each agent takes care of elemental tasks.
The applications are :-
(i) MLSM (P) loaded in CMP.

This carries out positioning, defence, audit security and communication.
(ii) MLSM (GETU) loaded in CMP

This carries out the management of ETU
(iii) MLURM (P) - Main component of MLURM loaded in CMP.
This carrier out

- Communication with control units
- Context Management
- Timing Management
- Handling UR/TS/EQ/LR positioning
- CSED positioning]
- UR-PCM extension
- Observation
- Initialisation of exchange date
- Traffic migration inch
- Regeneration
1. MLURM (S) secondary component loaded on CLTH carrying out
- Processing of TTC tables

- CCS#7 processing
- Inch of PRS configuration
- Switch over supervision
- Regeneration, alarm processing PCM & CRC4.
CMP (ACAJB/ACAJA)
ML (GETU)
MLURM (P)
Supervisor
Hypervisor
HYP HYP
CLTH 1 CLTH 2
(ICTSM) SUP SUP (ICTSM)
MLSM MLSM
(CLTH) (CLTH)
MLUR MLUR
M (S) M (S)
LAPD LAPD
Comm. Comm.
ETP ETP
Fig. 10 Software Architecture
Fig. 8 Indicates message flow for a new call, while passing

through various logical machine functions.
Chapter 8
Maintenance Multiprocessor Station (SMM)
1. ROLE : The SMM provides the facility for carrying out operation and mtce. of
OCB units and also manage the data base.
1.1 It carries out following functions:-

(a) Data base management and storage (secondary)
(b) Central defence of the OCB system
(c) Supervisor of token rings
(d) Processing of various commands
(e) General initialisation of the exchange.
It provides local link for data processing devices and administration terminals.
This can also be connected through X-25 link to a network management system
(NMS).
2. SMM ENVIRONMENT :
In order to carry out the function mentioned above the SMM should be accessible
to exchange units on one side and to the dialogue peripherals on the other side. The
SMM should also have access to mass storage devices for storage of data. Accordingly
the environment shall be as indicated below
Fig. 1
SMT SMX SMA
MAS (1 to 4)
SMC 1 SMC 2 n
SMC
MIS
TERMINAL BUS SCSI BUS

SMM
(Duplicate)
Alarm
ring Mag tape with
(MAL) DISK A&B Streamer coupler
X – 25
with (Optional
Synch with coupler
links V 24 coupler
for TMN asynch
links
For Fig. 1 (SMM Environment
dialogur
terminal
via
suitable
coupler
3. HARDWARE ARCHITECTURE :
The SMM consists of two processing subsystem. One acting as pilot and other as
a hot standby. Both systems share a common communication bus supporting various
communication peripherals and common SCSI bus for access to mass storage devices.
The two subsystems are referred to as SMMA and SMMB.
The overall, hardware architecture is indicated below in (fig. 2) and Fig. (3).
AD=0 AD=1
Disk.
(*)
AD = 0
Disk.
MTU
A A A
C C
MIS B B B MIS
A B S S B A
G G
AD=0 AD=1
Disk.
(*)
AD = 0 A
A A A
A A Disk. C
C C C
C C Stream A A-
A- B A
A C J
J B S J
J S A B A
B G B
A G S
B G
SCSCI bus
XBUS XBUS
A A A A A A A A
C U C U C C C U C U C C
F T M T M C C T M T M FT
T G G S S G G D
D S S G G S S
Local bus Local bus Local bus Local bus
From/to Terminal BUS B

From/to Terminal BUS A
-Processing units- SMM
SMM
(*) optional
Disk. = ACCDT (380 Mb) or ACDDG1 (1.2 Gb)
Stream = ACST2 (525 Mb) or ACSTG1 (1.2 Gb)
UT = ACUTG or ACUTG 2
Fig. 2 SMM HARDWARE ARCHITECTURE (X-Bus & SCSI bus components)

to SMM A
to SMM B
A A A
C C C
J T R
6 U A MAL
4 J L
2
A A A
C C C
A A A
links Async Alarm L L L
J 64 V 24 multiplex A A A
(4) (8) MAL
16
16
A1
A1
1 or 2 1 to 4 1 to 2
1 ACALA 1 ACALA
for each SM (Terminal bus/
1 or 6 streamer)
- Lime Couplers -
Fig. 3 SMM hardware architecture (Terminal bus Components)

4. PROCESSING SYSTEM :
The processing system comprises following functional component connected on a

common bus referred to as the X-bus.
(a) Processor – Memory pairs (ACUTG 2 – ACMGS)
These boards support the RTOS operating system and application software
running in SMM. The ACTUG 2 board is built around Motorolla 68030
processor (40 MHZ) with 16 mb private RAM. ACMGS is a 16 Mb RAM. This
can be addressed on 4 G bytes by X-Bus on local Bus (BL).
One to four such processor memory pairs can be provided depending upon
amount of processing required.
(b) Duplex Coupler – ACCSG board:

This is the board that provides communication between two subsystems and also
provides keys for carrying out different modes of initialisation and reset. This
also provides for connecting assistance console terminals.
This board is also responsible for control of locavar on stand by SMM system.
(c) Terminal Bus Coupler or Communication coupler – ACFTD :

This coupler supports the input output processor. The operating system of this
board (SYSPES) enables handler software to perform terminal bus line
management functions. The terminal bus issued by the ACFTD board can
support X 25, V 24 links and alarm link. For different communication protocol
different handlers are provided.
(d) SCSI Coupler – ACBSG board :

ACBSG board supports complete input/output software for SCSI bus. ACBSG
also has ROM – resident software controlling SCSI access, used when initialising
processing unit. There are two ACBSG boards, each supporting two SCSI
buses. The mass storage devices like hard disks, streamer and mag tapes are
connected to these SCSI buses through appropriate couplers.
(e) MIS or Secondary Coupler – ACAJA/ACAJB

These are usual coupler for coupling to MIS token ring.
9 Console functions:
The console function consists of some physical keys and lamps on the ACCSG
board edge strip and the PCB. These are :
Switch V 1 : middle position – normal lower position for automatic RTOS startup
Switch V 2 : up position temporary reset middle position is normal lower position
is for permanent reset
Switch I 1 : up position for manual start & down position for automatic start
Switch I2 : relevant only when I 1 is down i.e. if. It is up with I1 down and a
reset is given by V2 up then OM & exchange both will initialise and If
I2 is down with I1 down and reset is given then only OM will initialise with
through connection to exchange.
lamp D 1 when lit indicates pilot system
D 2 when lit indicates RTOS loaded in system.
It addition to these keys there are two more physical keys V 3 and V 4 on
a DACLE mini board placed behind ACCSG board in the back panel.
Switch V 3 up position is the idle position middle position (stable) defining sub
system always master. lower position (instable) indicating sub
system is master.
Switch V 4 up position is idle indicates manufacture absent mid position (stable)

and lower position (instable) indicate manufacturer present.
6. LOGICAL KEYS
Beside the physical keys there are a set of 48 logical keys. 16 keys are
dedicated to RTOS, 16 keys are divided between RTOS and TMNK, sixteen keys
are dedicated to OM. The logical keys can be set in assisted mode (V 1 down)
from console and in RTOS environment by MMC from WAM. Normal setting of
these keys is Zero but depending upon requirement. These can be set. Some of
the key settings are defence of the system. Only with the V 3 switch set to
manufacturer present state the dangerous keys can be set.
7. LINE COUPLERS:
Besides the X-Bus components there are different line couplers for
different type of peripherals.
The peripherals used are –

TTY, CV, IR & WAM type of terminals. These type of terminals are connected
to asynchronous lines derived from ACTUJ boards. One ACTUJ board gives
eight asynchronous lines. A max of 48 asynchronous line can be derived from a
max of 6 ACTUJ board. ACTUJ board consists of an EPROM (for self test and
code loading function via terminal bus) and a coupler software on ACFTD board
of X-Bus supporting the terminal bus.
Other peripherals could be computers at NMS connected to SMM over 64

Kbps X-25 links. These links are derived out of PCB ACJ64. One ACJ64 card
can support 4 synchronous links. The ACJ 64 boards are connected or terminal
bus supported by ACFTD board. In new supplies ACV11 board is being supplied
which has inbuilt modem.
In addition to the synchronous and asynchronous line couplers the

terminal bus also supports MAL rings through line coupler ACRAL 2.
8. Alarm processing function : Just as other stations SMM also has ACALA
board one in each system to take care of convertor alarms in main shelf and for
streamer also.
9. Mass storage Devices:

The following mass magnetic storage devices are placed on the SCSI bus
derived from ACBSG boards. These devices are used for data management and
loading.
9.1 Hard disk (ACDDG 2)
This PCB is an integral PCB supporting a coupler to SCSI bus and disk drive. The
disk capacity supplied at present is 4 Gb or 10 Gb. There are two hard disks supported
on different controllers of SCSI bus and physically mounted in the SMMA and
SMMB shelf. These are known as DISK “A” and DISK “B”.
9.2 Quarter inch Streamer (ACSTG 2)

<
This PCB also is an integral PCB supporting a streamer drive and its controller for
SCSI bus. This is generally used for initial loading of software and also during
upgrades.
9.2.1 Magnetic tape units:
This is an optional item of provided, there will be two mag tape units with
controllers for SCSI bus inbuilt and mounted on a separate rack. Mag tapes are
used for data management and for storage and processing of bulk billing and
detail billing data. At present with release R24 mag tapes are not being supplied
but mag tape management functions are still in use for which one hard disk
partition has been ear marked to function as a mag tape and referred to as external
support LFNE = DGMA.
10. DEFENCE :
10.1 Hardware defence :
Hardware defence is provided by duplication of SMM subsystems. In case of a
fault in the working system stand by is made operational and a locavar is initiated
on the faulty one.
10.1.1 Software defence :

A supervisor software keeps on watching the activity of other software sets
loading and presence and keeps track of malfunction messages transmitted by
these. In case of a major failure switch over or reinitialisation is initiated. In the
event of a major problem in the pilot subsystem a post mortem dump (PMD) is
generated and possibly reloading of faulty system.
11. Position of SMM in the rack:

The hardware of SMM is provided in three shelves on a CA type of rack. The top
two shelves accommodate one SMC and STS respectively. Shelf No. 3 and 5
contains the X-bus components of SMMA and SMMB respectively and these
shelves are known as ABUTP shelf. Shelf No. 4 partly accommodates the
infrastructure alarm couplers and recorded announcement system card and partly
contains the streamer and other line couplers. Shelf No. 4 is known as ABLAS
shelf.
A second rack known as DBM rack adjacent to CA rack accommodates a couple

of magnetic tape units. The SCSI bus is extended from first rack to second rack
for connecting mag tape. The DBM rack is optional and with current supply
DBM is not being supplied.
The rack layout and the card allocation in ABUTP and ABLAS shelves
are indicated below (fig. 4, fig. 5 and fig. 6)
MEB/PEB
SMC
STS
ABUTP (SMM A)
ABLAS or Streamer &

SSE
ABLAS 2 announcement Terminal bus
machine
ABUTP (SMM B)
ABLAS subrack (for CAO2) = SSE (infrastructure alarms/rack lamp panel controls) +
announcement machine and streamer + terminal bus with 4 ACTUJ + 2 ACJ64
ABLAS2 subrack (for CAO3) = same as ABLAS excepted for terminal bus where 6
ACTUJ can be fitted (or 2 ACJ64 + 4 ACTUJ)
ABUTP subrack=SMM A or B + SCSI devices (other than the steamer)
Fig. 4 SMM Rack layout (CA – rack)

BACKPLANES
The ABUTP subrack has two back planes :
- one AFUTP backplane connecting the boards of a processing unit with its
converter and its ACALA board and two ACDDG1 (or ACDDT) locations.
- one AFALI backplane connecting one or two AE12V boards and an AE5V40
converter (see next section).
- ABUTP SUBRACK-
A A A A A A A A A A A A A A A A A A A A A A
E C C C C C C C C C C C C C C C C C C E E E
5 A A A U MU M U M U M B B C F F D D 1 1 5
V L J J T G T G T G T G S S S T T D D 2 2 V
4 A B A G S G S G S G S G G G DD G G V V 4
0 1 1 0
. . . . . . . . .
AFUTP AFALI
(ACUTG = ACUTG ou ACUTG 2
FIG. 5 SMM or SMMB SUBRACK WITH X-BUS COMPONENTS AND ONE HARD DISK (ABUTP)
In CA02 rack
The ABLAS subrack has three backplanes :
- one AFMML2 backplane connecting the line coupler boards
- one AFMPS backplane connecting the ACST2 (or ACSTG1) streamer, an
ACALA board marshalling the subrack alarms and where applicable the two
announcement machine boards.
- 1 AFMMA2 backplane connecting the SSE boards.
-ABLAS SUBRACK-
A I I A A A A A A A A A A A
C C C C C C C C C C C C E E
A M S S J J T T T T R R 5 5
SSE L P M T 6 6 U UU U A A V V
A N P (2 ou 4 4 J J J J L L 4 4
2 G 1) 2 2 0 0
. . .. ... .
AFMMA2 AFMPS AFMML2
FIG. 6 SMM sub rack with line couplers (ABLAS)

12. SMM Software :
12.1 SMM software is composed of :

- Basic operating system RTOS
- Administrative Exploitation system (AES)
- Station Alarm Interface ( 1AS)
- Supervisor
- OM application software
- Software for TMN connection
- System and telephone application
RTOS
Fig. 7 Software organisation
12.2 Functions of RTOS

- Task and event Management
- Clock Management
- Inter processor communication
- Duplex function management through link between the two ACCSG
boards, e.g. Data update and SMM switch over.
12.3 Function of AES :

This software (RTOS application) enables to carrying out operation and mtce. of
SMM by using MMC from specific terminal referred to as PCWAM e.g.
s
LOCAVAR on SMM X-Bus and other PCB and Physical disk management etc.
can be carried out from WAM using the AES part of RTOS.
12.4 Function of software IAS :

This is again a RTOS application for managing alarms. This application actually
keeps watch on State of Boards in different units of OCB and in the event of
change of state gives necessary input to OM for issue of appropriate alarm
message.
12.5 Function SUP Software:
This is again a RTOS application incharge of global defence i.e. Thus in case of
a likely switch over of SMM this RTOS application should give suitable
indication to an application wanting to use RTOS. The likely switch over might
be initiated by either RTOS or another application.
12.6 Function of OM application software:
This is the main software used to carry out operation and maintenance on
exchange units. This consists of a subs system of operation and maintenance
(SSOM), system application and Telephone applications.
The SSOM basically comprises various handlers like:
CWT : for clock Management
QTC : Queue Management
REC : Programme executor
PLT : Loading from DISK to RAM
DCT : Disk Management
TCT : Mag tape Management
LCC : Exchange command Management
LCT : Terminal communication Management
SER : Service console Management
12.7 System and Telephone application functions :
12.7.1 . Telephone Application : Subs Management
Translation & routing
Trunk circuit Management
Charging Management
Observation Management etc.
12.7.2. System Applications Comprises: Equipment Management
Fault/Alarm Management
Locavar Management
Terminal Management
Data Management
12.8 Function of TMN :

The contains different type of Software to enable Management of exchanges from
a common node i.e. Telecom Management Network centre.
The various software components of SMM as also copy of data of various units of
OCB are all loaded on hard disk of SMM. For this the hard disk is divided in
number of logical partitions referred to as logical disks (DL). There are as many
as 60 partitions on the disk at present.
The logical disks are exactly alike in the two hard disks i.e. DISK ‘A’ and DISK
‘B’ but physical disks are not same and not interchangeable. A disk defined as
disk ‘A’ must be put in the position marked for disk ‘A’.
Some of the logical disk are for the RTOS and others for different applications
and some are for exchange data, secondary storage.
CHAPTER –9
SYNCHRONISATION AND TIME BASE STATION (STS)
1. This is the clock system of OCB-283 system which happens to be the most vital
unit of any digital switching system as switching takes place at the strobe of
clock. Since all modern switches not only switch voice but also picture graphics
and other data, the clock needs to be synchronised with the network. This
ensures almost a common clock at every switching station. The clock system in
OCB-283, therefore consists of two parts i.e. synchronisation part and time base
generator part.
2. Functional Components of Clock System & their Role

The clock system consists of.
2.1 HIS Synchronisation system implemented by two RCHIS PCBs working on

mutual exclusion. The synch interface carries and following functions.
2.1.1 Receives MAX 4 clock inputs from PCMs commg. from other exchange (higher
level) selects one of the PCMs as basic input on the basis of a defined crithrian
(usually first priority goes to first PCM and so on) and tries to phase lock its clock
with the clock of chosen PCM.
2.1.2 In the event of a error detected on the chosen PCM it shifts to other PCM and
gives alarm concerning the faulty PCM.
2.1.3 It maintains reasonably high quality of clock in terms of precision of frequency

irrespective of the quality of Synchronisation links.
2.1.4 Counteracts losses of all Synchronisation links by very high stability oscillator.
2.1.5 In the event of loss of PCM Synch runs on free run mode.
2.2 Triplicate time base (BTT) carries out following functions:-
2.2.1 BTT is driven by Synchroniser and distributes the clock to the switch.
2.2.2 In the event of loss of synch. BTT is capable of maintaining stable clock over a
reasonably.
LSRX
LCAL
To SMXs
3 X 16 Supplies
S branch ‘A’
M STS and
T branch ‘B’
PCM LH8M
LSBT
LMES
ALARMS
Fig. 1 Environment
3. STS Environment :
The location of STS with respect to other OCB-283 units is indicated
diagramatically in Fig. 1.
The STS has following links in its environment.

3.1 Reception:
3.1.1 1 to 2 LSRX (one for each synch unit from high stability caesium clock (optional)
3.1.2 1 to 2 LCAL links (one for each synch unit) at 5 MHZ for calibration (resetting)
3.2 Transmission:
3.2.1 48 LH8 M/LSBT
Each BT at the output gives 16 LH8M links at 8192 KHZ and 16 LSBT link at 8
KHZ for Synchronisation of trainees. This is given to switch matrix.
3.2.2 1 to 2 LMES links (1 for each synch.) for frequency measurements of synch pilot.
3.2.3 Alarm link to the MAL.
4. Functional Architecture:
There are two functional level of STS viz :
HIS - Synchronisation level which is duplicated with priority to HIS.
BTT - Triplicated time base giving clock to the entire system irrespective of
whether HIS is operational or not.
5. Hardware implementations:
STS comprises two RCHIS boards and 3 RCHOR board with one converter for
each RCHIS and RCHOR.. Besides these there are two ACALA board for
processing of alarms in the HIS and BTT parts.
DH4M
3
DSY8K 1
3 1
DMSY
6
RCHOR1 16
LCAL 3
DLSRX RCHIS0 1
‘DLSR
‘DLVR 5 1 1
4 1 6
LCM DSY8K RCHOR1 16
DMSY
4 4 3
1
1
RCHIS1 5 1 6
DLSRX 16
RCHOR2
LCAL 1
5/
3
LMES AHIS 1
FHIS 1
DH4M 3
MSHIS1
6/
NFLSR 1 NFH 1
NFLSRX NFHIS0
ACALA
ACALA
AHIS0
FHIS0
NFHIS1
MSHIS0
NMSEXT
CONVERT
3,4
5 9
ALARM RING
ALARM RING
Fig. 2 Architecture of STS station

CONVERTER 4
pos 144
CONVERTER 3 134
HIS backpanel ACALA 1 130
RCHIS 1 110
RCHIS0 084
RCHOR 2 pos 064
RCHOR1 052
RCHOR 0 040
BTT backpanel
ACALA 0 028
CONVERTER 2 019
CONVERTER 1 010
CONVERTER 0 001
Fig. 3 STS station sub-rack assembly

STS is mounted on a CA rack in the position of the second shelf.
5.1 Function of hardware components of STS.
5.1.1 RCHIS Board.
- Deliver a reference frequency to ensure RCHOR and BTT board
Synchronisation in the presence or absence of Synch links.
- Monitor the quality of Synchronisation links with respect to cuts,
frequency jumps frame alignment loss, Error rate etc.
- Allotment of next best quality PCM link for Synchronisation on failure of
highest priority link and return to highest priority link or restoration of
PCM.
The priority order for Synchronisation is LCAL, LSRX – LSRO-LSRI-LSR2-
LSR3
- Filtering of jitter
- Generate alarms related to quality of LSRX and LSR links.
- Generate visual signal on edge strip of RCHIS board.
5.1.2 RCHOR board:
- To deliver faithfully 8.192 MHZ clock and clock synch link (DLH8M-
DLSBT)
- Ensure clock supply inspite of failure of one RCHOR and identify the
faulty board.
- Generate alarms related to clock and HIS>
- Generate visual indicator related to alarms on edge strip of RCHOR board.
5.1.3 ACALA board:
There are two ACALA board One ACALA processes the alarm related to
RCHOR and its converters and second related to RCHIS and its
converters.
6. Operating Regimes of STS :

The operating regimes depend upon various factors like :
- Operating Regimes of STS link missing
- HIS faulty or out of service
- RCHOR faulty or out of service.
The following regimes are automatically generated by STS>
6.1 Normal synch regime:

STS is synchronised with one of the several synch links like LCAL, LSRX or
LSRO to LSR3.
6.2 Normal independent regime

In case of loss of synchronisation (i.e. missing of external synchronisation links..
The RCHIS contribute to give out the last memorised frequency and drives the
RCHOR.
6.3 BTT regime :
The RCHIS no longer drives the BTT but the RCHORs continue to deliver the
last memorised frequency at the time of faul in RCHIS.
6.4 Free Oscillation Regime :
The STS is used with the synchronisation links. The frequency delivered is that
generated in free run mode of the RCHOR. The frequency stability is defined by
factory calibration.
7. Identification of the input and output links

7.1 HIS : reception
- 4 DLSR 0 to 3 links (2048 KHz) and 4 DLVE 0 to 3 links (for validation)

common to the 2 HIS
• DLSR : synchronous differential reception link.
• DLVR : validation differential reception link.
- 1 to 2 DLSRX links (0 for HISO and 1 for HIS 1) at 2048 KHz.
• DLSRX : external synchronous differential reception link.
- 1 to 2 LCAL links (0 for HISO and 1 for HIS 1) at 5MHz.
• LCAL : Calibration link
- DHAM link (0 to 2) at 4096 KHz sent by BTT.
• DH4M : clock differential at 4.096 MHz.
- 1 5 MHz LCM link (0 for HISO and 1 for HIS 1) sent by other HIS.
• LCM : mutual control inks
7.2 HIS : receiption

- 3 DSY8K 0-2 links (8 KHz) and DMSY 0-2 (validation) to BTT from
each HIS.
• SDY8K : 8 KHz synchronous differential.
• DMSY : non-synchronous differential
- 1 5 MHz LMES link ( 0 for HISO and 1 for HIS 1)
• LMES : measurement link
- 11 alarms to ACALA board from HIS modules.
• HISO and HIS 1 sends :
- NFLSRi : LSRi (i = 0 to 3) no fault,
- NFLSRX : LSRX no fault
• HISO sends :
- AHISO : HISO alarm
- FHISO : HISO fault
- MSHISO : non – synchronous HISO
• HIS 1 sends :
- AHIS 1 : HIS 1 alarm

- FHIS 1 : HIS 1 fault
- MSHIS 1 : non – synchronous HIS 1
7.3 RCHOR : reception
1 DSY 8 K link and 1 DMSY link for each HIS
7.4 RCHOR : transmission
1 4096 KHz DH4M link to each HIS.
• DH4M : 4.096 MHz clock differential
16 8192 KHz DLH8M links and 16 DLSBT links at 8 KHz.
• DLH8 M : 8.192 MHz clock differential link
• DLSBT : time base synchronization differential link
6 alarms to an ACALA of BTT module.
• NFHISO : non-clock fault (i= 0 to 2).
• NFHISO : HISO no fault.
• NFHIS 1 : HIS 1 no fault
• NMSEXT : external synchronization present.
7.5 ACALA board for HIS module

This board receives alarms from HIS and 2 converters (no 48 and + 5 V, over
current)
It sends these alarms on an alarm ring.
7.6 BTT module ACALA board

This board receives alarms for 3 RCHOR boards and 3 converters (no – 48V and
+ 5V, over current)
The board sends all these alarms on an alarm ring.
8.1 Visual signalling on HIS module
D1 AHIS R 0
D2 MSEXT R 0
D3 LSRX/LCAL G 0
LEDs ON CONNECTING STRIP
D4 LSR / LCAL G 0
RCHIS BOARD (RCHIC + RCHIP)
V1 INT A C 0
AR AS RAP 0
LEDs ON BOARD
LX LSRX G 0
L3 LSR3 G 0
L2 LSR2 G 0
L1 LSR1 G 0
L0 LSR0 G
G
D1 red : -steady
FIG . 4
= HIS alarm
-flashing = HIS alarm by manual deactivation
D2 red: -steady = no HIS external synchro (free oscillation)
D3 green: -steady = synchronization on LSRX
D4 green: -steady = synchronization on LSR
D3/D4 : -flashing = synchronization on LCAL (external calibration)
V1 INTER : -momentary high position
= activates sequence for reinitialization of configuration
(definition of synchronization link priorities)
- middle idle position
= normal operation
- permanent low position
= manual deactivation (conditional)
AR green : - steady = rapid control status
LX green : -steady/flashing = active LSRX input
L3 green : - steady/flashing = active LSR3 input
8.2 Visual signalling of BTT module
0
D1 FHO G
0
D2 FH1 G
0
D3 FH2 G
0 LEDs ON CONNECTING STRIP
D4 MSEXT R
V1 FHIS1 G
V2 FHIS0 RCHOR BOARD
G
Fig. 5
D1 green : -off = clock error on RCHORO

D2 green : - off = clock error on RCHOR1
D3 green : - off = clock error on RCHOR2
D4 red: -lit = lack of external synchronization on BTT (free oscillation)
V1 green : -off = no HIS 1 synchronization

V2 green : - off = no HIS 0 synchronization
CONVERTER 4
pos 144
CONVERTER 3 134
HIS backpanel ACALA 1 130
RCHIS 1 110
RCHIS0 084
RCHOR 2 pos 064
RCHOR1 052
RCHOR 0 040
BTT backpanel
ACALA 0 028
CONVERTER 2 019
CONVERTER 1 010
CONVERTER 0 001
Fig. 2 STS station sub – rack assembly

DH4M 3
DH4M
31
LSMP
DSY8K 1
DSY8K 3 1
DMSY
DMSY 1 6
3 16
LCAL 1 RCHOR0 ‘DLHBM
DLSRX RCHIS0
‘DLSBT
‘DLSR 4 5 1 1
1 6
‘DLVR LCM DSY8K 16
RCHOR1
4 4 DMSY 3 ‘DLHBM
1 ‘DLSBT
5 1 1 6
RCHIS1 16
DLSRX RCHOR2
LCAL 3 5/ 1 ‘DLHBM
‘DLSBT
LMES AHIS 1
FHIS 1
DH4M 3
MSHIS1
6/
NFLSR 1 NFH 1
NFLSRX NFHIS0
ACALA
ACALA
AHIS0
FHIS0
NFHIS1
MSHIS0
NMSEXT
CONVERT
3,4
5 9
ALARM RING
ALARM RING
Fig. 3 Architecture of STS station

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Chapter –1

General Architecture of Digital Switching System

Subs access inter face

Other auxiliary inter Operation & Mtce. system with

A brief description of the components is given below:-

1.1 Subs access interface:

1.3 Auxiliary interface :

(a) Tone generation e.g. DT, BT, RBT NU etc.

The main control function are :-

Other control functions could be controllers for connection, message

The various control processes may be centralised or distributed depending upon

2. The Switch : A digital switch of different configuration e.g. a pure Time

3. OM functions : A general purpose computer is generally used with dedicated

4. Additional Features in new Switches:

FUNCTIONAL ARCHITECTURE OF OCB – 283 SWITCH

1. The functional architecture : The main functional blocks of a OCB-283 switch

Operator & Mtce

Communications multiplex (MIS)

Fig. 2 (OCB 283 Functional Architecture)

2.2 Host switching Matrix (MCX)/Switch Control Function “COM”

2.3.2 CCS # 7 Protocol Manager (PU/PE)

2.3.3 V 5.2 Protocol Handler : The signalling protocol between an access

2.4 Call Handler “MR”

Besides MR function there is one CC (Call Contorl) function which again

2.5 Data Manager TR:

2.7 Matrix handler (GX)

(a) request for connection and disconnection from MR or MQ (marker).

2.8 Message Distribution function (MQ) marker:

2.9 PCM controller (URM) :

- HDB3/Binary code conversion

OM function further provides features for saving detail billing/ bulk

The OM function possess a two way communication path with the

2.11 Subscriber access function :

Hardware architecture of OCB-283 Switching Systems

For this purpose functions are classified as under:-

1. Subs access functions

A detail description of subs interface provided in OCB shall be discussed

3. Control functions – Concept of station

Following type of stations are available:

3.4 SMC : Command or control multiprocessor station.

4. GENERAL CONCEPT OF A STATION

A station in OCB is a hardware unit consisting of number of processors and

The diagram shows structure of a SMC type of station Fig. 1

CMP : Principal Multiplex coupler for coupling to MIS token.

The various logical machines are :

MLPU/PE, MLETA, MLAN } SMA

Little more elaborate description of individual stations shall be discussed

(a) Station: SMC N +1 (N+1)th taking load on failure of any

(b) Logical Machines : MR – 1 to 7 , MQ, TX, TR, GX, PC are

Fig. 1 SMC Environment

2. Environment of SMC : Relative position of SMC in OCB exchange is

3. Hardware architecture of SMC :

CMP PUP MC PUS 1 PUS 2 PUS 3 PUS 4

CMS 1 CMS 2 CMS 3 CMS 4

Fig. 2 FUNCTIONAL ARCHITECTURE OF SMC STATION

- One Principal Multiplex Coupler (CMP) for connections to MIS token

4. Functional architecture of SMC

4.1 Function of various agents on BSM

NB : A station gets inserted on MIS right on powering up but on MAS after

4.1.2 ACAJA / ACAJB as CMS

4.1.3 ACTUR 5 AB as PUP

4.1.4 ACTUR 5 AB as PUS :