KIM TRA CUI K CU TRC MY TNH

(Nhm 15) Cu 1: Pht hin cc Hazard trong on m MIPS sau khi chy trn b vi x l pipeline 5 stages: - Ph thuc no l Data Hazard cn gii quyt bng Forwarding. - Ph thuc no l Data Hazard cn gii quyt bng stall (bubble) v forwarding. add $3, $4, $2 sub $5, $3, $1 lw $6, 200($3) add $7, $3, $6 C nhng data Hazard v cch gii quyt: Gia lnh V lnh Thng qua tghi add $3, $4, $2 sub $5, $3, $1 $3 add $3, $4, $2 lw $6, 200($3) $3 lw $6, 200($3) add $7, $3, $6 $6

Cch gii quyt forwarding forwarding Stall and forwarding

Cu 2: Xt on m MIPS sau khi chy trn b x l 34pipeline 5 stages: sw $6, 0($7) lw $8, 0($7) add $9,c $8, $2 - Pht hin cc Hazard v cch gii quyt ca b x l - Compiler c th thay i on m trnh vic phi chn thm 1 bubble nh th no? a) Pht hin Hazard v cch gii quyt ca b x l Lnh sw $6, 0($7) : Memory[$7+0] = $6 : a gi tr thanh ghi $6 vo A[0] vi $7 l a ch ca mng A Lnh lw $8, 0($7) : $8 = Memory[$7 + 0] : ly gi tr A[0] t b nh a vo thanh ghi $8. K c Hazard Gia lnh lw $8, 0($7)v add $9, $8, $2 c hazard thng qua thanh ghi $8, b x l gii quyt bng stall. b) Compiler c th thay i on m trnh chn stall: sw $6, 0($7) lw $8, 0($7)

nop add $9, $8, $2

Cu 3: 1 cache Direct Mapped 16 one-word blocks. Cho tham chiu b nh nh bn di, xc nh tnh trng ca cache: Word address Memory Block address Hit or Miss Type 1 1 Miss-CS 134 134 Miss-CS 212 212 Miss-CS 1 1 Hit 135 135 Miss-CS 213 213 Miss-CS 162 162 Miss-CS 161 161 Miss-CS 2 2 Miss-CS 44 44 Miss-CS 41 41 Miss-CS 221 221 Miss-CS - Ni dung sau cng trong cache: Block Data at Memory Block Address Block Data at Memory Block Address 0 8 1 1 161 9 41 2 162 2 10 3 11 4 212 12 44 5 213 13 221 6 134 14 7 135 15 Cu 4: Cho h thng nh: Level Hit Time Hit Rate Access Time L1 L2 5 cycles 90% 5 + 0.1*100=15 cycles Main Memory 50 cycles 99% 50 + 0.01*5000=100 cycles Disk 5000 cycles 100% 5000 cycles - Cache L1: a) Direct Mapped: Hit Time 1cycle, 80% Hit Rate b) 2-way Set Associate: Hit Time 2 cycles, 90% Hit Rate c) Fully Associate: Hit Time 3 cycles, 95% Hit Rate Kiu thc hin no cho 1 h thng nh nhanh nht?

a) Direct Mapped: AMAT = 1 + 15 * 0.2 = 4 cycles b) 2 way SA: AMAT = 2 + 15 * 0.1 = 3.5 cycles c) Fully Associate: AMAT = 3 + 15 * 0.05 = 3.75 cycles Vy Cache L1 theo kiu 2 way SA l tt nht

Cu 5: Cho h thng nh: Level Hit Time Hit Rate L1 1 cycle 90% L2 5 cycles 80% Main Memory 100 cycles 95% Disk 100000 cycles 100% - Gi s ch c thay i Miss Rate i vi 1 mc duy nht (L1, L2 hoc Main Memory) th thay i mc no l tt nht? a) Gim Miss Rate 1 na b) Tng Miss Rate gp i a) Gim Miss rate 1 na: - Gim Memory: AMAT = [(100000 x 0.025 +100) x 0.2 + 5] x 0.1 + 1 = 53.5 cycles - Gim L2: AMAT = [(100000 x 0.05 +100) x 0.1 + 5] x 0.1 + 1 = 52.5 cycles - Gim L1: AMAT = [(100000 x 0.05 +100) x 0.1 + 5] x 0.05 + 1 = 52.25 cycles Gim Miss Rate 1 na vs Cache L1 l tt nht b) Tng Miss rate gp i: - Tng Memory: AMAT = [(100000 x 0.1 +100) x 0.2 + 5] x 0.1 + 1 = 203.5 cycles - Tng L2: AMAT = [(100000 x 0.05 +100) x 0.4 + 5] x 0.1 + 1 = 205.5 cycles - Tng L1: AMAT = [(100000 x 0.05 +100) x 0.2 + 5] x 0.2 + 1 = 206 cycles Tng Miss Rate gp i vi Main memory l tt nht

Cu 6: Tnh ton tng s bit cn thit thc hin i vi tng b nh cache c kch c 16 word c thc hin khc nhau sau y (b nh nh a ch theo word s dng a ch 32 bit) a) Direct Mapped, block size: 1 word, write back b) Direct Mapped, block size: 4 word, write back c) 2 way Set Associative, block size: 1 word, write through d) Fully associate, block size: 1 word, write back, fetch on write miss B nh 232 word a) Direct Mapped, block size 1 word, write back - S block trong cache: 16 block - S block trong b nh 232 - Write back, cn 1 bit dirty cho mi block - Mi word cn 1 bit valid, do mi block 1 word, cn 1 bit valid trong 1 block - S bit data trong 1 block: 1word = 4 byte = 32 bit - S bit tag trong 1block: 232/24 = 228 nn cn 28 bit tag. Tng s bit cn thc hin: (1 + 1 + 28 + 32) x 16 = 992 bits b) Direct Mapped, block size 4 word, write back S block trong cache: 4 block S block trong b nh 232/22 = 230 block Write back, cn 1 bit dirty cho mi block Mi word cn 1 bit valid, do mi block 1 word, cn 1 bit valid trong 1 block S bit data trong 1 block: 4 word = 16 byte = 128 bit S bit tag trong 1block: 230/22 = 228 nn cn 28 bit tag. Tng s bit cn thc hin: (1 + 1 + 28 + 128) x 4 = 632 bits 2 way SA, block size 1 word, write through: Write through, k cn dirty S block trong cache: 16 block 1 set c 2 block, c 8 set S block trong b nh 232 block Mi word cn 1 bit valid, do mi block 1 word, cn 1 bit valid trong 1 block S bit data trong 1 block: 1word = 4 byte = 32 bit S bit tag trong 1block: 232/23 = 229 nn cn 29 bit tag. Tng s bit cn thc hin: (1 + 29 + 32) x 8 x 2 = 992 bits

c) -

d) Fully associate, block size: 1 word, write back, fetch on write miss: - S block trong cache: 16 block

Fetch on write miss, khng cn bit valid S block trong b nh 232 Write back, cn 1 bit dirty cho mi block S bit data trong 1 block: 1word = 4 byte = 32 bit S bit tag trong 1block: 232/1 = 232 nn cn 32 bit tag Tng s bit cn thc hin: (1 + 32 + 32) x 16 = 1040 bits

Cu 7: 1 cache 2-way Set Associate 16 one-word blocks. Cho tham chiu b nh nh bn di, xc nh tnh trng cache:

Word address 1 4 8 5 20 17 19 56 9 11 4 43 5 6 9 17 -

Memory Block address 1 4 8 5 20 17 19 56 9 11 4 43 5 6 9 17

Hit or Miss Type Miss-CS Miss-CS Miss-CS Miss-CS Miss-CS Miss-CS Miss-CS Miss-CS Miss-CS Miss-CS Hit Miss-CS Hit Miss-CS Hit Hit

Ni dung sau cng trong cache: Set Data at Memory Block Address 0 8 1 1 9 2 3 19 43 4 4 5 5 6 6 7

Data at Memory Block Address 56 17 11 20

Cu 8: Tnh CPU 7

p dng Miss Rate t cu 7. Cho thi gian stall time tnh theo chu k ca 3 level. Mi level cho chu k truy cp vo chng ( n v l cycles). Tnh thi gian truy cp trung bnh ca mi level. Cu b l tnh hiu sut.

Cu 9: Tm m my (nh phn) cho 2 lnh ca MIPS: Shift Left Logical (sll) v lnh nop. C nhn xt g khi so snh 2 lnh ny? sll $10, $15, 20 nop M my: - sll $10, $15, 20 : 000000 00000 01111 01010 10100 000000 - nop : Cu 10: Thit k datapath v control cho 2 lnh sll v nop ca b x l single cycle (Lu v gi tr ca tn hiu iu khin cn thit):