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B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14
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Code: 9A15502
B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14
3 4
7 8
*****
Code: 9A15502
B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14
2 3
7 8
*****
Code: 9A15502
B.Tech III Year I Semester (R09) Regular & Supplementary Examinations December/January 2013/14
(b) Explain compact algorithm used in PLA folding. 4 Apply D-algorithm to detect h SAO fault in the given circuit and derive the test vectors. A B f C X h
(a) Draw the general structure of a CPLD and explain how a logic function can be realized on CPLD with simple example. (b) How does the ASM chart differ from a software flow chart. Write a short note on: (a) Design for testability. (b) Field programmable gate arrays. (a) Apply PLA maximization procedure and obtain the minimized expression to be implemented on PLA. F = 2021 + 0022 +1200. (b) Obtain the minimum test vector set for the above function F in 7(a). What is testing? Explain briefly test generation and testable PLA design. *****