1. Use the inverter subcircuit to plot a transfer curve ( vs. ) for the CMOS Inverter.

Explain the function of PMOS when NMOS is ON, and the function of NMOS when PMOS is ON. The pmoss source is connected to vdd and the nmoss source is connected to ground. The pmos is on, when VGS is lower than Vt. The nmos is on, when VGS is higher than Vt. According to example, Vt is 0.8V for both pmos and nmos. The pmos is active, when Vt is more than VGS, the nmos is active, when VGS is more than Vt. When gate voltage is higher than 0.8V pmos will be off and nmos will be on. This will connect output voltage into ground. When gate voltage is lower than 0.8V pmos will be on and nmos will be off. This will connect output voltage into voltage source. Figure 1 is the transfer curve. We can see the transfer curve is 0 to 3 volts for output voltage and input voltage. In time domain graph, the output voltage is opposite of input voltage. So When input voltage is increasing, output voltage is decreasing.

Figure 1 transfer curve 0 to 3 voltage

2. Use the subcircuit to construct a 2-stage inverters with a load capacitor CL, as shown in Fig. 2. Apply a square wave input with a 50% duty cycle, an amplitude of 3V and f = 0.5 GHz in Spice simulation to estimate the propagation delay times tPHL and tPLH for the single inverter. Theoretically calculate these delay times and verify the accuracy of the theoretical prediction.

To find the

, it has to use the equation 1.

and

are given in the question, and

those values are 3V and 0.1 mA/V2. Equation 2 and 3 will give values for and C which are missing in the first equation. Given as 0.8V, as 3V, the values of found to be 1.959. The question gives W for nmos as , W for pmos as , as , , L as and as is for the . Using the values given above, both . The total load capacitance is , the value is are , is and . Since the equations are found all the values

Next, it require to find the

The equation 4 is for getting , but require to find the first with equation 5. Since values are exactly same from except the is negative, has same value as . C is the total load capacitance which it got from previews paragraph, and pmoss W is longer than nmoss. The is The figure 2 is time delay on high to low and the figure3 is time delay on low to high. Highlight part of each figures are the time difference on input voltage and output voltage. The is 114.37ps and the is 78.12ps. The present error for is around 21.8 %, and for is around 10.8%

Figure 2 time delay tpHL

figure 3 time delay tpLH

3. Use the subcircuit to construct a 9 stage ring oscillator. Perform transient simulation to observe the oscillation frequency. Include plots from the transient simulation and FFT analysis and label the frequency clearly in the FFT plot. Compare the observed frequency value to the frequency predicted using tpHL and tpLH observed in (2).

4. Observe the values of tpHL and tpLH from the ring oscillator output waveform in (3). Are these delay times different from those observed in (2)?

5. Increase VDD from 3V to 5V, and run the simulation of the ring oscillator. Discuss why and how the frequency changes substantially. Are you able to approximately predict the change of the frequency as a function of VDD ? Present the comparison between the prediction and the actually change observed in Spice simulation over a finite VDD range.