Fault models

Stuck-at-0 Transition /0 Reset coupling Inversion coupling AND bridging Neighborhood pattern sensitive aults !active"

1 0 0 1 0

1 1

0 1 1

1 0

0 0

Address decoder aults

ADR ADR

ADR ADR

ADR ADR

ADR ADR

0 0 0
0

0 0
1 1 0 1 1 1

1 Stuck-at-1 1 1 1 0 1 0 0 1 1
Transition /1 Set coupling Inversion coupling OR bridging Neighborhood pattern sensitive aults !passive"

ADR ADR

Elements of march test

!#0" $ % & ' ( ) 1 0 !#1" !r1*#0" !r0*#1"

x x x x x x x x

0 0 0 0 0 0 0 0

1 1 1 1 1 1 1 1

1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1

1 1 1 1 1 1 1 1

1 0 1 0 0 1 0 1 1 0 1 0 1 0 0 1

0 0 0 0 0 0 0 0

C - algorithm
!#0" !r0*#1" !r1*#0" !r0*#1" !r1*#0" !r0"

0 0 0 0 0 0 0 0

1 0 1 0 0 1 0 1 1 0 1 0 1 0 0 1

0 0 0 0 0 0 0 0

1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1

1 1 1 1 1 1 1 1

1 0 1 0 0 1 0 1 1 0 1 0 1 0 0 1

0 0 0 0 0 0 0 0

1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1

1 1 1 1 1 1 1 1

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0

Nu+ber o steps, 10n -ault coverage, A-s* SA-s* T-s* .-ins * .-ids

Checkerboard test and data retention

1 0 1 0 0 1 0 1 1 0 1 0 0 1 0 1
Designed to test re resh operations o DRA/s /a0i+i1es leakage current and detects leakage aults 2sed as data retention test To be e ective it +ust consider address scra+bling and la3out

Data backgrounds for word memories

) )# )!log !log #4 41" 1"backgrounds backgrounds 1%
)

/ultiple /ultipledata databackgrounds backgroundsto todetect detectcoupling couplingand andbridging bridging aults aultsbet#een bet#eencells cellso o the thesa+e sa+e#ord #ord -or -orever3 ever3pair pairo o cells cellsall all our ourco+binations co+binationsare arechecked checked 1%backgrounds backgrounds or or 1)5-bit#ide #ide+e+or3 +e+or3

1)5-bit

Nor+al Nor+aland andinverse inverse

D0 D1 D2 D 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 1 0 0 1 0 1 0 1 1 0 1 0

D! D" D# D$ 0 1 1 0 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 1 1 0 1 0 1 0

Data in word-oriented memor%

!#0" !r0*#1" !r1*#0" !r0*#1"

&arallel memor% '()*

.lock 7old

S3ste+ logic

F F S S M M

Data Data generator generator Address Address generator generator Control Control generator generator

-ail

Start

Done

6IST +ode

/e+or3

)erial memor% '()*

S3ste+ logic
Data output Serial input Serial output

/e+or3

/ini+al logic and routing 8onger test ti+e

r0 #1 r0 #1 r0 #1 r0 #1 r1

Address / 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 1 1 1 1 1

)erial-+arallel data interface trade-offs

/e+or3 /e+or3

/e+or3

/e+or3

,emor% '()* collar

-unctional logic
Memory Memory BIST BIST controller controller /e+or3 controller at the top level
To / -ro+ TA9 controller

;TA9 controller as test engine

:+bedded +e+or3 6IST collar

;+u0 address / control bus and data lines ;local co+parator #ith single pass/ ail ;local data generator to reduce routing area and ti+ing proble+s ;local address validation

/e+or3 arra3

)hared controller and +arallel test

-unctional logic
Memory Memory BIST BIST controller controller

To / -ro+ TA9 controller

Insert collars .onnect the+ through +e+or3 test bus

; ;

to +e+or3 6IST controller to TA9

/e+or3 arra3

/e+or3 arra3

&arallel memor% '()* collar

-unctional control 6IST control

6IST address -unctional address

6IST data -unctional data 9ass / -ail

Sin

/6IST +ode

<=

Sout
Address .trl Data in Data out

/e+or3 arra3
.lock

Full-)+eed test a++lication

Runs at s3ste+ clock speeds #ith single c3cle read/#rite operations 2ncovers speed-related de ects Reduce test application ti+e>
Clock C%cle 1 Clock C%cle 2 Clock C%cle Clock C%cle ! Clock C%cle "

Clock Addr-CntrlData ,emor% .ut+ut Com+are Circuitr% Circuit .ut+ut /rite

)etu+ )etu+ Read Read 1 1 )etu+ /rite 1 Read 1 Com+are Read 1 &ass-Fail Read 1 /rite 1 )etu+ Read 2 )etu+ Read Read 2 Com+are Read 2 )etu+ /rite 2 Read Com+are Read &ass-Fail Read 2

000

Diagnostics

Detect ailing location/data during test Should diagnose speed related de ects T#o t3pes - 7old and resu+e* 7old and restart 7o# it #orks=
; ; ; ;

6IST controller stops a ter 1 !or )" ailures -ail data is scanned out 6IST session resu+es ro+ #here it stops !7old and resu+e" 6IST session restarts a ter ail data is scanned out !7old and restart"

Full-s+eed diagnostics

,'()* controller

4
Restart

Diagnostic monitor

AT:

,emor% ,emor% arra% arra%

1ield im+ro2ement with memor% redundanc%

/e+or3 percentage* de ect rate* and redundanc3 a+ount a ect 3ield

Redundanc3 @ield I+prove+ent
100 A0 50 $0 %0 &0 '0 (0 )0 10 0 0 10 )0 (0 '0 &0 %0 $0 50 A0 100

Opti+al 8evel ( Redundanc3 8evel ) Redundanc3 8evel 1 Redundanc3 No Redundanc3

/e+or3 @ield

.hip /e+or3 9ercentage

Source, ?orian* Rodgers* DAT: )00)

Redundanc% and re+air

,emor% ,emor% '()* '()* controller controller

,emor% ,emor% Arra% Arra%

:0tra colu+ns* ro#s* or ro#s and colu+ns At the end o test - good* repairable* or non-repairable Repair data scanned out at the end o test

Full-Chi+ memor% '()* integration

Read in SO. netlist Identi 3 +e+ories

6IST B:N:RATION
Assign memories to controller 3'()* )cheduling4

,emor% '()* 5eneration 35enerate Controller-Collars4

6IST INS:RTION
(nsert controllers in the design )titch controllers to to+-le2el

Full Chi+ ,emor% '()* Control

).C
*, ) *C7 *R)* 'lock *A& Controller '()* 'lock ,emor% 1 '()* Controller test8done fail8h test8h ,'()* Data Register *D( 'oundar% )can Register

rst8l C67

'()* 'lock ,emor% 2

*D.

&rogrammable algorithms

Selection o algorith+s
; ;

/arch1* /arch)* /arch(* 2niCue Address* .heckerboard* D address Eu+ping user de ined prior to s3nthesis si+ple language nu+ber o seCuences* backgrounds* seCuence ele+ents etc>* de ect +echanis+s +a3 not be kno#n be ore abrication +e+or3 6IST controller i+ple+ents a class o algorith+s ield progra++able para+eters de ine active ele+ents o test seCuences

S3nthesi1able algorith+s
; ; ;

9rogra++able algorith+s
; ; ;

)ummar%
Fe3
; ; ; ;

co+ponents o a 6IST controller

algorith+ controller data background generator address generator co+parator

Ger3

high Cualit3 test o e+bedded arra3s 6IST controller shared across a nu+ber o +e+or3 arra3s to reduce area 6IST diagnostics helps in gathering ailure in or+ation 6uilt-in repair results in 3ield i+prove+ent