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Fall, 2010 RF CMOS Tranceiver Design 1/19

EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk









Tutorial-2
Low Noise Amplifier (LNA) Design

Written By: Rashad.M.Ramzan
rashad.ramzan@nu.edu.pk
Objective:
Low noise amplifiers are one of the basic building blocks of any communication system.
The purpose of the LNA is to amplify the received signal to acceptable levels with
minimum self generated additional noise. Gain, NF, non-linearity and impedance
matching are four most important parameters in LNA design.
The objective of this tutorial is to outline the basic tradeoffs between different amplifying
topologies w.r.t gain, NF and impedance matching. After this comparison it is concluded
that inductor degenerated common source topology gives the best performance to meet
the gain, NF, and impedance matching goals with minimum power consumption in case
of narrow band designs.
Goals:
After this tutorial, students should be able to
- Calculate the gain, input impedance and NF of common gate, common source,
and shunt feedback amplifiers.
- Understand the basic equations and tradeoff between different LNA topologies.
- Perform the calculation for inductor degenerated common source topology and
understand the tradeoff between the gain, NF, and impedance matching.
A supplement tutorial LNA lab is also part of this course which takes the circuit
from Problem-2.8 and guides through different analysis to design and practical
LNA.
Fall, 2010 RF CMOS Tranceiver Design 2/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
g
m
V
gs
C
gs
+C
gb

S
+
-
V
gs

I
in

I
o
I
in

G
C
gd

D
I
o

V
gs

+
-
Problem-2.1(Tutorial)
e
T
is single figure of merit for high frequency transistors. This is defined as frequency at which
current gain is extrapolated to fall to unity.
Although the dc gate current of an MOS transistor is essentially zero, the high- frequency
behavior of the transistor is controlled by the capacitive elements in the small- signal model,
which cause the gate current to increase as frequency increases.
a) Derive the expression for e
T.

b) For RF design we always use minimum length transistors. Why?

Solution:
a).





V
sb
= V
ds
= 0
So g
mb
, r
o
, C
sb
, C
db
have no effect on calculations. (This is drawback of et definition)
gs gd gb gs i
V C C C j i ) ( + + = e
gs m i
V g i ~
( )
gd gb gs
m
in
o
C C C j
g
i
i
+ +
=
e

According to definition 1 =
in
o
i
i
at
T
e
gd gb gs
m
T
C C C
g
+ +
= =e e
C
gb
and C
gd
are small compared to C
gs

So,
gs
m
gd gs
m
T
C
g
C C
g
~
+
~ e -----------------------(1)
b). ( )
2
2
T gs
ox o
D
V V
L
W C
I =


( )
T gs ox o
gs
D
m
V V
L
W
C
V
I
g =
c
c
= -----------------------(2)
Fall, 2010 RF CMOS Tranceiver Design 3/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk

And WL C C
o gs
= -----------------------(3)
Put (2) & (3) in (1)
( ) ( )
2
. . . L
V V
L W C L
V V W C
C
g
t gs o
ox
t gs ox o
gs
m
T

=

= =

e
( )
2
L
V V
t gs o
T

=

e
This means that
2
1
L
T
o e so thats why minimum L is preferred. But this approximation holds
for long channel devices for short channel
L
T
1
o e instead of
2
1
L
.
Problem-2.2(Tutorial)
NMOS transistor is racing horse in LNA design arena due to its higher mobility compared to
PMOS transistors. Calculate the IP3 of NMOS CS amplifier shown below. Assume that NMOS
transistor is in saturation.


a) Consider simplified square law model. (HW)
2
( )
2
n
D GS T
K
I V V =
b) Consider the short channel effects as (Tutorial)
2
1
( )
2 1 ( )
,
0.2 0.1
n GS T
D
GS T
GS T
K V V
I
V V
Velocity Saturation Mobility Degradation
V V V and V
u
u
u

(
=
(
+

=
= =

c) What conclusion can be drawn from part b) about the bias current and transconductance
of transistor for higher IP3?

Solution:
Fall, 2010 RF CMOS Tranceiver Design 4/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
V
DD

R
L

V
GS

X(t)
NMOS
DC-bias

a). Home work Ans: o = 3 IP

b). From Razavi
) ( ) ( ) ( ) (
3
3
2
2 1
t x t x t x x y o o o + + = ---------------(1)
3
1
2 1
3
4
3 cos cos ) (
o
o
e e = + = IP t A t A t x
( )
) ( 1 2
2
T GS
T GS n
D
V V
V V K
I
+

=
u

Here we assume that small signal x(t) over-rides (V
GS
V
T
).
So,
( ) | |
)) ( ( 1
) (
2
2
t x V V
t x V V K
I
T GS
T GS n
D
+ +
+
=
u

& V V V
T GS
A = --------------- Large signal
X(t) --------------- Small signal
| |
1 ) ) ( (
) (
2
2
+ A +
A +
=
V t x
V t x K
I
n
D
u

( )
( ) V t x
V t x R K
V R I V
L n
o L D o
A + +
A +
= =
) ( 1
) (
2
2
u
put K
R K
L n
=
2

1 << u So ( ) V x x A + ) ( is also small
2
1
1
1 x
x
=
+

( )
( )
2
) (
1
) ( 1
1 V t x
V t x
A +
~
A + +
u
u

( )
( )
|
.
|

\
|
A +
A + =
2
) (
1 ) (
2
V t x
V t x K V
o
u

( ) ( )
2
) ( ) (
3 2
u K
V t x V t x K V
o
A + A + =
) (
2
) (
2
3
) (
2
3
2
2
3 2 2 3 2
t x
K
t x V
K
K t x V
K
V K V
K
V K V
o
u u u u

|
.
|

\
|
A +
|
.
|

\
|
A A + A A =
---------------(2)
Small signal components
) (
2
) (
2
3
) (
2
3
2
3 2 2
t x
K
t x V
K
K t x V
K
V K V
o
u u u

|
.
|

\
|
A +
|
.
|

\
|
A A =
---------------(3)
Fall, 2010 RF CMOS Tranceiver Design 5/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk

Comparing (1) & (3)
2
1
2
3
2 V
K
V K A A =
u
o , V
K
K A =
2
3
2
u
o ,
2
3
u
o
K
=
|
.
|

\
|
A
A
=
A A
= =
2
2
3
1
3
2
3
8
2
2
3
2
3
4
3
4
3 V
V
K
V K v K
IP
u
u
u
o
o

u u
V V
IP
A
=
A
=
3
16 2
3
8
3
( )
u u
T GS
V V V
IP

=
A
=
3
16
3
16
3 ---------------(4)
Put V V 2 . 0 = A , 1 . 0 = u
Volts IP 27 . 3
1 . 0
2 . 0
3
16
3 = =
dBm mW dBm IP 20 1
50
1
.
2
27 . 3
log 10 ) ( 3
2
~
(
(

(
(

|
.
|

\
|
=
V V V I
g
T GS D
m
A
=

=
2 2

m
D
g
I
IP
u 3
32
3 ~
D ox n m
I
L
W
C g =
c).
- To increase IIP3 I
D
|(high power) or g
m
+ (high noise)
- g
m
also depends upon I
D,
so when ID | g
m
| but at that rate
D
I o
- When W increases gm | for same I
D
(Power consumption) so this decreases IP3
- The above observations are for long-channel. But for short channel ( ) ( ) |
T GS
V V 4 then
ID |any how.

Problem-2.3 (Tutorial)
It is preferred in current RF designs that the input of LNA be matched to 50 (Razavi, Pg168).
The easiest way is to shunt the gate with a resistor of 50 .
a) Calculate the gain, input impedance and NF in absence of gate noise. Assume that R
sh
=R
L

for NF derivation.
b) What are the disadvantage of shunt resistor with reference to gain and NF?
As 1 << u
2
3 V A can be ignored.
( )
2
2
T GS
ox o
D
V V
L
W C
I =


( )
V V V I
g
V V
L
W
C
V
I
g
T GS D
m
T GS ox n
GS
D
m
A
=

=
=
c
=
2 2


This is just an approximation with I
D

& g
m

Fall, 2010 RF CMOS Tranceiver Design 6/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
g
m
V
gs

S
D
V
out

R
L

d i
2

R
L
is noiseless
G
R
sh

Rsh n V ,
2

Rs n V ,
2

R
s

V
DD

R
L

R
sh

V
in

V
out

Z
in

R
s

(Baising not shown)


Solution:
a). (Please read assumption in problem statement carefully)







source input to due noise Output
power noise output Total
F =
f KTR V
s
Rs m A = 4 ,
2

L m
Gate
R g Gain =
f KTR V
sh
Rsh m A = 4 ,
2

|
|
.
|

\
|
+
=
sh s
sh
L m
R R
R
R g A for R
sh
= R
s

f g KT i
m
d A = 4
2

2
L
m
R
g A =
Using superposition, considering one at a time and shorting / opening other sources.
2
2
2
,
2
,
2
|
|
.
|

\
|
+
=
sh s
sh
L
m Rs n Rs on
R R
R
R g V V
2
2
2
,
2
,
2
|
|
.
|

\
|
+
=
sh s
s
L
m Rsh n Rsh on
R R
R
R g V V
Fall, 2010 RF CMOS Tranceiver Design 7/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk

L d d no R i V
2 2
,
2
=
Rs on
d o Rsh on
Rs on
d no Rsh on Rs on
V
V V
V
V V V
F
,
2
,
2
,
2
,
2
,
2
,
2
,
2
1
+
+ =
+ +
=
( )
( ) ( )
2
2 2 2
2
2
2 2 2
2
2 2 2
4
4
4
4
1
sh s
s L m
S
L
m
sh s
s L m
s
sh s
sh L m
sh
R R
R R g
f KTR
R f g KT
R R
R R g
f KTR
R R
R R g
f KTR
F
+

A
A
+
+

A
+

A
+ =


In case of impedance match R
s
= R
sh
s m
L m
s
m
L
s
L s m
s
m
L
R g R g
R
g R
R
R R g
R
g R
F
4
2
4
2
4
1 1
2 2
2
2
2 2 2
2
+ =

+ =

+ + =
b).
- Poor Noise Figure
- Input signal attenuated by voltage divider
- R
sh
adds extra noise.
- At high frequency, shunt L is needed to tune out C
gs

- Reduced gain

Problem-2.4 (Tutorial)
Another approach to get 50 input impedance match is shunt feedback amplifier shown below.

a) Calculate the gain, input impedance and NF in absence on gate noise. Neglect gate drain
and gate to bulk and gate to source capacitance.
b) What are the disadvantage of shunt feedback amplifier with reference to gain and NF?

Fall, 2010 RF CMOS Tranceiver Design 8/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
g
m
V
gs

V
out

R
L

nD I
2

(Equivalent noise model ignoring gate noise), RL is noiseless
R
s

Rs n V ,
2

RF n V ,
2

R
F

V
DD

R
L

V
out

Z
in

R
s

(Baising not shown)
R
F

V
in

g
m
V
gs

V
out

R
L

R
s
R
F

V
gs

i
in

V
in

R
L

V
out

I
in

R
s

R
F

I
in


Solution:








f KTR V f g KT I
S
RS
m
nD A = A = 4 , 4
2 2

source input to due power noise Output
power noise input Total
V A
V
NF
RS tot v
out n
= =
2
,
2
,
2

Here A
v,tot
= Gain from V
in
to V
out

Again using superposition theorem
RS tot v
out D
n
out RF
n
out RS
n
RS tot v
out n
V A
V V V
V A
V
NF
2
,
2
,
2
,
2
,
2
2
,
2
,
2
+ +
= =

Gain Calculation
( )
out F S in in
V R R i V + + =
( )
L gs m in out
R V g i V =
o F in gs
V R i V + =
( )
L S m L F S
L m L
in
out
tot v
R R g R R R
R g R
V
V
A
+ + +

= =
1
,

If R
F
>>R
S
& g
m
R
F
>>1
L m
F
S m
L
F
S
L m
tot v
R g
R
R g
R
R
R
R g
A ~
+
+ + +

=
1
1
,

L m tot v
R g A ~
,

Also
L m
L F
in
R g
R R
Z
+
+
=
1

By ignoring C
gs,
we have considered real part only.
Fall, 2010 RF CMOS Tranceiver Design 9/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
g
m
V
gs

out RF V ,
2

R
L

R
s
R
F

V
gs

i
RF V
2

g
m
V
gs

out nD V ,
2

R
L

R
s
R
F

V
gs

i
D n I ,
2


For source resistance
nRS tot v out nRS V A V
2
,
2
,
2
= ---------------(1)
For feedback resistance






out RF RF F S gs
V V iR iR V
,
+ = =
( )
gs m L out RF
V g i R V =
,

( )
( )
S m
F
L
RF
s m L
F S
RF out RF
R g
R
R
V
R g R
R R
V V + =
+
+
+
= 1
1
1
1
,

( )
2
,
2
, ,
2
1
(

+ =
S m
F
L
RF n out RF n R g
R
R
V V ---------------(2)
Similarly





0
, ,
=
+
+ + +
F S
out nD
gs m nD
L
out nD
R R
V
V g I
R
V

F S
out nD
S gs
R R
V
R V
+
=
,

L nD
F S
S m
F S L
D n
out nD
R I
R R
R g
R R R
I
V ~
+
+
+
+
=
1 1
,
,

So,
2
2
,
2
L
nD out nD R I V = ---------------(3)
Combaining (1) (2) & (3)
Fall, 2010 RF CMOS Tranceiver Design 10/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk

( )
RS n tot v
L nD
RS n tot v
S m
F
L
RF n
V A
R I
V A
R g
R
R
V
NF
,
2
,
2
2 2
,
2
,
2
2
,
2
1
1 +
(

+
+ =
L m tot v
R g A =
,
, f KTR V
S
RS n A = 4 ,
2
,
F
RF M KTR V 4 ,
2
= &
m
nD g KT I 4
2
=
S m S m F
S
R g R g R
R
NF

+
|
|
.
|

\
|
+ + =
2
1
1 1
b).
NF + g
m
R
S |
& R
F |
usually O = 50
S
R
- Better performance than CS amplifier
- R
F
induces noise
- At f
|
need shunt inductor to tune out C
gs

- Broadband

Amp @ Lower frequency
- To make NF + R
F
> R
S
g
m
R
S
>> 1

Problem-2.5 (HW)
Common gate amplifier also offers 50 input impedance match and solves the input matching
problem.

c) Calculate the gain, input impedance and NF in absence on gate noise. Neglect gate drain
and gate to bulk and gate to source capacitance.
a) What are the disadvantage of common gate amplifier with reference to gain and NF?

Problem-2.6 (Tutorial)
The disadvantages of three types of amplifiers in Problem-3, 4 & 5 can be circumvented by using
source degenerated LNA shown below.
Fall, 2010 RF CMOS Tranceiver Design 11/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
V
DD

R
L

V
S

V
out

R
s

(Baising not shown)
L
s

L
g

V
S

R
s

L
s

L
g

i
in
V
out
i
o

g
m
V
gs

V
in

V
gs

Z
in


a) Calculate the input impedance. This inductor source degenerated amplifier presents a
noiseless resistance for 50 for input power match. How we can cancel the imaginary
part of complex input impedance so that the LNA presents 50 real input resistance at
input port.
b) Calculate the NF in absence on gate noise. Neglect gate drain and gate to bulk and gate to
source capacitance.
c) C
gd
bridges the input and output ports. The reverse isolation of this LNA is very poor.
Why reverse isolation is important? Suggest the modification to improve reverse
isolation.

Solution:
a).








From model above we can write
( )
s o in s g in in
L j i
c j
i L j L j i V e
e
e e +
|
|
.
|

\
|
+ + =
1
---------------(1)
gs
in m gs m o
C j
i g V g i
e
1
= = ---------------(2)
Substituting (2) in (1)
( )
(
(

+ + + =
gs
s m
gs
s g in in
C
L g
C j
L L j i V
e
e
1



Fall, 2010 RF CMOS Tranceiver Design 12/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
V
in

R
s
L
g
+ L
s

gs
s
m
C
L
g
Z
in
V
gs

C
gs

Reference:
For series RLC Circuit

R L
C V
C

V
in

RC R
L
C
L
R
Q
o
o
s
e
e 1 1
= = =
And
in S C
V Q V =
For problem (1)
gs
m
T
C
g
~ e Unity gain frequency
for current


( )
gs
s m
gs
s g
in
in
in
C
L g
C j
L L j
i
V
Z + + + = =
e
e
1

( )
gs
s m
gs
s g in
C
L g
C j
L L j Z + + + =
e
e
1

For matching L
g
+ L
s
are canceled out by C
gs
. So at frequency of interest
( )
( )
gs s g
o
gs o
s g o
C L L C
L L
+
= = +
1 1
2
e
e
e
And
s
gs
m
S
L
C
g
R = O = 50
Notes:
a). L
s
is typically small and may be realized by bond wire.
b). L
g
can be implemented by spiral/external inductor.

b).
From part a)
( )
gs
s m
gs
s g in
C
L g
C j
L L j Z + + + =
e
e
1

We can draw this circuit as






Here
( ) ( )
S T S
s g o
gs
S m
S
s g o
in
L W R
L L
C
L g
R
L L
Q
+
+
=
+
+
=
e e

gs
m
T
C
g
~ e
gs
gs
S m
S o
in
C
C
L g
R
Q
|
|
.
|

\
|
+
=
e
1
For match load
gs
S m
S
C
L g
R =


Fall, 2010 RF CMOS Tranceiver Design 13/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
R
L

V
in

V
out

R
s

L
s

L
g

Z
in

V
gs


gs s o
in
C R
Q
e 2
1
=
Gain
in in gs
V Q V =
gs
out
m
V
V
g =
m in
in
m gs
in
out
m
g Q
V
g V
V
V
G = = =
m m
Qg G =
So,
L m
R G Gain = or
L m in
R g Q &
m in m
g Q G =

Noise Figure:
source input to due output at power noise
output at power noise Total
NF =
For this calculation we ignore channel noise.
OUT nRS
OUT nD
OUT nRS
OUT nD OUT nRS
V
V
V
V V
F
,
2
,
2
,
2
,
2
,
2
1+ =
+
=
L D n OUT nD R i V
2
,
2
,
2
= f g KT i
m
D n A = 4 ,
2

L m RS n OUT nRS R G V V
2 2
,
2
,
2
= f KTR V
S
RS n A = 4 ,
2
&
m in m
g Q G =
L m in RS n
L D n
R g Q V
R i
F
2 2 2
,
2
2
,
2
1+ =
m
D n g KT i 4 ,
2
= ,
S
RS n KTR V 4 ,
2
=
in
S m
Q R g
F
2
1

+ =

Notes:
- Very good NF value
- Narrow band matching
- NF +with
2
Q
- The Q is dependent upon L
g
+ L
s
, L
s
is small so Q depend upon L
g





Fall, 2010 RF CMOS Tranceiver Design 14/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
V
DD

R
L

V
S

V
out

R
s

L
s

L
g

V
DD

L
D

V
S

R
s

L
s

L
g

C
L

RL generates noise so replace
RL with LD so thats
L D
o
C L
1
= e
Reverse Isolation
V
out

L
o


V
DD

L
D

R
s

L
s

L
g

C
L

V
b

(Final Design)
C
gd


C). Draw Backs
i).








The C
L
can be the input capacitance of mixer or filter.

ii).









Reverse isolation depends upon C
gd
to make it better cascade input device

Problem-2.7 (HW)
Fill-in the Table below, use the data from Problem-2.4, 2.5, 2.6 and 2.7

Type of LNA Z
in
Noise Factor Gain NF (dB)
Shunt Resistor R
sh

4
2
m S
g R

+
2
m L
g R


Common Gate
Shunt Feedback
Source Degenerated

a) Calculate the NF for all above amplifiers. Assume =2, g
m
= 20mS, Rs = 50, R
F
=
500, and Q
in
= 2.
b) Which is best topology for Narrow Band LNA design at high frequency?

Fall, 2010 RF CMOS Tranceiver Design 15/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk
V
DD

L
D

R
REF

L
s

L
g

M
2

V
out

M
1

C
L
= 10pF
M
3

R
BIAS

R
S
C
B

V
in


Problem-2.8 (Tutorial)
Real Design: We will design the inductor source degenerated LNA shown in Fig below to meet
the specification outlined for IEEE802.11 (b) standard. The first cut approximate values are
calculated as a starting point for simulation. In LAB3: Design of LNA you will take the same
design and modify these component values to meet the specification.
LNA Specification:
NF < 2.5 db, Gain > 15dB, IP3 > -5dBm, Centre Frequency = 2.4 GHz
S11 < -20dB, S22 < -10dB, Load Capacitance = 1pF
Technology Parameters for 0.35um CMOS:
2 2 2
0.35 , 170 , 4.6 , 58 , 2
eff n ox ox p ox
L m C A V C mF m C A V = = = = =

Solution:
Technology:
( )

=
= = =
= =
2
2
2 2
170 , tan ) ( 11 . 802
4 . 2 , 2 , 6 . 4 ,
35 . 0 , 58 , 170
V A C dard S b IEE
GHz f m mF C CMOS
m V A C V A C
ox o
o ox
ox p ox o



Design Parameters
dB NF PF C V V R
L DD S
5 . 2 , 10 , 3 . 3 , 50 < = = O =







Fall, 2010 RF CMOS Tranceiver Design 16/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk

Component Description
L
s
Matches input impedance
L
g
Set the Resonant Frequency f
O
= 2.4 GHz
M
3
Biasing transistor which forms current mirror with M
1

L
d
Tuned output increases the gain and also work as band pass filter with C
L

M
2
Isolate tuned input and tuned output increases reverse isolation, also reduces the effect of
Miller capacitance C
gd

C
B
BC Blocking capacitor chosen to have negligible reactance at f
O
= 2.4 GHz
R
BIAS
Large enough so that its equivalent current noise is small enough to be ignored. (Dont
consider it as voltage noise source. Why??)

Design Procedure
Size of M1:
We will not go for global minimum noise figure as given by two-point noise theory (See lecture
on LNA Slide # 10)
( )
O
= =
50
1
1
5
2
C C G
gs opt

o
oe ---------------(1)
! ! 4 4
1
mm W pF C
M gs
~ ~ (not possible)
Solution:
A & B are from Thomos. H. Lee book (LNA Chapter)
LNA NF will be optimized for given Power
* It will not be best NF globally.
S ox eff o
opt
R C L
W
e 3
1
=
T
p
T
p
F F
e
e
e
e
o

6 . 5 1 4 . 2 1
min, min,
+ = + = ---------------(A)
From (1) we can derive
( )
T T
p
C C F
e
e

e
e
3 . 2 1 1
5
2
1
2
min,
+ = + =
T
p
F
e
e
3 . 2 1
min,
+ = ---------------(B)
(a) is minimum NF for a given power consumption.
(b) is global minimum noise figure.
The difference is usually 0.5dB to 1dB (no big deal for Lower Power)
Fall, 2010 RF CMOS Tranceiver Design 17/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk

Step - 1:
mA I I 5
2 1
= = (Low Power consumption)
Step - 2:
S ox eff
M
R C WL
W
3
1
1
=
o
M
m
W
e
=
50 6 . 4 35 . 0 3
1
1

= =
= =
= O =
GHz f f
m L V A C
m mF C R
o o o
eff ox n
ox S
4 . 2 , 2
, 35 . 0 , 170
, 6 . 4 , 50
2
t e

4
1
10 9 . 3

=
M
W
m W
M
390 10 9 . 3
4
1
= =


Step - 3:
ox eff M gs
C L W C
1 1
3
2
=
pF m C
gs
41 . 0 6 . 4 35 . 0 390
3
2
1
= =
1
1
1
2
DM
M
ox n m
I
L
W
C g
|
.
|

\
|
=
V mA m g
m
43 5
35 . 0
390
170 2
1
=
|
.
|

\
|
=
Sec rad G
pF
V mA
C
g
gs
m
T
104
41 . 0
43
1
1
= = ~ e
Assuming 2 =
Now
T
o
F
e
e
6 . 5 1
min
+ =
dB
G
G
F 55 . 2
104
4 . 2 2
6 . 5 1
min
~ + =
t

dB NF 55 . 2 ~
Its very close to what we derive, if the value is higher we can increase I
D
to increase
T
e and
hence low NF on expense of power.

Fall, 2010 RF CMOS Tranceiver Design 18/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk

Step - 4:
Source and gate inductance such that they cancel C
gs
and set O 50 input impedance
Sec rad G f
o o
15 4 . 2 2 2 = = = t t e
From previous problem
T S
gs
S
m
d Transforme S
L
C
L
g R R e = = =
nH
G
R
L
T
S
S
5 . 0
100
50
~ = =
e

nH L
S
5 . 0 = can be implemented using Band wire.
Now
( )
1
2
1
gs o
s g
C
L L
e
= +
( )
nH
pF G
L L
s g
81 . 10
41 . 0 15
1
2
=

= +
nH L
g
10 ~
Step - 5:
pF C
C
L
L
L o
d
1
1
2
= =
e

( )
nH
pF G
L
d
4 . 4
1 15
1
2
~

=
nH L
d
4 . 4 =
Step - 6:
Size of M3 is chosen to minimize power consumption
mA I K R m W
REF M
6 . 0 2 , 70
3 3
= O = =
O = K R
BIAS
2 (Large enough so that its equivalent current noise can be neglected)
pF C
B
10 = ( O ~ 6 . 6
C
X so good value @ 2.4G O = = 6 . 6
2
1
B o
B
C f
X
t
)
Step - 7:
Size M2 = M3
So that they can have shared Drain Area..
(Note: We will simulate same design in LAB # 2)
Fall, 2010 RF CMOS Tranceiver Design 19/19
EE Department, FAST-NU, Islamabad, Pakistan rashad.ramzan@nu.edu.pk

Problem-2.9 (Point to Ponder):
Connecting two Inductor source degenerated LNA as shown in Figure make the differential LNA.
Differential LNA has many advantages: higher common mode rejection ratio, less sensitivity to
the ground inductance variation Ls compared to single ended counterpart..


a) Compare intuitively the NF of single ended and differential if both have same power
consumption.
b) If low power is not parameter on interest, which LNA has lower NF?
Instructions:
For hand calculation of NF you can ignore the gate noise of the device and noise generated by the
load resistance R
L
.
















Acknowledgement: The major part of this tutorial was developed, while author was employed by
Linkoping University, Sweden.

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