Temperature Sensor with 10-bit SAR Analog-to-Digital Converter

Steven Pesut

Abstract The design, simulation and layout o a 10-bit digital temperature sensor are des!ribed" The design !onsists o three main stages" #irst, there is a !ir!uit that is sensitive to ambient temperature !hanges" An ampli i!ation stage then turns the output o the sensing !ir!uit into a usable signal" $astly, the ampli ied signal is ed into a 10-bit analog-to-digital !onverter" The ADC is a Su!!essive Appro%imation Register &SAR' whi!h utili(es an R-)R Digital-to-Analog !onverter to generate the digital outputs" Simulations show the sensor to have a resolution o appro%imately *"+ ,C with ea!h !onversion ta-ing appro%imately a minimum o ++0 .s and a ma%imum o 1"0+ ms" Test and veri i!ation pro!edures are outlined and des!ribed"

Contents
1 2 Introduction Circuit Design and Analysis )"1 Design o Temperature Sensing Stage """""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" )") Design o Ampli i!ation Stage """"""""""""""""""""""""""""""""////""""""""""""""""""""""""""""" )"0 Design o Analog-to-Digital Converter """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" )"0"1 Design o Digital-to-Analog Converter """""""""""""""""""""""""""""""""""""""""""""""""""" )"0") Design o SAR Controller $ogi! """""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" Design Layout 0"1 $ayout o Temperature Sensing Cir!uit """""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" 0") $ayout o Ampli i!ation Stage "//////"/""""""""""""""""""""""""""""""""""""/// 0"0 $ayout o SAR ADC """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" 0"3 Completed $ayout """""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" Circuit Simulation 3"1 Temperature Sensing and Ampli i!ation 4eri i!ation """"""""""""""""""""""""""""""""""""""""""" 3") Analog-to-Digital Converter Simulation """""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" 3"0 #ull Cir!uit Simulation """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" Test and Veri ication o De!ice +"1 Temperature Sensing Cir!uit 4eri i!ation """""""""""""""""""""""""""""""""""""""""""""""""""""""""""" +") Ampli i!ation Stage 4eri i!ation """""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" +"0 SAR ADC 4eri i!ation """"""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" 1 1 ) 0 + + 1 9 2 10 1) 10 14 13 15 11 1" 12 12 )0

Summary and Conclusion 2$ 5"1 Suggestion or #uture 6or- """""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" )1 5") 7iography """""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" )1 A&&endi' 21 1"1 Cir!uit S!hemati!s """""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" )1 1") #inal Cir!uit $ayout """""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""""" )2

Introduction
This report des!ribes the design, test and analysis o a temperature sensor with a 10-bit

Su!!essive Appro%imation Register Analog-to-Digital !onverter &SAR ADC'" The sensor is implemented using the A89 C+: pro!ess" The !ir!uit !onsists o three ma;or stages" The irst stage !onsists o a temperature dependent !ir!uit" The temperature value is de ined by a di erential output rom the stage" The se!ond stage ampli ies the di erential output to improve the resolution o the devi!e" $astly, a SAR ADC is used to provide a 10-bit digital output that is dire!tly proportional to the temperature" Se!tion ) des!ribes the design and analysis o the !ir!uit, in!luding s!hemati!s or all relevant !ir!uitry" Se!tion 0 shows the on-!hip layout o ea!h se!tion o the !ir!uit" Se!tion 3 presents the simulations used to veri y and !hara!teri(e the e%pe!ted devi!e behavior" Se!tion + outlines the pro!edures to veri y the abri!ated !hip is wor-ing properly" Se!tion 5 gives a summary o the pro;e!t, as well as improvements or the devi!e"

Circuit Design and Analysis

The !ir!uit was designed to operate as indi!ated in the blo!- diagram in #igure 1 below" The

design o ea!h o these blo!-s will be dis!ussed in se!tions )"1, )") and )"0 respe!tively"

Digital Out

in

Temperature Sensing Stage

Amplification Stage

SAR ADC

#igure 1< 7lo!- Diagram o Cir!uit =peration

)"1 Design o Temperature Sensing Stage

The temperature sensing !ir!uit relies on the temperature dependen!e o Poly-sili!on resistors" The resistors or the A89 C+: pro!ess have a toleran!e o )000 ppm, or ")> per ,C" All bodies in the !ir!uit are tied to the sour!e to eliminate the body e e!t on 4t" This !auses the mirrored !urrents to be more !onstant as temperature !hanges" The !ir!uit s!hemati! or the temperature sensing stage !an be seen below in #igure )"

#igure )< Temperature Sensing Cir!uit This !ir!uit operates by generating a bias !urrent in the le t-most bran!h" This bias !urrent is mirrored to the other two bran!hes to !reate a !urrent o 100 uA through the )0 -? and )+ -? resistors" 6ith the resistors varying at appro%imately ")> per ,C, this !auses the voltage di eren!e between 41 and 4) to !hange at 1 m4 per ,C" The bias resistor is bro-en out on one pin o the !hip to mitigate the )

temperature dependen!e o that !omponent" This enables the !urrent mirror to be held at a more !onstant !urrent as the temperature !hanges" Two versions o the !urrent sour!e were designed" The design shown above uses a relatively high bias !urrent &3 mA'" The se!ond design has a bias !urrent o 100 .A, whi!h redu!es the power dissipation o the !ir!uit" The !urrents mirrored through the resistors is set to 100 .A or both designs"

)") Design o Ampli i!ation Stage

The di erential signal rom the temperature sensor is then ampli ied into a signal analog signal that !an be ed into the Analog-to-Digital !onverter" The ampli i!ation stage !onsists o two ampli iers" The irst is a di erential ampli ier that in!reases the amount o gain on the signal or ea!h ,C o temperature !hange" Sin!e the resistan!e in!reases as temperature de!reases, this gives the largest voltage di eren!e at the lowest temperatures" This would !ause the ADC to give higher readings at lower temperatures" This is !orre!ted in the ampli i!ation stage using an inverting operation ampli ier" This se!ond stage not only lips the signal, but also adds more gain to the signal" The inal signal provides appro%imately )0 m4 o di eren!e per ,C" The s!hemati! o the ampli i!ation !an be seen below in #igure 0"

#igure 0< Ampli i!ation Stage

The operational ampli iers used in the design have very basi! re@uirements" Signi i!ant temperature !hanges o!!ur at a very low re@uen!y, and the largest gain above is 2"A" An ampli ier that has a gain o )0* d7 at re@uen!ies below 100 B( are more than su i!ient or the tas-" #or this reason, a simple two-stage ampli ier was designed" The design !onsists o a di erential pair stage ollowed by a !ommon sour!e stage at the output o the ampli ier" A 8iller !apa!itor is added between the !ommon sour!e input and output" This in!reases the phase margin o the ampli ier" The s!hemati! o the ampli ier is shown below in #igure 3"

#igure 3< =perational Ampli ier S!hemati!

)"0 Design o Analog-to-Digital Converter

The Analog-to-Digital !onverter is implemented using a Su!!essive Appro%imation Register or all !onversions" This design was !hosen be!ause it re@uires minimal logi! and spa!e on the !hip" The design operates in the ollowing way" A 10-bit register is setup to hold the digital value o the !onversion" These 10 bits are ed into a Digital-to-Analog !onverter" The output o the DAC is ed into a !omparator" The !omparator also has the output o the ampli i!ation stage ed into it" Depending on the output o the !omparator, a logi! blo!- lips the appropriate bit in the register to high or low" The bits are sele!ted one at a time and !hanged i ne!essary" A !onversion is !omplete on!e all bits have been ad;usted appropriately, giving the !orre!t digital value or the analog output o the ampli i!ation stage" The inal digital values are then !lo!-ed to a register o D #lip #lops whi!h are tied to output pins o the !hip" The operational ampli ier design rom the ampli i!ation stage is used here as the !omparator" The other two blo!-s o the SAR ADC will be dis!ussed in the ollowing se!tions" A blo!- diagram overview is shown below in #igure +"

#igure +< 7lo!- Diagram o SAR ADC

)"0"1 Design o Digital-to-Analog Converter

The DAC is designed as a simple R)-R networ-" 9nputs are ta-en rom the 10-bit register" These inputs are used to sele!t whether bits in the DAC are set to 4dd or ground" #or the DAC, R C 100-D" The s!hemati! design is shown below in #igure 5"

#igure 5< Digital-to-Analog Converter S!hemati!

)"0") Design o SAR Controller $ogi!

The logi! !ontroller ta-es the !omparator output and a !lo!- signal as inputs" The !ontroller starts every !onversion by (eroing out all o the bits in the 10-bit register" These bits are then lipped high one at a time E most signi i!ant to least signi i!ant" This is a!!omplished with a shi t register" The shi t register generates sele!t lines or ten multiple%ers" The shi t register ensures that only one sele!t line is high at any given time throughout the !onversion" A series o D lip lops is used to move the sele!t line one bit per !lo!-" These multiple%ers sele!t whether the previous bit state, or the !omparator output is ed into the 10-bit register" The pro!ess is demonstrated on one bit below in #igure 1"

#igure 1< Register 7it- lipping Pro!ess The !ontroller lips one bit high and !he!-s i the !omparator reads low &value is too large'" 9 the !omparator reads low, the bit must be lipped ba!- to its original low state" To lip the bit ba!- to its original state, the !lo!- into the shi t register must be blo!-ed" This -eeps all sele!t lines at the same value or an e%tra !lo!- !y!le, whi!h lips the bit ba!- to its previous state" This is a!!omplished with the ollowing logi! seen in #igure A"

#igure A< Clo!--7lo!-ing $ogi! The !onverter then moves on to the ne%t bit until all bits have been set appropriately" =n!e the inal value is rea!hed, the bits are written to an output register, and are reset to per orm the ne%t !onversion" The outputs are pinned out o the !hip and !an be read with a mi!ro!ontroller or logi! analy(er" A simulation o the SAR ADC is shown on the ne%t page in #igure )0" The DAC output is the blue line" 9t approa!hes the green line &simulated output o ampli i!ation stage'" 6hen all 10 bits have been stepped through, the digital outputs update" A simple ring os!illator designed to have an operating re@uen!y o appro%imately )0 -B( is used to !lo!- the ADC" This re@uen!y will lu!tuate with temperature" This is not an issue, be!ause the !onverter does not re@uire a spe!i i! re@uen!y to operate" Conversion times will !hange depending on on the temperature"

Design Layout
All design layout was per ormed using the 4irtuoso layout editor in the Caden!e design suite"

$ayouts were designed to minimi(e devi!e si(e as well as enable easy wire routing or the design"

0"1 $ayout o Temperature Sensing Cir!uit

7oth sensing !ir!uits &high !urrent and low !urrent' were laid out to minimi(e the ootprint on the !hip" The layout o the higher !urrent !ir!uit !an be seen in #igure 2"

#igure 2< $ayout o Temperature Sensing Cir!uit

0") $ayout o Ampli i!ation Stage

The building blo!- o the ampli i!ation stage is the operational ampli ier" The layout is shown below in #igure 10"

#igure 10< $ayout o =perational Ampli ier

10

These ne!essary resistors were added around the ampli iers to !omplete the stage" The resistors were laid out in su!h a way as to it !losely with other stages, whi!h allowed or a minimum si(e design" The ampli i!ation stage layout !an be seen below in #igure 11"

#igure 11< $ayout o Ampli i!ation Stage

11

0"0 $ayout o SAR Analog-to-Digital Converter

The SAR ADC was laid out in su!h a way that area was minimi(ed" The minimal layout o this se!tion allowed or two sensors to be put on ea!h !hip" The layout o the ADC !an be seen below in #igure 1)"

#igure 1)< $ayout o SAR ADC

1)

0"3 Completed $ayout

The inal layout !an be seen below in #igure 10" The lower hal o the layout is the low-!urrent sensor and the upper hal is the high-!urrent sensor"

#igure 10< Complete $ayout o the Chip

10

Circuit Simulation
All individual se!tions o the !ir!uit were simulated and veri ied separately be ore being

!ombined or the total simulation" The temperature sensing and ampli i!ation stage were !ombined into the irst simulation and the SAR ADC was simulated ne%t" The !omplete !ir!uit was then simulated and !hara!teri(ed" Fa!h o these simulations will be dis!ussed in the ollowing se!tions"

3"1 Temperature Sensing and Ampli i!ation 4eri i!ation

The irst portion o the !ir!uit that must be analy(ed is the operational ampli ier" The ampli ier must have a gain greater than )0 d7 at low re@uen!ies while having an a!!eptable phase margin" The simulation below in #igure 13 shows a low re@uen!y gain o )2"A1 d7 and a phase margin o )2"1," The ampli ier meets the ne!essary spe!i i!ations"

#igure 13< Simulation o =p Amp Chara!teristi!s

13

4oltages were measured rom the output o the ampli i!ation stage every 10 ,C rom -00 ,C to 100 ,C" These values were plotted and it with a line o best it" The result is a very linear relationship between the output voltage o the ampli i!ation stage and the temperature" The graph is shown below in #igure 1+"

#igure 1+< =utput o Ampli i!ation Stage vs" Temperature

1+

3") Analog-to-Digital Converter Simulation

The ollowing simulation shows the per orman!e o the ADC" A )0 -B( !lo!- was used to drive the simulation" The green line shows the target voltage level that represents the voltage generated by the temperature sensing and ampli i!ation stages" The blue line shows the output o the DAC" 9t !an be seen that only one bit is ad;usted per !lo!- !y!le until all 10 bits have been !y!led through" 9n the simulation the !onversion is !omplete at "1+ ms, and the digital output signals &red line' have been updated"

#igure 15< Simulation o SAR ADC

15

3"0 #ull Cir!uit Simulation

Simulations o the !ir!uit were run every 10 GC rom -00 GC to 100 GC" The digital output values were ta-en at ea!h o these points and !onverted to a de!imal value" The data was plotted in 8atlab and !hara!teri(ed using a linear it" The resulting graph gives a !hara!teri(ation o the devi!e or all temperature values within range" This graph is shown in #igure 11"

#igure 11< Simulated Digital =utput vs" Temperature #rom the line o best it e@uation, the sensor has a simulated ma%imum error o *"+ GC and a resolution o *")+ GC"

11

Test and Veri ication o De!ice

The devi!e has been laid out su!h that there are several ways o veri ying the per orman!e o

the !ir!uit" The pin mapping or the devi!e !an be seen below in the ollowing table" :ote< pins 1-12 re er to the high-!urrent design and pins )0-30 re er to the low-!urrent design" Table 1< Pin Conne!tions or the Chip (in )umber (in *unction 1 ) 0 3 + 5 1 A 2 10 11 1) 10 13 1+ 15 11 1A 12 )0 Digital =utH0I Digital =utH1I Digital =utH)I Digital =utH0I Digital =utH3I Digital =utH+I Digital =utH5I Digital =utH1I Digital =utHAI Digital =utH2I Ring =s!illator Post-7u er 7ias Resistor Pin 4oltage 7ias or Ampli i!ation Stage 4oltage 4) rom Temperature Sensing Stage 4oltage 41 rom Temperature Sensing Stage =utput rom irst ampli ier o the Ampli i!ation Stage 9nput to the ADC :C Ring =s!illator Pre-7u er Ring =s!illator Pre-7u er (in )umber )1 )) )0 )3 )+ )5 )1 )A )2 00 01 0) 00 03 0+ 05 01 0A 02 30 (in *unction 4dd Digital =utH0I Digital =ut1H1I Digital =ut1H)I Digital =ut1H0I Digital =ut1H3I Digital =ut1H+I Digital =ut1H5I Digital =ut1H1I Digital =ut1HAI Digital =ut1H2I Ring =s!illator Post-7u er 7ias Resistor Pin 4oltage 4) rom Temperature Sensing Stage 4oltage 41 rom Temperature Sensing Stage 4oltage 7ias or Ampli i!ation Stage =utput rom irst ampli ier o the Ampli i!ation Stage 9nput to the ADC :C Jround

1A

Several o the output pins !an be used to veri y ea!h se!tion o the !ir!uit" Debugging instru!tions or ea!h blo!- o the !ir!uit will be presented in the ollowing se!tions"

+"1 Temperature Sensing Cir!uit 4eri i!ation

The biggest down all o the temperature sensing !ir!uit is its relian!e on the resistor values" Although resistors were laid out to have the !orre!t value, it is li-ely that the resistors on !hip will not be at the designed values" This is due to pro!ess variation" 9 initial resistor values are in!orre!t, the di erential voltage output will be in!orre!t" This will lead to in!orre!t measurements" As a means o !ountera!ting this error, the bias resistor has been bro-en o o the !hip, to allow or the !urrent to be twea-ed" The pro!edure to determine this resistor value is as ollows" 1" Set the bias resistor to its !al!ulated value Rbias C 51A D &high !urrent' or Rbias C )3"A -D &low !urrent' )" 8easure voltages 41 and 4) 0" Ad;ust the value o Rbias until 41 C )4 and 4) C )"+4 &Assuming Temp C )1 ,C' =n!e 41 and 4) are appropriately set, the temperature sensing !ir!uit has been setup"

+") Ampli i!ation Stage 4eri i!ation

There should be ew errors present in the ampli i!ation stage" The irst ampli ier in the stage should have no issues" The gain should be largely independent o pro!ess variation sin!e all resistor ratios should be preserved" This ampli ier !an be veri ied by reading the output o pin 15 &high !urrent' or 01 &low !urrent'" A di erential gain o 2"A is e%pe!ted" Some amount o twea-ing !an be per ormed on the se!ond ampli ier in the stage" The 4bias o the inverting ampli ier is e%ternal to the !hip" This value !an be ad;usted to get the e%pe!ted value at the end o the ampli i!ation stage" The ollowing pro!edure !an be used to ad;ust the output o the ampli i!ation stage"

12

1" 4eri y the operation o the irst ampli ier by measuring the two inputs, 41 and 4), and the output" )" 8easure the output o the ampli i!ation stage" Ad;ust the e%ternal voltage supply to get the !orre!t input to the ADC" The input value !an be ound using the ollowing e@uation" 9nput C &"012AA5KTemp * )"3501' 4

+"0 SAR Analog-to-Digital Converter 4eri i!ation

There are a limited number o way to debug the SAR ADC due to pin limitations" The pro!edure to setup the SAR ADC and ta-e measurements is given below" 1" The ring os!illator may need to be started up manually" 8easure pin 11 and 0) with an os!illos!ope" 9 the os!illator is wor-ing properly s-ip step )" )" The ring os!illator was unable to start without initial !onditions" To provide the initial !onditions, tie pin 12 and )0 to ground momentarily" Remove the ground !onne!tion, and repeat step 1" 0" 8easure the analog input to the !onverter &pins 11 and 0A' as well as the digital output pins" The e%pe!ted digital value !an be ound using the ollowing e@uation" DigitalL=ut C 3"10AKTemp * +03"3+ The measurements resulting rom this pro!edure will be !ompared to simulated data on!e the abri!ated !hips have been tested" This report will be revised on!e these !omparisons have been made"

Summary and Conclusion

The design, simulation and layout o a 10-bit digital temperature sensor was des!ribed" The

design in!luded a !ir!uit sensitive to ambient temperature, an ampli i!ation stage that generated a usable input to the ADC and a SAR ADC that gave a 10-bit digital output" F%periment pro!edures were outlined" Results are orth!oming, but simulations show the sensor to have a resolution o appro%imately *")+ ,C with an ma%imum error o *"+ ,C" Fa!h !onversion too- an appro%imate minimum ++0 .s and an appro%imate ma%imum o 1"0+ ms" Test and veri i!ation pro!edures were outlined and des!ribed"

)0

5"1 Suggestion or #uture 6orCurrently, the biggest drawba!- o this devi!e is the number o 9M= pins re@uired to get a temperature reading" 9t ta-es a minimum o 10 pins on a mi!ropro!essor to get a valid reading" A state ma!hine !ould be added that responds to the 9)C proto!ol" =nly two pins would be re@uired i this were implemented" Aside rom the number o input pins, simulations indi!ate this devi!e should operate inline with many !ommer!ially o ered sensors in terms o !onversion time, resolution and a!!ura!y"

5") 7iography
Steven Pesut grew up in Crouseville, 8aine" Be graduated rom 6ashburn Distri!t Bight S!hool in 6ashburn, 8aine in )001" Be is !urrently !ompleting his 7a!helorNs degree in Fle!tri!al and Computer Fngineering at the Oniversity o 8aine and will be graduating in 8ay )011" Be will be wor-ing at Analog Devi!es, 9n!" as a produ!t test engineer starting Summer )011"

A&&endi'
1"1 S!hemati!s
)1

#igure 1A< Top-level Design S!hemati! ))

#igure 12< Temperature Sensing Cir!uit S!hemati!

)0

#igure )0< =perational Ampli ier S!hemati!

)3

#igure )1< Three-Stage Digital 7u er S!hemati!

)+

#igure ))< R)-R Digital-to-Analog Converter S!hemati!

)5

#igure )0< SAR $ogi! 7lo!- S!hemati!

)1

#igure )3< Shi t Register S!hemati!

)A

1") #inal Cir!uit $ayout

#igure )+< Complete Cir!uit $ayout

)2