1

Reactive Power Compensation using Sliding-Mode Controlled Three-Phase Multilevel Converters

Lus Encarnao, J. Fernando Silva, Senior Member, IEEE, and Vasco Soares

AbstractThis paper presents sliding-mode controlled multilevel converters for reactive power compensation. The reactive power compensation scheme here proposed includes a prototype three-phase multilevel converter and a digital signal processing system, in which sliding-mode and linear controllers are implemented. The instantaneous power theory is presented and used for reactive power compensation, together with the converter models needed for the application of the multilevel sliding-mode controllers and dc voltage capacitor equalization. Simulation and experimental results are shown in order to highlight the system operation and control robustness. Index Terms Reactive power, Sliding-mode control, Multilevel converter modeling, power quality enhancement.

I. INTRODUCTION he operation of electrical power lines at low power factor reduces the distribution capability, since current flow is unnecessarily increased, causing phase lag and voltage drops. Inductive loads such as induction motors and lighting ballasts are the main consumers of reactive power, worsening the regulation of the service voltage. Strategies to improve voltage regulation include tap changing transformers or the installation of shunt capacitor banks to reduce the current magnitude and shift it to be nearly in phase with the voltage. However, the shunt capacitor solution often produces parallel resonance frequencies near the 5th or 7th harmonic, increasing voltage distortion. Moreover, these compensation schemes are unsuccessful for rapidly varying loads. To solve these problems, reactive power compensation systems are being proposed, based in two-level three-phase electronic power converters. This work proposes the use of Neutral Point Clamped (NPC) three-phase multilevel converters, suitable for voltages in

the kV range. Closed loop control is accomplished using the instantaneous p-q theory [5,6,9], together with sliding-mode for line current control and linear controllers for dc capacitor voltage equalization [7,8]. All the controllers are implemented in a digital signal processing system (DSP). The fully controlled multilevel converter can operate as a source of reactive power (leading or lagging power factor). This paper presents the converter model (section II), as well as the instantaneous p-q theory to obtain the compensation currents for a linear three-phase inductive load (section III a). The sliding-mode approach, to enforce the line compensation currents, is presented in section III b. The controller for dc capacitor voltage equalization is described in section III c. The dc capacitor voltage control, being slow, uses a linear controller (section III d). Simulation results are presented in order to show the effectiveness of the proposed strategy (section IV). Section V shows experimental results. II. MULTILEVEL CONVERTER MODELING The NPC multilevel converter (fig. 1) model in systems coordinates (123) can be obtained using the Kirchhoff voltage and current, and assuming a ternary variable k(t) describing the output of each converter leg k:
1 if ( S k 1 S k 2 ) ON ( S k 3 Sk 4 ) OFF k ( t ) = 0 if ( S k 2 S k 3 ) ON ( S k 1 S k 4 ) OFF -1 if ( S S ) ON ( S S ) OFF k3 k4 k1 k2

(1)

Using also (2, 3, 4), the converter model is represent in (5)

1k = 2 k = k (1 + k ) 2 k (1 - k ) 2 (2)

(3)
221 22 23 (4) 21 + 222 23 21 22 + 223

Luis Rocha and Vasco Soares are with the Department of Electrical Engineering and Automation of the Instituto Superior de Engenharia de Lisboa, Instituto Politcnico de Lisboa, and Centro de Automtica da Universidade Tcnica de Lisboa, Portugal (e-mail: luisrocha@deea.isel.ipl.pt; vesoares@deea.isel.ipl.pt). J. Fernando Silva is with Energy group of the Department of Electrical and Computer Engineering, Instituto Superior Tcnico, and Centro de Automtica da Universidade Tcnica de Lisboa, 1049-001 Lisbon, Portugal, (e-mail: fernandos@alfa.ist.utl.pt). This work was supported in part by project POSC/EEA-ESE/60861/2004.

211 12 13 11 12 = = 1 + 2 22 11 12 13 21 3 2 + 32 13 11 12 31

This model will be used to control the dc voltage of capacitors, Udc. III. CONTROLLER DESIGN This section defines the line compensation currents using the instantaneous p-q theory [5, 6, 9] and the controllers synthesis using linear and non linear techniques. A. Compensation of reactive power
Fig. 1. Neutral Point Clamped (NPC) Three-Level Converter with IGBTs.
d i1 = R dt i2 L i3 0 U C1 U 0 C2 11 C1 21 C2 i1 i + 2 i3 U C1 U C 2 0 0

0 R L

0 0 R L 13 C1 23 C2

0 12 C1 22 C2

11 L 21 L 31 L 0 0

12 L 22 L 32 L

Using coordinates, the calculation of the references for the compensating currents can be obtained as a function of active or reactive power of the load (fig. 2). q T ; pT qL ; pL
Power Source Indutive Load

iT ; iT q C ; pC

iL ; iL iC ; iC

Reactive Power Compensation

Fig. 2. Block diagram of power flow

1 + L 0 0 0 0

0 1 L

0 0 1 L

0 0 0

0 0

u 0 S1 u S 2 0 uS 3 i0 0 1 C1 1 C2

Using the active power and coordinates, the following relations hold: (5)

pT = u q u T

u iT = u u iT u

u iL iC u iL iL

(8)

Solving for the currents as functions of total active power, pT, and total reactive power qT:

The multilevel converter model in 0 coordinates (6) can be obtained applying the Concordia transformation. This state-space model will be used to enforce the line compensation currents.
d i = R dt i L U C1 0 U C 2 - 1 C 1 2 - C 2 0 R L 1 C1 2 C2 1 L 1 L 0 0 2 i + 1 L L i 2 U C1 0 L U C 2 0 0 0 0 0 1 L 0 0 u 0 S uS 0 i0 1 C1 1 C2

iL iC = u i i u L L

u pT u qT

(9)

Since the system is conservative, the total active power equals the load active power pL=pT. To achieve reactive power compensation, we must have qT=0 (qC=qL), being:

(6)

iL iC = u i i u L L
Solving, it is obtained:

u pL u 0

(10)

The Parks transformation, applied to (6), gives the dq0 converter model presented in (7).
d i = R d dt i - L q U C1 - U C 2 - 1d C 1 2 d C2 R L 1q C1 2 q C2 1d L 1q L 0 0 2 d id + 1 0 L iq L 1 2 q U 0 C1 L L U C2 0 0 0 0 0 0 u 0 Sd uSq i 0 0 (7) 1 C1 1 C2

iL iC 1 i i = 2 2 L L u + u
Where the currents are:

u u

u pL u 0

(11)

u pL iC = iL 2 u + u2 u iC = iL pL 2 u + u2

(12)

Applying Parks transformation to (12) and using the reactive component, reference currents id ref and iq ref are derived. However, the id component must include the converter losses. Therefore, the active component id ref is obtained from the voltage control loop operating with the Udc variable (section III d). The compensating currents in coordinates (i ref and i ref) can be obtained applying inverse Parks transformation to id ref and iq ref. B. Sliding-mode control of the compensation currents This section presents the sliding-mode approach, to enforce the compensation currents references (i ref, i ref). The NPC converter model is non-linear and also 123 and models are time variant. Variable structure closed-loop control and sliding-mode in particular, can solve these problems in spite of requiring the reading or estimation of the system state variables. The control goal considered in this situation is defined by,

Fig. 3. Example of a controlled variable using sliding-mode control.

Therefore, if S ( ei, , t ) > + then S ( ei, , t ) < 0 , and if

S ( ei, , t ) < then S ( ei, , t ) > 0 . The power converter

control should increase or decrease the output voltage level to verify the precedent conditions. Therefore the multilevel switching laws are:
S ( ei , t ) > + S ( ei , t ) > 0 increase a level of u(t) until S ( e , t ) < 0 i

i = i ref i = i ref
and control errors are,

(17)

(13)

ei = i ref i . ei = i ref i

(14)

S ( ei , t ) < S ( ei , t ) < 0 decrease a level of u(t) until S ( e , t ) > 0 i

(18)

Since the state space model (6) is in controllability canonical form with respect to i and i currents, it can be concluded that the converter ac currents show a strong relative degree of one [7] (as its first time derivative contains the control variables). Therefore, according to the strong relative degree of each output variable, and considering the feedback errors as state variables, the sliding surfaces ensuring the robustness of the closed loop controlled system [8], are:

These conditions can be accomplished, considering that the capacitors voltages UC1 and UC2 are balanced for guarantee U U C1 U C 2 dc . Then, the output current vector dynamics, 2 in coordinates, is:

S ( ei , t ) = ki ( i ref i ) S ( ei , t ) = ki ei (15) S ( ei , t ) = ki ( i ref i ) S ( ei , t ) = ki ei

Sliding-mode exists if S ( ei, , t ) = 0 . To ensure that the system remains in sliding-mode operation the controller should also guarantee S ( ei, , t ) = 0 . These two conditions can only exist if an infinite switching frequency was used. In a practical power converter, the switching frequency is upper-bound limited by the semiconductors switching losses. Thus, a small current error (ripple) will be present (fig. 3). Since the controller is designed to stabilize the system, the following relation (sliding-mode stability condition) must be ensured:

d i = R dt i L 0

i - 1 0 L i R 0 L

u + 1 0 S L uS 1 0 L

U 0 S U S (19) 1 L

Using (15), the derivatives of the switching surfaces are:

R 1 1 d S ( ei , t ) = ki dt i ref + L i + L us L U s d R 1 1 S ( ei , t ) = ki i ref + i + us U s d t L L L Therefore:

(20)

S ( ei, , t ) S ( ei, , t ) < 0

(16)

S ( ei , t ) > 0 S ( ei , t ) < 0

d U S < L dt i + Ri + us d U S > L i + Ri + us d t

(21)

Then, the switching laws are:

S ( ei, , t ) > + S ( ei, , t ) > 0 (22) S ( ei , t ) > + S ( ei , t ) > +

capacitor voltage equalization will be discussed in the following section.

U s < L

d i ref + Ri + us dt d i ref + Ri + us dt

U s < L

S ( ei, , t ) < S ( ei, , t ) < 0 (23) d S ( ei , t ) < U s > L dt i ref + Ri + us d S ( ei , t ) < U s > L i ref + Ri + us dt When conditions (22) hold, the NPC converter controller must increase the level of the US voltage. Conversely, if the conditions (23) hold, the NPC converter controller must decrease that level. This is done increasing or decreasing integer variables , {-2,-1,0,1,2} and then selecting vectors in the plane accordingly. Considering again voltages UC1=UC2=Udc/2, the application of the Concordia transformation to the USk voltages (fig. 1) gives these voltages in the plane:

Fig. 4. Output voltage vectors (33=27) of three phase NPC, Multilevel Converter in frame.

Table II Switching Table for (UC1-UC2) in> 0 -2 -1 0 1 2 \ -2 25 25 12 7 7 -1 24 26 26 11 8 0 19 23 14 10 9 1 20 22 22 15 4 2 21 21 16 3 3

C. DC link capacitor voltage equalization The two DC-link capacitor voltages (UC1, UC2) must be balanced. The redundant vectors in tables I (2, 5, 6, 13, 17, 18) 1 1 1 U dc U 2 and II (10, 11, 15, 22, 23, 26) can provide an extra degree of 1 U = 2 2 2 3 2 (24) freedom to allow dc capacitor voltage equalization. Therefore 3 3 3 capacitor voltage equalization will enable the right choice 0 between the center vectors of table I and table II, done 2 2 according to the sign of the power flow in the two capacitors Being k given by (1), the converter presents 27 U, U midpoint. combinations or vectors (fig. 4). This multilevel converter From the circuit of fig. 5, it is written: shows nine levels for the component and five levels for component. To select one out of 25 vectors (3 are null vectors) in = iC1 iC 2 two 55 tables (table I and table II) were created, with the (25) integer variables , as inputs. Using (5): Table I Switching Table for (UC1-UC2) in< 0 3 3 -2 -1 0 1 2 \ I K + io iK 1K + io -2 25 25 12 7 7 dU C1 iC1 i + io k =1 = k =1 dt = C = C = -1 24 13 13 6 8 C1 C1 1 1 (26) 3 3 0 19 18 14 5 9 I K + io iK 2 K + io 1 20 17 17 2 4 dU C 2 iC 2 i+io k =1 = = = = k =1 2 21 21 16 3 3 C2 C2 C2 C2 dt The redundant vectors, present in these tables, will be used to dc capacitor voltage equalization. Table selection and

C1

UC1

iC1 iC 2
C2

in

UC2

D. Linear Control of the Udc Voltage The linear control of the Udc voltage provides the id ref component as said previously. The controller is designed from the converter model in dq0 coordinates (7), considering U C1 = C2 = 2C and U C1 = U C 2 = dc . 2 From (7) the Udc voltage dynamics is:

iq i dU dc id = d + q + o C C C dt
Fig. 5. Circuit and variables for capacitor voltage equalization.

(30)

At unity power factor, this leads to:

Therefore:
dU C1 i111 i2 12 i3 13 + io dt = C1 dU i i i + i C 2 = 1 21 2 22 3 23 o d t C2

dU dc id i = d + o dt C C
(27)

(31)

Considering C and the output dc current io as a disturbance U io = - dc the equivalent model (32) is obtained (fig. 7). Req
id io

Calculating the first derivative of the control error eC12=UC1-UC2, and considering C1=C2=C:
in = C
3 ( +1) 3 k (1 k ) deC12 = iK k k + iK dt 2 2 k =1 k =1

Udc

iC

The two capacitors midpoint current in is a function of i1 and i2:

C
d id

Req

in =

i1 32 12 + i2 32 22 C

) (

(28)

Fig. 7. Equivalent model of the converter dc side.

Therefore the switching law for eC12 is: If (UC1-UC2) in< 0 table I (29) If (UC1-UC2) in> 0 table II Figure 6 shows a MATLAB/Simulink implementation of this algorithm.

d Req U dc ( s ) = I d ref ( s ) Req Cs + 1

(32)

Assuming a small time delay Td in the current controlled current source d id, the block diagram for the Udc control is shown in fig. 8.
Udc ref. e C(s) Id ref.

d 1 + sTd

Id

Re q Re q Cs + 1

Udc

Fig. 8. Block diagram of the linear control.

The C(s) controller is a PI controller C(s)=kP +

with kC=kI and C=kP/kI. The zero of the s controller is used to cancel the system dominant pole, resulting in a 2nd order system with transfer function (33).

C(s) =

kC ( c s + 1)

kI s

or

kC d Req U dc ( s ) = U dc ref ( s )
Fig. 6. Controller for capacitor voltage equalization.

Td s kC d Req s2 + + Td Td

(33)

Comparing with 2nd order standard transfer function (34):

n2 Y (s) = 2 X ( s ) s + 2n s + n2
The following relations hold:

(34) i3T u3s u3s i3T

1 2n = T d 2 kC d Req n = Td k = k I C kP C = Req C = k I

1 n = 2T d n 2 Td k I = kC = d Req k = k R C I eq P

a) Before compensation

b) After compensation

(35)

Fig.10 Simulation Results showing: Current in line 3 (2A/Div) and voltage in phase 3 (100V/Div)

V. EXPERIMENTAL RESULTS A NPC multilevel inverter laboratory prototype was built using 1200V, 50A IGBT Transistors (MG50Q2YS50), switching frequencies near 5 kHz, neutral clamp diodes (IRKD56/16A, (fig. 11), C1=C2=4.7mF and inductive load RL (3x25mH, 10). The three level converter was controlled using DSpace DSP 1104 (fig. 12 and 13).

If the controller is designed with a damping factor <1 a strong voltage unbalance can arise. Therefore, a slower response speed is selected (=9), so that the Udc voltage error decreases to zero. Using the NPC converter parameters, C = 2.35 mF ; Req = 4.4 k ; Td = 0.1 ms ; d = 0.44 , the PI parameters are kI=0.02 and kP=0.16. IV. SIMULATION RESULTS The simulation results of shunt VAr compensator were obtained using Simulink environment in accordance with figure 9.

Fig. 11 Multilevel converter for experimental tests.

;
Conv

i ,

i ,
ref Conv

e ,

Fig. 9. Block diagram of the reactive power compensation system.

Fig. 10 shows the current in line 3 (1A/Div) and voltage in phase 3 (100V/Div) before a) and after compensation b).

Fig. 12 Block diagram of the multilevel converter prototype, load and control board

sliding-mode. Presented simulation and experimental results shown the effectiveness of the proposed strategy. VII. REFERENCES
[1] J. Fernando Silva, Control methods for Power Electronics, in Power Electronics Handbook, M.H. Rashid, Ed. New York, Academic Press, 2001, pp .67-75 cap19. J. Fernando Silva, F. Pires, S. Pinto, D. Barros Advanced Control Methods for Power Electronic Systems J. Fernando Silva, Sliding Mode Control Of Multilevel Power Converters, 9th Conference on Power Electronics and Motion Control EPE-PEMC2000 Kosice. J. Fernando Silva, Converso Multinvel em Electrnica de Potncia, Dezembro 2001. Watanabe, E. H, Aredes, M.,.(1998), Teoria de Potncia Ativa e Reativa Instantnea e Aplicaes Filtros Activos e FACTS, CBA98, Uberlndia, MG, Setembro. J. Afonso, M. J. Seplveda, J. S. Martins,.p-q Theory Power components Calculations, ISIE2003 IEEE International Symposium on Industrial Electronics, Rio de Janeiro, Brasil, 9-11 Junho de 2003, ISBN: 0-7803-7912-8. Gao W., Hung J., Variable structure control: A Survey IEEE Transactions on Industrial Electronics, vol. 40, no. 1, pp. 2-22, February 1993 J. Fernando Silva, Sliding Mode Control Design of Drive and Regulation Electronics for Power Converters Special Issue on Power Electronics of Journal on Circuits, Systems and Computers, vol. 5, no. 3, pp. 355-371, September 1995. Akagi, H.; Kanazawa, Y.; Nabae, A.; Generalized Theory of the Instantaneous Reactive Power in Three-Phase Circuits; JIEE-IPEC, pp. 1375-1386, 1983.

[2] [3]

[4] [5] Fig. 13 Multilevel converter for experiments and tests

Fig. 14 shows experimental results of the current in line 3 (1A/Div) and voltage in phase 3 (100V/Div) before a) and after compensation b). Fig. 14 shows the experimental voltages obtained in the two dc capacitors showing the equalization behavior.

[6]

[7]

[8]

[9]

i3T u3 s

i3T

VIII. BIOGRAPHIES
u3 s Lus Encarnao was born in Portimo, Portugal, in 1973. He received the B.S and electrical engineering degrees from Instituto Superior de Engenharia de Lisboa, Lisbon, Portugal in 1995 and 1999, respectively. Presently, he is an Assistant at the ISEL where he teaches Control Theory and a researcher at Centro de Automtica. He is currently working towards M.Sc degree. His research interests include control and modeling applied to energy systems and power electronics systems. J. Fernando Silva (M90) born in 1956, Mono Portugal, received the Dipl. Ing. in Electrical Engineering (1980), the Doctor Degree in Electrical and Computer Engineering (EEC) in 1990 and the Habil. Degree in Electrical and Computer Engineering in 2002, from Instituto Superior Tcnico (IST), Universidade Tcnica de Lisboa (UTL), Lisbon, Portugal. Currently he is an Associate Professor of Power Electronics, of the Energy group at the Department of EEC, IST, teaching Power Electronics and Control of Power Converters. As a researcher at Centro de Automtica of UTL, his main research interests include modeling, simulation, topologies and advanced control in Power Electronics. Vasco Soares was born in Lisboa, Portugal, on March 26, 1969. He received the Dipl. Ing. degree in Electrical Engineering and Automation from Instituto Superior de Engenharia de Lisboa, in 1993, and the M.S. and Ph.D. degrees in Electrical and Computer Engineering from Instituto Superior Tcnico, Lisboa, Portugal, in 1997 and 2005, respectively. In 1993 he joined Instituto Superior de Engenharia de Lisboa. Since 1999, he has been an Assistant Professor and Researcher. His fields of study are active filters, reactive power compensation, power quality, control of static power converters, instrumentation and signal processing.

a) Before compensation

b) After compensation

Fig.14 Experimental Results showing: CH1-Current in line 3 (CH1-2A/div) and CH2-Voltage in phase 3 (CH2-100V/div)

UC1

UC2

Fig.15 Experimental Results showing: Capacitor voltages UC1 and UC2 balanced (10V/Div)

VI. CONCLUSIONS This paper presented NPC multilevel converter model, as well as the instantaneous p-q theory, suitable to obtain the compensation currents for reactive power compensation of three-phase inductive loads. To enforce the line compensation currents a robust sliding-mode approach was presented. The dc link capacitor voltage control was designed using a linear controller, although dc link capacitor voltage equalization used