Spin

Semiconductor

SPINAsm&FV1InstructionSet
Assembler/DownloaderforSPINFV1ReverbChip

22April2008
SPN1001ASM080422

SpinAsmSoftwareInstallation......................................................................................................... 1
InstalledSpinAsmFolders............................................................................................................... 3
SPN1001USBDevelopmentBoardInstallation .............................................................................. 5
PluggingintheSPN1001 ................................................................................................................ 5
RunningSpinAsm............................................................................................................................ 8
TheMainToolbar............................................................................................................................ 8
TheAssemblerToolbar................................................................................................................... 9
SpinAsmMainWindowstatusbaratthebottomoftheSpinAsmwindow: ...................................... 10
Assemblyandtestingprograms .................................................................................................... 11
SpinAsmAssemblerErrors&Warnings ....................................................................................... 13
SpinAsmErrors&Warnings.......................................................................................................... 13
Warnings ...................................................................................................................................... 14
SpinAsmProjectMode................................................................................................................... 17
PreservingExistingProgramsinSPN1001ProgramMemory ........................................................ 19
BuildingaProject .......................................................................................................................... 20
ChipInternals ................................................................................................................................. 21
RegisterBank ............................................................................................................................... 21
DelaySRAM ................................................................................................................................. 21
LFOs............................................................................................................................................. 22
POTs ............................................................................................................................................ 22
ADC/DAC ..................................................................................................................................... 22
ALU .............................................................................................................................................. 23
InstructionLineFormat.................................................................................................................. 24
Operanddatatypes ........................................................................................................................ 24
Signedfixedpointvalues .............................................................................................................. 24
Unsignedandsignedintegers ....................................................................................................... 25
Bitvectors..................................................................................................................................... 25
AssemblerStatements ................................................................................................................... 26
EQUStatement............................................................................................................................. 26
MEMStatement ............................................................................................................................ 27
TheFV1InstructionSet................................................................................................................. 28
Accumulatorinstructions ............................................................................................................... 30
SOF.........................................................................................................................................................30
AND ........................................................................................................................................................31
OR...........................................................................................................................................................32
XOR ........................................................................................................................................................33
LOG ........................................................................................................................................................34
EXP.........................................................................................................................................................35
SKP .........................................................................................................................................................36
Registerinstructions...................................................................................................................... 38
RDAX ......................................................................................................................................................38
WRAX......................................................................................................................................................39
MAXX......................................................................................................................................................40
MULX .....................................................................................................................................................41
RDFX ......................................................................................................................................................42

WRLX......................................................................................................................................................43
WRHX .....................................................................................................................................................44
DelayRaminstructions ................................................................................................................. 45
RDA ........................................................................................................................................................45
RMPA......................................................................................................................................................46
WRA ........................................................................................................................................................47
WRAP......................................................................................................................................................48
LFOinstructions............................................................................................................................ 49
WLDS......................................................................................................................................................49
WLDR .....................................................................................................................................................50
JAM.........................................................................................................................................................51
CHORDA ...............................................................................................................................................52
CHOSOF................................................................................................................................................54
CHORDAL .............................................................................................................................................55
PseudoOpcodes .......................................................................................................................... 56
CLR.........................................................................................................................................................56
NOT ........................................................................................................................................................57
ABSA.......................................................................................................................................................58
LDAX ......................................................................................................................................................59
PredefinedSymbols ....................................................................................................................... 60
ChangeNotes ................................................................................................................................. 62

ii

SpinAsmSoftwareInstallation
Webor.msifileinstall:
LaunchSpinSetup.msifromanywhere.
YouwillseetheSpinAsmIDESetupWizard.
WindowsXP:

InitialSpinAsmsoftwareinstallationdialog.

YoumayinstallSpinAsmwhereveryoulike.Thedefaultc:\ProgramFiles\SpinAsmIDEfolderisused
duringsetupunlessyouenteraninstallfolderbyusingtheBrowsebuttonortypingitin.
Forsimplicity,clickEveryonetoinstallSpinAsmforallusersonyourcomputer.
ClickNexttoproceed.TheConfirmInstallationdialogwillbedisplayed.
AlsoclickNextontheConfirmInstallationdialogtoproceed.

ThisdialogisshownduringtheinstallationofSpinAsmsfilestoyourharddisk.
OnceithascompletedSpinAsmsoftwarewillbeinstalledonyourcomputer.ClicktheClosebuttonin
theInstallCompletewindowtocompletethisphaseoftheinstallation.

InstalledSpinAsmFolders
WhenthesoftwareinstallationiscompleteyourSpinAsmfoldercontainsthefollowingfolders:

c_hdrout

DefaultfolderforoutputofCsourcetypeheaderfilesgeneratedfromtheProjectBuild
feature.

driver

USBdriverfortheSPN1001DEVBFV1developmentboard.

help
hexout

SpinAsmhelpfilesandotherdocumentation.
DefaultFolderforIntelHexfileoutputfromtheProjectBuildfeature.

projects

DefaultfolderforSpinAsmprojects.

spnsrc

DefaultfolderforSpinAsmsourcefiles.
ThesedefaultdirectorysettingscanbechangedintheSetupDialogbox.

SPN1001USBDevelopmentBoardInstallation
IfyouhavetheSPN1001DevelopmentboardyouwillhavetoinstalltheUSBdriverforit.Thedriveris
locatedinthedriverfolderoftheSpinAsmprogramfolder.Formostinstallationsitwillbec:\Program
Files\SpinAsmIDE\driver.
TheSPN1001isactuallyaUSB2.0devicebutwillworkonanyUSB1or2host.

PluggingintheSPN1001
PlugtheSPN1001intoyourcomputerusingastandardUSBcable.
WindowswilldetectthenewUSBdevice:

ClickNo,notthistimetoallowyoutopointtheinstallertotheSpinAsmdriverfolderthatwascreated
duringtheSpinAsmsoftwareinstall.
ClickNexttoproceed.

WindowsknowsitissupposedtofindthedriverfortheSPN1001device.ClickonInstallfromlistora
specificlocation.
ClickNexttoproceed.

Settheoptionsupasshownhere.Ifyouhaveinstalledtheprograminadifferentdirectorythenyoumay
havetousetheBrowsebuttontoselecttheproperlocationofthedriverfolder.
ClickNexttoproceed.
Theinstallerstransferdialogwillpopupandyouwillseethiswarning:

ClickContinueAnywaytoproceed.Theinstallerwillbegintransferringfilesandadialogwilldisplaya
progressbarduringcopying.Whenfiletransferandinstallationarecompleteyouwillseethefollowing
dialog:

AtthispointyourSPN1001isreadytousewiththeSpinAsmIDEtodevelopandtestnewprograms.

RunningSpinAsm

SpinAsmShortcut
YoucanlaunchSpinAsmfromtheSpinAsmshortcutlocatedonyourdesktoporyoucangotoStart|
Programs|SpinAsmIDE andlaunchSpinAsmfromthere.

WhenSpinAsmstartsyouwillseeablankworksurfaceandtwotoolbars,

TheMainToolbar

Thistoolbarcontainsthestandardfilenew,fileopen,filesaveicons.
Gotospinsemi.com

OpentheProjectModeDialog
OpentheSetupDialog

TheAssemblerToolbar
(disabledwhennosourcefilesareloaded)
Assemblethecurrentsourcefile
Showthemachinecodefromthelastassembly

SpinAsmMainWindowstatusbaratthebottomoftheSpinAsmwindow:
StatusbarwithSPN1001disconnected

StatusbarwithSPN1001connectedandonline
TheSpinAsmStatusbaratthebottomofthemainwindowdisplaysthefollowinginformation:
1.
2.
3.
4.
5.
6.

StatusofSPN1001DevelopmentBoard.OnlineorOffline.
ProgressbarsfordownloadingUSBSoftwaretotheSPN1001USBcontroller
ProgressbarsforsendingSpinAsmassembledprogramstoSPN1001ProgramMemory
ErrorMessagesfromSourceCodeAssemblyduringdevelopment
EditorLineNumberinsourcefilebeingedited.
KeyboardStatus
a. CAP
b. NUM
c. SCRL

CapsLock
NumLock
ScrollLock

7. GeneralprogramstatusanderrormessagesfromSpinAsm
WiththeSPN1001disconnectedyouarestillabletocreateandassembleprogramsfortheFV1.
SpinAsmwillnotattempttowritetotheSPN1001andwillsimplyassembleyourprogramandallowyouto
debugit.

10

Assemblyandtestingprograms
YoucaneditanynumberoffilesinSpinAsmatonetimesimplybyloadingtheminorstartingnewfiles.
SpinAsmcontainsastandardbarebonestexteditorwithasinglelevelofundoandsimplefindand
replacetools.

AssemblyToolbar

AssembleButton
(disabledwhennosourcefilesareloaded)
ThefilewhichisintheactivewindowisthefilewhichwillbeassembledwhentheAssemble buttonis
pressed.
Program0
IfyouhavetheSPN1001developmentboardconnectedviaUSBwhileyouassembleSpinAsmwillwrite
theoutputfromasuccessfulassemblytothefirstprogramslot(prog0)oftheSPN1001program
memory..
WhentheSPN1001INTEXT switchissettoEXT theFV1willreaditsprogramsfromtheprogram
memoryinthesocketontheSPN1001.Asyouwriteandtestprogramsyouwilluseprogram0totestand
modifythem.MakesuretheprogramselectorswitchontheSPN1001issettoprogramzero.
AfterasuccessfulwritetotheSPN1001programmemorytheSPN1001willtoggletheFV1sINTEXT
lineandtheFV1willloaditsprogrammemoryfromtheEEProm.
NOTES:
WhentheSPN1001ispluggedinandonlineSpinAsmwillwritetheoutputofsuccessful
assembliesintotheSPN1001programmemoryautomatically.
InordertouseheartheresultsthisfeatureyoumusthavetheProgramSelectorswitchon
theSPN1001settoProgram0andtheINTEXTswitchsettoEXT.

11

AssemblyToolbar
SpinAsmOutputWindow
OnceSpinAsmbeginsassemblyofasourcefileanOutputwindowwillopenwhichwilldisplaytheresults
oftheassembly.

Asuccessfulassembly
AsyoucanseeherealistofLABELS,EQUATES,MEMORYallocationsandtheavailable(unallocated)
samplememoryisdisplayed.

12

SpinAsmAssemblerErrors&Warnings

Err#

AsmPassErrIDLineNumSourceCodeErrorDescription
SpinAsmErrorDisplay

Clickingonany partofanerrorlinewillbringyoutothesourcecodewheretheerroroccurred.

SpinAsmErrors&Warnings
GeneralError
ERR_GENERAL
ProgramFailure
ERR_PROGRAM_FAIL
Operandorcommamissing
ERR_NO_OPERAND
CalcErrorinoperand1
ERR_CALCERR
Addressoutofrange
ERR_DELAYADDR_RANGE
Coefficientoutofrange
ERR_COEFF_RANGE
Addressregisteroutofrange
ERR_REGISTER_RANGE
Extraoperand(s)online
ERR_EXTRA_OPERAND
Maskbitwidthoutofrange
ERR_MASK_RANGE
Toomanyelementsinoperand
ERR_OPERAND_SIZE
BadskipflagUSE{RUN,ZC,Z,GE,N} ERR_BAD_SKPFLAG
Skipoutofrange
ERR_SKIP_RANGE
TooManyMathOperators
ERR_EXTRA_MATHOPS
IllegalCharactersin
ERR_ILLEGAL_CHARS
UndefinedNameorForwardReferenceERR_FORWARD_REF
ProgramLengthExceedsLimit
ERR_PROGRAM_LENGTH
InvalidEquate
ERR_INVALID_NAME
EquateValueError
ERR_EQUATE_VALUE
NonAlphaCharcannotbeginName ERR_NONALPHA_START
BadLfoValue
ERR_BAD_LFOVAL
InvalidExpression
ERR_INVALID_EXPRESSION
IntegerValueoutofRange
ERR_INT_RANGE
NameExistsasaLabel
ERR_NAME_EXISTS_AS_LABEL
NameExistsasEquate
ERR_NAME_EXISTS_AS_EQUATE
NameExistsasMemDefine
ERR_NAME_EXISTS_AS_MEM
NameExistsasReservedWord
ERR_NAME_EXISTS_AS_RESERVED
MemoryDefineError
ERR_MEMORY_ERROR
NoLabelTextPreceedsColon
ERR_NO_LABEL
Whitespaceinlabel
ERR_LABEL_WHITESP
SRAMareaexceeded
ERR_SRAM_EXCEEDED
UnrecognizedorobsoleteOpcode
ERR_BAD_OPCODE
FAILEDOnPass
ERR_FAILED_PASS
UnimplementedOpcode
ERR_UNIMPLEMENTED_OPCODE

13

Warnings
RedefinitionEQUorMEM
Neg&PosskipflagsinSKPCondition

14

WARN_REDEFINE
WARN_SKP_FLAGS

AssemblyToolbar
MachineCodeButton

Tick

Opcode

SourceCode

Clickthe
buttonIfyouwanttoviewtheactualmachinecodeproducedbySpinAsmafteran
assembly.SpinAsmwilldisplaythemachinecodeslistingintheSpinAsmOutputWindow.Youmaycopy
thecontentsofthiswindowintotheclipboardbydraggingyourmousetoselectandtypingCTRL+C.Or
RIGHTCLICKandSelectAllandthenrightclickagainandselectCopy.
Note,intheSpinAsmprojectmodethisfeaturewillonlyshowtheresultsforthelastprogramassembled
inthebuild.Useitwheneditingandtestingsinglefilesasareference.

15

SpinAsmSetupDialog
MainToolbar
SpinAsmSetupDialog

SpinAsmSetupDialog
Usethebrowsebuttonstosetthefolderstoyourdesiredlocations.See(InstalledFolders)fora
descriptionofeachofthefolders.Youcanalsodoubleclickonthewhiteareastobrowseforafolder.
SpinAsmsavesthesesettingsinthespinasm.inifile,ratherthantheregistry,inyourwindowsdirectory.
SoundOn
SpinAsmwillbeepyourcomputersspeakerwhenerrorsoccurandattheendofasuccessfulassembly.
Usethischeckboxtoturnthosesoundsoff.Allothersystemsoundswillworkthesame.
ResetAll
ResetAllwillresetthedefaultfoldersforSpinAsmjustastheywerewhenyouinstalledit.Itwillalsoreset
thelocationsofanySpinAsmwindowstotheirdefaultpositions.Usethisfeatureifyouhaveinadvertently
placedtheoutputwindoworanyotheroffthescreenorifyouhaveremovedamonitorfromyour
workstationandcannolongerviewyouroutputorprojectwindows.

16

SpinAsmProjectMode
MainToolbar
SpinAsmProjectModeDialog

SpinAsmProjectModeDialogBox.
TheProjectModeallowsyoutoorganizeupto8FV1programsforwritingtotheEEPromprogram
memoryontheSPN1001developmentboard.
Fromtheprojectmodedialogyoucan:
a.
b.
c.
d.

LoadspecificFV1programsintoprogramslots18
Clearprogramslots
DirectthebuildtogenerateIntelHexfilesandCheadertypesourcefiles.
EnablewritingthebuildtotheSPN1001programmemory.

EachentryintheProjectDialogisafilenamewhichrepresentsaSpinAsmsourcefile.Thereareeight
entriescorrespondingtotheeightprogramslotsintheSPN1001programmemory.
WhenyoubuildyourprojectSpinAsmwillloadeachofthefilesoneatatimeandassemblethem
automatically.IfthereareanyerrorsthecurrentbuildsourcefilewillstayopenandtheSpinAsmoutput
windowwillremainopenwiththelistoferrors.Asinthenormaleditingmode,clickingonanerrorwill
bringyoutotheplaceinthesourcefilewheretheerroris.Youcanthencorrecttheerrorandclickonthe
Buildbuttontorebuildtheproject.

17

UsetheFullPathscheckboxtoshowonlythefilenamesorthefullpathsofyoursourcefiles.

FullPathsunchecked
ProjectModeRightClickMenu
Ifyourightclickononeoftheprogramslotsyouwillseethefollowingmenu:

rightclickonaprogramslot
LoadFileEntry:
ThismenuselectionwillallowyoutobrowseyoursourcecodefilesforaSpinAsmsourcefilefor
thatslot.Thefileyouselectwillbeassembledandusedduringaprojectbuild.
ClearFileEntry:
Thismenuselectionwillonlybeenableifthereisafilenameintheprogramslot.Selectingthis
willcleartheslotbackto
see"PreservingExistingPrograms".
EditThisFile:
Themenuselectionwillonlybeenabledwhenthereisafilenameintheprogramslotyouhave
rightclickedon.SelectingEditThisFilewillopenthesourcefileintheeditor.Ifthefileisalreadyopenit
staysopenandisselectedforediting.

18

PreservingExistingProgramsinSPN1001ProgramMemory
Whenyouopenanewprojectalloftheprogramslotswillcontainthetext:

Whenyouseethe[UNCHANGEDNOOVERWRITE]entryinaprogramslotitmeansthatwhenyou
buildyourprojectitwillpreserveanyprogramsalreadyinthosememorylocationsintheSPN1001
programmemory.Thisfeatureenablesyoutobuildprogramswithouterasingexistingprogramsinthe
SPN1001youwishtopreserve.
NOTE:
IfthereisnoSPN1001pluggedinanyprogramslotswithnofilenameentrywillbebuilt
withNOPs.ThisisbecausetheSPN1001EEPromwillnotexisttobereadfromso
SpinAsmdefaultsfillingthoseslotswithNOPS.

19

BuildingaProject

Onceyouhaveselectedallofthefilesyouwantinaparticularprogramgroupyoumaybuildthemintoan
EEPromimageand,ifyourSPN1001isconnected,writethatimagetotheSPN1001programmemory.
Herearethethreechoicesforaprogrambuild:
IntelHex
WriteanIntelhexformattedtextfileofthebuild.Thiswillalwaysincludeall8program
locations.
SourceFile
WriteaCformattedheadertypefilewitharrayentriesforeachprogram.
SpinAsmwillseparateeachprogramwithanewarrayname.
WriteEEProm
IftheSPN1001boardispluggedinthebuildwillbewrittentotheonboardEEProm
SelectyouroutputchoiceswiththecheckboxesandclickontheBuildbuttontobeginthebuild.The
SpinAsmOutputwindowwillopentodisplaythestatusofthebuildprocedure.

Successfulprojectbuildwithwriteenabled

Asyoucanseewevekepttheoutputverbose.Youwillseethesemessagesontheoutputscreenduring
abuild/writecycle.Shouldyouhaveproblemswithyourproductionsystemthisoutputcanbehelpfulin
debuggingit.

20

ChipInternals
TheFV1containsarichsetoffeaturesthatallowsthedevelopertocreateexcitingeffects.These
featuresaredescribedbelow.

RegisterBank
TheFV1hasaninternalregisterbankthatprovidesaccesstothevariousI/OslikeADC,DAC,POT
inputs,etc.Additionallyithas3224bitregistersforuseaslocalregistersseparatefromthedelay
memory.Theinstructionuseddetermineswhethertheuserisaccessingtheregisterbankorthedelay
memory,instructionsthatendwithandX(RDAX,WRAX,etc.)willaccesstheregisterbankwhile
instructionsthatdonotendinX(RDA,WRA,etc.)accessthedelaymemory.Pleaseseetheinstruction
setinformationlaterinthismanual.
Registerbankmemorymap
Address
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2531
3263

Name
SIN0_RATE
SIN0_RANGE
SIN1_RATE
SIN1_RANGE
RMP0_RATE
RMP0_RANGE
RMP1_RATE
RMP1_RANGE
Notused
Notused
Notused
Notused
Notused
Notused
Notused
Notused
POT0
POT1
POT2
Notused
ADCL
ADCR
DACL
DACR
ADDR_PTR
Notused
REG0REG31

R/W
W
W
W
W
W
W
W
W

Comments
WriteSIN0 frequencycoefficient
WriteSIN0range
WriteSIN1 frequencycoefficient
WriteSIN1range
WriteRMP0frequencycoefficient
WriteRMP0range
WriteRMP1frequencycoefficient
WriteRMP1range

R
R
R

ReadPOT0input
ReadPOT1input
ReadPOT2input

R
R
W
W
W

ReadleftADCinput
ReadrightADCinput
WriteleftDACoutput
WriterightDACoutput
Writeaddresspointerregister

R/W

24bitgeneralpurposeregisters

DelaySRAM
TheinternalSRAMisconfiguredas32Kx14.Dataisstoredinacompressedfloatingpointformat,itis
expandedto24bitfixedpointS.23formatafterbeingreadandpriortobeingusedintheALU.TheACC
intheALUcanbewrittentotheSRAM,itisconvertedtothe14bitfloatingpointformatpriortobeing
writtentoSRAM.TheSRAMaddressisgenerallycalculatedbyaddingtheaddressintheinstructiontoa
downcounterthatdecrementsonceeachsampleperiodandifitisachorusinstructionthatisbeing
executedthenalsotheoffsetfromtheLFO.Asaresultofusingadowncounter,delaysarewrittentothe
loweraddressandreadfromtheupperaddress.I.e.ifa20sampledelayisdesireditcanbe
implementedbywritingtoaddress0andreadingfromaddress20.

21

LFOs
TheFV1containstwoSIN(LFO0andLFO1)andtworamp(LFO2andLFO3)LFOs.TheSINLFOscan
beusedforeffectssuchaschorus,ringmodulators,flange,etc.Therampscanbeusedforpitchshifting
upordown.TheSINLFOsproducebothanaddressoffsetthatisaddedtotheaddresstotheSRAMand
acoefficientforusebytheALUmultiplierforinterpolationbetweenvalues.Therampgeneratorsgenerate
anaddressoffset,aninterpolationcoefficientandacrossfadecoefficienttocrossfadebetweentheramp
exitingoneendofthedelayandenteringtheotherend.Therampcangenerateappropriatewaveforms
forpitchingupordownbasedonthesignofthefrequencycoefficient,positiveispitchup,negativeis
pitchdown.
CoefficientsfromtheLFOsrangefrom0to+1.0

POTs
Thechipcanreadthevalueofthreeexternalpotentiometersconnectedtopins20,21and22.Thepots
canbereadwithapproximatelya10bitresolutionandthevaluescanbeusedascoefficientsin
programs.ThevaluesfromthePOTsrangesfrom0to+0.99

ADC/DAC
TheinternalADCsprovides24bitvaluesthatrangesfrom1.0to+0.99ValueswrittentotheDACwill
alsobeintherange1.0to+0.99

22

ALU
FromDRAM FromRegisters FromADCs FromPOTs FromLFOs

LR

Sat/Limit
FromLFOs FromInstruction
AND/OR/XOR

ACC

LOG

PACC

EXP
ToDRAM ToRegisters

ToDACs

ThetopALUadderis25bits,the24bitdatafromtheADC/SRAM/etc.issignextendedto25
bits.Themultiplieris25bitsby16bits.The16bitcoefficientactuallydependsontheinstruction
beingexecuted.Someinstructionsonlyallowforan11bitcoefficientfield,inthesecasesthe
coefficientis0paddedinitsLSBs.Theformatofthecoefficientis2compS1.XwhereXis14for
a16bitcoefficientand9foran11bitcoefficient.Asaresultcoefficientrangeis2.0to+1.9
Thetop27bitsfromthemultiplierarefedintothesecondadderandtheresultofthesecond
adderisfedintoasaturationlimitertolimittheresultto24bitsinaS.23format.
ThePACCregisteristheACCregisterdelayedonestate.

23

InstructionLineFormat
Thegeneralinstructionformatwithinasourcelineis:
[Label:]Opcode(,SubOpcode),Operand1(,Operand2)[Comment]
Asindicatedbythesquarebrackets,thelabelandcomment fieldsareoptional.Thepresenceofthe
SubOpcodeaswellasthenumberandtypeofoperandfieldsaredependentontheOpcode fieldand
willbeexplainedinfurtherdetailwithinthedescriptionoftheFV1instructionset.

[Label:]
Labelscanbeseenassymbolicalrepresentationsofinstructionlinesandareintendedtobeusedasan
operandwithintheSKPinstruction.Theyareallowedeitherwithinaninstructionlineprecedingthe
OpcodeFieldorstandaloneinaseparateline.Thelabellengthislimitedto32characters(blanksare
prohibited),thefirstcharactermustbealetterandeachLabelmustbeterminatedwithacolon.

[Comment]
Eachinstructionmaybefollowedbyacomment,whichmustbedelimitedfromtheinstructionbya
semicolon.Sincetheassemblerwillignoreallcharactersfromthesemicolontotheendoftheline,all
printablecharactersareallowedwithinacomment.

Operanddatatypes
SPINAsm willprocessthreebasicoperanddatatypes:

Signedfixedpointvalues
Unsignedintegers
Bitvectors

ForalloperanddatatypesSPINAsmperformsextensiverangechecking.WheneverSPINAsm
encountersanoperandthatisoutofrange,anerrormessagewillbedisplayedindicatingthelinethe
errorwasdetectedon.

Signedfixedpointvalues
Signedfixedpointvaluesareprimarilyusedascoefficients(Operand2)forthemultiplyportionofan
instruction.Dependingontheactualopcodetheymaybeinoneofthreedifferentformats,"S1.14","S1.9"
and"S.10".
"S1.14"meansthatthe16bitcoefficienthasonesignbit(MSB),oneintegerbitlefttothebinarypoint
followedby14fractionalbitsrighttothebinarypoint."S1.9"denotesan11bitcoefficientwhichdiffers
from"S1.14"inthatithasfewerbitsavailabletorepresentthefractionalportionofthesignedfixedpoint
value(lowerresolution).Lastbutnotleastthe"S.10"formatisalsoa11bitcoefficient,howeverin
comparisontothe"S1.9"format itshigherfractionalresolutioncomesattheexpenseoflackingthe
integerbit(smallerrange).Here'saquickoverviewregardingrangeandresolutionofthethreedifferent
coefficientformats.

S1.14
S1.9

Bits
16
11

Range
2to1.99993896484
2to1.998046875

24

Resolution(LSBvalue)
0.00006103516
0.001953125

S.10

11

1to0.9990234375

0.0009765625

Entryformats
SPINAsmallowsonetospecifysignedfixedpointvalueseitherasrealnumbersordirectlyin
hexadecimal.Realnumbersmayhaveaonedigitintegerportion,adecimalpoint,multiplefractional
digitsandcanbeprefixedwitha"+"or""sign.PleasenotethatSPINAsmwillroundtherealdecimal
numbertothenearestLSBvalueoftherequiredcoefficientformat
Ifsignedfixedpointvaluesareenteredinhexadecimalformat,theymustbeprefixedwitha"$"character.
Hexvaluesarealwaysassumedtoberightjustifiedwhichmeansthatleadingzerosbetweenthe"$"
specifierandthefirstnonzerodigitareoptional.
S1.14
Real
Hex

2
0.00006103516
0
0.00006103516
$8000 $FFFF$0000$0001$7FFF

S1.9
Real
Hex

2
0.001953125
0
0.001953125
1.998046875
$400$7FF$000$001$3FF

S.10
Real

0.0009765625

0.0009765625

1.99993896484

0.9990234375

Pleasenote"S.10"signedfixedpointvaluescannotbeenteredinhexadecimal.

Unsignedandsignedintegers
Unsignedintegersareprimarilyusedtospecifyanaddress(Operand1)withinaninstruction.The
(address)rangeofanunsignedintegerisdependentontheactualopcode,specificallywhetherthe
instructionwillaccessthedelayramortheinternalregisterfile.
Thesecondapplicationforunsignedintegersistospecifythenumberofinstructionstobeskippedwithin
theSKPinstruction.Inthiscasetheunsignedintegermustbeenteredindecimal.
Entryformats
Unsignedandsignedintegersmaybeenteredeitherindecimalorhexadecimal,inthelattercasethey
mustbeprefixedbya"$"character.

Bitvectors
ThecurrentFV1instructionsetsupportsbitvectorsofthreedifferentsizes:5bit,6bitand24bitas
definedbytheindividualopcode.
Entryformats
Ingeneralbitvectorscanbeenteredinbinaryrepresentationasacombinationof"0"and"1"characters,
prefixedwitha"%"character.Ifenteredinbinary(MSBfirst),allelements(bitpositions)withinthebit
vectormustexplicitlybedeclared,thatisa%01001literalfora6bitvectorisillegal.Toenhance
readabilityespeciallyof24bitvectors,underscorecharactersareallowedafterthe%prefix.Example:
%10110001_11111111_00000001.
Thesecondwayofenteringbitvectorsisinhexadecimalformatwhereasthehexvalueistreatedas
beingrightjustified.Asanexample$13willresultina %010011patternifappliedtoa6bit vector.
AthirdmethodofenteringbitvectorsisbyORingvaluestogethertosetparticularbits.Asanexample,
4|1wouldresultin%000101

25

AssemblerStatements
EQUStatement
TheEQUstatementallowsonetodefinesymbolicoperandsinordertoincreasethereadabilityofthe
sourcecode.TechnicallyanEQUstatementsuchas
Name EQU

Value

[Comment]

willcauseSPINAsmtoreplaceanyoccurrenceoftheliteral"Name"bytheliteral"Value"withineach
instructionlineduringtheassemblyprocessexcludingthecommentportionofaninstructionline.
Withtheexceptionofblanks,anyprintablecharacterisallowedwithintheliteral"Name".Howeverthere
arerestrictions:"Name"mustbeanuniquestring,islimitedto32charactersandthefirstcharactermust
bealetterexcludingthe"+"and""signsandthe"!"character.
Thereasonfornotallowingthesecharactersbeingthefirstcharacterof"Name"isthatanysymbolic
operandmaybeprefixedwithasignorthe"!"negationoperatorwithintheinstructionline.Theassembler
willthenperformtherequiredconversionoftheoperandwhileprocessingtheindividualinstructionlines.
Thereisanother,notsyntaxrelated,restrictionwhenusingsymbolicoperandsdefinedbyanEQU
statement:Predefinedsymbols.Asgivenintheendofthemanualthereisasetofpredefinedsymbolic
operandswhichshouldbeomittedas"Name"literalswithinanEQUstatement.Itisnotthatthese
predefinedsymbolsareprohibited,itisjustthatusingthemwithinanEQUstatementwilloverwritetheir
predefinedvalue.
Withtheliteral"Value"thingsareslightlymorecomplicatedsinceits formathastocomplywiththe
syntacticalrulesdefinedfortheoperandtypeitistorepresent.
AlthoughitissuggestedtoplaceEQUstatementsatthebeginningofthesourcecodefile,thisisnot
mandatory.However,theEQUstatementhastobedefinedbeforetheliteral"Name"canbeusedasa
symbolicaloperandwithinaninstructionline.
Remark:
SPINAsmhasnowayofperformingrangecheckingwhileprocessingtheEQUstatement.This is
becausetheoperandtypeofvalueisnotknowntoSPINAsmatthetimetheEQUstatementisprocessed
.Asaresult,rangecheckingisperformedwhenassemblingtheinstructionlineinwhich"Name"istobe
replacedby"Value".
Example:
Attn
Tmp_Reg
Tmp_Del

EQU0.5
EQU 63
EQU $2000

0.5=6dBattenuation
Temporaryregisterwithinregisterfile
Temporarymemorylocationwithindelayram

sof 0,0
ClearACC
rda Tmp_Del,Attn
Loadsamplefromdelayram$2000,
multiplyitby0.5andaddACCcontent
wrax Tmp_Reg,1.0
SaveresulttoTmp_RegbutkeepitinACC
wrax DACL,0
MoveACCtoDACleft(predefinedsymbol)
andthenclearACC
If Tmp_Del wasaccidentallyreplacedby Tmp_Reg withinthe rda instructionline,SPINAsmwould
notdetectthissemanticerrorsimplybecauseusing Tmp_Reg wouldbesyntacticallycorrect.

26

If Tmp_Reg wasmixedupwith Tmp_Del inthefirst wrax instructionline,a$2000valuefor

referencinganinternalregisterwouldclearlycausearangecheckerroranappropriateerrormessage
wouldbegenerated.

MEMStatement
TheMEMStatementallowstheusertopartitionthedelayrammemoryintoindividualblocks.
Amemoryblockdeclaredbythestatement
Name MEM Value

[Comment]

canbereferencedby"Name"fromwithinaninstructionline."Name"hastocomplywiththesame
syntacticalrulespreviouslydefinedwiththeEQUstatement,"Size"isanunsignedintegerintherangeof
1to32768whichmightbeenteredeitherindecimalorinhexadecimal.
Besidestheexplicitidentifier"Name"theassemblerdefinestwoadditionalimplicitidentifiers,"Name#"
and"Name^"."Name"referstothefirstmemorylocationwithinthememoryblock,whereas"Name#"
referstothelastmemorylocation.Theidentifier"Name^"referencesthemiddleofthememoryblock,or
inotherwordsit'scenter.Ifamemoryblockofsize1isdefined,allthreeidentifierswilladdressthesame
memorylocation.Incasethememoryblockisofsize2,"Name"and"Name^"willaddressthesame
memorylocation,ifthesizeisanevennumberthememoryblockcannotexactlybehalvedthemidpoint
"Name^"willbecalculatedas:sizeMOD2
Optionallyallthreeidentifierscanbeoffsetbyapositiveornegativeintegerwhichisenteredindecimal.
Althoughrangecheckingisperformedwhenusingoffsets,thereisnoerrorgeneratediftheresultofthe
addresscalculationexceedstheaddressrangeofthememoryblock.Thisisalsotrueforthosecasesin
whichtheresultwill"wraparound"thephysical32kboundaryofthedelaymemory.However,awarning
willbeissuedinordertoalerttheuserregardingtheoutofrangecondition.
MappingthememoryblockstotheirphysicaldelayramaddressesissolelyhandledbySPINAsm.The
userhasnopossibilitytoexplicitlyforceSPINAsmtoplaceacertainmemoryblocktoaspecificphysical
addressrange.Thisofcoursedoesnotmeanthattheuserhasnocontroloverthelayoutofthedelay
ramatall:KnowingthatSPINAsmwillmapmemoryblocksintheordertheybecomedefinedwithinthe
sourcefile,theusercanimplicitlycontrolthememorymapofthedelayram.
Example:

(mightsoundawful)

DelR MEM
DelL MEM

1024
1024

Rightchanneldelayline
Leftchanneldelayline

sof0,0
ClearACC
rdax ADCL,1.0
ReadinleftADC
wra DelL,0.25
Saveittothestartoftheleftdelay
lineandkeepa12dBreplicainACC
rdax DelL^+20,0.25
Addsamplefrom"centeroftheleftdelay
line+20samples"times0.25toACC
rdax DelL#,0.25
Addsamplefrom"endoftheleftdelayline
line"times0.25toACC
rdax DelL512,0.25
Addsamplefrom"startoftheleftdelay
line512samples"times0.25toACC
Remark:

27

Atthispointtheresultoftheaddresscalculationwillreferenceasamplefromoutsidethe"DelL"memory
block.Whilebeingsyntacticallycorrect,theinstructionmightnotresultinwhattheuserintended.Inorder
tomaketheuserawareofthatpotentialsemanticerror,awarningwillbeissued.
wrax DACL,0
rdaxADCR,1.0
wra DelR,0.25
rdax DelR^20,0.25
rdax DelR#,0.25
rdax DelR512,0.25

ResulttoDACL,clearACC

ReadinrightADC
Saveittothestartoftherightdelay
lineandkeepa12dBreplicainACC
Addsamplefromcenteroftherightdelay
line20samplestimes0.25toACC
Addsamplefromendoftherightdelayline
linetimes0.25toACC
Addsamplefromstartoftherightdelay
line512samplestimes0.25toACC

Remark:
Atthispointtheresultoftheaddresscalculationwillreferenceasamplefromoutsidethe"DelR"memory
block.Andevenworsethanthepreviouscase:Thistimethesamplebefetchedfromdelayramaddress
32256whichwillcontainasamplethatisapx.1secondold!
Again,syntacticallycorrectbutmostlikelyasemanticerrorwarningswillbeissued.
wrax DACR,0

ResulttoDACR,clearACC

TheFV1InstructionSet
TheinstructionsetoftheFV1processorisdividedintofivebasicgroupsofinstructions:

Accumulatorinstructions
Registerinstructions
DelayRaminstructions
LFOinstructions
Pseudoopcodes

FV1instructionsare32bitswide.ExceptforthemorespecializedLFOinstructionsaswellasthe
booleanaccumulatorinstructions,each32bitinstructionwordhastoencodesit's5bitopcode,a
coefficientandanaddressspecifier.
Withintheregisterinstructionsonly6bitsarerequiredforaddressingtheinternalregisterfile,the
coefficientis16bitswideandtheremaining5bitsarereservedandshouldbesetto0.
Withinthedelayraminstructionstheaddressportionoccupies16bits,(althoughinthecurrentversionof
thechiponlythe15LSBsareused)accordinglythecoefficientislimitedto11bits.
Thatmeansthatalgorithmsrequiringhighercoefficientresolution(suchashighQIIRfilters)should
preferablybeimplementedusingtheinternalgeneralpurposeregistersastemporarystoragelocations.
Pseudoopcodesdonotaddnewfunctionalitytotheinstructionset,allpseudoopcodescouldbereplaced
bythegenericinstruction(s)theyarebasedupon.Alltheydoistocombineagenericinstructionwitha
specialparametertoemulateamorespecializedfunction.ForexampletheFV1instructionsetfeaturesa
genericANDMASKfunction.Thisonesimplyperformsthe"and"functionofthecurrentACCandthe

28

specified24bitmask.Clearly,ifMASKis$000000thenACCbecomesclearedandthisisexactlywhat
thepseudoopcode"CLR"willdo.

29

Accumulatorinstructions
SOF
Mnemonic
SOF

Operation
C*ACC+D

Instructioncoding
CCCCCCCCCCCCCCCCDDDDDDDDDDD01101

Description
SOFwillmultiplythecurrentvalueinACCwithCandwillthenaddtheconstantDtotheresult.
PleasenotetheabsenceofanintegerentryformatforD.Thisisnotbymistakebutitshouldemphasize
thatDisnotintendedtobecomeusedforintegerarithmetic.Thereasonforthisinstructionisthatthe11
bitconstantDwouldbeplacedintoACCleftjustifiedorinotherwords13bitsshiftedtotheleft.
DisintendedtooffsetACCbyaconstantintherangefrom1to+0.9990234375.
Parameters
Name

Width

16Bit

11Bit

Entryformats,range
Real(S1.14)
Hex($0000$FFFF)
Symbolic
Real(S.10)
Symbolic

Syntax
SOFC,D
CodingExample:
Off

EQU

1.0

Halvewayrectifier
sof 0,0
ClearACC
rdax ADCL,1.0
ReadfromleftADCchannel
sof 1.0,Off
Subtractoffset
sof 1.0,Off
Addoffset

30

AND
Mnemonic
AND

Operation
ACC&MASK

Instructioncoding
MMMMMMMMMMMMMMMMMMMMMMMM000001110

Description
ANDwillperformabitwise"and"ofthecurrentACCandthe24bitMASKspecifiedwithintheinstruction
word.
TheinstructionmightbeusedtoloadaconstantintoACCprovidedACCcontains$FFFFFFortoclear
ACCifMASKequals$000000.(seealsothepseudoopcodesection)
Parameters
Name

Width

Entryformats,range
Binary
Hex($000000$FFFFFF)
Symbolic

24Bit

Syntax
ANDM
CodingExample:
AMASKEQU

$F0FFFF

or
$FFFFFF
SetallbitswithinACC
and $FFFFFE
ClearLSB
and %01111111_11111111_11111111 ClearMSB
and AMASK
ClearACC[19..16]
and $0
ClearACC

31

OR
Mnemonic
OR

Operation
ACC|MASK

Instructioncoding
MMMMMMMMMMMMMMMMMMMMMMMM000001111

Description
ORwillperformabitwise"or"ofthecurrentACCandthe24bitMASKspecifiedwithintheinstruction
word.
TheinstructionmightbeusedtoloadaconstantintoACCprovidedACCcontains$000000.
Parameters
Name

Width

Entryformats,range
Binary
Hex($000000$FFFFFF)
Symbolic

24Bit

Syntax
ORM
CodingExample:
OMASKEQU

$0F0000

sof 0,0
ClearallbitswithinACC
or
$1
SetLSB
or
%10000000_00000000_00000000 SetMSB
or
OMASK
SetACC[19..16]
and %S=[15..8]
SetACC[15..8]

32

XOR
Mnemonic
XOR

Operation
ACC^MASK

Instructioncoding
MMMMMMMMMMMMMMMMMMMMMMMM000010000

Description
XORwillperformabitwise"xor"ofthecurrentACCandthe24bitMASKspecifiedwithintheinstruction
word.
TheinstructionwillinvertACCprovidedMASKequals$FFFFFF.(seealsothepseudoopcodesection)
Parameters
Name

Width

Entryformats,range
Binary
Hex($000000$FFFFFF)
Symbolic

24Bit

Syntax
XORM
CodingExample:
XMASKEQU

$AAAAAA

sof 0,0
ClearallbitswithinACC
xor $0
SetallACCbits
xor %01010101_01010101_01010101 Invertallevennumberedbits
xor XMASK
Invertalloddnumberedbits

33

LOG
Mnemonic
LOG

Operation
C*LOG(|ACC|)+D

Instructioncoding
CCCCCCCCCCCCCCCCDDDDDDDDDDD01011

Description
LOGwillmultiplytheBase2LOGofthecurrentabsolutevalueinACCwithCandaddtheconstantDto
theresult.
ItisimportanttonotethattheLOGfunctionreturnsafixedpointnumberinS4.19formatinsteadofthe
standardS.23format,whichinturnmeansthatthemostnegativeBase2LOGvalueis16.
TheLOGinstructioncanhandleabsolutelinearaccumulatorvaluesfrom0.99999988to0.00001526
whichtranslatestoadynamicrangeofapx.96dB.
Danoffsettobeaddedtothelogarithmicvalueintherangeof 16to+15.999998.
Parameters
Name

Width

16Bit

11Bit

Entryformats,range
Real(S1.14)
Hex($0000$FFFF)
Symbolic
Real(S4.6)
Symbolic

Syntax
LOGC,D
CodingExample:
log

1.0,0

34

EXP
Mnemonic
EXP

Operation
C*EXP(ACC)+D

Instructioncoding
CCCCCCCCCCCCCCCCDDDDDDDDDDD01100

Description
EXPwillmultiply2^ACCwithCandaddtheconstantDtotheresult.
SinceACC(initsroleasthedestinationfortheEXPinstruction)islimitedtolinearvaluesfrom0to
+0.99999988,theEXPinstructionislimitedtologarithmicACCvalues(initsroleasthesourceoperand
fortheEXPinstruction)from16to0.LiketheLOGinstruction,EXPwilltreattheACCcontentasa
S4.19number.PositivelogarithmicACCvalueswillbeclippedto+0.99999988whichisthemostpositive
linearvaluethatcanberepresentedwithintheaccumulator.
DisintendedtoallowthelinearACCtobeoffsetbyaconstantintherangefrom1to+0.9990234375
Parameters
Name

Width

16Bit

11Bit

Entryformats,range
Real(S1.14)
Hex($0000$FFFF)
Symbolic
Real(S.10)
Symbolic

Syntax
EXPC,D
CodingExample:
exp

0.8,0

35

SKP
Mnemonic
SKP

Operation
CMASKN

Instructioncoding
CCCCCNNNNNN000000000000000010001

Description
TheSKPinstructionallowsconditionalprogramexecution.TheFV1featuresfiveconditionflagsthatcan
beusedtoconditionallyskipthenextNinstructions.Theselectionofwhichconditionflag(s)mustbe
assertedinordertoskipthenextNinstructionsismadebythefivebitconditionmaskCMASK. Onlyif
allconditionflagsthatcorrespondtoalogic"1"withinCMASKareassertedarethefollowingN
instructionsskipped.TheindividualbitswithinCMASKcorrespondtotheFV1conditionflagsasfollows:
CMASK

Flag

b4

RUN

b3

ZRC

b2
b1
b0

ZRO
GEZ
NEG

Parameters
Name

Description
TheRUNflagisclearedaftertheprogramhasexecutedforthefirsttime
afteritwasloadedintotheinternalprogrammemory.Thepurposeofthe
RUNflagistoallowtheprogramtoinitializeregistersandLFOsduringthe
firstsampleiterationthentoskipthoseinitializationsfromthenon.
TheZRCflagisassertedifthesignofACCandPACCisdifferent,a
conditionthatindicatesaZeroCrossing.
ZisassertedifACC=0
GEZ isassertedifACC>=0
NisassertedifACCisnegative

Width

CMASK

5Bit

6Bit

Entryformats,range
Binary
Hex($00$1F)
Symbolic
Decimal(163)
Label

Maybethemostefficientwaytodefinetheconditionmaskisusingit'ssymbolicrepresentation.Inorderto
simplifytheSKPsyntax,SPINAsmhasapredefinedsetofsymbolswhichcorrespondtothenameofthe
individualconditionflags.(RUN,ZRC,ZRO,GEZ,NEG).Althoughmostoftheconditionflagsaremutually
exclusive,SPINAsmallowsyoutospecifymorethanoneconditionflagtobecomeevaluatedsimplyby
separatingmultiplepredefinedsymbolsbythe"|"character.Accordingly"skpZRC|N,6"wouldskipthe
followingsixinstructionsincaseofazerocrossingtoanegativevalue.
Syntax
SKPCMASK,N
CodingExample:
Abridgerectifier
sof
rdax
skp
sof
pos: wrax
rdax
skp

0,0
ADCL,1.0
GEZ,pos
1.0,0
DACL,0
ADCL,1.0
N,neg

ClearACC
ReadfromleftADCchannel
SkipnextinstructionifACC>=0
MakeACCpositive
ResulttoDACL,clearACC
ReadfromleftADCchannel
SkipnextinstructionifACC<0

36

sof 1.0,0
pos: wrax 0,DACR

MakeACCnegative
ResulttoDACR,clearACC

37

Registerinstructions
RDAX
Mnemonic
RDAX

Operation
C*REG[ADDR]+ACC

Instructioncoding
CCCCCCCCCCCCCCCC00000AAAAAA00100

Description
RDAXwillfetchthevaluecontainedin[ADDR]fromtheregisterfile,multiplyitwithCandaddtheresult
tothepreviouscontentofACC.Thismultiplyaccumulateisprobablythemostpopularoperationfoundin
DSPalgorithms.
Parameters
Name

Width

ADDR

6Bit

16Bit

Entryformats,range
Decimal(063)
Hex($0$3F)
Symbolic
Real(S1.14)
Hex($8000$0000$7FFF)
Symbolic

InordertosimplifytheRDAXsyntax,seethelistofpredefinedsymbolsforallregisterswithintheFV1
registerfile.
Syntax
RDAX ADDR,C
CodingExample:
Crudemono
sof 0,0
rdax ADCL,0.5
rdax ADCR,0.5
wrax DACL,1.0
wrax DACR,0

ClearACC
GetADCLvalueanddivideitbytwo
GetADCRvalue,divideitbytwo
andaddtothehalfofADCL
ResulttoDACL
ResulttoDACRandclearACC

38

WRAX
Mnemonic
WRAX

Operation
ACC>REG[ADDR],C*ACC

Instructioncoding
CCCCCCCCCCCCCCCC00000AAAAAA00110

Description
WRAXwillsavethecurrentvalueinACCto[ADDR]andthenmultiplyACCbyC.Thisinstructioncanbe
usedtowriteACCtooneDACchannelwhileclearingACCforprocessingthenextaudiochannel.
Parameters
Name

Width

ADDR

6Bit

16Bit

Entryformats,range
Decimal(063)
Hex($0$3F)
Symbolic
Real(S1.14)
Hex($8000$0000$7FFF)
Symbolic

InordertosimplifytheWRAXsyntax,seethelistofpredefinedsymbols forallregisterswithintheFV1.
Syntax
WRAX ADDR,C
CodingExample:
Steroprocessing
rdaxADCL,1.0
....
....
wrax DACL,0
rdax ADCR,1.0
....
....
wrax DACR,0

ReadleftADCintopreviouslyclearedACC

...leftchannel
processing...

ResulttoDACLandclearACCforright
channelprocessing
ReadrightADCintopreviouslyclearedACC

...rightchannel
processing...

ResulttoDACRandclearACCforleft
channelprocessing

39

MAXX
Mnemonic
MAXX

Operation
MAX(|REG[ADDR]*C|,|ACC|)

Instructioncoding
CCCCCCCCCCCCCCCC00000AAAAAA01001

Description
MAXXwillcomparetheabsolutevalueofACCversusCtimestheabsolutevalueoftheregisterpointed
tobyADDR.IftheabsolutevalueofACCislargerACCwillbeloadedwith|ACC|,otherwisethe
accumulatorbecomesoverwrittenby|REG[ADDR]*C|.
Parameters
Name

Width

ADDR

6Bit

16Bit

Entryformats,range
Decimal(063)
Hex($0$3F)
Symbolic
Real(S1.14)
Hex($8000$0000$7FFF)
Symbolic

InordertosimplifytheMAXXsyntax,seethelistofpredefinedsymbolsforallregisterswithintheFV1
registerfile.
Syntax
MAXX ADDR,C
CodingExample:
Peakfollower
Peak
EQU 32

Peakholdregister

sof 0,0
ClearACC
rdax ADCL,1.0
ReadleftADC
maxx Peak,1.0
KeeplargerabsolutevalueinACC
Forapeakmeterinsertdecaycodehere...
wrax Peak,0

Save(new)peakandclearACC

40

MULX
Mnemonic
MULX

Operation
ACC*REG[ADDR]

Instructioncoding
000000000000000000000AAAAAA01010

Description
MULXwillmultiplyACCbythevalueoftheregisterpointedtobyADDR.Animportantapplicationofthe
MULXinstructionissquaringthecontentofACC,whichcombinedwithasingleorderLPisespecially
usefulincalculatingtheRMSvalueofanarbitrarywaveform.
Parameters
Name
ADDR

Width

Entryformats,range
Decimal(063)
Hex($0$3F)
Symbolic

6Bit

InordertosimplifytheMULXsyntax,seethelistofpredefinedsymbolsforallregisterswithintheFV1
registerfile.
Syntax
MULXADDR
CodingExample:
RMSconversion
Tmp_LP
EQU 32

TemporaryregisterforfirstorderLP

sof 0,0
ClearACC
rdax ADCL,1.0
ReadleftADC
RMScalculation=ACC^2>firstorderLP
mulx ADCL
ACC^2
rdfx Tmp_LP,x.x
Firstorder...
wrax Tmp_LP,1.0
...LPfilter
AtthispointACCholdstheRMSvalueoftheinput

41

RDFX
Mnemonic
RDFX

Operation
(ACCREG[ADDR])*C+REG[ADDR]

Instructioncoding
CCCCCCCCCCCCCCCC00000AAAAAA00101

Description
RDFXwillsubtractthevalueoftheregisterpointedtobyADDRfromACC,multiplytheresultbyCand
thenaddthevalueoftheregisterpointedtobyADDR.RDFXisanextremelypowerfulinstructioninthatit
representsthemajorportionofasingleorderlowpassfilter.
Parameters
Name

Width

ADDR

6Bit

16Bit

Entryformats,range
Decimal(063)
Hex($0$3F)
Symbolic
Real(S1.14)
Hex($8000$0000$7FFF)
Symbolic

InordertosimplifytheRDFXsyntax,seethelistofpredefinedsymbolsforallregisterswithintheFV1
registerfile.
Syntax
RDFX ADDR C
CodingExample:
SingleorderLPfilter
Tmp_LP
EQU 32

TemporaryregisterforfirstorderLP

ldax ADCL
ReadleftADC
rdfx Tmp_LP,x.x
Firstorder...
wrax Tmp_LP,1.0
...LPfilter
wrax DACL,0
ResulttoDACLandclearACC

42

WRLX
Mnemonic
WRLX

Operation
ACC>REG[ADDR],(PACCACC)*C
+PACC

Instructioncoding
CCCCCCCCCCCCCCCC00000AAAAAA01000

Description
FirstthecurrentACCvalueisstoredintotheregisterpointedtobyADDR,thenACCissubtractedfrom
thepreviouscontentofACC(PACC).ThedifferenceisthenmultipliedbyCandfinallyPACCisaddedto
theresult.WRLXisanextremelypowerfulinstructioninthatwhencombinedwithRDFX,itformsasingle
orderlowpassshelvingfilter
Parameters
Name

Width

ADDR

6Bit

16Bit

Entryformats,range
Decimal(063)
Hex($0$3F)
Symbolic
Real(S1.14)
Hex($8000$0000$7FFF)
Symbolic

InordertosimplifytheWRLXsyntax,seethelistofpredefinedsymbolsforallregisterswithintheFV1
registerfile.
Syntax
WRLX ADDR,C
CodingExample:
SingleorderLPshelvingfilter
Tmp_LP
EQU 32
TemporaryregisterforfirstorderLP

sof 0,0
ClearACC
rdax ADCL,1.0
ReadleftADC
rdfx Tmp_LP,x.x
FirstorderLP...
wrlx Tmp_LP,y.y
...shelvingfilter
wrax DACL,1.0
ResulttoDACLandclearACC

43

WRHX
Mnemonic
WRHX

Operation
Instructioncoding
ACC>REG[ADDR],(ACC*C)+PACC CCCCCCCCCCCCCCCC00000AAAAAA00111

Description
ThecurrentACCvalueisstoredintheregisterpointedtobyADDR,thenACCismultipliedbyC.Finally
thepreviouscontentofACC(PACC)isaddedtotheproduct.WRHXisanextremelypowerfulinstruction
inthatwhencombinedwithRDFX,itformsasingleorderhighpassshelvingfilter.
Parameters
Name

Width

ADDR

6Bit

16Bit

Entryformats,range
Decimal(063)
Hex($0$3F)
Symbolic
Real(S1.14)
Hex($8000$0000$7FFF)
Symbolic

InordertosimplifytheWRHXsyntax,seethelistofpredefinedsymbolsforallregisterswithintheFV1
registerfile.
Syntax
WRHX ADDR,C
CodingExample:
SingleorderHPshelvingfilter
Tmp_HP
EQU 32
TemporaryregisterforfirstorderHP

sof 0,0
ClearACC
rdax ADCL,1.0
ReadleftADC
rdfx Tmp_HP,x.x
FirstorderHP...
wrhx Tmp_HP,y.y
...shelvingfilter
wrax DACL,0
ResulttoDACLandclearACC

44

DelayRaminstructions
RDA
Mnemonic
RDA

Operation
SRAM[ADDR]*C+ACC

Instructioncoding
CCCCCCCCCCCAAAAAAAAAAAAAAAA00000

Description
RDAwillfetchthesample[ADDR]fromthedelayram,multiplyitbyCandaddtheresulttotheprevious
contentofACC.ThismultiplyaccumulateisprobablythemostpopularoperationfoundinDSP
algorithms.
Parameters
Name

Width

ADDR

(1)+15Bit

11Bit

Entryformats,range
Decimal(032767)
Hex($0$7FFF)
Symbolic
Real(S1.9)
Hex($400$000$3FF)
Symbolic

Syntax
RDA ADDR,C
CodingExample:
DelayMEM
CoeffEQU
Tmp EQU
rda
rda
rda
rda

1024
1.55
$2000
1000,1.9
Delay+20,Coeff
Tmp,2
$7FFF,$7FF

45

RMPA
Mnemonic
RMPA

Operation
SRAM[PNTR[N]]*C+ACC

Instructioncoding
CCCCCCCCCCC000000000001100000001

Description
RMPAprovidesindirectdelaylineaddressinginthatthedelaylineaddressofthesampletobemultiplied
byCisnotexplicitlygivenintheinstructionitselfbutcontainedwithinthepointerregisterADDR_PTR
(absoluteaddress24withintheinternalregisterfile.)
RMPAwillfetchtheindirectlyaddressedsamplefromthedelayram,multiplyitbyCandaddtheresultto
thepreviouscontentofACC.
Parameters
Name

Width

Entryformats,range
Real(S1.9)
Hex($400$000$3FF)
Symbolic

11Bit

Syntax
RMPA C
CodingExample:
Crudevariabledelaylineaddressing
sof
rdax
wrax
rmpa
wrax

0,0
POT1,1.0
ADDR_PTR,0
1.0
DACL,0

ClearACC
ReadPOT1value
Writevaluetopointerregister,clearACC
Readsamplefromdelayline
ResulttoDACLandclearACC

46

WRA
Mnemonic
WRA

Operation
ACC>SRAM[ADDR],ACC*C

Instructioncoding
CCCCCCCCCCCAAAAAAAAAAAAAAAA00010

Description
WRAwillstoreACCtothedelayramlocationaddressedbyADDRandthenmultiplyACCbyC.
Parameters
Name

Width

ADDR

(1)+15Bit

11Bit

Entryformats,range
Decimal(032767)
Hex($0$7FFF)
Symbolic
Real(S1.9)
Hex($400$000$3FF)
Symbolic

Syntax
WRA ADDR,C
CodingExample:
DelayMEM
CoeffEQU
sof
rdax
wra
rda

1024
0.5

0,0
ADCL,1.0
Delay,Coeff
Delay#,Coeff

ClearACC
ReadleftADC
Writetostartofdelayline,halveACC
Addhalfofthesamplefrom
theendofthedelayline
ResulttoDACLandclearACC

wrax DACL,0

47

WRAP
Mnemonic
WRAP

Operation
ACC>SRAM[ADDR],(ACC*C)+LR

Instructioncoding
CCCCCCCCCCCAAAAAAAAAAAAAAAA00011

Description
WRAPwillstoreACCtothedelayramlocationaddressedbyADDR thenmultiplyACCbyCandfinally
addthecontentoftheLRregistertotheproduct.PleasenotethattheLRregistercontainsthelast
samplevaluereadfromthedelayrammemory.Thisinstructionistypicallyusedforallpassfiltersina
reverbprogram.
Parameters
Name

Width

ADDR

(1)+15Bit

11Bit

Entryformats,range
Decimal(032767)
Hex($0$7FFF)
Symbolic
Real(S1.9)
Hex($400$000$3FF)
Symbolic

Syntax
WRAP ADDR,C
CodingExample:
rda ap1#,kapReadoutputofallpass1andmultiplyitbykap
wrap ap1,kapWriteACCtoinputofallpass1anddo
ACC*(kap)+ap1#(ap1#isinLRregister)

48

LFOinstructions
WLDS
Mnemonic
WLDS

Operation
SeeDescription

Instructioncoding
00NFFFFFFFFFAAAAAAAAAAAAAAA10010

Description
WLDSwillloadfrequencyandamplitudecontrolvaluesintotheselectedSINLFO(0or1).This
instructionisintendedtosetuptheselectedSINLFOwhichistypicallydonewithinthefirstsample
iterationafteranewprogramisloaded.AsaresultWLDSwillinmostcasesbeusedincombinationwith
aSKPRUNinstruction.Foramoredetaileddescriptionregardingthefrequencyandamplitudecontrol
valuesseeapplicationnoteAN0001.
Parameters
Name
N

Width
1Bit

9Bit

15Bit

Entryformats,range
SINLFOselect:(0,1)
Decimal(0511)
Hex($000$1FF)
Symbolic
Decimal(032767)
Hex($0000$7FFF)
Symbolic

Syntax
WLDSN,F,A
CodingExample:
Amp EQU 8194
Amplitudefora4097sampledelayline
Freq EQU 51
Apx.2Hzat32kHzsamplingrate

SetupSINLFO0
skp run,start
wlds 0,Freq,Amp
start:sof0,0
....
....

Skipnextinstructionifnotfirstiteration
SetupSINLFO0

49

WLDR
Mnemonic
WLDR

Operation
SeeDescription

Instructioncoding
01NFFFFFFFFFFFFFFFF000000AA10010

Description
WLDRwillloadfrequencyandamplitudecontrolvaluesintotheselectedRAMPLFO.(0or1)This
instructionisintendedtosetuptheselectedRAMPLFOwhichistypicallydonewithinthefirstsample
iterationafteranewprogrambecameloaded.AsaresultWLDRwillinmostcasesbeusedin
combinationwithaSKPRUNinstruction.Foramoredetaileddescriptionregardingthefrequencyand
amplitudecontrolvaluesseeapplicationnoteAN0001.
Parameters
Name
N

Width
1Bit

16Bit

2Bit

Entryformats,range
RAMPLFOselect:0,1
Decimal(1638432767)
Hex($4000$000$7FFF)
Symbolic
Decimal(512,1024,2048,4096)
Symbolic

Syntax
WLDRN,F,A
CodingExample:
Amp EQU 4096
LFOwillmodulatea4096samplesdelayline
Freq EQU $100

SetupRAMPLFO0
skp run,start
wldr 0,Freq,Amp
start:and0
....
....

Skipnextinstructionifnotfirstiteration
SetupRAMPLFO0

50

JAM
Mnemonic
JAM

Operation
0>RAMPLFON

Instructioncoding
0000000000000000000000001N010011

Description
JAMwillresettheselectedRAMPLFOtoitsstartingpoint.
Parameters
Name
N

Width
1Bit

Entryformats,range
RAMPLFOselect:0,1

Syntax
JAM N
CodingExample:
jam

Forceramp0LFOtoit'sstartingosition

51

CHORDA
Mnemonic
CHORDA

Operation
SeeDescription

Instructioncoding
00CCCCCC0NNAAAAAAAAAAAAAAAA10100

Description
LiketheRDAinstruction,CHORDAwillreadasamplefromthedelayram,multiplyitbyacoefficientand
addtheproducttothepreviouscontentofACC.However,incontrasttoRDAthecoefficientisnot
explicitlyembeddedwithintheinstructionandtheeffectivedelayramaddressisnotsolelydeterminedby
theaddressparameter.Instead,bothvaluesaremodulatedbytheselectedLFOatruntime,foranin
depthexplanationpleaseconsulttheFV1datasheetalongsidewithapplicationnoteAN0001.CHORDA
isaveryflexibleandpowerfulinstruction,especiallyusefulfordelaylinemodulationeffectssuchas
chorusorpitchshifting.
Thecoefficientfieldofthe"CHO"instructionsareusedascontrolbitstoselectvariousaspectsofthe
LFO.ThesebitscanbesetusingpredefinedflagsthatareORedtogethertocreatetherequiredbitfield.
ForasinewaveLFO(SIN0orSIN1),validflagsare:
SINCOSREGCOMPCCOMPA
WhileforarampLFO(RMP0andRMP1),validflagsare:
REGCOMPCCOMPARPTR2NA
Theseflagsaredefinedas:
Flag
SIN
COS
REG
COMPC
COMPA
RPTR2
NA

HEXvalue
$0
$1
$2
$4
$8
$10
$20

Parameters
Name
N

Width
2Bit

6Bit

ADDR

(1)+15Bit

Description
SelectSINoutput(default)(SineLFOonly)
SelectCOSoutput(SineLFOonly)
SavetheoutputoftheLFOintoaninternalLFOregister.
Complementthecoefficient(1coeff)
ComplementtheaddressoffsetfromtheLFO
Selecttheramp+1/2pointer(RampLFOonly)
Selectxfadecoefficientanddonotaddaddressoffset

Entryformats,range
LFOselect: SIN0,SIN1,RMP0,RMP1
Binary
Bitflags
Decimal(032767)
Hex($0$7FFF)
Symbolic

Syntax
CHORDA,N,C,ADDR
CodingExample:
Achorus
DelayMEM 4097
Chorusdelayline
Amp EQU 8195
Amplitudefora4097sampledelayline
Freq EQU 51
Apx.2Hzat32kHzsamplingrate

52


SetupSINLFO0

skp run,start
Skipifnotfirstiteration
wlds 0,Freq,Amp
SetupSINLFO0
start:

sof 0,0
ClearACC
rdax ADCL,0.5
ReadleftADC*0.5
wra Delay,1.0
Writetochorusdelayline
chorda,SIN0,REG|COMPC,Delay^SeeapplicationnoteAN0001
chorda,SIN0,,Delay^+1
fordetailedexamples&explanation
wrax DACL,0
ResulttoDACLandclearACC

53

CHOSOF
Mnemonic
CHOSOF

Operation
SeeDescription

Instructioncoding
10CCCCCC0NNDDDDDDDDDDDDDDDD10100

Description
LiketheSOFinstruction,CHOSOFwillmultiplyACCbyacoefficientandaddtheconstantDtothe
result.However,incontrasttoSOFthecoefficientisnotexplicitlyembeddedwithintheinstruction.
Instead,basedontheselectedLFOandthe6bitvectorC,thecoefficientispickedfromalistofpossible
coefficientsavailablewithintheLFOblockoftheFV1.ForanindepthexplanationpleaseconsulttheFV
1datasheetalongsidewithapplicationnoteAN0001.CHOSOFisaveryflexibleandpowerful
instruction,especiallyusefulforthecrossfadingportionofpitchshiftalgorithms.
Pleasesee"CHORDA"foradescriptionoffieldflags.
Parameters
Name
N

Width
2Bit

6Bit

16Bit

Entryformats,range
LFOselect:SIN0,SIN1,RMP0,RMP1
Binary
Bitflags
Real(S.15)
Symbolic

Syntax
CHOSOF,N,C,D
CodingExample:
Pitchshift
DelayMEM 4096
Pitchshiftdelayline
Temp MEM 1
Temporarystorage
Amp EQU 4096
RAMPLFOamplitude(4096samples)
Freq EQU 8192
RAMPLFOfrequency

SetupRAMPLFO0

skp run,cont
Skipifnotfirstiteration
wldr 0,Freq,Amp
SetupSINLFO0

cont:

sof 0,0
ClearACC
rdax ADCL,1.0
ReadleftADC*1.0
wra Delay,0
Writetodelayline,clearACC
chorda,RMP0,COMPC|REG,Delay SeeapplicationnoteAN0001
chorda,RMP0,,Delay+1
fordetailedexamples&explanation
wra Temp,0

chorda,RMP0,COMPC|RPTR2,Delay

chorda,RMP0,RPTR2,Delay+1

chosof,RMP0,NA|COMPC,0

chorda,RMP0,NA,Temp

wrax DACL,0
ResulttoDACLandclearACC

54

CHORDAL
Mnemonic
CHORDAL

Operation
LFO*1>ACC

Instructioncoding
110000100NN000000000000000010100

Description
CHORDALwillreadthecurrentvalueoftheselectedLFOintoACC.
Parameters
Name
N

Width
2Bit

Entryformats,range
LFOselect: SIN0,COS0,SIN1,COS1,RMP0,RMP1

Syntax
CHORDAL,N
CodingExample:
chordal,SIN0
wrax DACL,0

ReadLFOS0intoACC
ResulttoDACLandclearACC

55

PseudoOpcodes
CLR
Mnemonic
CLR

Operation
0>ACC

Instructioncoding
00000000000000000000000000001110

Description
CLRwillcleartheaccumulator.
Parameters

None

Syntax
CLR
CodingExample:
clr
rdax ADCL,1.0
....
....
wrax DACL,0

ClearACC
ReadleftADC

...leftchannel
processing...

ResulttoDACLandclearACC

56

NOT
Mnemonic
NOT

Operation
/ACC>ACC

Instructioncoding
11111111111111111111111100010000

Description
NOTwillnegateallbitpositionswithinaccumulatorthusperforminga1scomplement.
Parameters

None

Syntax
NOT
CodingExample:
not

1'scompACC

57

ABSA
Mnemonic
ABSA

Operation
|ACC|>ACC

Instructioncoding
00000000000000000000000000001001

Description
Loadstheaccumulatorwiththeabsolutevalueoftheaccumulator.
Parameters

None

Syntax
ABSA
CodingExample:
absa

AbsolutevalueofACC>ACC

58

LDAX
Mnemonic
LDAX

Operation
REG[ADDR]>ACC

Instructioncoding
00000000000000000000000000000101

Description
Loadstheaccumulatorwiththecontentsoftheaddressedregister.
Parameters
Name
ADDR

Width

Entryformats,range
Decimal(063)
Hex($0$3F)
Symbolic

6Bit

Syntax
LDAXREG
CodingExample:
ldax adcl

ADCleftinput>ACC

59

PredefinedSymbols
FollowingisthelistofpredefinedsymbolsintheSPINAsmassembler:
Symbol
Value:hex(dec)
Notes
SIN0_RATE
0x00(0)
SIN0rate
SIN0_RANGE
0x01(1)
SIN0range
SIN1_RATE
0x02(2)
SIN1rate
SIN1_RANGE
0x03(3)
SIN1range
RMP0_RATE
0x04(4)
RMP0rate
RMP0_RANGE 0x05(5)
RMP0range
RMP1_RATE
0x06(6)
RMP1rate
RMP1_RANGE 0x07(7)
RMP1range
POT0
0x10(16)
Pot0inputregister
POT1
0x11(17)
Pot1inputregister
POT2
0x12(18)
Pot2inputregister
ADCL
0x14(20)
ADCinputregisterleftchannel
ADCR
0x15(21)
ADCinputregisterrightchannel
DACL
0x16(22)
DACoutputregisterleftchannel
DACR
0x17(23)
DACoutputregisterrightchannel
ADDR_PTR
0x18(24)
Usedwith'RMPA'instructionforindirectread
REG0
0x20(32)
Register00
REG1
0x21(33)
Register01
REG2
0x22(34)
Register02
REG3
0x23(35)
Register03
REG4
0x24(36)
Register04
REG5
0x25(37)
Register05
REG6
0x26(38)
Register06
REG7
0x27(39)
Register07
REG8
0x28(40)
Register08
REG9
0x29(41)
Register09
REG10
0x2A(42)
Register10
REG11
0x2B(43)
Register11
REG12
0x2C(44)
Register12
REG13
0x2D(45)
Register13
REG14
0x2E(46)
Register14
REG15
0x2F(47)
Register15
REG16
0x30(48)
Register16
REG17
0x31(49)
Register17
REG18
0x32(50)
Register18
REG19
0x33(51)
Register19
REG20
0x34(52)
Register20
REG21
0x35(53)
Register21
REG22
0x36(54)
Register22
REG23
0x37(55)
Register23
REG24
0x38(56)
Register24
REG25
0x39(57)
Register25
REG26
0x3A(58)
Register26
REG27
0x3B(59)
Register27
REG28
0x3C(60)
Register28
REG29
0x3D(61)
Register29
REG30
0x3E(62)
Register30
REG31
0x3F(63)
Register31
SIN0
0x00(0)
USEDwith'CHO'instruction:SINELFO0

60

SIN1
RMP0
RMP1
RDA
SOF

0x01(1)
0x02(2)
0x03(3)
0x00(0)
0x02(2)

RDAL

0x03(3)

SIN
COS
REG
COMPC

0x00(0)
0x01(1)
0x02(2)
0x04(4)

COMPA

0x08(8)

RPTR2

0x10(16)

NA

0x20(32)

RUN

0x80000000

ZRC
ZRO
GEZ
NEG

0x40000000
0x20000000
0x10000000
0x8000000

USEDwith'CHO'instruction:SINELFO1
USEDwith'CHO'instruction:RAMPLFO0
USEDwith'CHO'instruction:RAMPLFO1
USEDwith'CHO'instruction:ACC+=(SRAM*COEFF)
USEDwith'CHO'instruction:ACC=(ACC*LFOCOEFF)+
Constant
USEDwith'CHO'instruction:ReadsvalueofselectedLFO
intotheACC
USEDwith'CHO'instruction:SIN/COSfromSINELFO
USEDwith'CHO'instruction:SIN/COSfromSINELFO
USEDwith'CHO'instruction:SaveLFOtempreginLFOblock
USEDwith'CHO'instruction:2'scomp:Generate1xfor
interpolate
USEDwith'CHO'instruction:1'scompaddressoffset
(GenerateSINorCOS)
USEDwith'CHO'instruction:Add1/2toramptogenerate2nd
rampforpitchshift
USEDwith'CHO'instruction:DoNOTaddLFOtoaddressand
selectcrossfadecoefficient
USEDwith'SKP'instruction:SkipifNOTFIRSTtimethrough
program
USEDwith'SKP'instruction:SkipOnZeroCrossing
USEDwith'SKP'instruction:SkipifACC=0
USEDwith'SKP'instruction:SkipifACCis'>=0'
USEDwith'SKP'instruction:SkipifACCisNegative

61

ChangeNotes

11July2006:

Firstrelease

28August2006:

FixedTypoin"chordal"example,change"S0"to"SIN0"

15November2006:

AddedCOSXto"chordal"toallowCOSoutputstobereadaswellasSIN,
SpinAsmupdatedtosupportsyntax.
FixedotherinstancesofSX/RXtoSINX/RMPX
DRAMreferencesupdatedtoSRAM

22April2008:

FixedJAMinstruction,typoinSpinAsmdocandassemblyerrorinSpinAsm.

62

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