A

December 11th, 2002

PIC12C508A & THE ADF4110 FAMILY OF PLL SYNTHESIZERS

Author : Pauline LEMORE.

Index
1. 2. 3. 4. Introduction The ADF 4110 Family of PLL synthesizer The PIC12C508A The software code 4.1. The bit banging protocol 4.2. Code Architecture 4.2.1. Configuration bits 4.2.2. Constants and variables definition 4.2.2.1. Outputs 4.2.2.2. Data registers to transmit 4.2.2.3 Variables 4.2.3. Processor initialization 4.2.4. Data transmission 4.2.5. Sub-routines Timings Schematic How to use this software code 7.1. Programming environment 7.2. How to get the wanted fixed frequency Software code p.1 p.2 p.9 p.10 p.10 p.11 p.11 p.12 p.12 p.12 p.13 p.13 p.15 p.15 p.17 p.19 p.23 p.23 p.23 p.25

5. 6. 7.

8.

Introduction:

Presently, it is possible to program any frequency from the 411X evalboard, using the evalboard software. Data is sent through a serial port from the PC to the board. The objective of this project is to use a micro-controller, instead of the software and serial port, to configure the PLL synthesizer. The objective is to have one fixed frequency, the value of which is programmed into the micro-controller. So, when the board is powered up, the micro-controller sends all configuration data to the synthesizer, which will lock the PLL at the desired frequency.

Although the 411X evalboard could be issued with a pre-programmed micro-controller, the serial connection will be still usable. Thus, the customer could choose to get any frequency by the software evalboard and the serial port, or use the micro-controller, and have a fixed frequency. The advantages of using the board with the PIC are mainly the possibility to choose the fixed frequency by changing its value into the software code and the simplicity of its use, just turn on the board and the PLL is locked.

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

a
1

The ADF4110 Family of PLL synthesizers:

This family of PLL synthesizers can deliver maximum output frequencies between 550 MHz and 4 GHz. To get a stable frequency, it is necessary to lock the PLL by programming it. To do that, 4 latches have to be configured. They are: the Reference counter latch, which selects the REFin frequency the N counter latch, where the A and B counters are the Function latch and the Initialization latch, both similar, and where the prescaler, the current and the muxout can be set.

Reference Counter Latch

Reserved
DB23 P2 P2
Lock Detect Precision

Test Mode Bits

Anti Backlash Width

SYNC CP Gain
G1

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DLY SYNC LDP T2 T1 ABP2 ABP1

Reserved

DB22 DB21

Prescaler Value

DB23 DB22 DB21 P1 PD2

Prescaler Value

DB23 DB22 DB21 P1 PD2

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

DLY

14-Bit Reference Counter

Control Bits
DB6 R5 DB5 R4 DB4 R3 DB3 R2 DB2 R1 DB1 DB0

DB15 DB14 DB13 DB12 DB11 DB10 R14 R13 R12 R11 R10 R9

DB9 R8

DB8 R7

DB7 R6

C2 (0) C1 (0)

N Counter Latch
13-Bit B Counter 6-Bit A Counter Control Bits
DB2 A1 DB1 DB0

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 B13 B12 B11 B10 B9 B8 B7 B6 B5

DB11 DB10 DB9 B4 B3 B2

DB8 B1

DB7 A6

DB6 A5

DB5 A4

DB4 A3

DB3 A2

C2 (0) C1 (1)

Function Latch
PHASE DETECTOR POLARITY

FastLock Mode

Fastlock Enable

Power Down 2
CPI6

Counter Reset

Power Down 1

CP 3-State

Current Setting 2

Current Setting 1

Timer Counter Control

MUXOUT Control
DB6 M3 DB5 M2 DB4 M1

Control Bits
DB1 DB0

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2

DB11 DB10 DB9 TC1 F5 F4

DB8 F3

DB7 F2

DB3 PD1

DB2 F1

C2 (1) C1 (0)

Initialisation Latch
PHASE DETECTOR POLARITY

FastLock Mode

Fastlock Enable

Power Down 2
CPI6

Counter Reset

Power Down 1

CP 3-State

Current Setting 2

Current Setting 1

Timer Counter Control

MUXOUT Control
DB6 M3 DB5 M2 DB4 M1

Control Bits
DB1 DB0

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2

DB11 DB10 DB9 TC1 F5 F4

DB8 F3

DB7 F2

DB3 PD1

DB2 F1

a
2

C2 (1) C1 (1)

They are all 24 bits and are programmed via the SPI port on the ADF411X chip. The programming order is the Initialization latch, then the Function latch, the N counter latch and the Reference counter latch. To help, below is the functional block diagram of the ADF4110 Family:
AVDD DVDD VP CPGND RSET
REFERENCE

REFIN

14-BIT R COUNTER

14 R COUNTER LATCH

PHASE FREQUENCY DETECTOR

CHARGE PUMP

CP

CLK DATA LE
24-BIT INPUT REGISTER
22 FUNCTION LATCH

LOCK DETECT

CURRENT SETTING 1

CURRENT SETTING 2

CPI3 CPI2 CPI1CPI6 CPI5 CPI4 SDOUT A, B COUNTER LATCH High Z FROM FUNCTIO N LATCH 19 13 AVDD

MUX

MUXOUT
SDOUT

N = BP + A

13-BIT B COUNTER
LOAD

RFINA RFINB

+ PRESCALER P/P+1 M3 M2 M1
LOAD

6-BIT A COUNTER

ADF4110/1/2/3

CE

AGND

DGND

The A ( 6-bit ) and B (13-bit ) counters, in conjunction with the dual modulus prescaler ( P/P+1 ), implement an N divider ( N = BP + A ). In addition, the 14-bit reference counter ( R counter ), allows selectable REFIN frequencies at the PFD ( Phase Frequency Detector ) input. The description of the bits of each register ( Initialization, Function, AB and Reference latches ) to configure is presented in these four following pages.

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

a
3

Initialization Latch
FastLock Mode Phase Detector Polarity Fastlock Enable Power Down 2
CPI6

Counter Reset

Power Down 1

CP 3-State

Prescaler Value

Current Setting 2

Current Setting 1

Timer Counter Control

MUXOUT Control
DB6 M3 DB5 M2 DB4 M1

Control Bits
DB1 DB0

DB23 DB22 DB21 P2 P1 PD2

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2

DB11 DB10 DB9 TC1 F5 F4

DB8 F3

DB7 F2

DB3 PD1

DB2 F1

C2 (1) C1 (1)

F1 0 1

Counter Operation Normal R, A, B Counters Held in Reset

F3 0 1

Phase Detector Polarity Negative Positive

F3 0 1

Charge Pump Output Normal 3-State

F4 0 Disabled 1 1

F5 X 0 1

Fastlock Mode F a s t l o c k Fastlock Mode 1 Fastlock Mode 2

TC4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CPI6 CPI3 0 0 0 0 1 1 1 1 CPI5 CPI2 0 0 1 1 0 0 1 1 CP14 CPI1 0 1 0 1 0 1 0 1

TC3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

TC2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ICP (mA)

TC1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Timeout (PFD Cycles) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63

M3 0 0 0 0 1 1 1 1

M2 0 0 1 1 0 0 1 1

M1 0 1 0 1 0 1 0 1

Output 3-State Output Digital Lock Detect N Divider Output AVDD R Divider Output N-Channel Open-Drain Lock Detect Serial Data Output DGND

2.7k 1.088 2.176 3.264 4.352 5.44 6.528 7.616 8.704

4.7k 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0

10k 0.294 0.588 0.882 1.176 1.47 1.764 2.058 2.352

CE Pin 0 1 1 1

PD2 X X 0 1

PD1 X 0 1 1

Mode Asynchronous Power-Down Normal Operation Asynchronous Power-Down Synchronous Power-Down

P2 0 0 1 1

P1 0 1 0 1

Prescaler Value 8/9 16/17 32/33 64/65

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

a
4

Function Latch
PHASE DETECTOR POLARITY

FastLock Mode

Fastlock Enable

DB23 DB22 DB21 X X PD2

CE Pin 0 1 1 1

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

Power Down 2
CPI6

Counter Reset

Power Down 1

CP 3-State

Current Setting 2

Current Setting 1

Timer Counter Control

MUXOUT Control
DB6 M3 DB5 M2 DB4 M1

Control Bits
DB1 DB0

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 CPI5 CPI4 CPI3 CPI2 CPI1 TC4 TC3 TC2

DB11 DB10 DB9 TC1 F5 F4

DB8 F3

DB7 F2

DB3 PD1

DB2 F1

C2 (1) C1 (0)

F1 0 1

Counter Operation Normal R, A, B Counters Held in Reset

F3 0 1

Phase Detector Polarity Negative Positive

F3 0 1

Charge Pump Output Normal 3-State

F4 0 1 1

F5 X 0 1

Fastlock Mode Fastlock Disabled Fastlock Mode 1 Fastlock Mode 2

TC4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CPI6 CPI3 0 0 0 0 1 1 1 1 CPI5 CPI2 0 0 1 1 0 0 1 1 CP14 CPI1 0 1 0 1 0 1 0 1

TC3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

TC2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 ICP (mA)

TC1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

Timeout (PFD Cycles) 3 7 11 15 19 23 27 31 35 39 43 47 51 55 59 63

M3 0 0 0 0 1 1 1 1

M2 0 0 1 1 0 0 1 1

M1 0 1 0 1 0 1 0 1

Output 3-State Output Digital Lock Detect N Divider Output AVDD R Divider Output N-Channel Open-Drain Lock Detect Serial Data Output DGND

2.7k 1.088 2.176 3.264 4.352 5.44 6.528 7.616 8.704

4.7k 0.625 1.25 1.875 2.5 3.125 3.75 4.375 5.0

10k 0.294 0.588 0.882 1.176 1.47 1.764 2.058 2.352

PD2 X X 0 1

PD1 X 0 1 1

Mode Asynchronous Power-Down Normal Operation Asynchronous Power-Down Synchronous Power-Down

a
5

N Counter Latch
CP Gain
Reserved 13-Bit B Counter 6-Bit A Counter Control Bits
DB2 A1 DB1 DB0

DB23

DB22 DB21 G1

DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 B13 B12 B11 B10 B9 B8 B7 B6 B5

DB11 DB10 DB9 B4 B3 B2

DB8 B1

DB7 A6

DB6 A5

DB5 A4

DB4 A3

DB3 A2

C2 (0) C1 (1)

A6 0 0 0 0 . . . 1 1 1 1

A5 0 0 0 0 . . . 1 1 1 1

.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........

A2 0 1 1 0 . . . 0 0 1 1

A1 1 0 1 0 . . . 0 1 0 1

A Counter Divide Ratio 1 2 3 4 . . . 60 61 62 63

B13 0 0 0 0 . . . 1 1 1 1

B12 0 0 0 0 . . . 1 1 1 1

B11 0 0 0 0 . . . 1 1 1 1

.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........

B3 0 0 0 1 . . . 1 1 1 1

B2 0 1 1 0 . . . 0 0 1 1

B1 1 0 1 0 . . . 0 1 0 1

B Counter Divide Ratio 1 2 3 4 . . . 8188 8189 8190 8191

F4 (Function Latch) Fastlock Enable 0 Setting 0 Setting 1 Setting 1

CP Gain 0 1 0 1

Operation Charge Pump Current 1 is permanently used Charge Pump Current 2 is permanently used Charge Pump Current 1 is used Charge Pump Current is switched to Setting 2. The time spent in Setting 2 is dependent on Mode is used. Latch

which Fastlock See Function Description

N = BP + A, P is prescaler value set in the Function Latch B must be greater than or equal to A For contiguous values of N, NMIN is (P2 - P)

These bits are not used by the device and are Don't Care Bits.

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

a
6

Reference Counter Latch

Reserved
DLY 0 0 1 1

Lock Detect Precision

Test Mode Bits

Anti Backlash Width

SYNC
LDP 0 1 SYNC 0 1 0 1

DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DLY SYNC LDP T2 T1 ABP2 ABP1

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

DLY

14-Bit Reference Counter

Control Bits
DB6 R5 DB5 R4 DB4 R3 DB3 R2 DB2 R1 DB1 DB0

DB15 DB14 DB13 DB12 DB11 DB10 R14 R13 R12 R11 R10 R9

DB9 R8

DB8 R7

DB7 R6

C2 (0) C1 (0)

R14 0 0 0 0 . . . 1 1 1 1

R13 0 0 0 0 . . . 1 1 1 1

R12 0 0 0 0 . . . 1 1 1 1

.......... .......... .......... .......... .......... .......... .......... .......... .......... .......... .......... ..........

R3 0 0 0 1 . . . 1 1 1 1

R2 0 1 1 0 . . . 0 0 1 1

R1 1 0 1 0 . . . 0 1 0 1

Divide Ratio 1 2 3 4 . . . 16380 16381 16382 16383

ABP2 0 0 1 1

ABP1 0 1 0 1

Anti-Backlash Pulse Width 2.9ns 1.3ns 6.0ns 2.9ns

Test Mode Bits should be set to 00 for Normal Operation

Operation 3 consecutive cycles of phase delay less than 15ns must occur before lock detect is set. 5 consecutive cycles of phase delay less than 15ns must occur before lock detect is set.

Operation Normal Operation Output of Prescaler is Resynchronized with non-delayed version of RF Input. Normal Operation Output of Prescaler is Resynchronized with delayed version of RF Input.

a
7

As was shown, using the SPI port on the PLL synthesizer configures all the registers. From the PIC, data is sent to the SPI, via three wires for the clock, data and the latch enable. Once the SPI buffer is filled, a pulse is sent on the latch enable input. Thus, the value in the buffer goes to the appropriate latch. This is determined with the last two bits, or the two LSB. So, it is necessary to send the 24 bits starting with the MSB and finishing with the LSB. Using SPI, SDATA is sampled on each rising edge of SCLOCK. This diagram shows the timings, which are minimum for a good working of the synthesizer.
t4

t5

CLOCK t2 t3

DATA

DB23 (MSB)

DB22

DB2

DB1 (CONTROL BIT C2)

DB0 (LSB) (CONTROL BIT C1) t7

LE t1 t6

LE

With:

t1 = 10 ns mini, LE Setup Time t2 = 10 ns mini, DATA to CLOCK Setup Time t3 = 10 ns mini, DATA to CLOCK Hold Time t4 = 25 ns mini, CLOCK High Duration t5 = 25 ns mini, CLOCK Low Duration t6 = 10 ns mini, CLOCK to LE Setup Time t7 = 20 ns mini, LE Pulsewidth

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

a
8

The PIC12C508A:

For this simple application, it was decided to work with one of the Microchip microcontrollers. The PIC12C5XX family has an internal oscillator at 4 MHz, 8-bit wide data and 8 pins. Moreover, they are in-circuit programmable. This is a special feature that could be used in the future, because for the present, the PIC is programmed with the PICSTART Plus development programmer. These micro-controllers are not SPI compatible. A transmission protocol, called bitbanging, will be used to transfer data from the PIC to the PLL synthesizer. This protocol is compatible with the SPI, as it is based on it. The PIC12C508A is one of the simplest and cheapest micro controllers from Microchip. Here it was decided to use an one-time programmable ( OTP ) chip, because of the wanted fixed frequency. So with the software code inside this report, only one frequency is pre-programmed into the PIC.

VDD GP5/OSC1/CLKIN GP4/OSC2 GP3/ /MCLR / VPP

1 PIC12C508A 2 3 4

8 7 6 5

VSS GP0 GP1 GP2/TOCK1

Figure 1: Pin diagram

VDD and VSS are the power supply and the ground. The pin /MCLR needs to be set at a high level. It is the master clear, which allows a reset for all the chip. Only three pins on the PIC are used, to implement the SPI protocol:

GP0 GP1 GP2

CLK DATA LE

Only GP4 and GP5 are left not used, but as they are input/output pins, they will not be connected. Finally, minimum timings for a good transmission were given in the previous section. The PIC will be synchronized with its internal oscillator at 4 MHz. Thus, its each Clock cycle will be 250 ns, large enough to ensure a good transmission of the data.

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

a
9

4
4.1

The software code:

The bit banging protocol:

As mentioned above, the PIC12C508A doesnt have a SPI support. Thats why was developed a bit banging protocol, to emulate an SPI interface. Three pins are used for data, clock and latch enable. Before the transmission, data cant be stocked in a 8-bit register, opposite to the SPI where its a 24-bit register. So, the data will be transmitted bit per bit. To know the data value, a left rotation through the carry is done. After testing the carry value, the pin DATA is set or cleared. The rotation needs to be left, because it is necessary to transmit the MSB first. Once the DATA is positioned, the CLK pin is set and cleared, creating a cycle. Then, the PLL synthesizer samples the DATA, on its pin, and loads it into its input latch. To be sure that sampling is correct, it is better to wait before clearing the pin CLK, doing the next left rotation through the carry, preparing the new data value to transmit. In the way of 8 repetitions, 8 bit-data can be sent bit per bit, and stocked in the 8-bit SPI latch of the synthesizer.

First left rotation

Test of the carry

=0 ?

=1 ?

x8

DATA = 0

DATA = 1

CLK = 1

Left rotation

CLK = 0

Figure 2:Functional diagram

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

10

4.2

Code Architecture:

4.2.1

CONFIGURATION BITS:

The 12 configuration bits allow the user to select several device configurations. Only five of them are writable, the others being unimplemented. Two are for the selection of oscillator type, one to enable the watchdog timer bit, one for the code protection and the last one to enable the /MCLR bit.
MCLRE Not implemented Bit 4 CP Bit 3 WDTE Bit 2 FOSC1 Bit 1 FOSC0 Bit 0

Figure 3: Configuration word for the PIC12C5XX During device operations, this register cant be addressable. So to configure it, specific instructions are used, as explained below. Underlined are the instructions that were chosen. FOSC0 1 1 0 0 FOSC1 1 0 1 0 INSTRUCTIONS _ExtRC_OSC _IntRC_OSC _XT_OSC _LP_OSC SELECTION External RC Oscillator Internal 4 MHz RC Oscillator Crystal/Resonator Oscillator Lower Power Crystal Oscillator

WDTE _WDT_ON _WDT_OFF

SELECTION Enabled Disabled

CP _CP_ON _CP_OFF

SELECTION Code protection on Code protection off

MCLRE _MCLRE_ON _MCLRE_OFF

SELECTION /MCLRE pin enabled /MCLRE tied to Vdd ( internally )

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

11

As the watch dog timer and the code protection are not used, the CP and WDT bits are off. The bit /MCLR is on to hardwire the RESET low. And the internal oscillator for our application will be used.

4.2.2

CONSTANTS & VARIABLES DEFINITION:

4.2.2.1 Outputs
Three I/O pins on the micro controller are connected to the 3-wire serial interface of the PLL synthesizer, allowing the PIC to transmit configuration data to frequency synthesizer. They are: GPIO of the PIC GP0 GP1 GP2 Pin labels CLK DATA LE

The pins GP0, GP1 and GP2 will be configured as outputs later in the code, by configuring the Tris register. Here we are simply labelling the pins of the PICis only a labelling for the pins of the PIC.

4.2.2.2 Data registers to transmit

The following data need to be entered by the user to program the PLL synthesizers output frequency Four 24-bit words have to be transmitted to the PLL synthesizer. As only data bytes are available in the PIC memory, each 24-bit word will be split into 3 bytes: one most significant, one middle and one least significant. So we have: For the Reference Latch, REF_LATCH_H REF_LATCH_M REF_LATCH_L AB_LATCH_H AB_LATCH_M AB_LATCH_L FCT_LATCH_H FCT_LATCH_M FCT_LATCH_L INIT_LATCH_H INIT_LATCH_M

For the AB Latch,

For the Function Latch,

For the Initialization Latch,

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

12

INIT_LATCH_L In this definition, memory space is allocated and its value in hexadecimal code is entered. See in the section 7, how to program them.

4.2.2.3 Variables
Temp is used in the SEND_BYTE sub-routine. It contains the value of one the register bytes to transmit. After each left rotation to get the new bit to send, the result is put in the Temp variable. Count, used in the same sub-routine as the Temp variable, is initialised to 8 and decremented at each rotation. Its a counter to send 8 bits, not more, not less. When it equals zero, the SEND_BYTE sub-routine is stopped.

4.2.3

PROCESSOR INITIALIZATION:

To initialise the processor, the following registers need to be configured: The OSCCAL where six of its eight bits allow the internal 4 MHz oscillator to be calibrated. Increasing the cal value, increases the frequency.

Cal 5 Bit 7

Cal 4

Cal 3

Cal 2

Cal 1

Cal 0 Bit 0

The OPTION_REGISTER contains the controls bit to configure timer0, timer0/watchdog prescaler, wake-up on change and weak pull-ups.
/GPWU Bit 7 /GPPU TOCS TOSE PSA PS2 PS1 PS0 Bit 0

/GPWU

SELECTION

0 1

Wake-up on pin change ( GP0, GP1, GP3 ) enabled Wake-up on pin change disabled

/GPPU

SELECTION

0 1

Weak pull-ups ( GP0,GP1,GP3 ) enabled Weak pull-ups disabled

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

13

TOCS ( timer clock source select bit )

SELECTION

0 1

Transition on internal instruction cycle clock Fosc/4 Transition on TOCK1 pin

TOSE ( timer0 source edge select bit )

SELECTION

0 1

Incrementing on low to high transition on the TOCK1 pin Incrementing on high to low transition on the TOCK1 pin

PSA ( Prescaler assignment bit )

SELECTION

0 1

Prescaler assigned to timer0 Prescaler assigned to the WDT

PS2 PS1 PS0

Timer0 rate

WDT rate

000 001 010 011 100 101 110 111

1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256

1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128

The GPIO is an 8-bit I/O register. Only the lowest significant bits are used, the others are unimplemented. GP3 in only an input. The TRIS register allows to configure each pins as an input or output of the GPIO. It is the output driver control register. A 1 from a TRIS register bit puts the corresponding output driver in a hi-impedance mode. A 0 puts the contents of the output data latch on the selected pins, enabling the output buffer.

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

14

4.2.4

DATA TRANSMISSION:

Four 24-bit words are sent each split into three bytes. There are four sub-routines, each specific for one of the four 24-bit words: SEND_INIT_WORD SEND_FCT_WORD SEND_AB_WORD SEND_REF_WORD First, the initialisation word is sent to the PLL synthesizer. It is needed for the first programming of the chip. Then, the function word, the N counter or AB counter word and, finally the Reference word, will be transmitted. Once all are sent, the micro-controller stays in an infinite loop doing nothing.

4.2.5

SUB-ROUTINES:

SEND_BYTE is the sub-routine for the bit banging protocol, based on the SPI serial interface. Its function is to clock out a byte of data via the data and clock outputs. See section bit banging protocol Variables: Temp, contains the data byte to send to the PLL synthesizer. Count, which is a counter initialised to 8. Send a byte is done as follows ( see figure 2: Functional diagram ): - Initialization of the variables Temp and Count, with the data byte to transmit from the W register and the hexadecimal value 8. - First left rotation through the carry, where the MSB is ready to be transmitted. - Carry test. If carry bit equals 1, call the ONE sub-routine to set the DATA pin. If carry bit equals 0, call the ZERO sub-routine to clear the DATA pin. - Clock pin is toggled and a new left rotation is done, allowing time for the PLL synthesizer to sample data. - Decrementing of the counter and back to the carry test, which has got the next bit to transmit with the rotation during the clock banging. A test is done on the Count value, while being decremented. When Count equals 0, eight bit-transmission is finished, and so, all the three bytes have been sent to the synthesizer. We return from this sub-routine to the sub-routine, which called it. It could be SEND_INIT_WORD, SEND_FCT_WORD, SEND_AB_WORD or SEND_REF_WORD.

SEND_INIT_WORD is a sub-routine to send the configuration word for the initialization latch of the PLL synthesizer. First, the most significant byte is sent using the SEND_BYTE routine. Then, the middle byte is sent, followed by the least significant byte. The value of those bytes is loaded from the memory to the W register, and then use in the SEND_BYTE routine with the local variable Temp.
PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

15

SEND_FCT_WORD, SEND_AB_WORD and SEND_REF_WORD are built in the same way as SEND_INIT_WORD, but their respective purpose is to transmit the configuration word for the function, N counter and Reference latches.

LATCH_ENABLE is the last sub-routine of the software code. It simply generates a pulse on the PIC pin linked to the PLL synthesizer LE. After the falling edge of a 24-bit register write operation, the clock to LE setup time(10 ns ) must be observed, so the minimum LE pulsewidth ( 20 ns ) before clearing the LE bit. Toggling the LE bit takes the 24 bit data, which has just been clocked into the synthesizers input shift register, and loads it into one of the corresponding data latch.

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

16

Timings

Below are the timings for programming a 411X PLL synthesizer with a PIC12C508A programmed for the fixed frequency of 900 MHz, and a PFD of 200 kHz. Data to configure the PLL at these working conditions, is:

INITIALIZATION LATCH FUNCTION LATCH AB LATCH REFERENCE LATCH

: : : :

9F 80 93h 9F 80 92h 00 8C 51h 00 00 C8h

There are four LE pulses, each one positioned after three packs of eight clock events ( or three bytes ). So, these 24 clock cycles correspond to the transmission of 24 bits, that is to say one configuration word to the PLL synthesizer. The first one is the configuration word for the initialisation latch, the second one for the function latch, the third one for the AB latch and the last one for the Reference latch.

DATA

CLK

LE
Initialization Function AB Reference

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

17

Below are represented, the average timings measured by scope, while sending data from the PIC12C508A to the PLL synthesizer.

DATA

81.20 us

CLK 9.2 us 6us

LE

1.4 us

To transmit one byte: 81.20 us To transmit one word: 250 us Time between two clock raising edge: 9.2 us Clock and LE Pulsewidth: 1.4 us Comparing with the timings of the SPI transmission in the section 2, they are large enough to allow a good transmission of the data, between the micro controller and the PLL synthesizer.

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

18

Schematic

The simplest connection schematic between the PLL synthesizer and the PIC, is the following:

VDD

ADF4110/1/2/3 CLK DATA LE LE

VDD PIC12C508A

GP0 GP1 GP2

SCK SDATA

On the following pages, are given the whole schematic of the board built for this application, with all the components, like decoupling capacitors, resistors, etc, for the good working of each chip on the board; and the silkscreen of this same board.

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

19

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

20

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

21

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

22

How to use this software code

This use guide of the software is based on the example of a PLL that we want it to work in the following conditions: Chip : Power : Icpmax : REFin : Output Frequency : PFD : Muxout : Rset : Prescaler : PD Polarity : Current settings (1&2 ) ADF4113 5V 5 mA 10MHz 900MHz 200kHz Digital lock detect 4,7kOhm 32 positive :7

7.1

Programming environment

The evalboard has been developed to use the PIC12C508A, SOIC package or DIP socket. The power supply could be 3V or 5V for both the PIC and the synthesizer. The output levels coming from the PIC depend of the power supply. To program the PIC, the user needs the PICSTART Plus development programmer, a PC with a serial port, the Microchip software MPLAB, version 5.20. The software code is written in the MPASM language, specific to the Microchip micro controllers.

7.2

How to get the wanted fixed frequency

While it is soldered on the board, the PLL synthesizer is programmed by the PIC. If the user does want to use the serial connection, the PIC would have been removed, which keeps the priority between both kinds of PLL synthesizers programming. The software given to the user is optimised to program an output frequency of 900 MHz for the ADF4113. To change the value of this output frequency, the new value to enter into each register of the synthesizer needs to be calculated. For that, it is possible to use the interactive tool on the ADI website: http://www.analog.com/techSupport/designTools/interactiveTools Then, by clicking on the link called ADF 4110/1/2/3 in the Phase-Locked Loop section, the tool to calculate the hexadecimal value of each register of the chosen device is launched. The only things to enter are the working conditions of the synthesizer on the top of the page.

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

23

Next to the registers, you can find their hexadecimal value to write into the software code following the same order that they are presented by the tool. If one of the hexadecimal values starts with a letter ( A, B, C, D, E or F ), a zero should be put before it. For example: To write the hex value C8h, it will be written 0C8h. However, a zero mustnt be put for a value with a letter in it, but starting with a number, as 9F. Remember that a register is split into three bytes. For example, the Reference latch value to enter is 0000C8h, you will fill the bytes in the code as shown below: REF_LATCH_H : 00h REF_LATCH_M : 00h REF_LATCH_L : 0C8h In the software code, a summary of these indications is done, above the variables to update.

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

24

Software code:

;***************************************************************************** ; * ; Filename : pic12c.asm * ; Date : 21/11/02 * ; * ; Author : Pauline LEMORE * ; Company : Analog Devices * ; * ;***************************************************************************** ; * ; Notes : The PIC12C508A is used with the EVAL-ADF411XEB1 * ; This PIC doesn't have an SPI. To transmit data * ; to PLL, the bit banging protocol is used. * ; * ;*****************************************************************************
list p=12c508a #include <p12c508a.inc>

;definition of the processor used ;include processor specific variable definitions

__CONFIG _CP_OFF & _WDT_OFF & _MCLRE_ON & _IntRC_OSC

;***************************************************************************** ; CONSTANTS DEFINITION * ;*****************************************************************************

#define CLK GPIO,0 #define DATA GPIO,1 #define LE GPIO,2

;===================================================================== ;= = ;= Following, data to configure the PLL synthesizer. = ;= = ;= They can be calculated using the following link : = ;= ---------------------------------------------------------------= ;= http://www.analog.com/techSupport/designTools/interactiveTools + ADF411x = ;= ---------------------------------------------------------------= ;= = ;= Notes : = ;= = ;= All configuration words are 24 bits, so for programming they are split = ;= into 3 bytes. It is important to start with the most significant byte. = ;= A useful link to help in programming the PIC is given just above. = ;= The registers have to be filled in the same order as presented by the design tool. = ;= = ;= Note, for programming the PIC, if the hex values starts with a letter, = ;= a zero should have been put before. For example : =
PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

25

;= = ;= To write the hex value C8h, it will be written 0C8h. = ;= But, to write the hex value 9F, a zero mustn't be put. = ;= = ;= --------------------------------------------------------------= ;= = ;= Example of programming: = ;= = ;= To get these working features for the EVAL-ADF4113EB1 : = ;= = ;= --------------------------------------------------------------= ;= chip : ADF4113 power : 5 V Icpmax : 5mA = ;= REFin : 10 MHz VCO : 900 MHz PFD : 200 kHz = ;= P : 32 Rset : 4,7 kohms = ;= Muxout : digital lock detect PD Polarity : ticked = ;= Current settings ( 1 & 2 ) : 7 = ;= ---------------------------------------------------------------= ;= = ;= the values to put in the registers are : = ;= = ;= REFERENCE LATCH : 00 00 C8h = ;= AB LATCH : 00 8C 51h = ;= FUNCTION LATCH : 9F 80 92h = ;= INITIALIZATION LATCH : 9F 80 93h = ;= = ;= As the REFERENCE latch is divided into 3 bytes, they will be filled as = ;= shown below : = ;= = ;= REF_LATCH_H : 00h the most significant byte = ;= REF_LATCH_M : 00h = ;= REF_LATCH_L : 0C8h the less significant byte = ;= = ;=====================================================================

#define REF_LATCH_H #define REF_LATCH_M #define REF_LATCH_L #define AB_LATCH_H #define AB_LATCH_M #define AB_LATCH_L #define FCT_LATCH_H #define FCT_LATCH_M #define FCT_LATCH_L #define INIT_LATCH_H #define INIT_LATCH_M #define INIT_LATCH_L

00h 00h 0C8h 00h 8Ch 51h 9Fh 80h 92h 9Fh 80h 93h

; High Reference Latch Byte ; Middle Reference Latch Byte ; Low Reference Latch Byte ; High AB Latch Byte ; Middle AB Latch Byte ; Low AB Latch Byte ; High Function Latch Byte ; Middle Function Latch Byte ; Low Function Latch Byte ; High Initialization Latch Byte ; Middle Initialization Latch Byte ; Low Initialization Latch Byte

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

26

; ; ;

------------------------------------------------------end of data to update -------------------------------------------------------

;***************************************************************************** ; VARIABLES DEFINITION * ;*****************************************************************************

temp count EQU EQU 08h 09h

;***************************************************************************** ; CODE CORE * ;*****************************************************************************

ORG 00h goto main main

; processor reset vector

; ; ;
INIT

------------------------------------------------------processor initialization ------------------------------------------------------clrf clrf OSCCAL GPIO

movlw 0CFh OPTION movlw 0FFh movwf OSCCAL movlw 00h TRIS 6

; ; ;

------------------------------------------------------to send data to the PLL synthesizer ------------------------------------------------------SEND_INIT_WORD SEND_FCT_WORD SEND_AB_WORD SEND_REF_WORD

SENDING call call call call nop B

$-1

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

27

;===================================================================== ;= to send configuration words for the pll = ;= --------------------------------------= ;= As the configuration words are 24 bits and the register for the serial = ;= transmission has 8 bits, the data need to be transferred in 3 goes or 3 bytes. = ;=====================================================================
SEND_BYTE movwf movlw movwf bcf rlf LOOP btfsc goto goto SEND_BIT bsf rlf bcf STATUS,C ONE ZERO temp 08h count STATUS,C temp,1

;data to transmit in the temp variable ;initialization of the counter for the 8-bit-transmission ;clear the carry ;MSB put into the carry, through a left rotation ;test of the carry. If equals to 1, set SPIDATA. ;If equals to 0, clear SPIDATA ;banging of the clock ;rotation to put the new bit to be transmitted into the carry ;when count equals to 0, all 8 bits have been transmitted

CLK temp,1 CLK

decfsz count,1 goto LOOP retlw 0 ONE bsf goto DATA SEND_BIT DATA SEND_BIT

ZERO bcf goto

; ; ; ;

------------------------------------------------send the configuration word for the Initialization latch ------------------------------------------------;loading of the highest byte of data to transmit ;transmission of the highest byte of data ;for the middle byte of data ;for the low byte of data

SEND_INIT_WORD movlw INIT_LATCH_H call SEND_BYTE movlw INIT_LATCH_M call SEND_BYTE movlw INIT_LATCH_L call SEND_BYTE call retlw LATCH_ENABLE 0

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

28

; ; ; ;

------------------------------------------------send the configuration word for the Function latch -------------------------------------------------

SEND_FCT_WORD movlw FCT_LATCH_H call SEND_BYTE movlw FCT_LATCH_M call SEND_BYTE movlw FCT_LATCH_L call SEND_BYTE call retlw LATCH_ENABLE 0

; ; ; ;

------------------------------------------------send the configuration word for the AB latch -------------------------------------------------

SEND_AB_WORD movlw AB_LATCH_H call SEND_BYTE movlw AB_LATCH_M call SEND_BYTE movlw AB_LATCH_L call SEND_BYTE call retlw LATCH_ENABLE 0

; ; ; ;

------------------------------------------------send the configuration word for the Reference latch -------------------------------------------------

SEND_REF_WORD movlw REF_LATCH_H call SEND_BYTE movlw REF_LATCH_M call SEND_BYTE movlw REF_LATCH_L call SEND_BYTE call retlw LATCH_ENABLE 0

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

29

; ; ;

------------------------------------------------to send the LE signal -------------------------------------------------

LATCH_ENABLE nop bsf LE nop bcf LE retlw 0

; ; ;

------------------------------------------------End of the program ------------------------------------------------END

PIC12C508A & the ADF4110 Family of PLL synthesizers December 11th, 2002

30