LAB 2 BEHAVIORAL LEVEL, RTL ,AND GATE LEVEL DESIGN

Overview In this lab student will learn the simple behavioural, Register Transfer Level and Gate level designs using ModelSim simulator. The first exercise will introduce the several levels of abstraction. Students then will simulate and analyse the circuit with different design levels. At the end of this lab, students must able to write a test-bench to simulate the design and able to identify the Verilog abstraction available. Objectives The objectives of this lab are: 1. To expose students with several levels of Verilog abstraction 2. To learn how to write a test-bench test a hardware design 3. To learn how to convert the Verilog coding to a circuit or otherwise. Part 1: Structural, Behavioral, RTL Design Ex 1.1 Structural design (Full Adder) 1. Create the structural adder file below in the text editor and save the files as addbit.v

2. Students are required to draw the 1 bit adder logic circuit. Understand the circuit and the HDL coding given above. 3. Create a test-bench file below and save the files as add_tst.v using text editor.

E&E Engineering, SKTM, UMS 2014

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4. Compile and simulate the Verilog HDL given according to the step in Part 1. 5. Select the suitable simulation running time. Analyze the waveform and re-simulate the hardware by adjusting the variable in the test-bench file. 6. Students are required to print-screen the waveform with the corresponding values for report purpose.

Ex 1.3 Behavioral design (Full Adder) 1. Create the behavioral adder file below in the text editor and save the files as addbit1.v

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2. Students are required to write a test-bench to simulate the behavioral adder design above. Save the file as add_tst1.v 3. Compile and simulate the Verilog HDL. Select the suitable simulation running time. Analyze the waveform.

Ex 1.3 RTL design (Full Adder) 1. Create the RTL adder file below in the text editor and save the files as addbit2.v

2. Students are required to write a test-bench to simulate the RTL adder design above. Save the file as add_tst2.v 3. Compile and simulate the Verilog HDL. Select the suitable simulation running time. Analyze the waveform.

Report 1. Access to E-Report System (ERS) at http://www.els.bugs3.com to submit online lab report before end of the lab. Please ask instructions from your lab demonstrator. 2. Your report must include the output/ waveform, test bench for Ex 1.2 and 1.3 and all related information that support your analysis. All the information MUST BE in SINGLE document. The extension file accept in the form is .doc / .docx / .pdf 3. All report submission must be on-time. Late submission will NOT BE accepted automatically.

References 1. ModelSim (v6.5b) Tutorial Chapter 3 to 6 2. Microelectronics Lecture Note

E&E Engineering, SKTM, UMS 2014

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