BY M ATTH E W H AN N T E X A S I N S T R U m E N T S

Use Spice to analyze DRL in an ECG front end

UNdersTANd THIs crITIcAl ANAlOg FrONT eNd FOr THIs uBIQuITOus, VITAl ECG MedIcAl INsTruMeNT.

CG (electrocardiography) is the science of converting the ionic depolarization of the heart to a measurable electrical signal for analysis. One of the most common challenges in the design of analog electronics interfaces to the electrodes or to patients is optimization of the DRL (driven-rightleg) circuit, which is often added to biological-signal amplifiers to reduce common-mode interference and to increase performance and stability. Using Spice to help in this effort can greatly simplify the process. In an ECG front end, the DRL amplifier provides a common electrode bias at the reference voltage, VREF, and feeds back the inverted common-mode noise signal, eNOISECM, to reduce the overall noise seen at the inputs of the instrumentation amplifiers gain stage. The positive and negative ECG sources, ECGP and ECGN, are split to show how the DRL amplifier provides the common reference point for a portion of the ECG signal that is seen at the positive
LEFT ARM

and the negative inputs of the instrumentation amplifier (Figure 1). The parallel RC (resistance/capacitance) combination for the left arm, the right arm, and the right leg represents the lumped passive-electrode connection impedances, which are 52 k and 47 nF. Assuming that eNOISE couples parasitically into the inputs, the feedback of eNOISECM will reduce the overall noise signal at each input, leaving the task of either externally filtering the residual noise or having the CMRR reject the instrumentation amplifiers commonmode noise. Figures 2, 3, and 4 show the variation in CMRR of the common-mode test circuit with the varying gain of the DRL amplifier. These plots show that you can achieve the best lowfrequency CMRR with no feedback resistor, yielding infinite gain. In reality, however, eliminating the dc path, setting RF to a high value, or using both of these methods may be impractical for applications that require the linear operation

ECGP

CP1 RIGHT ARM ENOISECM ENOISE CP2

+
R R INSTRUMENTATION AMP OR PGA

ECGN

RIGHT LEG

RF RI

BUFFER AMP

DRL AMP

VREF

Figure 1 The positive and the negative ECG sources, ECGP and ECGN, split to show how the DRL amplifier provides the common reference point for a portion of the ECG signal that the positive and negative inputs of the instrumentation amplifier sees.

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VCC
+ +

VREF

R4 52k

IC1 OPA333

RPROT1 100k C5 33 pF C7 33 pF RG1 6.1k

VCC
+ +

C2 47 nF C4 47 nF C6 1 nF RPROT2 100k

C10 1 F

RG RG

R12 500k VOUT

REF IC4 INA826

VCM

RG2 6.1k

RRLD 52k

R7 52k CRLD 47 nF R6 10k C11 1 nF RF 100k RI 10k

VCC

V1 5V

R1 1M

VREF

IC3 OPA2314
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R9 1M

RPROT3 100k

IC2 OPA2314
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VCC VREF

VCC

Figure 2 You can achieve the best low-frequency CMRR with no feedback resistor, yielding infinite gain.

80 RF =10 k 100 120 140 160 180 1 RF =100 M 10 100 1k 10k

DIANE

20 40 60 80 CMRR 100 (dB) 120 140 160 180 1 10 100 1k 10k 100k FREQUENCY (Hz) NO DRL DRIVE

RF =100 k RF =1 M RF =10 M

CMRR (dB)

Figure 3 Eliminating the dc path, setting RF to a high value, or using both of these methods may be impractical for applications that require linear operation of the DRL amplifier when you remove one of the input amplifier leads.

FREQUENCY (Hz) EDN MS4430 Fig 2.eps

Figure 4 Gain is higher in circuits with no DRL drive.

of the DRL amplifier when one of the input amplifiers leads is removed. Once you determine the gain of the DRL amplifier, the next step is to inject a small signal step in the loop and monitor the output response (Figure 5). In this case, the response shows a strong output oscillation, indicating instability in the
36 EDN | JANUARY 5, 2012

loop (Figure 6). The dominant feedback path causing this instability is the feedback path for the body, the electrode, and the instrumentation-amp feedback path around the DRL amplifier. A test circuit allows you to separate and analyze the feedback and the open-loop-gain curve of the DRL amplifier on a bode plot (Figure 7).
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VCC
+ +

VREF

R4 52k

IC1 OPA333 ECGP RPROT1 100k C5 33 pF C7 33 pF RG1 6.1k VCC

+ +

VTEST +

C2 47 nF C4 47 nF C6 1 nF RPROT2 100k

C10 1 F

RG REF RG IC4 INA826

R12 500k VOUT

RG2 6.1k

RRLD 52k

R7 52k CRLD 47 nF

ECGN

VCC

RF 10M

RI 10k

V1 5V

R1 1M

VREF

IC3 OPA2314
+ +

R9 1M

RPROT3 100k

IC2 OPA2314
+ +

VCC VREF

VCC

Figure 5 Once you determine the gain of the DRL amplifier, the next step is to inject a small signal step in the loop and monitor the output response.

2.3 ECGN 1.3 2.3 ECGP 1.3 2.7 VOUT 2.4 100m VTEST 100m 0 25

Without an external compensation network, the betadistribution curve approaches the open-loop-gain curve at a rate of closure greater than 20 dB per decade, indicating instability. To address this issue (Figure 8), add series resistor RC and capacitor CC (Figure 9) in the local feedback of the DRL amplifier. ZC then becomes the dominant feedback path between 20 and 30 kHz. The result for the simulation in Figure 7 is represented by the beta (feedback) curve in Figure 10. Figure 11 shows the full circuit of the DRL with compensation. Figure 12 shows the compensated beta-curve plots, employing variations in RC and CC. The overall beta EDN MS4430 Fig 5.eps DIANE curve intersects the open-loop-gain curve with a rate of closure that is 20 dB per decade or less and a loop gain with a phase margin greater than 45 (Figure 13). Spice can be a useful tool to quickly help analyze and optimize the performance and stability of the DRLs front-end circuitry. Keep in mind that the simulation is only as good as the models, so it is important to correctly model key specifications, 50 75 100 such as noise, open-loop gain, open-loop output impedance, TIME (SEC) and CMRR versus frequency, before analysis and design.EDN ACKNOWLEDGMENT This article originally appeared on EDNs sister site, Planet Analog, http://bit.ly/uDHbXT.
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Figure 6 The response shows a strong output oscillation, indicating instability in the loop.

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VCC
+ +

VREF

R4 52k

IC1 OPA333

RPROT1 100k C5 33 pF RG1 6.1k

VCC
+ +

C2 47 nF C4 47 nF C6 1 nF RPROT2 100k

C10 1 F

RG REF RG IC4 INA826

R12 500k

C7 33 pF

RG2 6.1k

RRLD 52k

R7 52k CRLD 47 nF VREF VORLD L1 ONE TURN RPROT3 100k

VCC

R3 10k

V1 5V

R1 1M

VREF

IC3 OPA2314
+ +

R9 1M

IC2 OPA2314
+ +

C1 ONE TURN VREF

VCC
+

VTEST

VCC

RF 10M RC CC

Figure 7 A test circuit allows you to separate and analyze the feedback and the open-loop-gain curve of the DRL amplifier on a bode plot.

Figure 9 Add series resistor RC and capacitor CC in the local feedback of the DRL amplifier.
VREF

OPA2314
+ +

VCC RF 10M RC VORLD

120

CC L2 ONE TURN

RI 10k

VREF VREF
GAIN (dB)

100 80 60 40 20 0 1 10 1k 10k 100k 1M 10M FREQUENCY (Hz) DIANE Z =10 k, 200 pF ZC=10 k, 800 pF ZC=10 k, 2 nF ZC=10 k, 4 nF
C

OPA2314
+ +

EDN MS4430 Fig 7.eps C3 ONE TURN VREF

+

DIANE

VG1

VCC

100

Figure 8 Without an external compensation network, the betadistribution curve approaches the open-loop-gain curve at a rate of closure greater than 20 dB per decade, indicating instability.

EDNMS4430 Fig 9.eps OPEN-LOOP GAIN BETA CURVE, INSTRUMENTATIONAMP/ELECTRODE FEEDBACK ZC=RC, CC

Figure 10 The result for the simulation in Figure 7 is represented by the beta curve.

38 EDN | JANUARY 5, 2012

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VCC VREF
+ +

R4 52k RPROT1 100k C2 47 nF C4 47 nF RPROT2 100k C6 1 nF C5 33 pF RG1 6.1k VCC

+

IC1 OPA333

RG + REF RG IC4 INA826

C10 1 F

R12 500k

C7 33 pF

RG2 6.1k

RRLD 52k

CRLD 47 nF

R7 52k

R2 10M RF 10k RI 10k

VCC

VREF

VORLD

IC2 OPA2314

VCC

Figure 11 The full circuit of the DRL includes compensation.

60

40 GAIN (dB) 20

OPEN-LOOP GAIN ZC=RC, CC ZC=10 k, 200 pF ZC=10 k, 800 pF ZC=10 k, 2 nF ZC=10 k, 4 nF

0 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz)

Figure 12 The compensated beta-curve plots employ variations in RC and CC.

AUTHORS BIOGRaPHY Matthew William Hann is a precision-analog-applications man- developed a focused expertise on the design of analog front ends EDNMS4430 Fig 10.eps for DIANE ager at Texas Instruments. He has more than a decade of prodmedical applications, such as ECGs, electroencephalograms, uct expertise, which includes temperature sensors, difference am- electromyograms, blood-glucose monitoring, and pulse oximetry. plifiers, instrumentation amplifiers, programmable-gain amplifi- Hann received a bachelors degree in electrical engineering from ers, power amplifiers, and TIs line of ECG analog-front-end the University of ArizonaTucson. You can reach him at ti_ devices. Through his role as an applications engineer, Hann has matthann@list.ti.com.
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RPROT3 100k

VCC

VREF

GAIN (dB) (a)

PHASE () (b)

Figure 13 The overall beta curve intersects the open-loop-gain curve with a rate of closure that is 20 dB per decade or less and a loop gain (a) with a phase margin greater than 45 (b).

+ +

C3 4 nF

V1 5V

120 100 80 60 40 20 0 180 135 90 45 0 1 10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

IC3 OPA2314

R1 1M VREF R9 1M

+ +