INA3

26

INA3

27

INA326 INA327

SBOS222D NOVEMBER 2001 REVISED NOVEMBER 2004

Precision, Rail-to-Rail I/O INSTRUMENTATION AMPLIFIER

FEATURES
G PRECISION LOW OFFSET: 100V (max) LOW OFFSET DRIFT: 0.4V/C (max) EXCELLENT LONG-TERM STABILITY VERY-LOW 1/f NOISE G TRUE RAIL-TO-RAIL I/O INPUT COMMON-MODE RANGE: 20mV Below Negative Rail to 100mV Above Positive Rail WIDE OUTPUT SWING: Within 10mV of Rails SUPPLY RANGE: Single +2.7V to +5.5V G SMALL SIZE microPACKAGE: MSOP-8, MSOP-10 G LOW COST

DESCRIPTION
The INA326 and INA327 (with shutdown) are high-performance, low-cost, precision instrumentation amplifiers with rail-to-rail input and output. They are true single-supply instrumentation amplifiers with very low DC errors and input common-mode ranges that extends beyond the positive and negative rails. These features make them suitable for applications ranging from general-purpose to high-accuracy. Excellent long-term stability and very low 1/f noise assure low offset voltage and drift throughout the life of the product. The INA326 (without shutdown) comes in the MSOP-8 package. The INA327 (with shutdown) is offered in an MSOP-10. Both are specified over the industrial temperature range, 40C to +85C, with operation from 40C to +125C.

INA326 AND INA327 RELATED PRODUCTS

PRODUCT INA337 INA114 INA118 INA122 INA128 INA321 FEATURES Precision, 0.4V/C Drift, Specified 40C to +125C 50V VOS, 0.5nA IB, 115dB CMR, 3mA IQ, 0.25V/C Drift 50V VOS, 1nA IB, 120dB CMR, 385A IQ, 0.5V/C Drift 250V VOS, 10nA IB, 85A IQ, Rail-to-Rail Output, 3V/C Drift 50V VOS, 2nA IB, 125dB CMR, 750A IQ, 0.5V/C Drift 500V VOS, 0.5pA IB, 94dB CMRR, 60A IQ, Rail-to-Rail Output

APPLICATIONS
G LOW-LEVEL TRANSDUCER AMPLIFIER FOR BRIDGES, LOAD CELLS, THERMOCOUPLES G WIDE DYNAMIC RANGE SENSOR MEASUREMENTS G HIGH-RESOLUTION TEST SYSTEMS G WEIGH SCALES G MULTI-CHANNEL DATA ACQUISITION SYSTEMS G MEDICAL INSTRUMENTATION G GENERAL-PURPOSE

V+ VIN 2 1 7

4 INA326 6 5 VO G = 2(R2/R1)

R1 8 3

VIN+

R2

C2

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Copyright 2001-2004, Texas Instruments Incorporated

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PACKAGE/ORDERING INFORMATION(1)
PACKAGE DESIGNATOR DGK SPECIFIED TEMPERATURE RANGE 40C to +85C PACKAGE MARKING B26 ORDERING NUMBER INA326EA/250 INA326EA/2K5 INA327EA/250 INA327EA/2K5 TRANSPORT MEDIA, QUANTITY Tape and Reel, 250 Tape and Reel, 2500 Tape and Reel, 250 Tape and Reel, 2500

PRODUCT INA326

PACKAGE-LEAD MSOP-8

"
INA327

"
MSOP-10

"
DGS

"
40C to +85C

"
B27

"

"

"

"

"

NOTE: (1) For the most current package and ordering information, download the latest version of this data sheet and see the Package Option Addendum located at the end of the data sheet.

ABSOLUTE MAXIMUM RATINGS(1)

Supply Voltage .................................................................................. +5.5V Signal Input Terminals: Voltage(2) .............................. 0.5V to (V+) + 0.5V Current(2) ................................................... 10mA Output Short-Circuit ................................................................. Continuous Operating Temperature Range ....................................... 40C to +125C Storage Temperature Range .......................................... 65C to +150C Junction Temperature .................................................................... +150C Lead Temperature (soldering, 10s) ............................................... +300C NOTES: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. (2) Input terminals are diode clamped to the power-supply rails. Input signals that can swing more than 0.5V beyond the supply rails should be current limited to 10mA or less.

ELECTROSTATIC DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PIN CONFIGURATION
Top View
INA326 R1 VIN VIN+ V 1 2 3 4 MSOP- 8 8 7 6 5 R1 V+ VO R2

INA327 R1 VIN VIN+ V (Connect to V+) 1 2 3 4 5 MSOP- 10 10 R1 9 8 7 6 V+ VO R2 Enable

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SBOS222D

ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V

BOLDFACE limits apply over the specified temperature range, TA = 40C to +85C
At TA = +25C, RL = 10k, G = 100 (R1 = 2k, R2 = 100k), external gain set resistors, and IACOMMON = VS /2, with external equivalent filter corner of 1kHz, unless otherwise noted. INA326EA, INA327EA PARAMETER CONDITION MIN TYP 20 MAX 100 UNITS V

INPUT Offset Voltage, RTI VOS VS = +5V, VCM = VS /2 Over Temperature vs Temperature dVOS/dT vs Power Supply PSR VS = +2.7V to +5.5V, VCM = VS /2 Long-Term Stability Input Impedance, Differential Common-Mode Input Voltage Range Safe Input Voltage Common-Mode Rejection CMR VS = +5V, VCM = (V) 0.02V to (V+) + 0.1V Over Temperature INPUT BIAS CURRENT Bias Current vs Temperature Offset Current NOISE Voltage Noise, RTI f = 10Hz f = 100Hz f = 1kHz f = 0.01Hz to 10Hz Voltage Noise, RTI f = 10Hz f = 100Hz f = 1kHz f = 0.01Hz to 10Hz Current Noise, RTI f = 1kHz f = 0.01Hz to 10Hz Output Ripple, VO Filtered(2) GAIN Gain Equation Range of Gain Gain Error(3) vs Temperature Nonlinearity OUTPUT Voltage Output Swing from Rail Over Temperature Capacitive Load Drive Short-Circuit Current INTERNAL OSCILLATOR Frequency of Auto-Correction Accuracy FREQUENCY RESPONSE Bandwidth(4), 3dB Slew Rate(4) Settling Time(4), 0.1% 0.01% 0.1% 0.01% Overload Recovery(4) BW G = 1 to 1k SR VS = +5V, All Gains, CL = 100pF tS 1kHz Filter, G = 1 to 1k, VO = 2V step, CL = 100pF 10kHz Filter, G = 1 to 1k, VO = 2V step, CL = 100pF 1kHz Filter, 50% Output Overload, G = 1 to 1k 10kHz Filter, 50% Output Overload, G = 1 to 1k IB IOS VCM = VS /2 VS = +5V VS = +5V RS = 0, G = 100, R1 = 2k, R2 = 100k

20

3 See Note (1) 1010 || 2 1010 || 14

0.1

124 0.4

V V/C
V/V || pF || pF V V dB dB nA nA

(V) 0.02 (V) 0.5 100 94

(V+) + 0.1 (V+) + 0.5 114

0.2 See Typical Characteristics 0.2

2 2

33 33 33 0.8 RS = 0, G = 10, R1 = 20k, R2 = 100k 120 97 97 4 0.15 4.2 See Applications Information G = 2(R2/R1) < 0.1 G = 10, 100, VS = +5V, VO = 0.075V to 4.925V G = 10, 100, VS = +5V, VO = 0.075V to 4.925V G = 10, 100, VS = +5V, VO = 0.075V to 4.925V RL = 100k RL = 10k, VS = +5V 0.08 6 0.004 5 10 500 25 90 20 1 Filter Limited 0.95 1.3 130 160 30 5 > 10000 0.2 25 0.01

nV/ Hz nV/ Hz nV/ Hz Vp-p nV/ Hz nV/ Hz nV/ Hz Vp-p pA/ Hz pAp-p

V/V % ppm/C % of FS mV mV mV pF mA kHz % kHz ms ms s s s s

75 75

ISC

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SBOS222D

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ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V (Cont.)

BOLDFACE limits apply over the specified temperature range, TA = 40C to +85C
INA326EA, INA327EA PARAMETER POWER SUPPLY Specified Voltage Range Quiescent Current Over Temperature CONDITION MIN +2.7 IQ IO = 0, Diff VIN = 0V, VS = +5V 2.4 TYP MAX +5.5 3.4 3.7 0.25 1.6 75 100 2 40 40 65 UNITS V mA mA V V s s A C C C C/W At TA = +25C, RL = 10k, G = 100 (R1 = 2k, R2 = 100k), external gain set resistors, and IACOMMON = VS /2, with external equivalent filter corner of 1kHz, unless otherwise noted.

SHUTDOWN Disable (Logic Low Threshold) Enable (Logic High Threshold) Enable Time(5) Disable Time Shutdown Current and Enable Pin Current TEMPERATURE RANGE Specified Range Operating Range Storage Range Thermal Resistance

VS = +5V, Disabled

5 +85 +125 +150

JA

MSOP-8, MSOP-10 Surface-Mount

150

NOTES: (1) 1000-hour life test at 150C demonstrated randomly distributed variation in the range of measurement limitsapproximately 10V. (2) See Applications Information section, and Figures 1 and 3. (3) Does not include error and TCR of external gain-setting resistors. (4) Dynamic response is limited by filtering. Higher bandwidths can be achieved by adjusting the filter. (5) See Typical Characteristics, Input Offset Voltage vs Warm-Up Time.

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SBOS222D

TYPICAL CHARACTERISTICS
At TA = 25C, VS = +5V, Gain = 100, and RL = 10k with external equivalent filter corner of 1kHz, unless otherwise noted.

GAIN vs FREQUENCY 1kHz FILTER 80 60 G = 1k 40 40 80 60

GAIN vs FREQUENCY 10kHz FILTER

G = 1k

Gain (dB)

Gain (dB)

G = 100 20 G = 10 0 20 40 10 100 1k 10k Frequency (Hz) 100k 1M G=1

G = 100 20 G = 10 0 G=1 20 40 10 100 1k 10k Frequency (Hz) 100k 1M

COMMON- MODE REJECTION vs FREQUENCY 1kHz FILTER 160 G = 1k 140 G = 100 120 120 140 160

COMMON- MODE REJECTION vs FREQUENCY 10kHz FILTER

CMR (dB)

100 G = 10 80 G=1 60 40 20 10 100 1k 10k Frequency (Hz) 100k 1M

CMR (dB)

G = 1k 100 80 G = 100 60 G=1 40 20 10 100 1k 10k Frequency (Hz) 100k 1M G = 10

POWER- SUPPLY REJECTION vs FREQUENCY G = 100, 1k 100 80

PSR (dB)

INPUT- REFERRED VOLTAGE NOISE AND INPUT BIAS CURRENT NOISE vs FREQUENCY 10kHz FILTER

Input-Referred Voltage Noise (nV/Hz)

120 G = 10 G=1

10k Current Noise (all gains) 1k G=1

0.1

60 40 20 0 10 100 1k Frequency (Hz) 10k 100k Filter Frequency 10kHz 1kHz

100 G = 100

G = 10

0.01

G = 1000 10 1 10 100 Frequency (Hz) 1k 10k

0.001

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SBOS222D

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Input Bias Current Noise (pA/Hz)

TYPICAL CHARACTERISTICS (Cont.)

At TA = 25C, VS = +5V, Gain = 100, and RL = 10k with external equivalent filter corner of 1kHz, unless otherwise noted.

INPUT OFFSET VOLTAGE vs TURN- ON TIME 1kHz FILTER, G = 100 Filter Settling Time Device Turn- On Time (75s)

INPUT OFFSET VOLTAGE vs WARM- UP TIME 10kHz FILTER, G = 100

Input Offset Voltage (20V/div)

Input Offset Voltage (20V/div)

Device Turn- On Time

Filter Settling Time

1 Turn- On Time (ms)

0.1 0.2 0.3 Warm- Up Time (ms)

0.4

SMALL- SIGNAL RESPONSE G = 1, 10, AND 100

SMALL- SIGNAL STEP RESPONSE G = 1000

1kHz Filter

1kHz Filter

50mV/div

10kHz Filter

500s/div

50mV/div

500s/div

LARGE- SIGNAL RESPONSE G = 1 TO 1000

0.01Hz TO 10Hz VOLTAGE NOISE

1kHz Filter

10kHz Filter

500s/div

200nV/div

2V/div

10s/div

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SBOS222D

TYPICAL CHARACTERISTICS (Cont.)

At TA = 25C, VS = +5V, Gain = 100, and RL = 10k with external equivalent filter corner of 1kHz, unless otherwise noted.

OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION G=1

OFFSET VOLTAGE PRODUCTION DISTRIBUTION G=1

Population

Population
Offset Voltage Drift (V/C)

OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION G = 10

Population

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 4.0

Population

Offset Voltage Drift (V/C)

OFFSET VOLTAGE DRIFT PRODUCTION DISTRIBUTION G = 100, 1000

Population

Offset Voltage Drift (V/C)

INA326, INA327
SBOS222D

100 90 80 70 60 50 40 30 20 10 0 10 20 30 40 50 60 70 80 90 100 Offset Voltage (V)

0 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 0.20 0.22 0.24 0.26 0.28 0.30 0.32 0.34 0.36 0.38 0.40

Population

1000 900 800 700 600 500 400 300 200 100 0 100 200 300 400 500 600 700 800 900 1000

10,000 9000 8000 7000 6000 5000 4000 3000 2000 1000 0 1000 2000 3000 4000 5000 6000 7000 8000 9000 10,000
Offset Voltage (V)

0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

OFFSET VOLTAGE PRODUCTION DISTRIBUTION G = 10

Offset Voltage (V)

OFFSET VOLTAGE PRODUCTION DISTRIBUTION G = 100, 1000

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TYPICAL CHARACTERISTICS (Cont.)

At TA = 25C, VS = +5V, Gain = 100, and RL = 10k with external equivalent filter corner of 1kHz, unless otherwise noted.

GAIN ERROR PRODUCTION DISTRIBUTION G = 100 100 110 120

VOUT (dBV)

INPUT- REFERRED RIPPLE SPECTRUM G = 100 100.000 31.600 1.000 0.316 0.100 0.030 0.010 0.003 0.001 1M
VOUT (Vrms)

Population

130 140 150 160 170 180

200 180 160 140 120 100 80 60 40 20 0 20 40 60 80 100 120 140 160 180 200

200k

Gain Error (m%)

400k 600k Frequency (Hz)

800k

QUIESCENT CURRENT vs TEMPERATURE 3.0 VS = +5V 2.5 2.0 2.0 1.5 1.0 IB

INPUT BIAS CURRENT vs TEMPERATURE

IQ (mA)

1.5 1.0 0.5 0 50

IB (nA)

VS = +2.7V

0.5 0 0.5 1.0 1.5 IB+

25

50 Temperature (C)

25

75

100

125

2.0 50

25

25 50 Temperature (C)

75

100

125

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SBOS222D

APPLICATIONS INFORMATION
Figure 1 shows the basic connections required for operation of the INA326. A 0.1F capacitor, placed close to and across the power-supply pins is strongly recommended for highest accuracy. RoCo is an output filter that minimizes auto-correction circuitry noise. This output filter may also serve as an antialiasing filter ahead of an Analog-to-Digital (A/D) converter. It is also optional based on desired precision. The output reference terminal is taken at the low side of R2 (IACOMMON). The INA326 uses a unique internal topology to achieve excellent Common-Mode Rejection (CMR). Unlike conventional instrumentation amplifiers, CMR is not affected by resistance in the reference connections or sockets. See Inside the INA326 for further detail. To achieve best high-frequency CMR, minimize capacitance on pins 1 and 8.

SETTING THE GAIN

The INA326 is a 2-stage amplifier with each stage gain set by R1 and R2, respectively (see Figure 5, Inside the INA326, for details). Overall gain is described by the equation:

G=2

R2 R1

(1)

The stability and temperature drift of the external gain-setting resistors will affect gain by an amount that can be directly inferred from the gain equation (1). Resistor values for commonly used gains are shown in Figure 1. Gain-set resistor values for best performance are different for +5V single-supply and for 2.5V dual-supply operation. Optimum value for R1 can be calculated by: R1 = VIN, MAX/12.5A where R1 must be no less than 2k. (2)

DESIRED GAIN 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000 2000 5000 10000

R1 () 400k 400k 400k 200k 100k 40k 20k 10k 4k 2k 2k 2k 2k 2k 2k 2k

R2 || C2 ( || nF) 20k || 40k || 100k || 100k || 100k || 100k || 100k || 100k || 100k || 100k || 200k || 500k || 1M || 2M || 5M || 10M || 5 2.5 1 1 1 1 1 1 1 1 0.5 0.2 0.1 0.05 0.02 0.01 2 1

2.5V +2.5V 0.1F 7 4 INA326 8 3 5 6 RO VO 100 VO Filtered CO(1) 1F G = 2(R2/R1) fO = 1kHz R2 C2(1) IACOMMON(2) (1) C2 and CO combine to form a 2-pole response that is 3dB at 1kHz. Each individual pole is at 1.5kHz. (2) Output voltage is referenced to IACOMMON (see text).

VIN

R1

VIN+

DESIRED GAIN 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000 2000 5000 10000

R1 () 400k 400k 400k 400k 200k 80k 40k 20k 8k 4k 2k 2k 2k 2k 2k 2k

R2 || C2 ( || nF) 20k || 40k || 100k || 200k || 200k || 200k || 200k || 200k || 200k || 200k || 200k || 500k || 1M || 2M || 5M || 10M || 5 2.5 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.2 0.1 0.05 0.02 0.01
VIN R1 8 VIN+ 3 2 1

V+ 0.1F 7 4 INA326 5
(3)

Single-supply operation may require R2 > 100k for full output swing. This may produce higher input referred offset voltage. See Offset Voltage, Drift, and Circuit Values for detail. RO VO 100 VO Filtered CO(1) 1F G = 2(R2/R1) fO = 1kHz C2(1) IACOMMON(2)

R2

(1) C2 and CO combine to form a 2-pole response that is 3dB at 1kHz. Each individual pole is at 1.5kHz. (2) Output voltage is referenced to IACOMMON (see text). (3) Output offset voltage required for measurement near zero (see Figure 28).

NOTES: (1) C2 and CO combine to form a 2-pole response that is 3dB at 1kHz. Each individual pole is at 1.5kHz. (2) Output voltage is referenced to IACOMMON (see text). (3) Output offset voltage required for measurement near zero (see Figure 6).

FIGURE 1. Basic Connections. NOTE: Connections for INA327 differsee Pin Configuration for detail.

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SBOS222D

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Following this design procedure for R1 produces the maximum possible input stage gain for best accuracy and lowest noise. Circuit layout and supply bypassing can affect performance. Minimize the stray capacitance on pins 1 and 8. Use recommended supply bypassing, including a capacitor directly from pin 7 to pin 4 (V+ to V), even with dual (split) power supplies (see Figure 1).

The enable time following shutdown is 75s plus the settling time due to filters (see Typical Characteristics, Input Offset Voltage vs Warm-up Time). Disable time is 100s. This allows the INA327 to be operated as a gated amplifier, or to have its output multiplexed onto a common output bus. When disabled, the output assumes a high-impedance state.

INA327 PIN 5 OFFSET VOLTAGE, DRIFT, AND CIRCUIT VALUES

As with other multi-stage instrumentation amplifiers, inputreferred offset voltage depends on gain and circuit values. The specified offset and drift performance is rated at R1 = 2k, R2 = 100k, and VS = 2.5V. Offset voltage and drift for other circuit values can be estimated from the following equations: VOS = 10V + (50nA)(R2)/G dVOS/dT = 0.12V/C + (0.16nA/C)(R2)/G (3) (4) Pin 5 of the INA327 should be connected to V+ to ensure proper operation.

DYNAMIC PERFORMANCE
The typical characteristic Gain vs Frequency shows that the INA326 has nearly constant bandwidth regardless of gain. This results from the bandwidth limiting from the recommended filters.

These equations might imply that offset and drift can be minimized by making the value of R2 much lower than the values indicated in Figure 1. These values, however, have been chosen to assure that the output current into R2 is kept less than or equal to 25A, while maintaining R1s value greater than or equal to 2k. Some applications with limited output voltage swing or low power-supply voltage may allow lower values for R2, thus providing lower input-referred offset voltage and offset voltage drift. Conversely, single-supply operation with R2 grounded requires that R2 values be made larger to assure that current remains under 25A. This will increase the input-referred offset voltage and offset voltage drift. Circuit conditions that cause more than 25A to flow in R2 will not cause damage, but may produce more nonlinearity.

NOISE PERFORMANCE
Internal auto-correction circuitry eliminates virtually all 1/f noise (noise that increases at low frequency) in gains of 100 or greater. Noise performance is affected by gain-setting resistor values. Follow recommendations in the Setting Gain section for best performance. Total noise is a combination of input stage noise and output stage noise. When referred to the input, the total mid-band noise is:
VN = 33nV / Hz + 800nV / Hz G

(5)

The output noise has some 1/f components that affect performance in gains less than 10. See typical characteristic Input-Referred Voltage Noise vs Frequency. High-frequency noise is created by internal auto-correction circuitry and is highly dependent on the filter characteristics chosen. This may be the dominant source of noise visible when viewing the output on an oscilloscope. Low cutoff frequency filters will provide lowest noise. Figure 3 shows the typical noise performance as a function of cutoff frequency.
1k

INA327 ENABLE FUNCTION

The INA327 adds an enable/shutdown function to the INA326. Its pinout differs from the INA326see the Pin Configuration for detail. The INA327 can be enabled by applying a logic HIGH voltage level to the Enable pin. Conversely, a logic LOW voltage level will disable the amplifier, reducing its supply current from 2.4mA to typically 2A. For battery-operated applications, this feature may be used to greatly reduce the average current and extend battery life. This pin should be connected to a valid high or low voltage or driven, not left open circuit. The Enable pin can be modeled as a CMOS input gate as in Figure 2.

Total Output Noise (VRMS)

G = 1000 100

10

G = 100

V+ 2A Enable 6

G = 10 1 1 G=1 10 100 1k Required Filter Cutoff Frequency (Hz) 10k

FIGURE 3. Total Output Noise vs Required Filter Cutoff Frequency. FIGURE 2. Enable Pin Model.

10

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SBOS222D

Applications sensitive to the spectral characteristics of highfrequency noise may require consideration of the spurious frequencies generated by internal clocking circuitry. Spurs occur at approximately 90kHz and its harmonics (see typical characteristic Input-Referred Ripple Spectrum) which may be reduced by additional filtering below 1kHz. Insufficient filtering at pin 5 can cause nonlinearity with large output voltage swings (very near the supply rails). Noise must be sufficiently filtered at pin 5 so that noise peaks do not hit the rail and change the average value of the signal. Figure 3 shows guidelines for filter cutoff frequency.

Thermocouple

INA326 5

FIGURE 4. Providing Input Bias Current Return Path.

HIGH-FREQUENCY NOISE
C2 and CO form filters to reduce internally generated autocorrection circuitry noise. Filter frequencies can be chosen to optimize the trade-off between noise and frequency response of the application, as shown in Figure 3. The cutoff frequencies of the filters are generally set to the same frequency. Figure 3 shows the typical output noise for four gains as a function of the 3dB cutoff frequency of each filter response. Small signals may exhibit the addition of internally generated auto-correction circuitry noise at the output. This noise, combined with broadband noise, becomes most evident in higher gains with filters of wider bandwidth.

INPUT PROTECTION
The inputs of the INA326 are protected with internal diodes connected to the power-supply rails. These diodes will clamp the applied signal to prevent it from damaging the input circuitry. If the input signal voltage can exceed the power supplies by more than 0.5V, the input signal current should be limited to less than 10mA to protect the internal clamp diodes. This can generally be done with a series input resistor. Some signal sources are inherently current-limited and do not require limiting resistors.

FILTERING INPUT BIAS CURRENT RETURN PATH

The input impedance of the INA326 is extremely high approximately 1010. However, a path must be provided for the input bias current of both inputs. This input bias current is approximately 0.2nA. High input impedance means that this input bias current changes very little with varying input voltage. Input circuitry must provide a path for this input bias current for proper operation. Figure 4 shows provision for an input bias current path in a thermocouple application. Without a bias current path, the inputs will float to an undefined potential and the output voltage may not be valid. Filtering can be adjusted through selection of R2C2 and ROCO for the desired trade-off of noise and bandwidth. Adjustment of these components will result in more or less ripple due to auto-correction circuitry noise and will also affect broadband noise. Filtering limits slew rate, settling time, and output overload recovery time. It is generally desirable to keep the resistance of RO relatively low to avoid DC gain error created by the subsequent stage loading. This may result in relatively high values for CO to produce the desired filter response. The impedance of ROCO can be scaled higher to produce smaller capacitor values if the load impedance is very high. Certain capacitor types greater than 0.1F may have dielectric absorption effects that can significantly increase settling time in high-accuracy applications (settling to 0.01%). Polypropylene, polystyrene, and polycarbonate types are generally good. Certain high-K ceramic types may produce slow settling tails. Settling time to 0.1% is not generally affected by high-K ceramic capacitors. Electrolytic types are not recommended for C2 and CO.

INPUT COMMON-MODE RANGE

Common instrumentation amplifiers do not respond linearly with common-mode signals near the power-supply rails, even if railto-rail op amps are used. The INA326 uses a unique topology to achieve true rail-to-rail input behavior (see Figure 5, Inside the INA326). The linear input voltage range of each input terminal extends to 20mV below the negative rail, and 100mV above the positive rail.

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INSIDE THE INA326

The INA326 uses a new, unique internal circuit topology that provides true rail-to-rail input. Unlike other instrumentation amplifiers, it can linearly process inputs up to 20mV below the negative power-supply rail, and 100mV above the positive power-supply rail. Conventional instrumentation amplifier circuits cannot deliver such performance, even if rail-to-rail op amps are used. The ability to reject common-mode signals is derived in most instrumentation amplifiers through a combination of amplifier CMR and accurately matched resistor ratios. The INA326 converts the input voltage to a current. Current-mode signal processing provides rejection of common-mode input voltage and power-supply variation without accurately matched resistors. A simplified diagram shows the basic circuit function. The differential input voltage, (VIN+) (VIN) is applied across R1. The signal-generated current through R1 comes from
V+

A1 and A2s output stages. A2 combines the current in R1 with a mirrored replica of the current from A1. The resulting current in A2s output and associated current mirror is two times the current in R1. This current flows in (or out) of pin 5 into R2. The resulting gain equation is:
G=2 R2 R1

Amplifiers A1, A2, and their associated mirrors are powered from internal charge-pumps that provide voltage supplies that are beyond the positive and negative supply rails. As a result, the voltage developed on R2 can actually swing 20mV below the negative power-supply rail, and 100mV above the positive supply rail. A3 provides a buffered output of the voltage on R2. A3s input stage is also operated from the charge-pumped power supplies for true rail-to-rail operation.
0.1F V

7 Current Mirror

INA326 2 VIN 1 A1 IR1 IR1

Current Mirror IR1 R1 IR1 Current Mirror

8 VIN+ 3 A2

2IR1

2IR1 6 VO

2IR1 Current Mirror

2IR1 2IR1

A3

5 R2 C2 IACOMMON

FIGURE 5. Simplified Circuit Diagram.

12

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SBOS222D

APPLICATION CIRCUITS
2 1 R1 8 3 R2 INA326 5 R0 6 VREF C0 VO

R2 and R2 are chosen to R2 C2 create a small output offset voltage (e.g., 100mV). Gain is determined by G = 2 (R2 || R2)/R1 the parallel combination of R2 and R2.

FIGURE 6. Generating Output Offset Voltage.

VREF

2 1 2k 8 3 INA326 5 6

RO 100 CO 1F 200k

A/D Converter

G = 2(200k || 200k)/2k = 100

200k

C2

FIGURE 7. Output Referenced to VREF/2.

+5V

RS IL 2k R1 8 3 NOTE: Connection point of V+ will include ( ) or exclude ( ) quiescent current in the measurement as desired. Output offset required for measurements near zero (see Figure 6). R2 2 1 INA326 7

RS must be chosen so that the input voltage does not exceed 100mV beyond the rail.

6 5

RO 100 VO CO 1F C2 R2 R1

RL

VO = 2(IL RS)

FIGURE 8. High-Side Current Shunt Measurement.

INA326, INA327
SBOS222D

www.ti.com

13

+5V 2 1 R1 8 3 2k R2 INA326 7 6 5 C2 RO 100 VO CO 1F VO = 2(IL RS) R2 R1

RL

IL RS

RS must be chosen so that the input voltage does not exceed 20mV beyond the rail.

NOTE: Connection point of V will include ( ) or exclude ( ) quiescent current in the measurement as desired. Output offset required for measurements near zero (see Figure 6).

FIGURE 9. Low-Side Current Shunt Measurement.

1nF RF = 100k NOTE: 0.2% accuracy. Current shunt monitor circuit can be designed for 250V supply with appropriate selection of high- voltage FET. +5V 2 3 RSTART 100k ZVN4525G (zetex) RL IL + VS = 0mV to 50mV max 48V RS RI = 2k 2 1 8 3 VCC (High- Voltage n- Channel 7 FET) 6 5 0.1F ZMM5231BDICT 5.1V 7 OPA336PA 4 6 VO = 2(IL RS) RPULL- DOWN 200k RF RI

8.45k

INA326 GND 4

FIGURE 10. Low-Side 48V Current Shunt Monitor.

+48V + 3 VSHUNT = 0mV to 50mV Load RSHUNT RI 2k 8 1 2 7 VCC INA326 GND 4 5 6 ZVP4525 (zetex) (High- Voltage p- Channel FET) 3 2 1nF 0.1F ZMM5231BDICT 5.1V

+5V 7 OPA336PA 4 49.9k 6

8.45k

VO = 0.1V to 4.9V

75k

165k

FIGURE 11. High-Side +48V Current Shunt Monitor.

14

INA326, INA327
www.ti.com
SBOS222D

2 + VIN 2k 8 3 1nF 100k 1 INA326 5 6 VO = VIN (100) + VDAC

+5V 2
VDAC = 0.075V to 4.925V DAC

7 INA326 6 5 4 3
(2)

1 VD R1 8 3 VCM

+15V NC(1) 2 7 OPA277 4 15V 6 VO

FIGURE 12. Output Offset Adjustment.

+1.8V to +5V

R2
Logic +5V

C2

2 1 R1 10 3

9 6 Enable 8 7 4 1nF R2(1)

NOTES: (1) NC denotes No Connection. (2) Typical swing capability 20mV to (+5V + 100mV).

INA327

FIGURE 14. Output from Pin 5 to Allow Swing Beyond the Rail.
+5V

2 1 R3 10 3

9 6 Enable 8 7 4 1nF R4
(1)

INA327

VO

0V < VDAC < +5V DAC R1 200k 2 1

+5V ((+VREF) (VDAC)) R1 50nA

7 INA326 6 5 4 CF

IOUT =

+5V

8 3

VREF = +2.5V
2 1 R5 10 3 4 1nF NOTE: (1) R2, R4, and R6 could be a single, shared resistor to save board space. R6(1) INA327 9 6 Enable 8 7

RF = 10k

NOTE: Output resistance is typically 800M. Resolution < 5nA. Recommended values of CF = 1nF to 1F.

FIGURE 13. Multiplexed Output.

FIGURE 15. Programmable 25A Current Source with High Output Resistance.

INA326, INA327
SBOS222D

www.ti.com

15

VREF = +2.5V

+2.5V

DAC RI = 200k

2 1

7 INA326 6 5 4 2.5V 10k 49.9

8 3

IOUT = 2

VREF VDAC 200k

1+

10k 49.9

IO 0.1F RL

IO = 5mA with 0.1A stability.

FIGURE 16. Programmable 5mA Current Source.

RI = 1k VI

RF = 100k +30V

20k

2 3 IB

7 OPA551 4 6 VO = 27V VOS = 100V at 200mA G= RF RI = 100V/V

+5V

2 1 2k 8 3

7 INA326 5 4 6

30V

20k

Offset of the high- voltage op amp is controlled by the INA326. Internal charge pump in the INA326 allows 1M this node to swing 20mV below ground without a negative supply.

10nF

NOTES: (1) The OPA551 is a 60V op amp. (2) The INA326 does not require a negative supply to correct for negative VOS values from the high-voltage op amp. (3) Voltage offset contribution of IB (OPA551) is 100pA 2k = 0.2V.

FIGURE 17. 27V Output at 200mA Amplifier with 100V Offset.

16

INA326, INA327
www.ti.com
SBOS222D

+5V Input VS + C4 10 F Common Error Amplifier R13 20 R10 1k VS + 4 R15 200 VS V+ V 0.1F VS IN+ 3 8 4 INA326 1 2 R8 100k C5 1nF R19 100k VBIAS VBIAS 1/4 OPA4340 VS 5 C7 22nF 6 VO R9 2k IN 1/4 OPA4340 R14 10k 7 R16 Loop Gain 2k Adjust POT VBIAS C3 1nF R18 10k R17 5k POT REF1004- 2.5 D1 RINT 10M CINT 1F C6 10F 8 Integrator TC: 1s to 10s

INA326, INA327
V+ 1/4 OPA4340 V Summing Amplifier VBIAS Proportional R1 100k R21 10k 1/2 OPA2340 C8 0.1F R25 10k R23 10k C1 1nF CDIFF 1F V+ 1/2 OPA2340 V C2 470nF VBIAS R20 5k POT R2 100k 1/4 OPA4340 Differentiator TC: 100ms to 1s RDIFF 1M R22 10k VBIAS Bias Generator R5 20k R4 20k VBIAS

FIGURE 18. Single-Supply PID Temperature Control Loop.

SBOS222D

R12 15k

R11 14.3k

RTHERM 10k

www.ti.com

R7 1k POT

Set Temp

R6 9.53k

Gain = 100V/V

Output to TEC Driver Common

17

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

PACKAGING INFORMATION
Orderable Device INA326EA/250 INA326EA/250G4 INA326EA/2K5 INA326EA/2K5G4 INA327EA/250 INA327EA/250G4 INA327EA/2K5 INA327EA/2K5G4 Status
(1)

Package Type Package Pins Package Drawing Qty VSSOP VSSOP VSSOP VSSOP VSSOP VSSOP VSSOP VSSOP DGK DGK DGK DGK DGS DGS DGS DGS 8 8 8 8 10 10 10 10 250 250 2500 2500 250 250 2500 2500

Eco Plan
(2)

Lead/Ball Finish

MSL Peak Temp

(3)

Op Temp (C) -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 B26 B26 B26 B26 B27 B27 B27 B27

Top-Side Markings
(4)

Samples

ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE

Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br) Green (RoHS CU NIPDAUAG Level-2-260C-1 YEAR & no Sb/Br)

(1)

The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

11-Apr-2013

(4)

Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins Type Drawing VSSOP VSSOP VSSOP VSSOP DGK DGK DGS DGS 8 8 10 10

SPQ

Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 330.0 180.0 330.0 12.4 12.4 12.4 12.4 5.3 5.3 5.3 5.3

B0 (mm) 3.4 3.4 3.4 3.4

K0 (mm) 1.4 1.4 1.4 1.4

P1 (mm) 8.0 8.0 8.0 8.0

W Pin1 (mm) Quadrant 12.0 12.0 12.0 12.0 Q1 Q1 Q1 Q1

INA326EA/250 INA326EA/2K5 INA327EA/250 INA327EA/2K5

250 2500 250 2500

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Jan-2013

*All dimensions are nominal

Device INA326EA/250 INA326EA/2K5 INA327EA/250 INA327EA/2K5

Package Type VSSOP VSSOP VSSOP VSSOP

Package Drawing DGK DGK DGS DGS

Pins 8 8 10 10

SPQ 250 2500 250 2500

Length (mm) 366.0 366.0 210.0 367.0

Width (mm) 364.0 364.0 185.0 367.0

Height (mm) 50.0 50.0 35.0 35.0

Pack Materials-Page 2

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