CD4528BC Dual Monostable Multivibrator

October 1987 Revised August 2000

CD4528BC Dual Monostable Multivibrator

General Description
The CD4528B is a dual monostable multivibrator. Each device is retriggerable and resettable. Triggering can occur from either the rising or falling edge of an input pulse, resulting in an output pulse over a wide range of widths. Pulse duration and accuracy are determined by external timing components Rx and Cx.

Features
I Wide supply voltage range: I Separate reset available I Quiescent current = 5.0 nA/package (typ.) at 5.0 VDC I Diode protection on all inputs I Triggerable from leading or trailing edge pulse I Capable of driving two low-power TTL loads or one lowpower Schottky TTL load over the rated temperature range 3.0V to 18V

Ordering Code:
Order Number CD4528BCM CD4528BCN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code.

Connection Diagram

Truth Table
Inputs Clear L X X H H A X H X L B X X L Q L L Outputs Q H H

Top View

H = HIGH Level L = LOW Level = Transition from LOW-to-HIGH = Transition from HIGH-to-LOW = One HIGH Level Pulse = One LOW Level Pulse X = Irrelevant

2000 Fairchild Semiconductor Corporation

DS005998

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Block Diagram

Logic Diagram
( of Device Shown)

Note: Externally ground pins 1 and 15 to pin 8.

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Absolute Maximum Ratings(Note 1)

(Note 2) DC Supply Voltage (VDD) Input Voltage, All Inputs (VIN) Storage Temperature Range (TS) Power Dissipation (PD) Dual-In-Line Small Outline Lead Temperature (TL) (Soldering, 10 seconds) 260C (Note 3) 700 mW 500 mW

Recommended Operating Conditions (Note 2)

DC Supply Voltage (VDD) Input Voltage (VIN) Operating Temperature Range (TA) 3V to 15V 0V to VDD VDC

0.5 VDC to +18 VDC 0.5 VDC to VDD +0.5 VDC 65C to +150C

40C to +85C

Note 1: Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed. Except for Operating Temperature Range, they are not meant to imply that the devices should be operated at these limits. The table of Electrical Characteristics provides conditions for actual device operation. Note 2: VSS = 0V unless otherwise specified.

DC Electrical Characteristics
Symbol IDD Parameter Quiescent Device Current VDD = 5V VDD = 10V VDD = 15V VOL LOW Level Output Voltage VDD = 5V VDD = 10V VDD = 15V VOH HIGH Level Output Voltage VDD = 5V VDD = 10V VDD = 15V VIL LOW Level Input Voltage

Conditions

40C Min Max 20 40 80 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.52 1.3 3.6 0.2 0.5 1.4 0.3 0.3 3.5 7.0 11.0 0.44 1.1 3.0 0.16 0.4 1.2 4.95 9.95 14.95 Min

+25C Typ 0.005 0.010 0.015 Max 20 40 80 0.05 0.05 0.05 5.0 10.0 15.0 2.25 4.50 6.75 2.75 5.50 8.25 0.88 2.25 8.8 0.36 0.9 3.5 105 105 0.3 0.3 1.5 3.0 4.0

+85C Min Max 150 300 600 0.05 0.05 0.05 4.95 9.95 14.95 1.5 3.0 4.0 3.5 7.0 11.0 0.36 0.9 2.4 0.12 0.3 1.0 1.0 1.0

Units A A A V V V V V V V V V V V V mA mA mA mA mA mA A A

VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V

VIH

HIGH Level Input Voltage

VDD = 5V, VO = 0.5V or 4.5V VDD = 10V, VO = 1V or 9V VDD = 15V, VO = 1.5V or 13.5V

IOL

LOW Level Output Current (Note 4)

VDD = 5V, VO = 0.4V VDD = 10V, VO = 0.5V VDD = 15V, VO = 1.5V VDD = 5V, VO = 4.6V VDD = 10V, VO = 9.5V VDD = 15V, VO = 13.5V VDD = 15V, VIN = 0V VDD = 15V, VIN = 15V

IOH

HIGH Level Output Current (Note 4)

IIN

Input Current

Note 3: VSS = 0V unless otherwise specified. Note 4: IOH and IOL are tested one output at a time.

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AC Electrical Characteristics (Note 5)

TA = 25C, CL = 50 pF, RL = 200 k, Input tr = tf = 20 ns, unless otherwise specified Symbol tr Parameter Output Rise Time Conditions tr = (3.0 ns/pF) CL + 30 ns, VDD = 5.0V tr = (1.5 ns/pF) CL + 15 ns, VDD = 10.0V tr = (1.1 ns/pF) CL + 10 ns, VDD = 15.0V tf Output Fall Time tf = (1.5 ns/pF) CL + 25 ns, VDD = 5.0V tf = (0.75 ns/pF) CL + 12.5 ns, VDD = 10V tf = (0.55 ns/pF) CL + 9.5 ns, VDD = 15.0V tPLH tPHL Turn-Off, Turn-On Delay A or B to Q or Q Cx = 15 pF, Rx = 5.0 k Turn-Off, Turn-On Delay A or B to Q or Q Cx = 100 pF, Rx = 10 k tWL tWH Minimum Input Pulse Width A or B Cx = 15 pF, Rx = 5.0 k Cx = 1000 pF, Rx = 10 k tPLH, tPHL = (1.7 ns/pF) CL + 240 ns, VDD = 5.0V tPLH, tPHL = (0.66 ns/pF) CL + 8 ns, VDD = 10.0V tPLH, tPHL = (0.5 ns/pF) CL + 65 ns, VDD = 15.0V tPLH, tPHL = (1.7 ns/pF) CL + 620 ns, VDD = 5.0V tPLH, tPHL = (0.66 ns/pF) CL + 257 ns, VDD = 10.0V tPLH, tPHL = (0.5 ns/pF) CL + 185 ns, VDD = 15.0V VDD = 5.0V VDD = 10.0V VDD = 15V VDD = 5.0V VDD = 10.0V VDD = 15.0V PWOUT Output Pulse Width Q or Q For Cx < 0.01 F (See Graph for Appropriate VDD Level) Cx = 15 pF, Rx = 5.0 k For Cx > 0.01 F Use PWout = 0.2 Rx Cx In [VDD VSS] Cx = 10,000 pF, Rx = 10 k tPLH tPHL Reset Propagation Delay, tPLH, tPHL Cx = 15 pF, Rx = 5.0 k Cx = 1000 pF, Rx = 10 k VDD = 5.0V VDD = 10.0V VDD = 15.0V VDD = 5.0V VDD = 10.0V VDD = 15.0V VDD = 5.0V VDD = 10.0V VDD = 15.0V VDD = 5.0V VDD = 10.0V VDD = 15.0V tRR Minimum Retrigger Time Cx = 15 pF, Rx = 5.0 k Cx = 1000 pF, Rx = 10 k VDD = 5.0V VDD = 10.0V VDD = 15.0V VDD = 5.0V VDD = 10.0V VDD = 15.0V Pulse Width Match between Circuits in the Same Package Cx = 10,000 pF, Rx = 10 k VDD = 5.0V VDD = 10.0V VDD = 15.0V 15 10 15 Min Typ 180 90 65 100 50 35 230 100 65 230 100 65 60 20 20 60 20 20 550 350 300 29 37 42 325 90 60 7.0 6.7 6.7 0 0 0 0 0 0 6 8 8 25 35 35 45 90 95 600 225 170 Max 400 200 160 200 100 80 500 250 150 500 250 150 150 50 50 150 50 50 Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s s s ns ns ns s s s ns ns ns ns ns ns % % %

Note 5: AC parameters are guaranteed by DC correlated testing.

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Pulse Widths

FIGURE 1. Pulse Width vs Cx

FIGURE 2. Normalized Pulse Width vs Temperature

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AC Test Circuits and Waveforms

Duty Cycle = 50%

FIGURE 3. Power Dissipation Test Circuit and Waveforms

*Includes capacitance of probes, wiring, and fixture parasitic. Note: AC test waveforms for PG1, PG2, and PG3 in Figure 4.

Input Connections Characteristics tPLH, tPHL, tr, tf, PWout, PWin tPLH, tPHL, tr, tf, PWout, PWin tPLH(R), tPHL(R), PWin PG3 PG1 PG2 VDD VSS PG2 CD VDD A PG1 B VDD

FIGURE 4. AC Test Circuit

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AC Test Circuits and Waveforms

(Continued)

FIGURE 5. AC Test Waveforms

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Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

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CD4528BC Dual Monostable Multivibrator

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILDS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 9 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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