EC1610 Advanced Digital Design.

Spring 2014

Assignment 2. Due 12/3/14.

Please bring your code to lab and demonstrate your design on the board and also turn in a printed write-up containing your code and a small description of your design. In Verilog you can compose a module that consists of other modules. This is called a structural description. For example you can build a 4-input mux using three 2input mux modules as follows: module mux_4b ( input select0, input select1, input [3:0]data_in, output mux_out ); // instantiate first mux_2b wire i1_out; mux_2b i1( .select (select0), .data0 (data_in[0]) , .data1 (data_in[1]), .mux_out (i1_out) ); // instantiate second mux_2b wire i2_out; mux_2b i2( .select (select0), .data0 (data_in[2]) , .data1 (data_in[3]), .mux_out (i2_out) ); // instantiate third mux_2b mux_2b i3( .select (select1), .data0 (i1_out) , .data1 (i2_out), .mux_out (mux_out) ); endmodule

This will create the following circuit: 1

EC1610 Advanced Digital Design. Spring 2014

Assignment 2. Due 12/3/14.

select0 data_in[0] i1 data_in[1] i3 mux_out i1_out select1

select0 data_in[2] i2 data_in[3] i2_out

For this assignment you will design the following tap_counter module that counts up each time BTN0 is pressed and displays the count on the seven segment display. tap_counter

btn0 B18 clk B8 reset H13

debouncer

incr

counter_4b

bin_to_sseg

an0 ca cb cg

count[3:0] For use by testbench

tap_counter is the top module of this design and consists debouncer, counter_4b and bin_to_sseg. For this assignment you will do the following: Write counter_4b Use debouncer module provided at the end 2

EC1610 Advanced Digital Design. Spring 2014 Write tap_counter re-use bin_to_sseg from assignment 1 write testbench to verify your design

Assignment 2. Due 12/3/14.

Input btn0 is connected using FPGA pin B18 to BTN0 on the board. Input reset is connected using FPGA pin H13 to BTN3 on the board. Input clk is connected using FPGA pin B8 to the 50MHz clock on the board. Outputs an0, ca, cb, cc, cd, ce, cf and cg connect to the seven segment display on the board the same way as in assignment 1. The debouncer module will detect BTN0 press and generate the incr signal to the counter_4b module. When BTN0 is pressed input btn0 is high and when BTN0 is released the input btn0 is low. The counter_4b module is a 4-bit counter that resets back to 0 if reset is high otherwise counts up by one when incr signal is high. The 4-bit count output of the counter_4b signal is connected to the sw3, sw2, sw1 and sw0 inputs of the bin_to_sseg module. Perform the following steps: 1. Create counter_4b.v file and write the counter_4b module in it. 2. Create debouncer.v file and write in it the code provided below for the debouncer module. 3. Add bin_to_sseg.v from assignment 1 to this project. 4. Create tap_counter.v file and write in it the tap_counter module that connects the debouncer, counter_4b and bin_to_sseg modules. 5. Write the pins.ucf file. 6. Write a testbench module for your design that verifies that the tap_counter counts up by only one for each button press and that count resets to zero if reset is high. Note that the count[3:0] is an output of tap_counter so that it can be used in the testbench. Use the following code for the debouncer (put in debouncer.v file): module debouncer ( input reset, input clk, input btn0, output reg incr );

EC1610 Advanced Digital Design. Spring 2014

Assignment 2. Due 12/3/14.

// flip flop chain for detecting button pressed reg dff0; reg dff1; reg dff2; reg dff3; always @(posedge reset or posedge clk) begin if (reset) begin incr = 0; dff3 = 0; dff2 = 0; dff1 = 0; dff0 = 0; end else begin // assignment order is important below incr = dff2 & ~dff3; dff3 = dff2; dff2 = dff1; dff1 = dff0; dff0 = btn0; end end endmodule