Feedforward Operational Amplifier

High Speed, High Gain Operational Amplifier Research
Basem Soufi Iowa State University basem@iastate.edu
1/7/2005
Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005
Research Interest
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Next Stage
SUBADC
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The Classical Pipeline Stage has many different performance limitations. Amplifier Design is the main challenge when designing for low power, low voltage, high speed and resolution
Amplifier Settling Time (Bandwidth) Amplifier Settling Accuracy (Gain) Slew Rate
Performance Limitations
My personal research specific interest at Iowa State University
Capacitor Mismatch Offset
Basem Soufi Copy Right (c)
Feed forward Architecture to Bypass Parasitic Poles !ast "pdate #$%&%'$$&
(he Opamp Pro)lem

The operational amplifier problem is a very matured analog problem. Researching the literature found no architecture can solve all the problems at once. !ey amplifier characteristics are to have high high" " gain high" high"bandwidth high GBW/Power ratio high output signal swing and fast settling step response.
Bad Assumption in *ultistage Opamp +esign

#hen designing multi" multi"stage amplifiers most authors even with feed" feed"forward architectures assume that the internal parasitic poles are located at a very high speed and can be ignored for design purposes. This is a very bad assumption when you need to build amplifiers with operational fre$uencies near those ignored poles.
Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005 5
Fre,uency Segregation Structure - Intuiti.e Idea +e.elopment

% By passing internal parasitic poles of earlier stages that are not needed at high fre,uencies. &' has the highest () gain and lowest power consumption &* has the highest speed and most of the power consumption +B and Slew"Rate are mostly determent by &*,that-s good news. /012 of power in &*.3 If &* is simple )S amp then +B#567#8R is of single stage and 9rail" to"rail: output swing. 6
In phase signals %
Smaller feature si4e is actually good for this architecture /Better +B#56ower ratio3 while maintaining high () gain and going well )eyond the speed of internal parasitic poles
(wo(wo -Stage implementation and modeling without parasitics

In phase /;<6 =ero3 /ircuit Issues0 1#2 '3 6ositive feedbac> through Cf ?3 @egative capacitance at the input *3 6ole"=ero doublet /process variations3 Sol.ing issues #3'0 &dd a buffer. This will consume power. Several design strategies and circuit techni$ues can be used. #ill use Ideal Buffers for now.
7pen ;oop poles and 4ero /ignoring RsAIdeal Buffer &dded3C GB A Cf/(C' B Cf)*gm?5CII Z A gm'5Cf P' A go'5CI (CI=C1+Cf) P? A go?5CII (CII=C2+CL) Basem Soufi -Feedforward Operational 4ant P'56
Amplifier- ISU Copyright (c) 2003-2005
Open !oop *odel Fre,uency Response
First Order Overall Frequency Response with perfect zero-pole cancellation
Pole-Zero cancellation
90 Degrees Flat Phase Response
Two stage model ac simulation when no parasitics poles are included. Used ideal vccs resistors caps and a buffer to simulate the model.
*odel Step Response
Two Stage model simulation when no parasitics poles included. Used ideal vccs resistors caps feedbac> networ> and a buffer to simulate the model.
(uning the PolePole-6ero *ismatch with process .ariations /ase with no parasitic poles
"DE phase shift occurs at the pole. BDE phase shift occurs at the 4ero. Idea7
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(etect the respective fre$uencies of the phase shifts of the 4ero and pole and tune one of them to overlap the other. The principle of pole"4ero mismatch correction is 8O( new. 1'2
#hen we have the closed loop poles widely separated then the best settling time is achieved when we have '112 pole"4ero cancellation. For widely separated poles the maGimum allowable overlap mismatch that results in a system that settles at least as fast as one without a mismatch is in the order of the settling accuracy re$uirement. So for 1.11'2 settling accuracy we need 1.11'2 tuning accuracy 192 this fact ma>es tuning very difficult if one desires very fast settling Basem Soufi -Feedforward Operational re$uirement.
Amplifier- ISU Copyright (c) 2003-2005 10
/losed-loop dominant pole mo.ement with different feed)ac: /losedfactors when perfect ;ero;ero-pole cancellation occurs *odel simulation with no parasitic pole in the first stage
Accurate second stage pole and zero cancellation
Dominant pole movement
Feedback factor = 1 Feedback factor = 0
(ominant pole rolls to higher fre$uencies as the feedbac> factor increases identical to a first"order closed loop response. This occurs with accurate pole"4ero cancellation.
Ideal two stage model with no parasitics in the first stage Poles mo.ement with different feed)ac: factors when the ;ero is faster than the second stage pole
Second Stage Dominant Pole Zooming in
Z First Stage Dominant Pole
First stage and second stage pole come together and form a comple< con=ugate pair at low feed)ac: factor .alues >close to #%>second stage open loop gain??, then, the pole of the second stage come )ac: close to the ;ero and the first stage tra.els to higher fre,uencies
Ideal two stage model with no parasitics Poles mo.ement with different feed)ac: factors when the ;ero is slower than the second stage pole
Zooming in
Second Stage Dominant Pole
Z First Stage Dominant Pole
First stage pole come closer to the ;ero and gets partially cancelled and forms a dipole 4hile the second stage tra.els to higher fre,uencies
So, what does this tell us@ The relative position of the 4ero in respect to open loop poles has drastic effects on the behavior of the closed loop poles. It is an interesting case" case"study to see how fast the system settles relative to a two" two"pole system and how sensitive to process variations the system is when we have small closed loop factor or more specifically when we have compleG conHugate pair and a 4ero.
14
Studying the circuit with parasitic poles in the first stage
15
*odeling the two stage amplifier with a parasitic pole in the first stage
Feed-Forward Cap
Ideal Buffer
Cascode First Stage Model
Second Stage Model Vout
Vin
(eriving the transfer function Iout5Iin we see a three pole two 4ero system. If there are more parasitic capacitances in the first stage getting by"passed by the capacitor then an additional 4ero will appear. The case of one parasitic pole in the first stage is chosen to simplify the analysis.
Some simulations to pro.e the concept of )y)ypassing parasitic poles
7verall Stage +ain First Stage +ain
Second Stage +ain Second Stage 6hase
4ithout Feedforward ByPass Path
First Stage 6hase
A nasty Parasitic pole
17
Parasitic Pole ByBy-Passed7
8ear First Order (ransfer /ur.e
4ith FeedForward ByPass Path
(he main 6ero-Pole cancellation
18
*o.ement of the poles in the closed loop configuration when the model has a parasitic pole in the first stage
In all the following figures +reen is the dominant pole of the first stage red is the dominant pole of the second stage and blue is the parasitic pole of the first stage. #e can see the additional 4ero in the transfer function due to by"passing the parasitic pole. #e can also observe that the parasitic pole always travels to much higher fre$uencies.
#hen the dominant =ero is after the pole of the second stage.
#hen the dominant =ero is before second stage pole.

#hen the dominant =ero accurately cancels the second stage pole.
19
(uning Facts
Tuning poles and 4eros in FF opamps is 8O( new J?K. #hen having a parasitic pole the pole location of the second stage and the dominant 4ero are not located at "DE and BDE phase shifts respectively as the case when we had an ideal first order first stage amplifier. This ma>es the tuning the amplifier in the open loop phase domain harder if not impossible. <owever sweeping the FF capacitor in simulation over a certain range will guarantee a pole 4ero cancellation. Such tuning is illustrated neGt. #hen changing the FF capacitor will also change the +B of the amplifier however fine tuning change in the feedforward capacitor changes the +B negligibly.
20
10
Simulation to pro.e the tuning concept )y linear sweeping of the FF capacitor

E11fF L11fF
Feedbac> factor is 1.E
E11fF 'pF (his is a three pole, two ;ero system
6ero mo.ement with FF capacitance sweeping, and fine tuning the dominant ;ero location )y sweeping a .aractor at the parasitic node will )e shown ne<t
6eros mo.ement with FF capacitor sweeping
(ominant 4ero movement.
@on"(ominant 4ero movement.
22
11
Fine tuning the dominant ;ero )y sweeping a .aractor added at the parasitic node
Fine tuning the dominant 4ero by sweeping a varactor at the parasitic node.
;arge sensitivity of @on" (ominant 4ero M its movement while incrementing the parasitic capacitance
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(uning Ideas
#e can have a spectrum based tuning. Since it is a differential circuit the amplifier can be configured in a closed loop S) amplifier. The third" third "order harmonic distortion can be detected and the capacitor can be swept to minimi4e it. In &() design calibration algorithms can be used to tune the amplifier for less integral non" non" linearity. Since in two stage &mplifier there is only one 4ero" 4ero"pole cancellation ta>ing place the search algorithm for the optimal tune can be done with small compleGity.
12
Sol.ing the Positi.e Feed)ac:

&dding a buffer in the forward path to bloc> the positive feedbac> will compromise the performance of the operational amplifier. )reating a negative feedbac> to cancel the positive feedbac> should in principle mitigate the positive feedbac> effect. Matching between the canceling paths becomes an issue
Sol.ing the Positi.e Feed)ac:Feed)ac:continue

6assive 6aths provide bidirectional connectivity. @o power consumption by the path. @o speed5power tradeoff.
Buffered forward path adds a pole to the system with speed limitation and added power consumption. <owever the positive feedbac> is solved.
"'
)ancellation of the positive feedbac> with a negative feedbac> eliminates the pole in the feedforward path and provides a much more attractive speed5power tradeoff.
13
Final /ircuit Schematic
The final circuit contains a feedforward path whose positive feedbac> path is cancelled with a buffered negative feedbac>. The canceling feedbac> paths should match well. This means the buffer should be as close to "' as possible while having the capacitors matched as well. Since the opamp &' already has a finite input capacitance there is a room for mismatch in the cancellation method The bandwidths of the buffer of the canceling negative feedbac> needs not to be any larger than the bandwidth of &'.
27
/omparison - #
The circuit in JEK provides and to a certain degree pole" pole "4ero trac>ing with process variations. <owever the feedforward path consumes a lot of power for a certain bandwidth as the designer in JEK saysC 9The 9 main restriction here is that the nondominant pole of the feedforward and second stage must be placed after the overall unity"gain bandwidth of the amplifier in order to minimi4e phase degradation.: The feedforward path of JEK consumes L'2 of total power...
28
14
/omparison/omparison -'
The circuits presented in JDK and JEK reduce the output impedance of amplifier ma>ing it very difficult to maintain the () characteristic of the amplifier. To re" re"iterate the active feedforward scheme consumes a lot of power degrades the phase and reduces the output impedance.
29
/omparison/omparison -9
The presented circuit provides <igh +ain <igh Bandwidth without sacrificing much power in the feedforward bandwidth. If step response is very critical pole" pole"4ero calibration should ta>e place. If the amplifier is used in pipeline &() tuning can be done via detecting the lowest linearity errors of the outputs during the calibration process. & hybrid between this FF techni$ue and the regular miller compensation can be developed to provide a highest possible efficiency for an operational amplifier.
15
+esign A<ample for /apaciti.e (wo stage Feedforward Amplifier

/ascode /ascade e<ample in (S*/ /*OS $ #BCm0 B BGH;, D&dB, ED&mA, BDP*, &$$fF on each end
31
Openloop performance of the first stage separately

(otal open loop phase shift due to first stage /ascode when the parasitic )y-pass is not employed
32
16
References
J'K 9# ' F mi<ed analog%digital circuits using $ 9 Cm /*OS !SI technologyG Matsuura T.N Oano !.N <ira>i M.N Sasa>i O.N Miyamoto M.N Ishii T.N @agai R.N @ishida T.N Se>i !.N Imai4umi 8.N &nbo T.N Sumi @.N Ri>ino !.N Solid" Solid"State )ircuits )onference '00D. (igest of Technical 6apers. D'st ISS)). '00D I888 International 'P" 'P"'Q Feb. '00D 6age/s3C?E1 " ?E' J?K 9(echni,ue to eliminate slowslow-settling components that appear due to dipolesG Schlarmann M.8.N +eiger R.;.N )ircuits and Systems ?11'. M#S)&S ?11'. 6roceedings of the DDth I888 ?11' Midwest Symposium on Iolume ' 'D 'D" "'L &ug. ?11' 6age/s3CLD " LL vol.' J*K 9Relationship )etween amplifier settling time and polepole-;ero placements for second second-order systemsG Schlarmann M.8.N +eiger R.;.N )ircuits and Systems ?111. 6roceedings of the D*rd I888 Midwest Symposium on Iolume ' Q"'' &ug. ?111 6age/s3CED " E0 vol.' JDK 9A new multipath amplifier design techni,ue for enhancing gain without sacrificing )andwidthG Schlarmann M.8.N ;ee 8.!.F.N +eiger R.;.N )ircuits and Systems '000. IS)&S R00. 6roceedings of the '000 I888 International Symposium on Iolume ? *1 May" May"? Sune '000 6age/s3CP'1 " P'E vol.? JEK 9A ro)ust feedforward compensation scheme for multistage operational transconductance amplifiers with no *iller capacitorsG Thandri B.!.N Silva" Silva"Martine4 S.N Solid" Solid"State )ircuits I888 Sournal of Iolume *Q Issue ? Feb. ?11* 6age/s3C?*L T ?D*
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High Speed, High Gain Operational Amplifier Research

Basem Soufi Iowa State University basem@iastate.edu

Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005

My personal research specific interest at Iowa State University

Capacitor Mismatch Offset

Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005

Basem Soufi Copy Right (c)

Feed forward Architecture to Bypass Parasitic Poles !ast "pdate #$%&%'$$&

Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005

(he Opamp Pro)lem

Basem Soufi Copy Right (c)

Bad Assumption in *ultistage Opamp +esign

Fre,uency Segregation Structure - Intuiti.e Idea +e.elopment

Basem Soufi Copy Right (c)

(wo(wo -Stage implementation and modeling without parasitics

Open !oop *odel Fre,uency Response

First Order Overall Frequency Response with perfect zero-pole cancellation

90 Degrees Flat Phase Response

Basem Soufi Copy Right (c)

*odel Step Response

Basem Soufi Copy Right (c)

Dominant pole movement

Feedback factor = 1 Feedback factor = 0

Z First Stage Dominant Pole

Basem Soufi Copy Right (c)

Second Stage Dominant Pole

Z First Stage Dominant Pole

Basem Soufi Copy Right (c)

Studying the circuit with parasitic poles in the first stage

Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005

Cascode First Stage Model

Second Stage Model Vout

Basem Soufi Copy Right (c)

Some simulations to pro.e the concept of )y)ypassing parasitic poles

7verall Stage +ain First Stage +ain

Second Stage +ain Second Stage 6hase

4ithout Feedforward ByPass Path

First Stage 6hase

A nasty Parasitic pole

Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005

Parasitic Pole ByBy-Passed7

8ear First Order (ransfer /ur.e

4ith FeedForward ByPass Path

(he main 6ero-Pole cancellation

Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005

Basem Soufi Copy Right (c)

#hen the dominant =ero is before second stage pole.

Basem Soufi Copy Right (c)

Simulation to pro.e the tuning concept )y linear sweeping of the FF capacitor

Feedbac> factor is 1.E

E11fF 'pF (his is a three pole, two ;ero system

6eros mo.ement with FF capacitor sweeping

(ominant 4ero movement.

@on"(ominant 4ero movement.

Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005

Basem Soufi Copy Right (c)

Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005

Basem Soufi Copy Right (c)

Sol.ing the Positi.e Feed)ac:

Sol.ing the Positi.e Feed)ac:Feed)ac:continue

Basem Soufi Copy Right (c)

Final /ircuit Schematic

Basem Soufi Copy Right (c)

Basem Soufi -Feedforward Operational Amplifier- ISU Copyright (c) 2003-2005