Lecture 21 and 22

Course Computer Based Automation WS 06/07 1 Stephan Simons
Computer Based Automation

Winter Term 06/07
Prof. Dr. Stephan Simons
University of Applied Sciences Darmstadt
Master of Science in Electrical Engineering
Contents of the course
1. Introduction to automation systems
2. Fundamentals
a) numerical representations, b) logical functions and operations
3. Programmable Logic Controller (PLC)
a) basics, b) principle of operation, c) architecture, d) PLC family
4. PLC S7-300 with interface modules
5. Programming of a PLC
1. Overview PLC standard IEC 1131-3
2. Programming Languages for S7 family & program structure
3. Basic operations of STEP 7 in STL, LAD and FBD: Flags, Edge
evaluation, Result of logic operation & Status word, Set and reset
operations (flip flop), Timer instructions, Counter instructions,
Particular instructions
4. Program organization units
5. Indirect Addressing
6. Structured Control Language (S7-SCL)
7. Sequential Control Language (S7-Graph)

today


Repetition of last lecture
Comparison functions
Functions in STL, FBD & LAD; Example
Arithmetic functions
Functions in STL, FBD & LAD; Example Two step controller
Meaning of and working with EN input and ENO output
Mathematical functions
Functions in STL, FBD & LAD
Conversion functions
Functions in STL, FBD & LAD; Conversions to REAL; Conversions from REAL to INT
Example for mathematical function with conversion functions including normalization
Normalization of analog values using the AD & DA converter
Working with analog physical inputs (Conversion of transducer, AD converter,
Normalization, processing a mathematical function, conversion of DA converter,
conversion of actuator)
Jump instructions
J umps in STL, FBD & LAD; Additional jumps in STL incl. jump distributer and loop
Example: Using the jump instruction to restrict an analog value
Free PLC Development SW similar to STEP 7
http://www.mhj-software.com/de/
Comparison functions in STL
Comparison
function
INT DINT REAL
Equal ==I ==D ==R
Not equal <>I <>D <>R
Greater >I >D >R
Greater or equal >=I >=D >=R
Less <I <D <R
Less or equal <=I <=D <=R
INT: Integer DINT: Doubleinteger REAL: floating point
Example: Comparison functions in STL
The input word IW0 is compared with the literal 120
(10)
. If both values are
equal Bit Q4.0 shall be set to 1 , otherwise Q4.0 shall be 0.
No. STL Comments
1 A Q4.0
Q4.0
IW0
120
Q4.0
2 R // Q4.0 is set to 0
3 L // load IW0 into ACCU 1
4 L // transfer IW0 from ACCU 1 into ACCU 2 and load 120
// into ACCU 1
5 ==I // Compare ACCU 1 with ACCU 2 to be equal
6 S // Set Q4.0 to 1 if ACCU 1 = ACCU 2
Example comparison function in FBD
The input word IW0 is compared with the literal 120
(10)
. If both values are
equal Bit Q4.0 shall be set to 1 , otherwise Q4.0 shall be 0.
Arithmetic functions
Additional: DEC n (Decrements ACCU 1 by the value of n)
(only in STL) INC n (Increments ACCU 1 by the value of n)
Arithmetic function INT DINT REAL
Addition +I +D +R
Subtraction -I -D -R
Multiplication *I *D *R
Division with quotient as
result
/I /D /R
Division with remainder as
result
- MOD -
Examples for arithmetic functions
L MW0
L MW2
+I
T MW10
L MD0
L MD2
-D
T MD10
L MD0
L MD2
*R
T MD10
L MD0
L MD2
/R
T MD10
Fct. LAD FBD STL
I1-I2
I1+I2
I1*I2
I1/I2
Mathematical functions
Square, square-root
Sine, cosine, tangent
Arc sine, arc cosine, arc tangent
Exponential function to base e, natural logarithm
All these mathematical functions only work with values of the data type
REAL!
Conversion functions for REAL INTEGER (in STL):
lTD Conversion of INT to DINT
ITB Conversion of INT to BCD
DTR Conversion of DINT to REAL
RND Conversion of REAL to DINT with rounding to the next higher
integer number
Conversion
16 bit Integer
to
32 bit Integer
Conversion
32 bit Integer
to
REAL
Input Data
Integer
16 Bit
Program
algorithms
using REAL
Conversion functions INT DINT REAL
LAD FBD STL
MW12
MD20
MD20
MD28
L MW12
ITD
T MD20
L MD20
DTR
T MD28
MW12
MD20
MD20
MD28
Conversion fromReal 32 bit DINT
Round (FBD & LAD) / RND (STL): Rounds to the next integer. When the fraction
of the number is exactly between an even and uneven result, the operation chooses
the even result. Examples: +1.49 +1; 1.5 2; 2.5 2; 2.51 3
Trunc: Round with truncation of the fraction part. The result is only the integer part
of the real data. Examples: 1.6 1.
Ceil / RND+: Round to the next highest integer. This operation rounds the
converted number to the smallest integer, that is greater than or equal to the
converted integer. Examples: +1.2 +2; -1.5 -1.
Floor / RND-: Round to the next lowest integer. This operation rounds the
converted number to the largest integer, that is smaller or equal to the converted
integer. Examples: +1.5 +1; -1.5 -2.
Conversion function: Example
(PIW288) (PQW320)
Analog Input: PIW288 (16 bit Integer)
Analog Output: PQW320 (16 bit Integer)
Realize the following function f(x) with a PLC:
x * . y 16 3 =
with: 0V <= x <= 10V, 0V <= y <= 10V
0V 10 V 0 27648
(10)
Normalization (Scaling)
x y * 16 , 3 =
V 10 27648
int
=
8 , 2764 *
int
y y =
8 , 2764 *
int
x x =
8 , 2764
* 16 , 3
8 , 2764
int int
x y
=
int int
* 8 , 2764 * 16 , 3 x y =
int int
* 157 , 166 x y =
7)
1)
2)
3)
4)
5)
6)
Internal representation of analog value in case of
bipolar measurement range
Increments Voltage
measurement range
Current
measurement range
Range
dec. hex. 10 V 20 mA
32767 7FFF 11,851 V 23,70 mA
32512 7F00
32511 7EFF 11,759 V 23,52 mA
27649 6C01
27648 6C00 10 V 20 mA
20736 5100 7,5 V 15 mA
1 1 361,7 V 723,4 nA
0 0 0 V 0 mA
1 FFFF -361,7 V -723,4 nA
20736 AF00 7,5 V 15 mA
27648 9400 10 V 20 mA
27649 93FF
32512 8100 11,759 V 23,52 mA
32513 80FF
32768 8000 11,851 V 23,70 mA
Underflow
Underrange
Rated range
Overange
Overflow
Table for normalization
System Voltage
measurement
range
Current measurement range Range
dez. hex. 10 V 0..10 V 20 mA 0..20 mA 4..20 mA
27648 6C00 10 V 10 V 20 mA 20 mA 20 mA
0 0 0 V 0 V 0 mA 0 mA 4 mA
27648 9400 10 V 20 mA
Rated
range
Revolution measurement: transducer
10 V, 20 mA, 16 mA
1000 U/min
365
500 865
1500 rpm
0 27648 Incr. 13824
1000
10092
Analog value conversion and processing
865 rpm 3,65 V 10092 Incr
10092
(INT)
10092
(DINT)
10092,0
10092,0 *2,2 22202,4
22202,4 22202
(DINT)
22202 Incr
22202 Incr 8,03 V 1303 rpm
Transducer
A/D-Converter
L PIWn
ITD DTR
Programmed algortihm
RND T PQWn
Actuator
D/A-Converter
J ump unconditional
LAD FBD STL
J umps conditional
LAD FBD STL
All jump instructions in STL
Unconditionally jumps:
JU label J ump Unconditional
JL label J ump to Labels
J umps based on RLO:
JC label J ump if RLO = 1
JCN label J ump if RLO = 0
JCB label J ump if RLO = 1 with BR
JNB label J ump if RLO = 0 with BR
J umps based on another bit in the status
word:
JBI label J ump if BR = 1
JNBI label J ump if BR = 0
JO label J ump if OV = 1
JOS label J ump if OS = 1
J umps based on the result of a
calculation:
JZ label J ump if Zero
JN label J ump if Not Zero
JP label J ump if Plus
JM label J ump if Minus
JPZ label J ump if Plus or Zero
JMZ label J ump if Minus or Zero
JUO label J ump if Unordered
Loop instruction
LOOP label call a program
segment multiple
times
Instruction contents of lecture
Bit logic instructions
Bit logic instructions with expressions in parenthesize
Edge triggered instructions
Memory functions: Setting / Resetting bit addresses
Timer instructions
Counter instructions
Load and transfer instructions
Comparison instructions
Integer and floating-point arithmetic instructions
Floating point mathematical instructions
Jump instructions

Contents of the course
1. Introduction to automation systems
2. Fundamentals
a) numerical representations, b) logical functions and operations
3. Programmable Logic Controller (PLC)
a) basics, b) principle of operation, c) architecture, d) PLC family
4. PLC S7-300 with interface modules
5. Programming of a PLC
1. Overview PLC standard IEC 1131-3
2. Programming Languages for S7 family & program structure
3. Basic operations of STEP 7 in STL, LAD and FBD: Flags, Edge
evaluation, Result of logic operation & Status word, Set and reset
operations (flip flop), Timer instructions, Counter instructions,
Particular instructions
4. Program organization units
5. Indirect Addressing
6. Structured Control Language (S7-SCL)
7. Sequential Control Language (S7-Graph)

Functions
Circuit diagram of a hwp realization:
Functions
Circuit diagram of a hwp realization:
Logic plan
Logic plan
PLC realization:
Inputs
I0.1 I0.2 I0.3 I0.4
PLC S7-300
Q4.1
I0.5
Logic plan
Declaration of the variables of the function
Networks of the function using symbolic variables
Logic plan
Declaration of variables of OB1
Only system variables are declared!
No declaration of variables for function FC0 are needed!
Calling of function FC0 withihn OB1
Logic diagramof a BCD counter
BCD-Counter with J K-FFs
1.) Designing a function block for J K-FF
R: reset input
X: 0 or 1
Logic diagramJ K-FF: Realization with mit two
memory FF (Master-Slave)
Function block J K-FF: Declaration of the variables
Function
block
J K-FF:
Networks
1 & 2
Function block J K-FF: Networks 3 & 4
OB1 calling function block FB11 (J K-FF) with
instance data block DB11
OB1 calling function block FB11 (J K-FF) with
instance data block DB11
Instanz-Datenbaustein DB11 fr J K-FF
Funktionsbaustein
Usage of instance data blocks in STEP 7
1.) Generate a function block (Insert, S7 block, Function Block)!
2.) Declare the interface variables in the function block and implement the
algorithms of the function block!
3.) Insert a call of the function block at the desired place e.g. in OB1 by
double clicking on it in the container FB blocksof the program
elementsoverview.
4.) Specify the instance data block number for the inserted function block!
The data block will be generated automatically after inquiring if it does not
exist at that time.
5.) If the function block shall be used at another place of the program with
another instance data block, insert it there once again and specify the
appropriate instance data block!
6.) If the interface parameters of a function block are changed, the data block
has to be generated new (as a precaution delete the data block before!)
Logic diagramof a BCD counter
Inputs and outputs of BCD counter realization
Clock input for all FFs: I0.0
Reset input for all FFs: I0.7
FFA: J A=KA: I0.1=1, QA: Q4.0, QA: Q4.4
FFB: QB: Q4.1, QB: Q4.5
FFC: QC: Q4.2, QC: Q4.6
Realization of BCD counter (I)
Network 1: FFA
1. J K-FF. Instance data block: DB11
J =K=I0.1=1, Clock=I0.0, R=I0.7,
QA=A4.0, QAN=Q4.4
Network 2: FFB:
QB=A4.1, QBN=Q4.5
Realization of BCD counter (II)
Network 4: FFD
QD=A4.3, QDN=Q4.7
Network 3: FFC:
QC=A4.2, QCN=Q4.6
Realizing the BCD counter with mutliple instances
Programthe J K-FlipFlop in FB11!
Generate a newfunction block e.g. FB5!
Declare the flipflops FFA, FFB, FFC and FFD in the interface variable
declaration section of function block FB5 as static variables of data type
FB11. By this all variables needed by the several calls of function block
FB11 are created as local variables in FB5.
Insert each flipflop at the desired place in FB5 by picking the appropriate
flipflop (e.g. FFA) fromthe container multiple instancesof the program
elementsoverview.
Call the function block FB5 at the desired place in OB1 one time and
specify the instance data block. This instance data block contains all
parameters of all flipflops declared in FB5.
Realization see pdf files in
Example BCD counter with mutli instances.zip
Event-driven
program
processing
of a S7 PLC
Symbolic addressing
In functions and function blocks only use
symbolic addressing (also in exam)!
Its also possible to use symbolic addressing in organization
blocks:
Therefore open LAD/STL/FBD Editor and
choose Symbol tablein menue Options.
Declare the symbols in the table.
Those symbols can afterwards be used globally.
Important OBs used beside OB1
OB100 ( startup OB )
Determines the startup behavior of the PLC.
Is processed once directly after power up of the PLC (before first
instruction of other OBs e.g. of OB1).
Is used to set initial values for the PLC outputs or global variables.
Makes sure, that the process gets into a safe state if the voltage of
the PLC returns after a power failure.
OB35 ( Cyclic interrupt OB )
Realizes start of processing of programs in fixed time intervals i.e.
programs are processed with fixed sampling rates.
Is used to realize digital control loops or to sample measurement
values with fixed sampling rates.
Generating organization blocks in STEP 7
In SIMATIC Manager in container Blocks ( Bausteine ) of the project tree
choose Insert , S7 Block , Organization Block from the menu bar
OB100 is processed automatically first after power failure after downloading
the program into the PLC
Definition of the execution time (sampling rate) of a cyclic interrupt
organization block:
Select the desired SIMATIC station in the SIMATIC Manager e.g. SIMATIC
300(1)
Open the hardware configuration by double clicking on the Hardware icon
Select the CPU in Slot 2
Choose Edit, Object propertiesfrom the menu bar
Choose the Cyclic Interruptsection
Define the priority and the execution time (sample time in ms)
Download hardware configuration to PLC
Example for a global data blocks
Generating a global data block in STEP 7
In SIMATIC Manager in container Blocks
(Bausteine) of the project tree choose Insert,
S7 Block, Data Blockfrom the menu bar
Afterwards open the data block by double clicking
on it and declare data by inserting the data in the
table.
Indirect Addressing
Using indirect addressing addresses can be changed when
processing the program.
The indirect addressing is only possible with absolute
addressing!
Symbolic variables can not be addressed indirectly.
Indirect addressing exists only in STL, but not in FBD or LAD!
Indirect Addressing
Absolute addressing recognizes the following cases:
Immediate addressing
direct addressing
indirect addressing.
Immediate addressing means that the number value is specified
together with the operation. Example: L +152
With direct addressing data the address is given together with the
operator. Example: A I 0.5
With indirect addressing the statement indicates where the address is
to be found instead of containing the address itself.
There are two types of indirect addressing:
Memory-inidirect addressing
Register-indirect addressing.
Memory-indirect addressing
Uses an address from the system memory
Example: T QW [MD 220]
The address of the output word is located in the memory double word
MD 220.
The address in the has the form of an area-internal pointer
Area-internal pointer
A double word with 32 bit width with the following structure:
For a simplification the address can be loaded as a pointer.
Byte n Byte n+1 Byte n+2 Byte n+3
0 0 0 0 0 0 0 0 0 0 0 0 0 y y y y y y y y y y y y y y y y x x x
Byte address Bit address
Examples for memory-indirect addressing
1. Example: Load address using a pointer
L P#0. 1 // Load pointer with address 0.1 into ACCU 1.
T MD 10 // Transfer pointer 0.1 from ACCU1 to MD10.
A I [ MD 10] // Load I0.1.
A I 0. 2 // I0.1 AND I0.2
= Q 4. 0 // Assign (I0.1 AND I0.2) to output Q4.0
2. Example: Load address directly:
L 16#00000001 // Address 0.1 is loaded directly in hex-code into ACCU1;
// Byte address: y...y = 0, Bit address: xxx = 1.
T MD 10 // Transfer Pointer 0.1 from ACCU1 to MD 10.
A I [ MD10] // Load I0.1.
A I 0. 2 // I0.1 AND I0.2
= Q 4. 0 // Assign (I0.1 AND I0.2) to output Q4.0
L 4 // Load 4
T MW20 // Transfer 4 into MW 20.
OPN DB [ MW20] // Open global DB4.
L DBW4 // Load DW 4 of DB4 into ACCU 1.
T QW4 // Transfer DW 4 to output QW 4.
OB1: 1. Example: Indirect addressing of blocks
With a number blocks can be addressed indirectly.
Network 1: Indirect addressing of a data block
The data block number is located in memory word MW 20 (e.g. data block no. = 4).
DB 4:
L 4 // Load 4
T MW20 // Transfer 4 to MW 20.
A I 0. 2
CU C [ MW20] // Count up
A I 0. 3
CD C [ MW20] // Count down
A I 0. 4
L C#20
S C [ MW20] // Load value 20 into counter.
A I 0. 7
R C [ MW20] // Reset counter to 0.
L C [ MW20] // Load counter value in dual code.
T MW10 // Transfer counter value to MW10.
NOP 0
A C [ MW20] // Get binary counter output.
= Q 5. 7 // Assign binary counter output to Q5.7
OB1: 2. Example: Indirect addressing of blocks
With a number blocks can be addressed indirectly.
Network: 1 Indirect addressing of a counter
Usage of the counter with the number located in MW 20 (here 4).

Lecture 21 and 22

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Course Computer Based Automation WS 06/07 1 Stephan Simons

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Course Computer Based Automation WS 06/07 24 Stephan Simons

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