2012CS1120224

Convolutional Coding And Viterbi Decoding Algorithm

Devansh Dalal ( 2012CS10224 )

Abstract Viterbi algorithm is an efficient technique to decode convoluted codes. It is a dynamic programming algorithm which gives most likelihood decoding of convolution codes. It is the most widely used error correcting technique in communication channels-mainly wireless and mobile communication systems for optimal decoding of convolutional codes. This paper discuses the uses and need of convolutional codes as Error correcting codes. The Viterbi algorithm is explained with various units used for hardware implementation along with performance analysis. Index Terms Error Correction, Convolutional Codes, Viterbi
Decoding, Trellis Diagram, Hard and Soft Decoding,(Adaptive Viterbi Algorithm) AVA ,Bit Error Rate(BER),

Unlike Block codes, these are generated using serial input and and hence slow to encode. In block codes, information

bits are followed by parity bits. In convolution codes, information bits are spread along the sequence.

1.Convolutional encoder (rate , K=3)

I. INTRODUCTION

ccording to recent estimate at Qualcomn(a global

The encoder maintains a sliding window of K ( K > 1) bits and it takes k subsets of these K words and generate the output after adding the elements of each set in 2 i.e normal XOR operation between them. The size of window in bit is called the constraint length of the encoder. If a convolutional code that produces k parity bits per window and slides the window forward by n bits, its coding rate (number of output bits per input bit) is given by Rc = k/n So a convolutional code can be represented by 3 parameters uniquely as (n , k , K ) or (k/n, K). Also if there is not any feedback from any of the output back to the input (i.e. any combinational logic with input) then the generated code is called Non-recursive code, but if there is some such feedback then the encoder is called Recursive encoder. A. Properties Longer constraint length K More powerful and efficient code More complex decoder More coding delay Smaller coding rate Rc More powerful code due to extra redundancy added Large communication overhead

telecommunication company) 1015 per second are now being decoded by the Viterbi Algorithm in digital TV sets around the world per second per day. The integral part of Viterbi decoding are convolutional codes. Convolutional encoding is a forward error correcting (FEC) technique of correcting the errors in signals due to noise in the channel. FEC means correcting the corrupted signal at the receiver end. Actually the Viterbi algorithm can be thought of an equivalent graph problem of minimizing the cost of traversing the graph according to some given output symbols and escape probability from any state si to sj from some starting point.

II. CONVOLUTIONAL ENCODING Encoding essentially means adding some redundant bits to the data prior to transmission so that at the receiver end the information sequence can be reconstructed effectively reducing the probability of error due to bit flips in between.

Author-Devansh Dalal , 2012CS10224 , Computer Science And Engineering, IITD, New Delhi, India . (e-mail: cs1120224@cse.iitd.ac.in).

2012CS1120224 III. THE ALGORITHM The algorithm uses dynamic programming to find the most optimal string of bits possible for the given received input string encoded using convolutional code. We define here two metrics: the branch metric (BM) and the path metric (PM). The branch metrics are hamming distances/Euclidean distances/probabilities depending on the type of encoding. The path metric is a value associated with a state in the trellis. For hard decision decoding, it corresponds to the Hamming distance over the path with smallest Hamming distance between the initial state and the current state from the initial state to the current state in the trellis. The path with the smallest hamming distance reduces maximum number of bit errors and hence is the most likely one. The trellis diagram for K=3 and rate=1/2 as shown in figure 2 is very helpful in understanding the working of the algorithm. In fig the bit pairs marked yellow have wrong values. IV. HARD AND SOFT DECODING

The hard Decoding converts the received analog signal to digital signal converting all the voltages above a threshold to 1 and lesser to 0. Suppose the Vth is 0.5 V, any voltage between 0.501 to 0.999 is converted to 1 V. Clearly some information is lost in this regarding the actual value of the bit may have. The soft decoding exploits this aspect of data. With soft decision decoding, the decoding algorithm is identical to the one previously described above, except that the branch metric is no longer an integer Hamming distance but a positive real number (if the voltages are all between 0 and 1, then the branch metric is between 0 and 1 as well). Actually soft decoding doesnt digitalizes the input signal and since it tries to use more information than hard so its performance is better theoretically. In soft decoding algorithm the Euclidean distances are used instead of hamming distances. Here branch metric is a function of the continuous analog signal. Square of the difference between received signal and the signal which is expected to be received from that state is a good candidate for Branch metric. Suppose we are given a convolutional code of p parity bits i.e rate=1/p. Then p received analog samples are v = v1, v2,. vp and u =u1,u2,.., up be the expected signal for the output after reaching the next state.

BMsoft( si , sj ) =
=1

( )2

For simplicity, suppose encoding of rate 1/n and constraint length K and decoding is hard decision decoding. Let S be set of all 2k states .The algorithm consists of 3 steps. 1. Calculation of branch metrics for all possible transitions from each state to every other state in S and store them in RAM or flip flops for next steps. 2. Calculation of path metrics recursively for the jth bit using the path metrics for (j-1)th bit for all the states This is known as add-compare-select (ACS) recursion. 3. Recursively trace back (TB) to find the ML(most likelihood) path in the trellis constructed in step 1 and 2. For the calculations of path metrics, let P[ s , i ] denote the path metric after i iterations of the state s and B[ s , c ] denote the Branch metric for state between s and c calculated in step 1 recursively. PM[s, i +1] = min( PM[, i ]+B[ , i ]) After the whole procedure finishes, for each state we have a processor state. So we trace back from the last most likely state back to the beginning to recover the encoded data. To avoid integer overflow of the path metrics we need to subtract the maximum PM of them till that stage periodically to maintain correctness.

where BMsoft( si , sj ) denote the branch metric that will be added to the path metric while transitioning from state si to sj. Suppose while decoding we are at state s at given step i, then path metric is defined in the same way by PMsoft (s , i+1) = min( PMsoft [, i] + BM[,s]) (1) Since branch metric in this case are closely related to the probability of translating from one state to other because more the voltage difference is, lesser is the probability of transitioning to that given state.

Psoft (s , i+1) = max( Psoft [, i] * p[ ,s])

(2)

Where Psoft (s , j) is the probability of transitioning to the state s at the jth step and p[ ,s]) is the probability of transitioning to the state s from state . But due to limitation of floating point operations, eq (1) cannot help, because soon the product will become 0. Since we need to maximize the probability and we can maximize logb Psoft (s , i+1) ( = PLsoft (s , i+1) ).

PLsoft (s , i+1) = max( PLsoft[, i] +logep[ ,s])

Since loge(p[ , s ] )= * (-d2) (from ref. [9]) Where is a constant and d = V i - Ve , Vi : received analog signal b\w o and 1 Ve: expected binary bit 0 or 1. This gives,

PLsoft (s , i+1) = max( PLsoft[, i] - d2)

2012CS1120224 V. HARDWARE IMPLEMENTATIONS The hardware for Hard Decoding Viterbi decoding requires mainly 3 Units namely 1. BMU-(Branch Metric Unit) 2. ACS-(Add Compare Select Unit) 3. SMU-(Survivor Memory Unit) The BMU units function is to calculate the values for the branch metrics which is hamming distance between received Code word and expected bit string. It is just the number of different bits between the two. When branch metric counting is done and all the branch metrics are sent to ACS unit. For simplicity, we Consider a convolutional code of rate=1/2 and constraint length of 3 method is a bit more complicated, but works well for longer constraint length codes

The RE(register-exchange) approach assigns a register to each state. The register records the decoded output sequence along the path starting from the initial state to the final state, which is same as the initial state Consider a trellis diagram shown in Figure The register of state S1 at t=3 contains 101. Note that the trellis follows along the bold path, and the decoded output sequence is 101. This approach eliminates the need to traceback, since the register of the final state contains the decoded output sequence. Hence, the approach may offer a high-speed operation, but it is not power and hard ware efficient due to the need to copy all the registers in a stage to the next stage.

3.ACS unit implemented using simple adder, comparator and MUX.

The major task of ACS (Add-Compare-Select) is to add the branch metrics to the previous metrics while reaching the current state and select the path metric for each state corresponding to the state with the minimum hamming distance. A simple ACS unit is shown in figure below.

4.Register exchange information generation method

As compared to PMU, the RE is faster simplest conceptually and a commonly used technique in most of the demanding applications. VI. APPLICATIONS OF VITERBI i. ii. iii. Digital Cellular Phones Wireless LAN Satellite Communications Photographs from spacecraft e t c Because BER in space is very large Digital Video Broad Casting Digital wireless Transmitters and receivers VII. OPTIMIZATIONS AND RECENT IMPROVEMENTS In terms of time complexity, the Viterbi algorithm is O(n2 k) in order notation ,where n is length the input encoded code and k is the constraint length of the encoding scheme. As we know that for better error correction we need large constraint length, but we cannot increase the k to large numbers (generally k<=10) due to exponential dependence of Viterbi algorithm on k. But there are many modifications possible as I have studied from recent papers. The quality of Viterbi decoder design is generally measured by these three criteria Power dissipation Speed of decoding Error correction rate

The two adders shown in fig compute the partial path metric for the given state and the comparator compares the two path metrics and the Mux selects the minimum of them. All the ACS compute this in parallel and we are left with path metrics of all the 2(k -1) states for the current iteration or the clock cycle.
The SMU of a Viterbi algorithm can be implemented using two types of approaches a. RE (Register Exchange) b. TB (Trace Back Unit) TBU traces back to recover the output sequence. When the trellis diagram is finished, the trace-back module will search the most likely path from the final State to the beginning state. Each time, the trace-back block just left shifts one bit of the binary state number and add one bit from the survivor path metric to compute the previous state. By doing this, the most likelihood path is found. It consists of a series of registers which record the survivor path of each state selected by the ACS module. The corrected output sequence is produced by tracing the decision vectors. Advantages of this method are that trace-back unit takes less area to implement and power consumption is low that is why TBU is preferred when power and available resources are low but due to its sequential nature it is slow. The traceback

iv. v.

2012CS1120224 1. Adaptive Viterbi decoder In normal Viterbi decoder, at any time the path metric for any given state exceeds the minimum path length(dm ) for that level by a threshold dth ,then both the paths originating from that state are not extended. This significantly reduces the number of comparison ACS unit have to make and the comparator have to select lesser paths. The total number of paths originating from each
8. 9. ST[i]:current ML state no. reaching the i^th bit. PM[i]:PM till i^th iteration starting from 0.

10. RE:will contain recovered bit string; 11. Program: 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. 25. 26. PM[1]=0 for i=2,3,...,2^K do PM[i]=inf for i=1,2,3,...,N do #initializations #PM calculations

s=ST[i-1] #current_sate min=PM[ST[i-1]]+(maximum BM possible) for all states sj such that s->sj do if(PM[i]>PM[s]+BM[sj,s]): PM[i]PM[s]+BM[sj,s] if(PM[i]<min): min=PM[i] ST[i]=state no. of sj for min. PM for i=N,N-1,...2,1, do #trace back calculations RE[i]=0/1 accod. to output of ST[i-1]>ST[i] #depends on the type of encoding used RE[1,2,..]:contains the decoded sequence.

27.

decoding by AVA, X marked paths are not extended.

VIII. CONCLUSION stage are comparably less than normal decoder. Hence the power dissipation is lesser because of less activity of ACS unit. Since many states go dormant each iteration, consequently stronger codes (10K) can be used for decoding for more accuracy. 2. Look-ahead Transformation One alternate approach is that instead of calculating the PM for the next state, we can compute PM for the next to next state. Of course, ACS unit have to do 4 comparisons instead of 2 for each state, But speed up is almost double of simple implementation. This way speed can be increased on the cost of hardware used.
Table : Simulation Results[11] Sequential VA Optimized VA Execution Time(s) 38.3294 20.0305

Although among the most widely used ,the Viterbi algorithm has exponential computational complexity in terms of constrain length. Due to this it requires more resources and time to decode the encoded messages. The paper have discussed some of these basic optimizations. Since error correcting is main concern of communication channels, especially mobile networks to develop power efficient decoder and space vehicles and satellites. IX. REFERENCES
[1] [2] [3] K. S. Arunlal and Dr. S. A. Hariprasad, AN EFFICIENT VITERBI DECODER , Vol. 2, No.1, February 2012 G. DAVID FORNEY,JR.,The Viterbi Algorithm,VOL.61, NO.3, MARCH 1973 Nitin S. Sonar, Dr. Faris S. Al-Naimy, Dr. R.R. Mudholkar, An Improved Dynamically Reconfigurable Pipelined Adaptive Viterbi Decoder for High Throughput Volume 2, Issue 7, January 2013 Matthias Kamuf,, Viktor wall, and John B. Anderson , Optimization and Implementation of a Viterbi Decoder Under Flexibility Constraints vol. 55, no. 8, SEPTEMBER 2008. Francois Chan, David HoccunAdaptive Viterbi Decoding of Convolutional Codes over Memoryless Channels,vol45,NO. 11,Nov97. Swati Gupta1, Rajesh Mehra, FPGA Implementation of Viterbi Decoder using Trace back Architecture May to June Issue 2011 Hiral Pujara, Pankaj P. Prajapati , Development of IP Core for Viterbi Decoder using VHDLvol 2, issue 4,april 2013. Matthias Kamuf, John B. Anderson, Viktor wall, Survivor Path

3.

Pipelined Viterbi decoder The ACS unit performs 3 operations for a given state i.e. generations, comparisons and selection of the candidates for PM for the next state. When one of these operation is being performed the other hardware units are ideal. This indicates that pipeling can improve the performance similar to the pipeling in a simple processor. Here pipeline may contain two stages at the same time

[4]

[5] [6] [7] [8]

Below is a pseudo code for implementation of Viterbi algorithm in software:

Processing in Viterbi Decoders Using Register Exchange and Traceforward. VOL. 54, NO. 6, JUNE 2007.
[9] Viterbi Decoding of Convolutional Codes(February 29, 2012). Available:http://web.mit.edu/6.02/www/s2012/handouts/8.pdf. [10] Spatially Close Signals Separation via Array Aperture Expansions and Spatial Spectrum Averaging. Available: http://etrij.etri.re.kr/Cyber/BrowseAbstract.jsp?vol=26&num=1&pg=45 [11] Nitin S. Sonar, Dr. Faris S. Al-Naimy, Dr. R.R. Mudholkar An Improved Dynamically Reconfigurable Pipelined Adaptive Viterbi Decoder for High Throughput Volume 2, Issue 7, January 2013 [12] C. ARUN, V. RAJAMANI A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering, available: http://www.SciRP.org/journal/ijcns/

1. 2. 3. 4. 5. 6. 7.

Inputs: K : constraint length. Y : recieved bitstring of size N. BM[i][j]:BM for tansitioning from state i to j. //In case of soft-decision decoding BM may not be int Assume the states are numbered 1 to 2^K Outputs: