ANALOG INTEGRATED CIRCUITS DESIGN PROJECT

DESIGN OF A CMOS FULLY DIFFERENTIAL OPERATIONAL TRANSCONDUCTANCE AMPLIFIER

Naveen Gopalakrishnan Nikhilesh Kamath 7th December 2013

- We, Naveen Gopalakrishnan and Nikhilesh Kamath, have neither given nor received any unauthorized aid on this project

Executive Summary
The operational transconductance amplifier has been realized using a Rail to Rail Op Amp design topology for the main op-amp and the gain boosting technique through current mirror baby op-amps. The OTA achieves a common mode input range of 0 to 1.8V. The common mode feedback circuit is that of topology 4 where the feedback is given through differential pairs. The design specifications were successfully met. The overall design is made such that we have a stable operation for entire input common mode range.

Design Results - Compliance Table

Parameter Low Frequency Gain Gain-bandwidth product Phase margin Settling Time Required Specification 85dB >180 MHz 75 degree < 90 nsec with 3pF external load 0.85V single ended peak to peak 1.7V differential peak to peak Input Common Mode Range 0.8V overlap with output signals >120dB >120dB 1.8V Pdiss < 6mW >20 V/usec < 15 nV/Hz. Report the 1/f corner frequency Achieved Achieved Results 111.7dB 183.16 MHz 75.1 degree 89.8 nsec

Output Swing

2.05873V differential peak to peak

CMRR PSRR+ Supply Voltage Power Dissipation Slew Rate Input-referred Noise Voltage Floor

129.47dB 232.1353dB 1.8V 3.2085mW 22.4 V/usec 8.325 nV/Hz Corner frequency - 441.64 MHz

Rail to Rail Operational Tranconductance Amplifier Design

Initially, we designed an NMOS folded cascode op amp with single ended output. We were able to achieve a gain of around 59-63dB. Design calculations were based on the gain-bandwidth product (GBWP) requirement of 180MHz. The transistor parameter k values f or NMOS and PMOS of the gpdk180 design kit were initially calculated. Devices were sized to achieve a low Vdsat of roughly 0.18V. Before going for the rail to rail design, we simulated the NMOS and PMOS folded cascode op amps separately and ensured that the gain requirements were met. The 2 circuits were then merged to give rail to rail operation.

OTA Circuit Schematic

Zoomed View of the Schematic

Circuit Schematic view 1

Circuit Schematic view 2

Circuit Schematic view 3

Circuit Schematic view 4

Gain Boosting Topology Current Mirror Op-Amp

It was clear that we need a gain boosting topology in our circuit. We initially went with a basic differential amplifier as the baby op amp. The gain achieved with this topology was roughly 35dB. A cascode was added at the output stage to increase the gain, but this required 2 additional biasing voltages. Instead, a current mirror op amp was used to provide gain boosting. This turned out to be a much simpler topology giving much higher gain, roughly, 55-60dB. A capacitor of 750f F was connected from output to ground for

compensation.

NMOS gain boosting topology

NMOS gain boosting topology operating points

PMOS gain boosting topology

PMOS gain boosting topology operating points

Common Mode Feedback Topology

Common mode feedback is required in all fully-differential amplifiers using active loads. The common mode feedback requirement was met by implementing the topology number 4. Differential pairs were used to sense the common mode output variation and respond. The current through the diode connected device PM6 is an average of the currents through NM7 and NM8. The current flow through the transistors of diff pair on the right is a mirror image of the current flow through the diff pair on the left. In order for this configuration to be effective and measure voltages over a wide common mode input range the diff pairs should be design for a high Vdsat or a low gm.

Common Mode Feedback Topology

Supply Independent Biasing

Initially the circuit was working with ideal current and voltage sources. After ensuring successful circuit operation, these current sources were replaced by current generators from the bias circuit and also the voltage bias points were obtained from bias circuit. The need for this is to generate currents that are independent of the supply voltage variations and thus can be controlled. The boot strapping method is used to generate the reference current of 50uA. Here we have employed Vgs based current reference topology where the current is determined by the Vgs of the bottom MOSFET and the resistor connected across it.

Supply Independent Biasing Circuit

Supply Independent Biasing Circuit operating points

Common Mode Input Range

Using a Rail to Rail Topology we achieve the common mode input range from 0 to 1.8V and hence we also ensure that there is an overlap of 0.8V with output signal as per the design specification.

Phase Margin Requirement

A phase margin of 75.1 degrees was achieved over the entire input common mode range 0-1.8V and hence ensuring the stability of operation. Note: All the required simulations and calculations shown are for a nominal common mode input of 0.9V.

Test bench for Simulation

SIMULATION RESULTS:

Common Mode Rejection Ratio (CMRR)

The red line is the differential mode gain and the purple line is the common mode gain. The CMRR = 110.4212dB 121.7141dB = 232.1353dB

Power Supply Rejection Ratio (PSRR)

PSRR+ = 232.1353dB

Output Swing

Compensation
The entire circuit has multiple feedback loops and they need to be compensated to achieve adequate phase margin over the entire input common mode range. The common mode feedback topology is compensated. This is tested by breaking the loop at a point of high input impedance and plotting the frequency response. The output node of the main op-amp is compensated to counter the phase margin. Again it should be made sure that the cross over frequency of the baby op-amp should lie between the 3dB frequency and the crossover frequency of the main op-amp so that it doesnt affect the stability.

Frequency Response of Gain Boosting Topology Current Mirror Op Amp

Power Dissipation
Ideally the OTA should consume as low power as possible. The power dissipation of our OTA is 3.2 mW which is below the limit of 6mW.

Noise Simulation
The noise was found to be within the required margin. The 1/f corner frequency is 441.64MHz.

Settling Time and Slew Rate

Conclusion
We were able to successfully implement an operational transconductance amplifier which met all design specifications. We were able to achieve this with a relatively low power consumption. The main conclusion we have drawn from this project is that the design can be further improved by improving the sizing the CMOS members of the OTA circuit to ensure a healthy gain bandwidth product with a safe margin from the limit throughout the input common mode range. Also designing the project gave us valuable insight into operation of the circuit. Through this project we also gained valuable confidence in using the simulation tool CADENCE.

References
Dr. Brian Floyds Lecture Notes for Analog Electronics (ECE 511)