Texas Instruments Incorporated

Data Acquisition

How delta-sigma ADCs work, Part 1

By Bonnie Baker
Signal Integrity Engineer
Analog techniques have dominated signal processing for years, but digital techniques are slowly encroaching into this domain. The design of delta-sigma (DS) analog-todigital converters (ADCs) is approximately three-quarters digital and one-quarter analog. DS ADCs are now ideal for converting analog signals over a wide range of frequencies, from DC to several megahertz. Basically, these converters consist of an oversampling modulator followed by a digital/ decimation filter that together produce a high-resolution data-stream output. This two-part article will look closely at the DS ADCs core. Part 1 will explore the basic topology and func tion of the DS modulator, and Part 2 will explore the basic topology and function of the digital/decimation filter module. The DS converters primary internal cells are the DS modu lator and the digital/decimation filter. The internal DS modulator shown in Figure 1 coarsely samples the input signal at a very high rate into a 1-bit stream. The digital/decimation filter then takes this sampled data and converts it into a high-resolution, slower digital code. While most converters have one sample rate, the DS converter has twothe input sampling rate (fS) and the output data rate (fD).

The DS modulator
The DS modulator is the heart of the DS ADC. It is responsible for digitizing the analog input signal and reducing noise at lower frequencies. In this stage, the architecture implements a function called noise shaping that pushes lowfrequency noise up to higher frequencies where it is outside the band of interest. Noise shaping is one of the reasons that DS converters are well-suited for low-frequency, highaccuracy measurements. The input signal to the DS modulator is a time-varying analog voltage. With the earlier DS ADCs, this input-voltage signal was primarily for audio applications where AC signals were important. Now that attention has turned to precision applications, conversion rates include DC signals. This discussion will use a single cycle of a sine wave for illustration.

DS converters: An overview
The rudimentary DS converter is a 1-bit sampling system. An analog signal applied to the input of the converter needs to be relatively slow so the converter can sample it multiple times, a technique known as oversampling. The sampling rate is hundreds of times faster than the digital results at the output ports. Each individual sample is accumulated over time and averaged with the other input-signal samples through the digital/decimation filter.

Figure 1. Block diagram of DS ADC

Sample Rate (fS )

Analog Input

Modulator

fS /fD = Decimation Ratio

Data Rate (fD) Digital Filter Decimator Digital Output

Digital/Decimation Filter

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Figure 2. Input signal to the DS modulator

Input Amplitude Input Magnitude

Time

Frequency

(a) Time domain

(b) Frequency domain

Figure 2a shows a single cycle of a sine wave for the input of a DS modulator. This single cycle has voltage ampli tude that changes with time. Figure 2b shows a frequency-domain representation of the time-domain signal in Figure 2a. The curve in Figure 2b represents the continuous sine wave in Figure 2a and appears as a straight line or a spur. There are two ways to look at the DS modulatorin the time domain (Figure 3) or in the frequency domain (Figure 4). The time-domain block diagram in Figure 3 shows the mechanics of a first-order DS modulator. The modulator converts the analog input signal to a high-speed, single-bit, modulated pulse wave. More importantly, the frequency analysis in Figure 4 shows how the modulator affects the noise in the system and facilitates the production of a higher-resolution result. The DS modulator shown in Figure 3 acquires many samples of the input signal to produce a stream of 1-bit codes. The system clock implements the sampling speed, fS, in conjunction with the modulators 1-bit comparator.

In this manner, the quantizing action of the DS modulator is produced at a high sample rate that is equal to that of the system clock. Like all quantizers, the DS modulator produces a stream of digital values that represent the voltage of the input, in this case a 1-bit stream. As a result, the ratio of the number of ones to zeros represents the input analog voltage. Unlike most quantizers, the DS modulator includes an integrator, which has the effect of shaping the quantization noise to higher frequencies. Consequently, the noise spectrum at the output of the modulator is not flat. In the time domain, the analog input voltage and the out put of the 1-bit digital-to-analog converter (DAC) are differ entiated, providing an analog voltage at x2. This voltage is presented to the integrator, whose output progresses in a negative or positive direction. The slope and direction of the signal at x3 is dependent on the sign and magnitude of the voltage at x2. At the time the voltage at x3 equals the comparator reference voltage, the output of the comparator switches from negative to positive, or positive to negative,

Figure 3. First-order DS modulator in the time domain

Difference Amplifier + VREF Comparator (1-Bit ADC)

Analog Input

xi

Integrator

fS x3
+

x2

ei x4

Output to

yi Digital Filter

x4
1- Bit DAC

yi = xi 1 + (ei ei 1)

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Data Acquisition

Figure 4. First-order DS modulator in the frequency domain

Sigma (Integrator) 1-Sample Delay

ei yi
Output to Digital Filter Signal

Delta

xi
Analog Input Magnitude

1-Bit ADC

1-Bit DAC Frequency Quantization Noise

fS

depending on its original state. The output value of the comparator, x4, is clocked back into the 1-bit DAC, as well as clocked out to the digital filter stage, yi. At the time that the output of the comparator switches from high to low or vice versa, the 1-bit DAC responds by changing the analog output voltage of the difference amplifier. This creates a different output voltage at x2, causing the integrator to pro gress in the opposite direction. This time-domain output signal is a pulse-wave representation of the input signal at the sampling rate (fS). If the output pulse train is averaged, it equals the value of the input signal. The discrete-time block diagram in Figure 3 also shows the time-domain transfer function. In the time domain, the 1-bit ADC digitizes the signal to a coarse, 1-bit output code that produces the quantization noise of the converter. The output of the modulator is equal to the input plus the quan tization noise, ei ei 1. As this formula shows, the quantization noise is the difference between the current quantization error (ei ) and the pre vious quantization error (ei 1 ). Figure 4 illustrates the frequency location of this quantization noise.

Figure 4 also shows that the combination of the integrator and sampling strategy implements a noise-shaping filter on the digital output code. In the frequency domain, the time-domain output pulses appear as the input signal (or spur) and shaped noise. The noise characteristics in Figure 4 are the key to understanding the modulators frequency operation and the ability of the DS ADC to achieve such high resolution. The noise in the modulator is moved out to higher frequencies. Figure 4 shows that the quantization noise for a first-order modulator starts low at zero hertz, rises rapidly, and then levels off at a maximum value at the modulators sampling frequency (fS ). Using a circuit that integrates twice instead of just once is a great way to lower the modulators in-band quantization noise. Figure 5 shows a 1-bit, second-order modulator that has two integrators instead of one. With this second-order modulator example, the noise term depends on not just the previous error but the previous two errors. Some of the disadvantages of the second- or multi-order modulators include increased complexity, multiple loops,

Figure 5. Block diagram of a second-order DS modulator

Integrator IN + Integrator +

1- Bit ADC

OUT

xi

yi ei
1- Bit DAC

yi = xi 1 + (ei 2ei 1 + ei 2)
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and increased design difficulty. However, most DS modulators are higher-order, like the one in Figure 5. For instance, Texas Instruments DS converters include second- through sixth-order modula tors. Multi-order modulators shape the quantization noise to even higher frequencies than do the lower-order modulators. In Figure 6, the highest line at the frequency fS shows the third-order modulators noise response. Note that this modulators output is very noisy all the way out at its sampling frequency of fS. However, down at lower frequencies, below fD and near the input-signal spur, the third-order modulator is very quiet. fD is the conversion frequency of the digital/decimation filter. Selecting a value for fD will be discussed in Part 2 of this article series.

in the final output of the converter. Part 2 of this article series will discuss how to get rid of this noise with a lowpass digital/decimation filter.

References
1. R. Jacob Baker, CMOS: Mixed-Signal Circuit Design, Vol. II. John Wiley & Sons, 2002. 2. Texas Instruments, Nuts and Bolts of the Delta-Sigma Video Tutorial [Online]. Available: http://focus.ti.com/ docs/training/catalog/events/event.jhtml?sku= WEB408001

Related Web site

dataconverter.ti.com

Modulators: The first half of the story

The modulator of the DS ADC successfully reduces lowfrequency noise during the conversion process. However, the high-frequency noise is a problem and is undesirable

Figure 6. DS modulator noise shaping versus modulator order with a sampling frequency of fS

Third-Order Modulator

Output Noise

fD

Second-Order

Modulator

First-Order

Modulator

fD
Frequency

fS

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Data Acquisition

How delta-sigma ADCs work, Part 2

By Bonnie Baker
Signal Integrity Engineer
A strong addition to the process-control design environment is the delta-sigma (DS) analog-to-digital converter (ADC). This devices claim to fame is its high 24-bit resolution, which provides 224 or about 16 million output codes. Granted, not all of the lower bits are noise-free, but it is not unusual for a DS ADC to have 20 noise-free bits, or about 1 million noise-free output codes. This is at least four times better than the performance of 16-bit converters. Figure 1 shows a block diagram of a DS ADC. As explained in Part 1 of this article series (see Reference 1), the modulator of a DS converter shapes the data in such a way as to allow high reso lution by reducing low-frequency noise. Part 1 also pointed out that the undesirable characteristics of the modulator output are high-frequency noise and a high-speed, 1-bit output rate. Once the signal resides in the digital domain, a low-pass digital-filter function can be used to attenuate the high-frequency noise, and a decimator-filter function can be used to slow down the output-data rate. This article, Part 2, will consider each function independently, although real-world designs intertwine them in the same silicon.

The digital-filter function

The digital-filter function implements a low-pass filter by first sampling the modulator stream of the 1-bit code. Figure 2 shows a first-order, low-pass averaging filter. An averaging filter is the most common filter technique used in DS converters. As can be seen, the digital filter in Figure 2 is a weighted averaging filter. Almost all DS ADCs incorporate a class of averaging filters called sinc filters, named for their frequency response. Many DS devices, especially audio devices, use other filters in conjunction with sinc filters as part of a process called two-stage decimation. Low-speed industrial DS ADCs usually use only the sinc filter.

Figure 1. Block diagram of DS ADC

Sample Rate (fS )

Analog Input

Modulator

fS /fD = Decimation Ratio (DR)

Data Rate (fD) Digital Filter Decimator Filter Digital Output

Digital/Decimation Filter

Figure 2. First-order, low-pass averaging filter

Input b1

Delay b2

Delay b3

Delay bi

Output

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The output rate of a digital filter is the Figure 3. Outputs of a digital filter same as the sampling rate. Figure 3 shows a digital filters outputs. In the time domain (Figure 3a), the digital filter is responsible 7FFFFF for the high resolution of the DS converter. Signal Notice that the 24-bit code train resembles the original signal. However, in the frequency domain (Figure 3b), the digital filter applies 0000000 only a low-pass filter to the signal. In so doing, it attenuates the modulators quantization fS noise; but it also reduces the frequency 800000 bandwidth, as any good low-pass filter will. Quantization Noise With the quantization noise reduced, the signal re-emerges in the time domain. (a) Time domain (b) Frequency domain The signal is now a high-resolution, digital version of the input signal, but it is still too fast to be useful. The designer could have This may seem a bit distressing. Previously, there was a the converter deliver every one of the samples, but it beautiful sine wave that was well-defined with a large would be pointless to do so because: number of samples. Throwing away a large number of This converter would require a very fast controller or those samples leaves a skeleton of the original signal; but, processor. remember, most of those samples are not real. They can While it might appear that there is an abundance of be thought of as the filters work-in-process samples. In high-quality samples at the high sampling rate of the fact, according to the Nyquist theorem, the new skeletal modulator, most of them dont provide any useful inforversion of the signal has exactly the same informational mation, since a low-pass filter has been applied. In other content as the previous waveform, but now it is at a words, the extra samples are interpolations or intermemanageable data rate. Decimating some of the samples diate results. has not caused any information to be lost. The decimator-filter function Figure 4 conceptually shows the decimation process. The digital filters time-domain output in Figure 3a has The second function of the digital/decimation filter is the been brought forward to Figure 4a. Figure 4b shows the decimator. The word decimate was originally used by the decimator-filter functions output signal. Roman army to mean the killing of every tenth man of a This completes the description of the digital-filter and group that was guilty of mutiny. In the case of the digital/ decimator-filter functions in a DS converter. decimation filter, the decimation of the digital filters samples is much more dramatic. In the decimation circuit, Pulling the DS ADC together the digital signals output rate is reduced by throwing Part 1 of this series showed the inner workings of the away or killing portions of the output data. The way to modulator in the time and frequency domains. It also do this is to discard some of the samples. showed how the modulator shaped noise into higher

Figure 4. Digital/decimation filters output from decimation process

7FFFFF

7FFFFF

fS /fD = Decimation Ratio (DR)

0000000

0000000

800000

800000

(a) Input sampling rate (fS)

(b) Output-data rate (fD)

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Data Acquisition

frequencies because of an oversampling sysFigure 5. Increased DR provides a lower-noise, slower tem with negative feedback. As previously output signal stated in the present article, the digital/ decimation filter reduces high-frequency noise and passes the input signal to the outSignal Signal put of the converter at a reduced data rate. The combination of these two components provides a high-resolution ADC. The meaningful variables in this system are the modulators sampling rate (fS ) and the digital/decimation filters output-data fS fD fS fD rate (fD). The ratio between these two variQuantization Quantization ables is defined as the decimation ratio Noise Noise (DR). The decimation ratio is equal to the fS /fD = Decimation Ratio (DR) number of modulator samples per data output. Decimation ratio values range anywhere (a) High DR decreases noise (b) Low DR increases noise from 4 in the Texas Instruments (TI) ADS1605 ADC to a maximum of 32,768 for TIs ADS1256 ADC. Consider the output spectrum of the DS noise that was shaped by the modulator stage and reduces modulator in Figure 5. The modulator samples at a frethe data-output rate of the device to a usable frequency. quency of fS and, in doing so, shapes the quantization noise into higher frequencies. Many DS converters permit There is a strong relationship between the output-data the designer to program the data rate directly by adjusting rate and the converters resolution. If the sample rate is the decimation ratio. Suppose the data rate is chosen to kept constant, lower data rates provide high effective reso lution, or ENOB, at the output of the converter. be some fraction of fS, as shown in Figure 5a. The freDS ADCs have other functions besides the basics in these quencies from 0 to fD, which constitute the output, are in two articles, acting as current sources, voltage sources, the signal band. Note the noise level in the signal band. input buffers, etc. However, examining any DS ADC will In Figure 5a, the effective number of bits (ENOB) is always reveal a modulator and a digital/decimation filter. very high. Since the output-data rate (fD) is determined by the decimator-filter function, it depends on the decimaIn choosing a DS ADC, it is best to start with the fundation ratio (DR), where DR = fS /fD . Figure 5b shows that mentals and then see what else the device has to offer. the value for fD, which has moved to the right, is now References higher. Unfortunately, there is also more noise. Most of the For more information related to this article, you can down noise is in the higher frequencies, decreasing the signal-toload an Acrobat Reader file at www.ti.com/lit/litnumber noise ratio and the ENOB. and replace litnumber with the TI Lit. # for the There is a way to increase the sampling speed (fS ) while materials listed below. keeping the ENOB the same, and that is to increase the master-clock rate. This will also increase fD but will not Document Title TI Lit. # decrease the decimation ratio. Unfortunately, increasing 1. Bonnie Baker, How delta-sigma ADCs work, the master-clock rate will also increase power consumpPart 1, Analog Applications Journal tion. Additionally, most converters have a practical limit (3Q 2011) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SLYT423 for fS beyond which they will not function properly. 2. 16-bit, 5MSPS analog-to-digital converter,

Conclusion
A DS ADC fundamentally includes a modulator and a digital/decimation filter. The modulator converts the analog signal directly into the digital domain by using a 1-bit ADC and oversampling. The modulator topology implements a noise-shaping function that drives the lower-frequency quantization noise into higher frequencies. The low-pass digital/decimation filter throws away the high-frequency

ADS1605/6 Datasheet . . . . . . . . . . . . . . . . . . . . . SBAS274 3. Very low noise, 24-bit analog-to-digital converter, ADS1255/6 Datasheet . . . . . . . . . . . SBAS288

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