Bias Circuits for RF Devices

Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul/

A lot of RF schematics mention: bias circuit not shown; when actually one of the most critical yet often overlooked aspects in any RF circuit design is the bias network. The bias network determines the amplifier performance over temperature as well as RF drive. The DC bias condition of the RF transistors is usually established independently of the RF design. Power efficiency, stability, noise, thermal runway, and ease to use are the main concerns when selecting a bias configuration. A transistor amplifier must possess a DC biasing circuit for a couple of reasons. We would require two separate voltage supplies to furnish the desired class of bias for both the emitter-collector and the emitter-base voltages. This is in fact still done in certain applications, but biasing was invented so that these separate voltages could be obtained from but a single supply. Transistors are remarkably temperature sensitive, inviting a condition called thermal runaway. Thermal runaway will rapidly destroy a bipolar transistor, as collector current quickly and uncontrollably increases to damaging levels as the temperature rises, unless the amplifier is temperature stabilized to nullify this effect. Amplifier Bias Classes of Operation Special classes of amplifier bias levels are utilized to achieve different objectives, each with its own distinct advantages and disadvantages. The most prevalent classes of bias operation are Class A, AB, B, and C. All of these classes use circuit components to bias the transistor at a different DC operating current, or ICQ. When a BJT does not have an A.C. input, it will have specific D.C. values of IC and VCE. These values will correspond to a specific point on the D.C. load line, point named Quiescent Current ICQ.

In the graph above the circuit is said to be midpoint biased since the values of IC and VCE at Quiescentpoint are one-half of their maximum values. Class A single-ended amplifiers are ordinarily used only in small-signal non-power applications. Class A will generally require a constant current bias source to fix the operating point regardless of the RF drive and output. The circuit will have to have some sort of feedback to keep the output current at a fixed level, or a circuit must be created whose current is large compared to the amount of output power required (i.e., it is quasi class A in that the operating point movement is minimal). Simply by decreasing the Icq of the amplifier by a small amount, Class AB operation can be reached. But any Class AB single-ended power amplifier will create more output distortion than a Class-A type due the output clipping of the signals waveform. Class AB or B operations require some form of positive biasing - though the operating point will move with RF drive. This will require an open loop circuit with some sort of compensation over ambient conditions.

Class C will generally require a negative bias of some kindor in most cases, the input of the transistor is tied to ground with an inductor or resistor, which is sufficient to keep the conduction angle correct.

Typical BJT Load-Line Characteristic for Different Bias Classes The most predominant biasing schemes used to obtain both temperature stabilization and single-supply operations are: base-biased emitter feedback voltage-divider emitter feedback collector-feedback diode feedback active-feedback bias All five are found in Class A and AB operation, while Class B and C amplifiers can implement other methods. Biasing Considerations for RF Bipolar Junction Transistors (BJT) Usually the manufacturer supplies in their datasheets a curve showing ft versus collector current for a bipolar transistor. For good gain characteristics, it is necessary to bias the transistor at a collector current that results in maximum or near-maximum ft. On the other hand, for best noise characteristics, a low current is generally most desirable. Finally, one must consider the maximum signal level expected at the input of the transistor. The bias point must be at a sufficiently high current (and voltage) level to prevent the input signal from swinging the collector current out of the linear region of operation. It is assumed that a transistor has been chosen having a sufficient operating current level to prevent the input signal from driving the transistor into the so-called saturated region of operation, which would also be an operating condition that would prevent linear operation. If the amplifier is to work over a range of temperature, have to design a bias network that maintains the D.C. bias point as the operating temperature changes. Two basic internal transistor characteristics are known to have a significant effect on the DC bias point. These are VBE and !. The base-emitter voltage of a bipolar transistor decreases with increasing temperature at the rate of about 2.5 mV/C. Emitter voltage VE tends to minimize the effect because as base current increases (as VBE decreases), collector current increases, and this causes VE to increase also. However, as VE increases, collector current tends to decrease. In the same time, the transistors D.C. current gain ! typically increases with increasing temperature at the rate of about 0.5% per degree Celsius.

The BJT is quite often used as a Low Noise Amplifier due to its low cost. With a minimal number of external matching networks, the BJT can quite often produce an LNA with RF performance considerably better than an MMIC. Of equal importance is the DC performance. Although the devices RF performance may be quite closely controlled, the variation in device DC parameters can be quite significant due to normal process variations. Important for an RF BJT is that variation in hFE from device to device (up to 3 to 1) will generally not show up as a difference in RF performance. Two BJT devices with widely different hFEs can have similar RF performance as long as the devices are biased at the same VCE and IC. This is the primary purpose of the bias network, i.e., to keep VCE and IC constant as the DC parameters vary from device to device. Base-biased emitter feedback works in the following way: The base resistor (RB), the 0.7 V base-to emitter voltage drop (VBE), and the emitter resistor (RE), are all in series;

Base-biased emitter feedback - As the collector current (IC) increases due to a rise in the transistors temperature, the current through the emitter resistor will also increase, which increases the voltage dropped across RE. - This action lowers the voltage that would normally be dropped across the base resistor and, since the voltage drops around a closed loop must always equal the voltage rises, this reduction in voltage across RB decreases the base current, which then lowers the collector current. The capacitor (CE) located across RE bypasses the RF signal around the emitter resistor to stop excessive RF gain degeneration in this circuit. The higher the voltage across RE (VE), the more temperature stable the amplifier, but the more power will be wasted in RE due to VE 2/RE, as well as the decreased AC signal gain if RE is not bypassed by a low reactance capacitor. Standard values of VE for most HF (high frequency, or amateur band) designs are between 2 to 4 V to stabilize VBE. UHF amplifiers and higher frequencies will normally completely avoid these emitter resistors. For better temperature compensation the most common method is Diode Temperature Compensation. Two diodes, D1 and D2, attached to the transistors heatsink or to the device itself, will carefully track the transistors internal temperature changes.

Diode temperature compensation bias

This is accomplished by the diodes own decrease in its internal resistance with any increase in heat, which reduces the diodes forward voltage drop, thus lowering the transistors base-emitter voltage, and diminishing any temperature-induced current increase in the BJT. A very low-cost biasing scheme for RF and microwave circuits, but with less thermal stability than above, is called collector-feedback bias.

Collector feedback The circuit, employs only two resistors, along with the active device, and has very little lead inductance due to the emitters direct connection to ground. Collector-feedback bias temperature stabilization functions so: - As the temperature increases, the transistor will start to conduct more current from the emitter to the collector. - But the base resistor is directly connected to the transistors collector, and not to the top of the collector resistor as in the above biasing techniques, so any rise in IC permits more voltage to be dropped across the collector resistor. - This forces less voltage to be dropped across the base resistor, which decreases the base current and, consequently, IC. For bipolar transistors, Class-C amplifiers permit the use of three biasing techniques: signal external self bias The average Class-C transistor amplifier is normally not given any bias at the base whatsoever, but in order to lower the chances of any BJT power device instability the base should be grounded through a low-Q choke, with a ferrite bead on the base leads grounded end. These biasing techniques will still require an RF signal with high enough amplitude to overcome the reverse (or complete lack of) bias at the Class-C input.

Class-C signal bias

A less common method in Class-C amplifiers is to use an external bias.

Class-C external bias This circuit uses a negative bias supply to bias the base, and a standard positive supply for the collector circuit. The RFC acts as high impedance for the RF frequency itself so that it does not enter the bias supply. Some low-frequency high gain IF amplifiers (Intermediate Frequency) will split the single emitter feedback resistor into two separate emitter resistors, with only one of these resistors having an AC capacitor bypass, while the other one is providing constant degenerative feedback to enhance amplifier stability, reducing the chance of oscillations. This topology allows to solidly setting the gain of the amplifier, just changing the value of R4 resistor.

Stable IF Amplifier Cascode approach is a configuration that is inherently stable. In the example below the first transistor operates common emitter and sees as its load, the low input impedance of a common base stage. The 10k base resistor is common for both stages, and the bias is done through a 2:1 transformer used to get a wide-band matching.

Stable BJT Cascode LNA with resistive bias scheme

Highly Stable Active Bias for High Frequency Amplifiers The most common form of biasing in RF circuits is the current mirror. This basic stage is used everywhere and it acts like a current source. It takes a current as an input and this current is usually generated, along with all other references, by a circuit called a bandgap reference generator. A bandgap reference generator is a temperature-independent bias generating circuit. The bandgap reference generator balances the VBE dependence on temperature, to result in a voltage or current nearly independent of temperature. The most basic current mirror topologies are:

In this mirror, the bandgap reference generator produces current Ibias and forces this current through Q1. Scaling the second transistor allows the current to be multiplied up and used to bias working transistors. One major drawback to this circuit is that it can inject a lot of noise at the output due primarily to the gain of the transistor Q1 which acts like an amplifier for noise. A capacitor can be used to clean up the noise, and resistors degeneration can be put into the circuit to reduce the gain of the transistor. With any of mirror topologies, a voltage at the collector of N.Q1 must be maintained above a minimum level or else the transistor will go into saturation. Saturation will lead to bad matching and nonlinearity. Temperature Reference Circuits The general recipe for making temperature independent references is to add a voltage that goes up with temperature to one that goes down with temperature. If the two slopes cancel, the sum will be independent of temperature. To realize this idea bandgap voltage reference circuits are the most used. It produces an output voltage that is traceable to fundamental constants and therefore relatively insensitive to circuit variations, temperature and supply.

Temperature reference circuit With proper choice of R1 and R2, the output voltage will have zero variation with temperature, providing in the same time at the emitters of Q1 and Q2 a voltage proportional with temperature (thermometer output).

Generally is stated that the output impedance of the bias circuitry should be kept small, in order to increase the linearity of the output bias stage. However, the output impedance is typically designed to have a large resistance in order to reduce the noise contribution from the bias circuitry, and to avoid significant loading on the RF input port. For example, to use an inductor in the bias circuit to form low impedance near DC, and high impedance near the RF signal band. It is difficult to compare different bipolar LNAs if the biasing arrangement is not mentioned. Using an external bias from an external power supply can increase the IIP3 of an LNA compared to an LNA with an on-chip bias.

Active bias LNA The transistor, Q2, increases the accuracy of the current mirror, since the required base current for the LNA and Q1 is not taken from the reference current, IR1. It may be necessary to remove Q2 for low supply voltages, since the current mirror formed by LNA, Q1, and Q2 requires a supply which is at least two times the base emitter voltage. Sometimes high-frequency LNAs uses an emitter degeneration inductor for better matching, and is possible that the series resistance of this inductor to affect the accuracy of the current mirror. The NF of the LNA is increased if the noise from the bias is not properly filtered out. This can be done by using appropriate filtering capacitors. This can be done by using appropriate filtering capacitors as C1 and C2, which shunt the noise from the biasing to ground. If Q3 is a power amplifier mounted on a heatsink, Q2 shall be mounted on its own heatsink for power dissipation, when Q1 shall be mounted on the main heatsink, as close as possible to the RF transistor, in order to perform temperature compensation. A different method used to increase the IIP3 of the LNA by biasing is presented below:

Dual-bias LNA

The dual-biasing is constructed using two different bias paths. The primary biasing is a current mirror and the secondary bias a diode bias feed circuit. With a small signal, the current mirror provides the bias current for the Q3 LNA. When the signal is increased, the Q3 base current increases and the voltage across the biasing resistor R2 increases, reducing the base voltage. As the voltage drops, the current to the base of the input transistor through the diode bias-feed (Q4) increases, compensating the base-voltage drop. Therefore, the LNA linearity and compression point are both improved. This bias circuit features the lowest source impedance of the less complex bias circuits. Therefore, it is recommended for high power device biasing and for other demanding applications. Bias Circuit using supply regulator

The main advantages of the bias source shown in the figure above: The circuit it provides the lowest source impedance at a relatively low cost, The bias voltage remains independent of variations in the power supply voltage Temperature compensation is easy to implement. The diode D1 performs this function and should be in thermal contact with the heat source. Depending on the current requirement and the pass transistor used, Q1 may have to be cooled. It has a positive temperature coefficient to the bias voltage, but the temperature coefficient is negligible compared to the negative coefficient of D1. This permits Q1 to be attached to the main heat sink. R1 and D2 are only necessary if the RF amplifier is operated at a supply voltage higher than 40 V, which is the maximum rating for the regulator. This circuit also provides regulation against supply variations. The source impedance mainly depends on the hFE of Q1. Active bias design for LNAs using lumped elements or distributed elements.

Active-bias LNA Lumped elements

Active-bias LNA Distributed elements

The bias circuit shown has to be carefully bypassed at both high and low frequencies. There is one inversion from base to collector of RF transistor, and another inversion may be introduced by RFC, matching components and stray capacitances, resulting in positive feedback around the loop at low frequencies. Low ESR electrolytic or tantalum capacitor from the collector of Q2 to ground is usually adequate to ensure stability.

Steps designing an active bias for the schematic above: 1. Select an ID current through the diode of 2 mA. 2. Select an appropriate IC current for Class-A bias of the RF transistor amplifier 3. Select a VCC for the active bias network that is approximately 2V or 3V greater than the VCE required for the RF transistor. 4. Select an RF choke (RFC) for the active bias circuit with the appropriate SRF (self resonant frequency) that is greater than the frequency of operation. 5. Select both a silicon PNP transistor with a beta of at least 30 and a low-frequency silicon diode (a PNP transistor is used so that the VCC may be a positive voltage) The idea adding a diode in the circuit is to compensate for the "2.5 mV/C of the PNP baseemitter junction with the same factor introduced appropriately into the active bias circuit.

Active Voltage-Feedback Bias A good biasing scheme is shown below and uses two transistors (PNP and NPN) in a voltagefeedback scheme from the collector to the base of Q1.

Voltage-Feedback Bias The voltage-feedback it maintains the collector of the RF LNA Q1 at one-half the supply voltage plus one VBE (base-to-emitter voltage, about 0.4V). Transistor Q2 measures the voltage difference between the collector of Q1 and the center point of the two resistors R1 and R2, which is amplified and fed back to the base of Q1. Q1s collector voltage holds quite accurately at half the supply voltage plus one VBE because of the gain in the feedback loop. Gain changes with temperature in all of the transistors are corrected for, and no adjustable resistor is required. The bias circuit has to be carefully bypassed at both high and low frequencies.

FET Bias Bias networks are what are used to put a FET at the intended quiescent operating point. For example, you might want to operate a FET in a power amplifier at 12 volts VDS and at 50% of the saturated drain current (IDSS/2). This is the quiescent point. The same as in BJT case there are at least three ways to bias up a FET amplifier to get to the intended quiescent operating point. One option is to have separate DC power supplies for the gate and drain connections, with the gate supply being adjustable, and ground the source. Grounding the source will provide the most gain and efficiency from the FET. In this case generally the gate bias supply is a fixed negative power supply 5 Volts, with an adjustable resistor-divider network being employed to supply the needed gate voltage. Another method of biasing a FET is with an active bias network, generally designed in a feedback configuration to maintain constant quiescent current. Common-source FETs can utilize a common Class-A biasing technique called source bias, a form of self bias.

FET Source Bias With FETs, unlike BJTs, no gate current will flow with an input signal present, so the drain current will always be equal to the source current. However, source current does flow through the source resistor RS, creating a positive voltage at the top of this resistor. Since the FETs source is shared by both the drain and the gate circuits, and the gate will always be at 0V with respect to ground (since no gate current equals no voltage drop across RG), then the gate is now negative with respect to the common source. This allows the FET to be biased at its Class A, AB, or B quiescent currents Icqs, depending on the value chosen for RS, while a capacitor can be inserted across RS in order to restrain the bias voltage to a steady DC value. The Source de-coupling capacitor CS is required to ensure that there is no RF power loss on RS. The downsides to using self-bias schemes are that amplifier efficiency is lost due to the voltage drop of the source resistor.

FET Active Feedback bias example Suppose that we have the following GaAs FET bias circuit:

432MHz GaAs-FET LNA

1. The DC current through diode D1 increases (due to temperature variation or change in device) 2. Then, the voltage drop across R3 will increase, reducing VBE, Q1. 3. The collector current of Q1 drops, reducing the voltage drop across R4. This reduces VGS and ID of Q2 to correct for the change in step 1. Negative -5V supply voltage for biasing GaAs FETs The following circuit is providing a -5V bias voltage from a positive +12V power supply. The inverter is based on a NE555 circuit followed by a push-pull amplifier and a voltage doubler detector. The oscillation frequency is approximately 32kHz, which must be well DC filtered at the output to dont pass through the bias of the RF circuits.

-5V bias voltage from a +12V power supply Biasing of MOSFETs Since MOSFETs have gate threshold voltages up to 5 to 6 volts, they require some gate bias voltage in most applications. They can be operated in Class C (zero gate bias), but at a cost of low power gain. Zero bias is often used in amplifiers intended for signals that do not need linear amplification (such as FM signals and some forms of CW signals), and efficiencies in excess of 80% are not uncommon. In Class B, the gate bias voltage is set just below the threshold, resulting in zero drain idle current flow. The power gain is higher than in Class C but the drain efficiency is 10 to 15% lower. Class B is also suitable only for non-linear amplification. Between classes of operation, one must decide whether the system has power gain to spare and how important efficiency is. At higher frequencies, such as UHF, a good compromise may be Class B or even Class AB. In Class AB, the gate bias voltage is somewhat higher than the device threshold, resulting in drain idle current flow. The idle current required to place the device in the linear mode of operation is usually given in a data sheet. In this respect, MOSFETs are much more sensitive to the level of idle current than are bipolar transistors. They also require somewhat higher current levels compared to bipolars of similar electrical size.

The temperature compensation of MOSFETs can be most readily accomplished with networks consisting of thermistors and resistors.

The ratio of the two must be adjusted according to the thermistor characteristics and the gFS of the FET. The changes in the gate threshold voltage are inversely proportional to temperature and amount to approximately 1 mV/C. These changes have a larger effect on the Idq of a FET with a high gFS than one with a low gFS. Unfortunately, the situation is complicated by the fact that gFS is also reduced at elevated temperatures, making the drain idle current dependent on two variables. The thermistor is thermally connected into a convenient location in the heat source in a manner similar to that described for the compensating diodes with bipolar units discussed earlier.

The circuit above shows a typical MOSFET bias voltage source using the 723 IC regulator. The temperature slope is adjusted by the ratio of the series resistor (R5) and the thermistor (R6). In addition to maintaining a constant bias voltage, this circuit also features a bias voltage regulation against changes in the power supply voltage. MOSFET Closed-Loop Biasing

Figure above shows a Closed-Loop system for MOSFET biasing. It provides an automatic and precise temperature compensation to any MOSFET regardless of its electrical size and gFS. No temperature sensing elements need be connected to the heat sink or to the device housing. In fact, FETs with different gate threshold voltages can be changed in the amplifier without affecting the level of the idle current. This means that the gate threshold voltage can vary within wide limits over short or long periods of time for a variety of reasons. In addition to temperature, other factors affecting VGS(th) might be moisture, atmospheric pressure, etc. The principle of operation of the circuit shown as follows: the idle current of the MOSFET amplifier is initially set to Class A, AB, or anywhere in between these bias limits by R7, which also provides a stable voltage reference to the negative input of the operational amplifier U1. Current flows through R1 with a

consequent voltage generated across it. This voltage is fed to the positive input of U1, which results in the output of U1 following it in polarity, but not in amplitude. Due to the voltage gain in U1, which operates in D.C. open-loop mode, its output voltage excursions are much higher than those generated across R1. Thus, if the current through R1 tends to increase for any reason, part of the output voltage of U1 fed to the amplifier gate bias input will adjust to Cascode MOS LNA Bias

Cascode MOS LNA Cascading transistor M2 is used to reduce interaction of the tuned output with tuned input. Transistor M3 essentially forms a current mirror with M1. The current through M3 is set by the supply voltage and R2 in conjunction with VGS of M3. The bias resistor R1 is chosen large enough that its equivalent noise current is small enough to be ignored. In a 50 ohms system values of several hundred ohms to kilo ohms or so are adequate MMIC Amplifier Biasing

Typical MMIC internal schematic (DC blocking caps, Rbias and RFC are external components) The current-biased MMIC will attempt to draw more current as the temperature rises. The biasing is primarily determined by the current, where the voltage is relatively unimportant. The effectiveness of this temperature bias control is dependent on the voltage drop across RBIAS, a value of up to 4 V may be required for proper stabilization across a minus 25C to a plus 100C temperature range. If the RBIAS does not add up to 600# or more, then the gain of the MMIC stage will suffer. If RBIAS does not compute to be at or over 600#, then an RFC should be added in series with RBIAS to increase the output to this value, or approximately RBIAS + XL > 600#. These amplifiers are unconditionally stable at all frequencies, and they can be easily cascaded for higher gain. The inductor bias-feed circuit is preferable to obtain low-noise performance, high gain, and linearity. By using an inductor as the bias feed, becomes constant and can increase in the large-signal region to extend its output power.

Diode and Transistor bias for Linear Power Amplifiers The use of Class-A and Class-AB amplifiers for linear power amplification relies on the use of a standing bias current, applied to the base (in case of BJT) in order to bias the RF device into partial or full conduction. This bias current must remain constant, despite the varying envelope of the input signal to the amplifier, which will cause significant variations in the collector current (and hence base current) required by the device. When considering low power RF amplification, simple resistive biasing techniques may be used however, such techniques are not appropriate for medium or high-power amplifiers due to their requirement for low impedance, relative high current, voltage source.

Class-AB Power Amplifier Diode biasing provides a low impedance voltage source, and requires a high standing current to flow through it than the bias current required by the transistor. Whether employing diode or transistor bias, it is essential to thermally connect these components to the RF transistor itself. This allows the semiconductor bias components to track the power amplifiers temperature variations, and thus increase/ decrease the 0.7 V placed across Q1s base, maintaining the PAs collector current at a steady DC level. (As the temperatures rise, a silicon semiconductor junctions voltage decreases from its room temperature value of 0.7 V). Further, in order to force PA bias stability no matter what the input and output RF power levels may be, the standing current through the diode or transistor bias components must be high enough to permit a steady voltage to be maintained across the PAs base.

Amplified Diode Bias The clamping diode circuit presented above can be improved by the addition of an emitter follower to amplify the diode current, and hence reduce the required current through the diode by a factor to the current gain of the transistor used. The circuit employs two diodes in series, since one is required to compensate for the base emitter voltage drop of the transistor.

Bias Modulation Effects The function of a bias network is to supply an appropriate (and constant) voltage or current to the gate or base of the device. If the RF signals or their modulation are concerned, it should appear to be a high impedance at RF, and possibly a very low impedance in the case of modulation signals. The bias design should not allow such signals to pass to any part of the power supply and the reflected back to the input of the active device. Signals at the modulation frequency (or harmonics) are generated by nonlinearities in the base or gate of the active device and these are often reflected, rather than absorbed by matching network. These modulation frequency signals must be absorbed by the bias network and not reflect back to the gate or the base of the device, otherwise there will be a modification of the IM products, and in the symmetry of the side shoulders. Low Source-Impedance Active Biasing Complex Thermal Compensated Bias circuit for Class-AB BJT Power Amplifiers

This biasing scheme for RF power transistor provides near-constant low-frequency (1MHz) smallsignal impedance presented at the base of RF transistor. The R2/R3 ratio it will set the bias current. This bias scheme is capable of providing independent control of bias impedance and class of the power amplifier for optimum efficiency and linearity.

Power MOS-FET bias

Biasing Power FET devices is usually simpler than biasing BJT devices. In many cases is sufficient to provide a bias voltage directly on the gate through suitable impedance. This impedance must be capable of minimizing the amount of RF feeding into the bias supply.

A typical network consists of a voltage supply (a variable voltage regulator) fed via a bias resistor whose primary function is to aid the decoupling of the gate from the bias supply, and a quarter-wave transmission line, which provides the RF isolation between gate and the bias supply. Power GaAs MESFET bias Optimizing of the MESFET for maximum output power requires the device to be capable of sustaining large peak-voltage and current amplitudes. A typical MESFET current vs voltage (I-V) illustrates that with positive gate bias, the MESFET can conduct current levels of 15% to 20% above saturated drain-source current Ids.

Typically Power MESFET Load line The maximum current is denoted as Idssm, whereas Idss is measured at zero gate-source bias. The transition from the linear operating region to the current saturation region occurs at the drainto-source voltage above the knee voltage Vk. The highest voltage that can exist between the drain and the source is the gate-to-drain breakdown voltage Vgdb minus the pinch-off voltage Vp. This maximum voltage will be reached only as the drain current approaches zero. The drain-to-source voltages below Vk should be avoided because they imply high microwave losses in the non-saturation region.

Power LDMOS Bias LDMOS transistors are CMOS devices designed for high frequency, high voltage operation. LDMOS transistors exhibit an annoying characteristic called bias or IDQ drift. All LDMOS parts exhibit the hot carrier injection effect to some degree. Hot carrier injection results in charge build-up in the gate-drain region, which causes the gate field to change. This is seen by the user as a change in the quiescent current (IDQ) with a fixed gate voltage. The use of adaptive bias circuits it requires a circuit that adjusts VGS periodically to maintain a constant IDQ. A simplified circuit of an LDMOS amplifier bias circuit is shown below:

The DC bias on these amplifiers is set by applying a DC voltage to the gate (VGS) and monitoring the drain current (IDD). Ideally, this IDD will be constant over temperature, but since the VGS of LDMOS amplifier devices varies with temperature, some type of temperature compensation is required. One method of setting this DC bias involves using an adjustable reference, DAC, or Digital potentiometer combined with a temperature compensation source, such as a transistor VBE multiplier. A new way to bias an LDMOS amplifier involves digitally converting temperature information and adjusting the DC bias using Look-Up Table (LUT) memory. The memory is programmed at final test using measured parameters from the amplifier circuit being tested. DC bias performance is optimized over the required temperature range. A very simple and effective way to construct the lookup table is to make measurements at two temperatures that represent the target range for the product, and then interpolate values for the other temperatures with a linear regression. A more accurate method would include more temperature points and then interpolate between those points. LDMOS amplifiers also have a characteristic IDD drift overtime (drain current reduces for a given VGS), as well as temperature. This can be addressed with lookup table correction with a slightly higher constant bias offset, so that over time the IDD will drift closer to the target bias value, not further away. LDMOS PA bias example The gate-source bias voltage is supplied through a voltage divider set by adjusting the potentiometer P1 to control the optimum Q2 drain current Idq. In this example Idq was set to 750 mA to achieve the performances. Deviations from this optimal bias point will result in suboptimal trade-offs of performance parameters such as gain compression and efficiency. The device is more linear, but less efficient for the tune shown here at higher drain voltages. If the user has severe efficiency requirements, 26V may be more suitable on the drain. If the user has more requirements for linearity, 30V on the drain may be more appropriate.

LDMOS Power Amplifier with active bias and regulator

Oscillator Bias Circuits For the design a low phase-noise oscillator, the biasing circuit should be properly regulated and filtered to avoid any unwanted signal modulation ore noise injection. Variations on the supply voltages or currents may also cause undesirable output power fluctuations and frequency drift. Oscillator biasing of its amplifier section is employed for multiple reasons: To allow the use of a single VCC; to positions the bias point for a certain class of operation to swamp out any device variations in beta to stabilize the active device over wide temperature variations. some oscillator topologies use noise feedback bias for phase noise cancellation. For accurate design of the bias of the oscillator to meet the gain and phase conditions (G$0dB, Phase shift around the loop=0) the closed-loop feed back can be broken in an open-loop analysis. The circuit can be further tuned for optimal performance, in terms of gain and phase margin. Few bias conditions shall be followed for best oscillator design: Minimize the oscillators transistor bias current as much as possible, since this can substantially lower the 1/f (flicker) noise frequency of the active device, as well as optimize the BJTs noise figure. Avoid driving the oscillators transistor too far into compression. Most oscillators are biased for equivalent Class-A operation. For near-class-A operation oscillator, if limiting is due to cutoff, the oscillation amplitude is proportional to the emitter bias current. If limiting is due to saturation, the amplitude is proportional to the quiescent dc collector-emitter voltage. These parameters may be established with nearly any desired degree of stability by the selection of bias network type and complexity. In a well-designed near-class-A oscillator, the frequency is determined primarily by the resonator. As the loaded Q is increased, the active-device reactances become less significant in determining the oscillation frequency. Changes in these parameters from device to device, with temperature and with supply voltage, have less effect. A simple test of how well the active-device reactances are isolated from the resonator is to observe the operating frequency as the supply voltage is varied. The simplest method of ensuring near-class-A operation is to design the resonator amplifier cascade with small excess loop gain. The problem with this approach is ensuring that the loop gain does not fall below unity with temperature, device, loading, or other circuit changes. A second problem is that starting in an oscillator with low loop gain is slower. Oscillator with Noise Feedback cancellation The DC control PNP transistor Q2 acts both as a DC bias stabilization transistor and a noise feedback. This type of feedback bias circuit can provide a drastic noise improvement within the loop bandwidth of the circuit used. The noise sampling is done in the collector of Q1. Q3 connected as a diode provide temperature stabilization. The noise improvement can be expanded to 1 MHz off the carrier if the feedback circuit has the appropriate gain and exactly 180 phase shift within the required bandwidth.

150MHz Oscillator with Noise cancellation feedback bias Class-C Power Oscillators When high output power is required, and stability and noise are of less concern, the oscillator may be biased for class-C operation.

High Power Class-C L-band Oscillator This oscillator has an output power of 2 watts with an efficiency of nearly 30%. The bias is very stiff. There is no collector resistor and the emitter resistance is only 7.8 ohms. High peak currents, limited primarily by the transistor, flow for a small fraction of the waveform period, but supply substantial power to the tank. RF Bias Circuit Issues Any emitter bias resistor and emitter capacitor can create low-frequency instability and bias oscillations, as well as increasing the NF and decreasing the gain of an amplifier. This demands that RF transistors have a directly grounded emitter lead, with no emitter feedback caused by the lead wire inductance. Thermal compensation is a concern for most bias circuitries because the bias point for a particular quiescent current will change with temperature. All devices experience this phenomenon, and in some cases (Bipolar transistors) the current gain will change with a positive coefficient eventually causing device destruction if the thermal effects are not accommodated in a bias circuit. While a BJT will change at fixed rate of "2.4 mV/C, a FET has an inconsistent bias point rate of change with temperature and therefore will have to be empirically measured over the expected operating temperature range for the device chosen. Supply Modulation Effects - The variation in the current drawn from the power supply for a linear RF power amplifier ranges from almost zero for Class-A amplifiers, to the full current capability of the supply, for Class-B amplifiers. These large current variations should be isolated from the power supply circuitry (which usually has a poor RF and envelope frequency response) by means of the decoupling network. This filter network should be mounted as close as possible to the required point to ensure that all envelope frequencies are adequately decoupled.

References: 1. RF Circuit Design - C.Bowick 2. High Linearity RF Amplifier Design P. Kenington 3. Oscillator Design and Computer Simulation - R. Rhea 4. Radio Frequency Integrated Circuit Design J. Rogers, C. Plett 5. Low-Noise Amplifiers for Integrated Multi-Mode Direct-Conversion Receivers J. Ryynanen 6. The Design of CMOS Radio Frequency Integrated Circuits T. Lee 7. Complete Wireless Design C. Sayre 8. RF and Microwave Circuits, Measurements, and Modeling M. Golio, J. Golio 9. Microwave Circuit Design Using Linear and Nonlinear Techniques - G.Vendelin, A.Pavio, U.Rohde 10. Radio Frequency Transistors - N. Dye, H. Granberg 11. Crystal Oscillator Circuits R. Matthys 12. RF/Microwave Circuit Design for Wireless Applications U. Rohde, D. Newkirk 13. A Comparison of Various Bipolar Transistor Biasing Circuits AN1293 Agilent 14. Microwave Journal 1996 - 2009

Frequency Multipliers
Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul

There are few approaches how to generate a high frequency signal for microwaves frequencies.
Direct Signal Generation First approach is to generate the high frequency directly, at the fundamental, using an oscillator tuned on the desired frequency. Few sensitive issues appears here due to high working frequency as, stability, jitter, phase noise, pulling, pushing, low output power, and cost of the active component to meet the performances. A FET oscillator may be stabilized by a dielectric resonator. Problems may involve in this situation are: phase noise, frequency stability and accuracy.

Sub-Harmonic Mixer Another approach how to minimize the issues of a high frequency oscillator is to use a Sub-Harmonic mixer.

Sub-harmonic mixer Sub-harmonic mixers are useful at higher frequencies when it can be difficult to produce a suitable LO signal. They have the LO input at frequency = LO/n. Sub-harmonic mixers use anti-parallel diode pairs and they produce most of their power at odd products of the input signals. Even products are rejected due to the I-V characteristics of the diodes. Attenuation of even harmonics is determined by diodes balance. The diode matching is critical in this type of mixers. The short circuit LO/2 stub at the LO port is a quarter of a wavelength long at the input frequency of LO/2 and so is open circuit. However, at RF frequency this stub is approximately a half wavelength long, so providing a short circuit to the RF signal. At the RF input the open circuit LO/2 stub presents a good open circuit to the RF but is a quarter wavelength long at the frequency LO/2 and so is short circuit.

Up-Conversion Mixer The third option to generate a high frequency signal is to use an up converter. The design of an up converter has typically received much less attention in terms of design methodology than down converter design, which is common approach in most of the receiver designs. There are some aspects to up converter design which are not relevant to down converters, and vice versa. An up-conversion mixer requires high linearity and low noise to minimize the amount of spurious power spread into adjacent channels. Have to take careful attention at LO amplitude, and LO-to-RF isolation. A good approach for an up-conversion mixer is the balanced mixer which provides good commonmode rejection to suppress LO feed-through and good linearity. The LO level should provide a reasonable compromise between conversion gain and LO power, but should not limit the 1 dB gain-compression input voltage.

Balanced up-conversion mixer

Frequency Multipliers
Another alternative method to generate high frequency signal power with low phase noise is to generate a high-quality lower frequency signal and employ a frequency multiplier to deliver the high frequency output at the desired frequency. This approach is the subject of this paper. Frequency multipliers will always be a way of generating the highest frequencies. A frequency multiplier has the property that the frequency of the output signal has an integer multiple of the input frequency.

This approach is commonly adopted in microwave transceivers.

Frequency multiplier based microwave transceiver block diagram

Even if a multiplier introduces no Phase Noise of its own, the process of frequency multiplication even by an ideal, noiseless multiplier, inevitably increases the Phase Noise.

The reason for this unfortunate characteristic is that a frequency multiplier is in fact a phase multiplier, so it multiplies the phase deviations as well as the frequency of the input signal. A square-wave contains odd harmonics. However, by varying the duty cycle of the waveform, so that rectangular-wave results, even order harmonic content can be introduced. The 2nd harmonic content of a rectangular-wave peaks when the duty cycle is 25%, and a 3rd harmonic peaks when duty cycle peaks 16%. The minimum Carrier-to-Noise degradation, CNR, in decibels, caused by an ideal frequency multiplier is: CNR[dB] = 20*LOG (N) where N is the multiplication factor. Thus, a frequency doubler (N=2) degrades CNR at the input signal by at least 6dB and a quadrupler (N=4) degrades CNR by at least 12dB.

Multiplying a very stable low-frequency reference signal can still produce signals with better Phase Noise than producing them directly in the microwave frequency range. For example typical Phase Noise of a 10 MHz Crystal Oscillator is: -170 dBc/Hz @ 100 kHz offset. Using a multiplier chain (10 x 24 = 240) to get a 2.4 GHz signal, degrades this Phase Noise by 20*LOG(240) = 48 dB, yielding: -170 dBc/Hz + 48 dB = -122 dBc/Hz @ 100 kHz offset. Compare this Phase Noise to a standard LC-tank oscillator working directly at 2.4 GHz, which has a typical Phase Noise of -100dBc/Hz @ 100 kHz offset.

A frequency multiplier circuit should contain a nonlinear device and filters that enable to select the desired component at the output and separate the source from the generated harmonics.

Frequency Multiplier Chain with Filters The nonlinear device will produce voltages of higher order from the current of the first harmonic. One of these voltages is of the desired order and will be allowed to exit through the band-pass filter. Low-pass and band-pass filters will present high impedance to all unwanted harmonic voltages. But it turns out that if we allow the currents of the other harmonics to flow, the intermodulation products of those harmonics will contribute to the desired harmonic of the output frequency. That means we should try to short the currents of the non-desired harmonics. As we want to deliver as much power as possible to the load the frequency multiplier should be matched at the input (for the input frequency) and at the output (for the output frequency).

To obtain higher order frequency multiplication we can cascade several multipliers. This can increase conversion efficiency but also increases complexity. There are different possibilities concerning the nonlinear device: We need a device with a nonlinear characteristic in order to produce higher order harmonics. The nonlinear characteristic might be a nonlinear I-V or C-V relationship. Usually wideband multipliers use a nonlinear I-V characteristic, but when we want to design a frequency multiplier with high efficiency, and not high bandwidth, we prefer the nonlinear C-V characteristic. For example a varactor diode has a nonlinear C-V characteristic.

Frequency Multipliers Waveforms Any non-sinewave repetitive waveform contains energy at harmonics of the fundamental frequency. The task is to create a non-linear circuit that produces a waveform with significant signal strength at the desired harmonics. Figure below shows the amplitude terms (peak value of the nth harmonic sine wave) for various waveforms.

Harmonic amplitude terms for various waveforms (C. Wenzel) Can be seen that waveforms with fast edges have larger high frequency harmonics. Harmonics without vertical edges have n2 in the denominator, but the waveforms with fast edges only have n in the denominator. The timing (duty-cycle) between the positive and negative edges of a pulse determines which harmonics are emphasized. For example, a 50% duty-cycle square-wave has only odd harmonics. In this situation the timing is wrong for the buildup of even-harmonic energy, but a 25% duty-cycle contains large even harmonics: the edges occur at the right time to reinforce certain even harmonics.

Figure below shows the harmonic content of a square pulse as a function of its duty-cycle.

Square Pulse Harmonic content vs Duty-Cycle (C. Wenzel) As was mentioned before the chart suggests that the most 2nd harmonic energy will be generated when the duty-cycle is 25%. But it can also be seen that if the duty-cycle is increased to 33% then the third harmonic drops to zero which could simplify output filtering with little drop in the desired 2nd harmonic.

Frequency Multipliers Characteristics Conversion Loss and Maximum Input Signal Power Semiconductor diodes used in microwave frequency multipliers are essentially lossy passive devices and for this reason they dissipate energy. Embedding circuits also dissipate energy. As a result, multipliers input/output power conversion efficiency is less than unity. Conversion Loss used to characterize microwave frequency multipliers conversion efficiency is defined as the ratio of the available source power Pin_source to the output harmonic power Pout_harmonic delivered to the load. Conversion Efficiency is defined as the ratio of the output power Pout delivered to the load to the available power of the input source Pin, and usually is expressed in percent. The goal of the circuit design is to minimize the conversion loss (or maximize the conversion efficiency) for a given device and input/output frequencies. When get low conversion efficiency, virtually all the input power is dissipated in the nonlinear element. The maximum input power is limited by the device power handling capability and must be clearly stated when specifying a frequency multiplier. Source and Load Impedance One of the conditions for a diode frequency multiplier to achieve minimum conversion loss is that optimum source and load impedances should be provided to the diode. The source impedance should be very close to the complex conjugate of the multiplier input impedance Zin to minimize reflection loss at the input. The load impedance should be equal to the optimum load value, otherwise leads to an increased conversion loss or decreased output power. Bandwidth BW represents the output or input frequency range over which conversion loss is in the specified limits. Harmonics A nonlinear device produce undesired harmonics along with the desired ones, and this might affect the performance of the system where the multiplier is used. Noise Conversion In all practical situations the resulting noise sidebands are subject of frequency conversion together with the carrier. The multiplier devices add their own noise, and is important to predict the resulting output noise spectrum. Phase Noise Conversion All frequency multipliers will increase the phase noise by the same factor (N) that they multiply, because frequency and phase are both multiplied. In dB this would be 20 log N.

Diode Frequency Multipliers

Diode frequency multipliers can be generally classified as being of varistor (Schottky barrier diode) or varactor type. In the first case, frequency multiplication is performed by a nonlinear resistance or conductance with consequent poor conversion efficiency but a very large potential bandwidth. In the varactor case a nonlinear reactive element (with nonlinear capacitance) is used. Varactor type multipliers have high potential conversion efficiency, but exhibit a narrow bandwidth and a high sensitivity to operating conditions, and sometimes stability problems. In theory, a cascade of low-order multipliers usually has greater efficiency than a single high-order multiplier, but must consider the additional losses in cascading two multipliers (it is invariably necessary to use an isolator between them), and especially the additional cost.

Resistive (Varistor) Frequency Multipliers Resistive frequency multipliers use the nonlinear I-V characteristic of a Schottky-barrier diode to distort a sinusoidal waveform. This distortion generates harmonics. The more is distorting the input sinusoid, the greater the harmonic currents in the diode, but the maximum still not very great because resistive frequency multipliers are not very efficient. In theory a diode doublers have 6dB conversion loss (1/N2) but in reality the conversion loss is about 10dB and there is no reason to make higher-harmonic resistive multipliers. The advantage of resistive multipliers is, they are very broadband.

Simplified model of a Resistive (diode) Frequency Doubler The parallel LC resonators are ideal because they short-circuit the diode at the unwanted harmonics, decoupling the input from the output, and put the diode in parallel with the input at the fundamental frequency and in parallel with the output at the second harmonic. The inductor can be tapped to optimize the source and load impedances of the diode. The frequency doubler using microstrip lines presented below is suitable for microwave frequencies. - The circuit use a /4 at fo, short-circuited through a stub at the input side of the Schottky diode (which is equivalent to /2 at 2xfo), which is used to create a short-circuit at 2xfo to prevent the output power generated in the diode from traveling backward. - Similarly use a /4 at fo open-ended stub at the output side, which creates an RF short at fo and causes the input signal penetrating through the diode to be reflected back to the diode. - A section of the transmission line is used as an inductor to resonate the diode junction capacitance. - The /4 impedance transformers at the input and output are used to transform 50 ohms source and load to optimum diode impedance terminations.

Microwave Microstrip Frequency Doubler Varactor Diode Frequency Multipliers A nonlinear reactance also can distort the sinusoidal signal. The pros and cons of varactor multiplier are the opposite of those of resistive multiplier. A varactor is capable of higher efficiency and higher power than a resistive multiplier, theoretically 100% for all harmonics, but they are very narrowband. A design issue of varactor multipliers is they are extreme sensitive to almost every parameter of the circuit, and small changes in the circuit parameters (tuning reactances, bias voltages, input power level, etc) change the output power. Making a varactor multiplier work (and keep working) needs a lot of empirical tuning. Varactor diode frequency multipliers in general generate very little noise (phase- as well as amplitude noise). The only noise source is the thermal noise of the series resistance of the varactor and the circuit loss resistances.

 The power capability of a varactor multiplier is limited by the devices break-down. The varactor always has a parasitic resistance in series, which dissipates power. In order to minimize the loss power, one would tend to present an open for all the undesired harmonics, resulting in zero current and therefore no loss. At the example of the pure square-law diode we see that it produces only a 2nd order harmonic directly. This is the reason to present a short to the undesired (intermediate) harmonics. The shorting circuits are called idlers. Without idlers the varactor multiplier does not generate harmonics efficiently beyond the 2nd harmonic. If a current at the 2nd harmonic is prohibited, we dont get the desired higher order harmonics. If current is allowed at the 2nd harmonic, it will mix with the first harmonic and generate therefore higher order harmonics. A varactor tripler (x3) can be obtained only with a second harmonic idler. A varactor quadrupler (x4) could have a 2nd harmonic idler, or both a 2nd harmonic and a 3rd harmonic idler. A varactor quintupler (x5) would likely have at least 2nd and 3rd harmonic idlers. Idlers are usually realized as short-circuit resonators that are separate from the input and output matching circuits. In practice, idlers are usually realized by a series resonance that is chosen more for its convenience than for high performance. Frequently, the series resonance of the varactors package is used as an idler at high frequencies, and tuning elements are often included to tune the resonance precisely to the desired harmonic. To minimize power dissipation and thus to obtain high efficiency, is essential to use high unloaded Q (low-loss) idler resonators. Both phase noise and amplitude noise are strongly dependent on the level of the input signal pumping the diode. Varactor frequency multipliers are relative unstable. Their instability is a kind of chaotic process, not a simple oscillation. Controlling the broadband embedding impedance characteristic very carefully is the best way to insure good stability. In particular, the input source and output load must be linear and not vary with input or output level. One must not drive a mixers LO port directly from a multiplier, or the multiplier directly from another multiplier; an isolator should be used. The input and output networks must not have any spurious resonances. Introducing a resistor in the diodes DC return path, this current can be used to bias the diode. The resistor also helps to reduce the sensitivity of the output power level to the input power level; as input drive is increased, the resulting increase in DC current further reverse-biases the diode, reducing the multipliers efficiency and leveling the output power. The design of the bias circuit often has a strong effect on stability. Low frequency resonances in the bias circuit are a common cause of instability.

Lumped elements Frequency Tripler

Distributed Elements Frequency Doubler

A variant of varactors are Schottky-Barrier varactor diodes which can obtain output frequencies of up to several hundred of GHz.

One of the most important advantages of Schottky-Barrier based multipliers is the generation of odd harmonics without filtering the even ones. This capability is based on the symmetry of the electrical characteristics for unbiased devices. Thus, the load impedances for even harmonics have no effect on the efficiency characteristic.

Step Recovery Diode and PIN Diode Frequency Multipliers Step Recovery Diodes (also called snap-off diodes) are based on a PIN configuration. They are commonly employed in the design of frequency multipliers of high order. Step Recovery Diodes have relatively little capacitance change under reverse bias and are used for higher efficiency applications. A conventional step recovery diode multiplier consists of a diode, a biasing resistor, and matching filters at input and output. The output filter reflects the un-tuned harmonics back to the diode where they mix to form additional power at the tuned frequency. Step Recovery Diodes do not require idler circuits to enhance efficiency (as varactors). The SRD multiplier is a reactive multiplier and theoretically doesnt have the efficiency limitation (1/N2) as resistive multipliers. In the design of high-order frequency multipliers, the efficiency of Step Recovery Diodes is much higher than that of varactor diodes. There is, however, a limit to the output frequency of the multiplier circuit. Single Diode multiplier is useful mainly for low-cost, low-performance applications or high frequency waveguide structures where fundamental frequency is easy to reject. A single diode multiplier has the advantage of easy to provide DC bias to it, which will help optimizing the multiplier. A conventional diode multiplier can use one diode or an anti-parallel pair of diodes. The additional diode results in the suppression of even order products, the enhancement of odd order products, and the elimination of the bias resistor.

Single diode multipliers lumped and distributed elements

Single Diode Multiplier

Anti-Parallel pair of Diodes

Balanced Diode Multipliers have significant advantages compared to single-ended multipliers; the most important are increased output power and inherent rejection of the fundamental frequency and of certain unwanted harmonics. The input or load impedance of a balanced multiplier in some cases differs by a factor of two from that of a single-diode multiplier; therefore, a balanced multiplier sometimes provides more satisfactory input or load impedance. The antiparallel diode connection is probably the simplest form of a balanced multiplier; it rejects even harmonics of the input frequency and consequently can be used only as an odd-order multiplier. In an antiparallel-diode multiplier, each diode effectively short circuits the other at the second harmonic, so each diode acts as a type of idler for the other. This circuit does not reject the fundamental frequency, however, so it requires an output filter.

x5 Frequency Multiplier using anti-parallel PIN diodes

The above circuit is an x5 multiplier operating from a 100 MHz input at +13 dBm, and frequency output at 500MHz and level at about -6dBm. The input was matched with a shunt inductor, and other passive components were added to the output to provide filtering of unwanted signals.

Because the stability of a varactor multiplier is sensitive to small unbalance between the diodes, varactor multipliers are rarely realized as anti-parallel circuits.

Frequency Tripler using Step Recovery Diodes The circuit below shows a singly balanced multiplier using a balun transformer. The difference compared to a DC power supply circuit (which looks like) is, that in a power supply we are looking only for DC component, filtering all the harmonics, when here we are looking for 2nd harmonic, shorting the DC current using an RF choke.

Singly Balanced frequency doublers using: Transformer balun, Microstrip balun and Rat-Race Hybrid The Bridge Rectifier circuit is a practical way to realize resistive frequency doublers. The design of these multipliers is not the same as the design of a diode ring mixer because the diodes are connected as in a different manner. The ring mixers require baluns when the bridge rectifier requires transformers. The voltage and current waveforms in the balanced bridge multiplier are identical to those of a full-wave rectifier in a DC power supply. The current consists of a train of half-sinusoidal pulses, which has no odd harmonic components. Thus, the multiplier inherently rejects the two most troublesome harmonics, the first and third, and the fourth is usually weak enough to require little or no filtering.

Bridge Diode Frequency Doubler Charles Wenzel got an RF Design Award for the bridge frequency tripler presented below.

Wenzel Bridge Diode Frequency Tripler How the circuit works: The heart of the multiplier is a sinewave to squarewave converter circuit, which basically is simply a full-wave bridge diode (Schottky barrier) with an inductor short-circuiting the DC terminals. The inductor is chosen to have high impedance at the operating frequency so that an AC input results in DC in the inductor. This DC flows through alternate pairs of diodes due to the commuting action of the input voltage. Therefore, if one AC terminal of the bridge is driven with low impedance sinewave, the other AC terminal will supply a squarewave to a low impedance load. The load must have low impedance since the compliance of this current source is exactly equal to the input voltage. Because the diodes switch at the input signals zero crossing the circuit introduce a minimum of AM/PM conversion. The input matching network it provides a low impedance to ground for the switching current; and it isolates the input from the switching current. The output network presents the required low impedance to the bridge while directing the desired harmonic to the output. The conversion efficiency is as high as diode frequency doublers, even though the multiplication factor is higher.

Active Frequency Multipliers

The main reason using active frequency multipliers is they got better efficiency compared to diode frequency multipliers, at the expense they have worst noise levels compared to varactor diodes. In contrast to diode multipliers which always exhibit loss, FETs or BJTs multipliers can achieve conversion gain over broad bandwidth while getting also good DC to RF efficiency. The same as amplifiers the active frequency multipliers work in different classes. A practical form for an active frequency multiplier is to operate in equivalent Class-B power class, where they are very stable and have good gain, efficiency, and output power.

 An active FET frequency multiplier generates harmonics by rectifying the sinusoidal input signal when is biased near its turn-on point (pinch-off), and the input sinusoid turns the device on over part of its cycle. The condition is obtained by applying a positive drain voltage and a negative voltage to the gate. A practical application is to replace the negative supply to a self-bias source resistance, and a gate grounding resistor. The duty cycle of the input signal is adjusted to maximize the desired output harmonic. The higher the harmonic, the shorter the duty cycle must be. For a frequency doubler the optimum duty cycle is about 25% (1/4) when for a frequency tripler is about 16% (1/6). Figure below shows the circuit of a basic broadband frequency multiplier that uses an ideal FET.

Broadband Active Frequency Multiplier (FET) The output resonator is tuned to the nth harmonic of the excitation frequency, so it short circuits the FETs drain at other frequencies, especially the excitation frequency (fo) by using an /4 open stub. The gate-bias voltage Vg in an efficient FET multiplier must be equal to or less than (more negative than) the threshold voltage, Vt. In this case the FETs channel conducts only during the positive half of the excitation cycle, and the drain conducts in pulses; the shape of the pulses is approximately a rectified cosine. The duty cycle of the pulses varies with the DC gate bias, Vg. If Vg = Vt the duty cycle is 50%, If Vg < Vt (the usual situation), the FET is turned off over most of the excitation cycle. The duty cycle in this case is less than 50%. If Vg is much smaller than Vt the magnitude of the peak reverse voltage establishes a limit on the difference.

The second important bias point (after Class-B) is with zero gate voltage, which sometimes is referred as Class-A multiplier. This bias point should give the same performance as the pinch-off, if the gate voltage swings from zero to pinch-off and a low-impedance is connected to the drain. Microwave transistors are unconditionally stable only within certain frequency ranges, usually above a certain minimum frequency, and we know that the load termination at the fundamental frequency has a major effect on circuit stability. Because the load termination controls the series and parallel resonance of the transistor parasitics, and is controlling the peak of the rectified current or the distorted drain voltage, it will affect the multiplier gain, input impedance and bandwidth. The proper drain termination is the one that induces the highest peak current. This is obtaining by short-circuit at the fundamental frequency. Ideally the load should be short circuit at all harmonic

frequencies, but the presence of a load at a specific harmonic deviates the signal trajectory in the input plane and the load line becomes a function of frequency. Sometimes using other terminations, especially an open-circuit drain termination at the fundamental frequency, has advantages over a short circuit. The primary advantage of using other terminations is that greater gain can be achieved, although the increase in gain usually is the result of undesirable feedback and getting unpredictable oscillation. To get a good conversion gain the input power should not be very high. The required input power is proportional to square of fo (fo2), so the required input power increases 6 dB per octave; or, in other terms, the available gain decreases by 6 dB per octave. If the input is well matched across a broad bandwidth, a gain slope inevitably results.

The generation of harmonics using FET transistors can be done not only from current or voltage clipping, but also due to mixing of fundamental frequency, and any one of the generated harmonics. One way to use mixing is to reflect all generated harmonics back to the drain and the other is to feed them back to the gate. The initial step in an active multiplier design is to find the performances of the active device at fundamental frequency, looking to parameters as: transconductance gm, transition frequency ft, and the maximum oscillation frequency fmax. The transconductance (gm) has a direct impact in the devices power performance and multiplication gain, and ft and fmax determined the limits to be used as a frequency multiplier. Harmonic Load Pull Test This is a method which employs no device model and is essentially an experimental process. This method is very useful designing a nonlinear frequency multiplier. The active device is inserted into a circuit that has the input tuned at the fundamental frequency and the output tuned at the desired harmonic frequency. The active device is than removed and the matching networks are measured using a Vector Network Analyzer, getting the desired impedances which to be applied to the device. After that, a conventional linear simulator could be used to synthesize the matching network. Frequency FET Doublers Below is presented a High-Frequency Doubler using a high frequency FET transistor.

High-Frequency FET Doubler To get good input VSWR and maximum power transfer, the input is conjugate matched using microstrip distributed and lumped elements. For moderate bandwidth (less than 30% of the center frequency), can resonate the input capacitance with a series inductor. For uniform conversion gain may need to match the input best at highest frequency of the band. The output matching network it consists of a filter, to short-circuit the drain at the fundamental frequency and unwanted harmonics, followed by a matching transformer.

A half-wave filter is ideal for the output; it consists of a cascade of alternating high- and lowimpedance transmission-line sections, each /4 long at fo; these sections are /2 long at 2*fo and 3 /4 long at 3*fo. So, the frequencies of maximum rejection occur at fo and 3*fo, but the filter has no rejection at the output frequency 2*fo. The imperfect output termination could make the multiplier unstable and cause fundamental frequency leakage.

The Narrow-band Frequency Doubler presented below contains the matching transmission line elements TL1 and TL2, and the bias filter elements TL3 and TL4.

Single Ended Frequency Doubler Narrowband The drain circuit use the transmission line phase-shifter TL5 to adjust the phase of the fundamental frequency impedance, and a harmonic band pass filter. The output BPF it is composed of /4 transmission lines TL6, TL7 and TL8, which block the fundamental frequency and the 3rd harmonic, and present 50 ohms termination at the 2nd harmonic. The electrical angles (phase) of the gate and drain transmission lines, TL5 and TL6, affect the multiplication gain up to 3dB. The drain bias filter is composed of elements TL9 and TL10 and their function is to isolate the bias from the generated 2nd harmonic. The RC circuit in parallel with the power supply is for overall stabilization.

The Wide-band Frequency Doubler presented below use a transmission line (TL5) in series with the output BPF to adjust the phase of the impedance at the fundamental frequency.

Single Ended Frequency Doubler - Wideband The BPF rejects the fundamental and the 3rd harmonic frequencies. There is also a band-stop filter (TL7, TL8, TL9) which blocks the 2nd harmonic, and presents low-loss at fundamental and 3rd harmonic.

Frequency FET Triplers An important difficulty in frequency triplers is the need to short circuit the drain at the unwanted harmonics. For example a frequency doubler is easy to do using a /4 stub, which effectively shorts the first and third harmonic, while the fourth and higher harmonics are weak enough to neglect. But is not very simple for terminating the drain in a frequency tripler. The output network can be difficult to design; the inevitable result is a suboptimum termination, which makes very hard to optimize efficiency and get the risk of instability. This is an example of a FET frequency tripler:

FET Frequency Tripler The input stub, grounded at high frequencies by a capacitor, provides a match for the fundamental input frequency, while in the same time it facilitates bias injection at the gate of the FET device by providing some decoupling. The bias scheme adopted for the frequency tripler was a self-bias arrangement with resistor between source and ground. Such a self-bias configuration tends to bias a FET device towards pinch-off, with the resistor value determining how close the device is to pinch-off. The larger the value of the closer the bias point is to pinch-off. If the gate bias is connected to an external supply, an option effectively to over-write the self-bias setup is made available. At the output, a double stub arrangement has been placed. These stubs get multiple functions. First, they form an output match for the desired 3rd harmonic signal. Secondly, they implement some filtering of undesirable fundamental and 2nd harmonic leakage to the output. Using here the real life stubs, it can be difficult to filter the fundamental without rejecting the desired 3rd harmonic at the same time. This happened when considers the simplest stub arrangement to reject the fundamental, which is an open circuit /4 stub. However, such a stub is long 3 /4 at the 3rd harmonic and tends to reject this frequency as well. As a consequence, the design of the output stub pair involved a compromise in terms of fundamental and 2nd harmonic rejection, without excessively loading the 3rd harmonic response. The output stubs is essentially a short circuit stub, the high frequency short being provided by a capacitor to ground. This stub also facilitates drain bias injection.

Balanced Frequency Multipliers Reasons using of Balanced Frequency Multipliers are: they have improved input match over wide bandwidth, they have good isolation between multiplier stages, they are very stable since the device is terminated in 50 ohms over a wideband frequency.

Balanced Frequency Doubler using Branch Line Hybrids

Branch Line Hybrid and the Distributed and Lumped equivalents The input hybrid coupler introduces a 90 phase shift and the output hybrid another 90. Therefore, the odd harmonics are 180 out of phase, are cancelled at the output port, and dissipated at the coupler termination. The even harmonics at the output port are in phase and added in power. A balanced multiplier has 3dB greater output power than an equivalent single-device circuit. The main bandwidth limitation is given by the FETs input and output matching networks not matched for wideband response. The circuit is self-biased using TL3 and Rg gate to the ground and Rs as source resistor. The bias is chosen to be near pinch-off point.

Balanced to Unbalanced Frequency Doubler Another option is to use only at the input a 180 Rat-Race hybrid to drive each device in anti-phase. In this way the fundamental drain currents are also in anti-phase and good rejection is obtained by paralleling both drains, and the drain connection point becomes a virtual ground for fundamental and for all odd harmonics. The even harmonics of the drain currents in the two FETs have no phase difference, however, so the drain-current components at those frequencies combine in phase at the output.

Balanced to Unbalanced Frequency Doubler using Rat-Race Hybrid

Rat-Race Hybrid and the Distributed and Lumped equivalents To get a constant gain at the output, the gates matching networks are designed for maximum gain at fundamental high-end and around 3dB less gain at the low-end of the useful band. The disadvantage of this topology is sensitivity to device DC imbalances and input matching networks, compared to the balanced multiplier using hybrids at both, input and output. Any imbalance is reflected back to the generator requiring an attenuator at the input to minimize the resulting standing wave.

Balanced Frequency Doubler using Active Balun The frequency doubler using an active balun presented below is suitable for small size circuits, replacing the passive balun topologies.

Balanced Frequency Doubler using Active Balun In this frequency doubler, a simple combination of Common-Gate FET and Common-Source FET provides the required 180 phase difference for the cancellation of the fundamental. This active balun has the advantage getting small size at low frequencies. The stability has to be controlled, in contrast to a passive balun, and the circuit should be unconditionally stable for all input impedance attached. To get unconditional stability and to avoid negative resistances at gate and drain of the CommonGate FET, a series resistance Rg, is added to gate. This reduces the gain, but it improves stability by decreasing the loop gain at the same time. In addition, two series resistors Rd are added in both drain connectors to decrease the loop gain. The frequency doubler has a short-circuited stub TL4 and a series transmission line TL3 for an output impedance adjustment at the connection of the two drains. These elements provide a short for the fundamental and additional match for the 2nd harmonic. The bias point was chosen at Vg=0 to obtain high fundamental suppression and 2nd harmonic.

Balanced Frequency Tripler

Balanced Frequency Tripler The input match is made with open-circuited stubs TL1, and high-impedance lines TL2. The /4 TL3 connecting both inputs introduces a short at the 2nd harmonic, improving the performance. The output match contains only a /4 high impedance transmission lines TL4, to parallel tune the drain output impedance at the fundamental frequency. The device is self-biased and the source resistor Rs is decoupled with Cs.

Higher Order FET Frequency Multipliers The direct generation of harmonics of higher order can be obtained by biasing the device at different conduction angles. For even order the device is biased in Class-AB similar for frequency doubler, in order to maintain a rectified sinusoidal drain current which is reach in even harmonics. For odd order harmonics the optimum bias condition is the one that generates an output waveform with distorted positive and negative peaks. The first option would be to bias the device in Calss-A, about the center of the drain current, and apply a high power at the gate. The magnitude of higher harmonic components like 5th, 6th, 7th, etc, becomes too small, requiring a high load resistance to compensate the reduction in output power.

BJT Frequency Multipliers The theory of bipolar multipliers is essentially the same as that of FET multipliers. A few notes on the differences, however, are in order. Unlike FETs, whose channel currents are limited to a little over Idss, bipolar devices do not have such a strict limit. Silicon BJTs experience high-level injection effects, which tend to limit the peak current and reduce transconductance at high collector current. Bipolar devices have a large, strongly nonlinear base-to-emitter capacitance. Because of that capacitance, BJT multipliers are susceptible to modes of oscillation that are not unlike those of junction varactor multipliers for example. As with varactors, the best (and simplest) way to avoid such instability is to short-circuit the base and drain at all unwanted harmonics. Have to verify also that active DC bias supplies do not exhibit negative resistance or couple the collector to the base at low frequencies. Because multiplying devices are turned off under quiescent conditions, BJT multipliers should not be current-biased; they must be biased from a voltage source, ideally with a series resistance.

BJT Frequency Tripler Balanced Push-Push Harmonic Oscillator Another option generating high frequency signal, using most of the characteristics of the frequency multipliers, is the Harmonic Oscillator. Below is presented an example of a balanced harmonic oscillator.

Balanced Push-Push Harmonic Oscillator The push-push harmonic oscillator employing two transistors, each oscillating at one half the desired output frequency. The transistors oscillate out-of-phase with respect to each other, causing the fundamental frequency to cancel and the second harmonic to add in phase. Push-push designs have several advantages over other topologies. Designing at one half the frequency increases resonator Q, decreases the parasitics which appeard, and extends the useful frequency range of transistors. The dielectric resonator is placed between the two gates transmission lines (TL1) Biasing the circuit in Class-AB, guaranties the start-up and stable oscillation, and also the generation of even harmonics at the output.

Refrences: 1. 2. 3. 4. Design of FET Frequency Multipliers and Harmonic Oscillators E. Camargo Nonlinear Microwave and RF Circuits S. Maas The RF and Microwave Circuit Design Cookbook S. Maas Microwave and Millimeter-Wave Diode Frequency Multipliers M. Faber, J. Chramiec, M. Adamski 5. Microwave Communications Engineering - Volume 1 I.A. Glover, S.R. Pennock, P.R. Shepherd 6. Millimeter-Wave Integrated Circuits E. Carey, S. Lidholm 7. Varactor Frequency Tripler R. Zingg 8. New Topology Multiplier Generates Odd Harmonics C. Wenzel 9. Choosing a Frequency Multipliers Waveform C. Wenzel 10. A Highly Integrated Ka- band MMIC Quadrupler K. Kamozaki, T. Bos, E. Camargo 11. Low Cost Frequency Multipliers Using Surface Mount PIN Diode Application Note Agilent 12. RF Design Magazine, 1990 2005 13. Microwave Journal Magazine, 1996 2010 14. High Frequency Electronics Magazine, 1996 2010 15. Microwaves & RF Magazine, 2000 2010

Impedance Matching
Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul/
Reactance and LC Resonance Reactance X is a measure of the opposition to the current of Capacitance C and Inductance L. Reactance is measured in ohms and varies with the frequency of the AC signal. Reactance takes two forms - Inductive (XL), and Capacitive (XC). XL = *L = 2*!*f*L XC = 1 / ( *C) = 1 / (2*!*f*C) Where: is angular frequency, f is frequency, L is inductance, and C is capacitance. When the magnitudes of L reactance and C reactance are equal, the L-C pair resonates. At resonance the net reactance of a series-connected L-C circuit is zero (a short circuit), and the net reactance of a parallel-connected L-C circuit is infinite (an open circuit). The resonant frequency is getting by equating the magnitudes of the L and C reactances (XL = XC) Resonant frequency is given by: Q-Factor The quality factor (Q) serves as a measure of a reactances purity (how close it is to being a pure reactance, and not a resistance), and is defined as the ratio of the energy stored in a component to the energy dissipated by the component.

Q is a dimensionless unit and is expressed function of reactance X and resistance R as: Q=X/R It should be stated that Q of the L-C circuit is defined at circuit resonance. If the circuit reactance is plotted as a function of frequency, the slope of the reactance at resonance is a measure of Q. The quality factor Q of a reactive component (inductor or a capacitor) is the ratio of its reactance magnitude to its resistance. Q of an inductor: Q of a capacitor:

Unloaded-Q The loaded quality factor QL is the ratio of the magnitude of the reactance of either L or C at resonance, to the total circuit resistance In real physical reactive elements there are always some resistive losses. The loss in a component (a capacitor or an inductor) can be described in terms of its Q. For example, if a lossy inductor is placed in parallel with a lossless capacitor, the Q of the resulting parallel circuit is almost equal to the Q of the inductor. The unloaded-Q (QU) is the Q associated with the reactive elements only (i.e., without the load).

Loaded-Q The loaded Q of a resonant circuit is dependent upon three main factors: 1. The source resistance (Rs). 2. The load resistance (RL). 3. The component Q-factor as defined above.

The resonant circuit sees an equivalent RP resistance, RS in parallel with RL, as the load. The RP resistance is smaller in value than either RS or RL RP = (RS *RL) / (RS + RL) Assuming lossless components: RP = equivalent parallel resistance of RS and RL XP = inductive or capacitive reactance (both equal at resonant frequency)

To optimize the loaded-Q there are two options. First, we can select the optimum values for source and load impedances, or second, we can use different ratio values for L and C. Decreasing the RP will decrease the Q of the resonant circuit, and an increase in RP will increase the Q of the circuit. Can get the same effect if we keep RP constant and varying XP.

Example: Using a parallel L-C circuit, at the same resonant frequency (178MHz), we get different Q values just changing the L and C values, when keeping RP constant (50 ). - If RP = 50 - If RP = 50 , C = 8pF, L = 100nH, at 178MHz we get: XP = XC = XL = 111.8 , results Q = 0.45 , C = 400pF, L = 2nH, at 178MHz we get: XP = XC = XL = 2.2 , results Q = 22.7

Impedance Impedance is an important parameter to characterize electronic circuits, components, and materials used to make components. Impedance Z is defined as the total opposition of a device or circuit to the flow of an alternating current (AC) at a given frequency, and is represented as a complex quantity which is graphically shown on a vector plane. An impedance vector consists of a real part (resistance, R) and an imaginary part (reactance, X). Impedance can be expressed using the rectangular-coordinate form Z = R + jX or in the polar form as a magnitude and phase angle: Z = |Z| !!

Impedance varies with frequency, when the effect of resistance is constant regardless of frequency.

Maximum Power Transfer Designing circuits involves the efficient transfer of the signals. In the early days of electric motors, it was found that to get the most efficient transfer of power from the battery (source) into the motor (load) required that the resistance of the different parts of the circuit be the same, in other words, matched; this is known as the maximum power transfer theorem. For DC circuits, maximum power will be transferred from a source to its load if the load resistance equals the source resistance. A simple proof of this theorem is given by the following example:

The circuit and graph to prove the condition for maximum power transfer

(vs and vout refer to r.m.s. value) With the equation above we can calculate and plot the power delivered to the load for various load resistances. When the load is zero, no power can be delivered to it, and as the resistance RL increases above zero, the voltage across it and dissipated power increases. As the RL further increases, the value of Pout reaches a peak (where RL = Rs) and thereafter decreases.

Impedance Matching
Impedance Matching was originally developed for electrical power, but can be applied to any other field where a form of energy (not necessarily electrical) is transferred between a source and a load. The first Impedance Matching concept in RF domain was related to antenna matching. Designing an antenna can be seen as matching the free space to a transmitter or receiver. Impedance Matching is always performed between two specified terminations. The main purpose of Impedance Matching is to match two different terminations (Rsource and RLoad) through a specific pass-band, without having control over stop-band frequencies. We may assume that component losses are negligible but parasitic effects need to be considered. The main role in any Impedance Matching scheme is to force a load impedance to look like the complex conjugate of the source impedance, and maximum power can be transferred to the load. When a source termination is matched to a load with passive lossless two-port network, the source is conjugated matched to the input of the network, and also the load is conjugate matched to the output of the network. Any reactance between Rs and RL reduces the current in RL and with it the power dissipated in RL. To restore the dissipation to the maximum that occurs when Rs = RL, the net reactance of the loop must be zero. This occurs when the load and source are made to be complex conjugates one of another, so they have the same real parts and opposite type reactive parts. If the source impedance is Zs = R + jX, then its complex conjugate would be Zs* = R " jX.

Impedance Matching of a resistive source and a complex load for maximum power transfer

Using only one series reactive element between two equal resistive terminations creates a voltage drop that reduces the voltage across the load. Impedance Matching can eliminate or minimize the unwanted reactance through a range of frequencies. The matching process becomes more difficult when real parts of the terminations are unequal, or when they have complex impedances.

Example: Match a 50 resistive source at 100MHz, to a 50 resistive load that has in series a 1.59pF capacitance. Since the terminations are equal, the required matching circuit can be a series inductor to negate the reactance of the series capacitance. XC = 1 / (# x C) = 1 / (2 x $ x f x C) = 1 / (2 x 3.14 x 100 x 106 x 1.59 x 10-12) = 1000 At 100 MHz the capacitive reactance Xc = j1000 We need to negate this capacitive reactance by adding +j1000 in series (series inductor). At resonance: XC = XL = # x L The matching inductor: L = XL / # = 1000 / (2 x $ x f ) = 1000 / (2 x 3.14 x 10 x 106) = 1.59uH Adding just a 1.59uH series inductor between the two resistive terminations provides match at 100MHz. . Conjugate match is obtained only at one frequency, where the two reactive components resonate. As the frequency is increased or decreased from this value, the transmitted power rolls off at a rate determined by the loaded-Q of the circuit.

When Rs = RL matching requires only a series reactive element The 3-dB frequency bandwidth of a matching network is: BW3dB = fR / QSRES Q for series resonance is: Qseries = (Reactance of one resonant element at fR) / (Total series resistive loading) In the above example using 1000 reactance, and (50+50) So, BW 3dB = (10 x 106) / 10 = 10MHz total resistive loading, gives Qseries = 10

If in the above example the load capacitance was in parallel with RL, then a parallel inductor would be used to resonate the load parasitic capacitance. In this case Q for parallel resonance is: Qparallel = (Total parallel resistive loading) / (Reactance of one resonant element at fR) Matching high-Q terminations leads to narrow bandwidths.

For a given resistance, there are few possibilities for high-Q when associated parasitic reactance is one of the following: - Large series or small parallel inductance - Small series or large parallel capacitance

When the resistive portion is very small or very large (i.e. input resistance of a high-power transistor, or output impedance of a low-current device), even small amount of parasitic inductance or capacitance can lead to high-Q making Impedance Matching a challenging task. In parallel resonant circuits, high-value loading resistors lead to high-Q, while in series circuits the opposite is true. A broader band match usually can be obtained when the tuning is performed close to the load. Accepting an approximate match at the center frequency may result in a better average match over the operating band.

Common mistake of Impedance Matching is to connect a source Zs = R +jX to a load ZL = R + jX. The net result is the real part of the source, R, sees an effective load of R + j2X, leading to power reflection back to the source.

Interconnecting two identical complex impedances doesnt lead to maximum power transfer If the two terminations are not equal (as in the previous example) first have to develop a technique to take care about this issue, and then expand the technique to also include reactive elements. At a single frequency, an appropriate pair of L-C elements can provide a match to both terminations. Impedance Matching using Resistor Networks Using a resistive network can match simultaneous input and output, but create more loss. R1 = RS (RL*R2) / (RL+R2) R2 = RL % [(RS) / (RS-RL)] For example, if there is a series-parallel resistor combination to match 50 simultaneous, the transmission loss it will increases to 21.6dB. Impedance Matching using Transformers Another possible option to match resistive source and resistive load is to use transformers. Transformers convert source power from one voltage and current level to another voltage and current level. The load impedance is transformed as a square of the voltage-transformation ratio. The ratio of the voltage transformation comes from the number of turns on the input winding (primary), divided by the number of turns on the output winding (secondary). To achieve Impedance Matching, the Turns Ratio of the transformer is the square root of the ratio of Load Resistance over the Source Resistance. Turns Ratio = " (Load Resistance / Source Resistance) For example to match a 50 resistive source to a 5 resistive load we need a transformer with 5 Turns Ratio = = 0.32 50 That means if the primary has 100 turns, the secondary must have 100 x 0.32 = 32 turns. source and 5 load

The terms step-up or step-down refer to ability of the transformer to change (transform) the voltage or the current that passes through it. The amount of power (P = I x V) that goes into a transformer is always equal to the amount of power that comes out (discounting negligible losses). While a step-down transformer is changing the input voltage to a lower voltage, it is also changing the input current to higher current. Transformers match only the real part of the impedance. If there is a large amount of reactance in the load, a transformer will not eliminate these reactive components. In fact, a transformer may exaggerate the reactive portion of the load impedance. This reactive component results in power that is reflected to the generator. Transformers however works poorly at microwave frequencies, but provide wider bandwidths than L-C matching circuits. Advantages of using transformers for Impedance Matching are: - Wide bandwidth, exceeding 1000 MHz. - Excellent amplitude and phase balance. - Higher return loss (lower VSWR) at the primary side. Impedance Matching using Quarter-Wave (#/4) Transmission Lines An impedance transformer may be realized by inserting a section of a different transmission line with appropriate characteristic impedance. A quarter-wave impedance transformer is a component used in RF engineering consisting of a length of transmission line one quarter of a wavelength (&/4) long and terminated in some known impedance ZL. Although quarter-wave transformer can in theory used to match complex impedances, it is more common to use it to match real impedances. However, a complex load impedance can always be transformed to a real impedance by adding the correct series or shunt reactive component. At the operating frequency, the electrical length of the matching section is &/4. But at other frequencies the length is different, so a perfect match is no longer obtained. The quarter wave transformer has a limited bandwidth, like other transformation methods.

Zo = " (Zin x ZL) The characteristic impedance of the quarter-wave line is the geometric average of Zin and ZL. a)

A quarter-wave &/4 transformer provides a perfect match at only one frequency. b) A broadband design may be obtained by a cascade of &/4 line sections of gradually varying their characteristic impedance.

It is not possible to obtain exactly zero reflection coefficient for all frequencies in the desired band. Therefore, available design approaches specify a maximum reflection coefficient (or maximum VSWR) which can be tolerated in the frequency band of operation. The change of characteristic impedances Zn must increase ore decrease monolithically. c)

Another broadband matching approach may use a tapered line transformer with continuously varying characteristic impedance along its length (characteristic impedance varies continuously in a smooth fashion). In this case, the design obtains reflection coefficients lower than a specified tolerance at frequencies exceeding a minimum value. The required length of the taper section should be about 0.5 to 1.5 of wavelength. A different narrow-band approach involves the insertion of a shunt imaginary admittance on the line. Often, the admittance is realized with a section (or stub) of transmission line and the technique is commonly known as stub matching. The end of the stub line is short-circuited or open-circuited, in order to realize an imaginary admittance. A second narrow-band example involves the insertion of series impedance (stub) along the line.

Shunt-stub Impedance matching using L-C sections

Series-stub

Any two resistive terminations can be simultaneous matched by adding two reactive elements between them. If we need to match in a narrow frequency a source Rs and a load RL, we can get almost the same performance by using a high-pass or low-pass network configuration. The pass-band performances near the matching frequency are very similar for both networks, when the out-of-band characteristics of the low-pass and high-pass are different. A low-pass rejects signals at the high-end, and allow passing at low frequencies. The high-pass network does the opposite.

Four possible single matching L-C networks

To increase the impedance level, the series matching element must be placed next to the termination with smaller resistance. Steps to follow for Impedance Matching using two reactive elements: 1) Add a series reactive element next to RSMALLER and a parallel one to RLARGER. Series element could be either Inductor or Capacitor but the parallel one must be opposite type. If the series element is an inductor we create a low-pass topology, and when the series element is a capacitor we get a high-pass topology. In case of transistor matching, usually the gain of the transistor is higher at lower frequencies, so there may be a low-frequency stability problem. In such a case, sometimes a high-pass LC network at the input (series C, shunt L) may be more stable. At the output of the transistor harmonic filtering is required this can be done with a low-pass matching network (series L, shunt C). 2) Add a series reactive element to RSMALLER and a parallel one to RLARGER, forms two sub-networks, one inductive and other capacitive (one in series and one in parallel), and they must represent complex conjugates impedances to each other, at design frequency. Therefore, the Q-factors of these two sub-networks must be equal at the matching frequency.

Q = QS = QP =

3) Knowing the Q-values, we can find the series and parallel elements, reactances, and get the values of the inductor and capacitor of the network using the following equations:

Example: To match a 5 to a 50 resistive load at 850MHz, we can add a series inductor to RSMALLER (5 and a shunt capacitor to RLARGER (50 ). To calculate the required Q-factors for the new sub-networks:

To find the inductor and the capacitor values at 850MHz we use:

A low-pass L-C section used to match two resistive terminations shows an asymmetric broadband frequency response, with negligible loss near the matching frequency. Loss below matching frequency is caused by the mismatch between the two terminations.

Mismatch Loss [dB] = 10*LOG (1 - '2)

Loss above matching frequency is caused by the roll-off the low-pass network (12dB/octave slope). An L-C matching network response shows symmetry only near the matching frequency, and the 3dB bandwidth is meaningless if the mismatch loss between the two terminations is less than 3dB.

Tapped Capacitive Impedance Transformer The tapped capacitor circuit is another approximate method for obtaining impedance level transformation.

When RS < RL The maximum value of the inductance L used by the tapped impedance transformer is:

The upper limit of L is when C2 is not required, while at low L/C ratios the circuit becomes sensitive to small component value changes. As a general rule, L must be smaller than LMAX but not very much smaller. Example: If C1 = 100pF, and C2 = 200pF, we can match: Rs = 50 with RL = 450 If the matching frequency is 100MHz, the maximum value of parallel inductance will be, L = 253nH Bandwidth of the Matching Networks In the example above matching section can be either low-pass or high-pass. Comparing the frequency responses of the low-pass and high-pass networks shows considerable difference. The low-pass network absorbs the parasitics on both sides, while the high-pass circuit resonate them, resulting in narrower bandwidth.

If the bandwidth obtained by a single section L-C network is not sufficient, we can increase it by adding another section. Instead transforming the impedance directly from one to another, first transform to an intermediate impedance RINT and finish the matching circuit with a second L-C section.

Advantage of the Tee or Pi networks is, using an extra element there is an extra degree of freedom to control the value of Qn in addition to performing impedance transformation/matching. For equal component sensitivities set the RINT = % (RS x RL) RINT is not an actual component: it only indicates the intermediate impedance level. If the increase is not sufficient, adding more sections brings further bandwidth improvement. The bandwidth improvement is caused by reducing the termination ratio, which in turn reduces the Q of the matching sections. When 3 elements are used in a matching network, we are no longer limited to a single value of network Q as using 2 element circuit. For a given set of source/load resistances now we can select any Q higher than the one when using 2 element L type network. The 3 element Pi or Tee type networks can match a source that is either higher or lower than the load resistance, simply by alternating ratio of the two shunt components.

Pi and T type matching networks on Smith chart The Pi network can be described as two back to back L networks that are both configured to match the load and the source to a virtual resistance located at the junction between the two networks. The virtual resistance RINT must be smaller than either RS or RL because is connected to the series arm of each L section. RINT is defined by the desired Loaded-Q of the circuit that was specified by the design process. Pi Loaded-Q = " [(RLARGEST / RINT) -1] where RLARGEST is the largest terminating resistance Rs or RL. The Tee network design is the same as for Pi network except that with Tee you match the load and the source, through two L-type networks to a virtual RINT resistance which is larger than either Rs or RL. The Tee network is often used to match two low valued impedances when a high-Q arrangement is needed. The Loade-Q of the Tee network is determined by the L section that has the highest Q. The L section with highest Q will occur at the end which has the smallest terminating resistance (each terminating resistor is in the series leg of each network) Tee Loaded-Q = " [(RINT / RSMALLEST) -1] where RSMALLEST is the smallest terminating resistance Rs or RL. Impedance Matching of Complex Terminations In case of complex loads maximum power will be transferred when source is conjugately matched to a load. So, transform one complex termination to the complex conjugate of the second termination. If a load is purely resistive, the source should appear to be resistive with the same value.

If the load is complex the source should appear to have the same resistance but the opposite reactance. The two reactances will then cancel (resonate) leaving only the identical source and load resistances. When a network transforms a given load to complex conjugate of a given source, the reverse is also true. The source is simultaneously transformed by the same network into complex conjugate of the load. When one or both of the impedances to be matched already has imaginary parts, two possibilities exist for computing (absorption or resonance). - Absorb the parasitic into matching network. - Resonating the excessive parasitic inductance or parasitic capacitance. Source and load inductance or capacitance may be integrated into the matching network as long as the Q-factor of the termination does not exceed the computed nodal-Q of the L-C network. The limit is set by the resistance ratio of the terminations to be matched. When the parasitic of termination exceed the maximum value that the matching network can absorb use one of the two situations: - Fully resonate the parasitics and proceed matching to the leftover resistive part of the termination - Resonate only the excessive part of the parasitic and use the remainder as part of the matching circuit. Both these resonance-based techniques reduce the bandwidth, the more reactance we have to resonate, the narrower the frequency response becomes.

Source with series inductance

Load with parallel capacitance

When the Q of a termination exceeds the limit set by the nodal-Q calculations, we need to neutralize the excessive amount of parasitic reactance. In the example below, the 20pF parallel load capacitance is 8.8pF higher than the maximum limit, set by the computed Q of 3.0, and it is fully resonated by the inductor LR.

after that we can combine LR and LM in a single parallel inductor LMR

If the inductor LR is selected to resonate 8.8pF of the 20pF load capacitance, the remaining 11.2pF can be used with inductor LM to match the two terminations. We get more bandwidth this approach compared to the circuit shown above.

Impedance Matching with Transmission Lines using Smith Chart Smith Chart is a good choice when Impedance Matching is done using transmission lines. Cascading transmission lines always follow a clockwise rotation on the Smith Chart. Moving away from a termination on a transmission line, always follow a clockwise circular rotation on the Smith Chart. If the chart is normalized to the characteristic impedance of the transmission line, the rotation is a along a concentric circle. The radius of the concentric circle is determined by the normalized termination. A complex source can be matched to the 50 load with a cascade series transmission line and a parallel short-circuited stub. There are 4 adjustable parameters: ZTL, (TL, ZSS, (SS A parallel stub is treated as an equivalent parallel inductor or capacitor at specific frequencies, depending on what type of reactance it represents. If we use several cascade lines with different characteristic impedances, the Smith chart must always be renormalized to the appropriate impedance.

Following a counter-clockwise rotation on the chart is equivalent to de-embedding, which is incorrect for this application. Moving away from any termination (source or load) with a transmission line, always leads to a clockwise rotation. In general, one shunt capacitor and two series transmission lines is sufficiently to transform any load to any input impedance.

Example: Transform a load ZL = 30 + j10, to an input Zin = 60 + j80, at frequency f = 1.5GHz Steps for Impedance Matching with Transmission Lines using Smith chart: - From ZL go to point A using a series-TL (l1 = 0.055&) - From point A go to point B using a shunt capacitor (C1 = 4.37pF) - From point B go to Zin using a series-TL (l2 = 0.26&)

Impedance Matching Guide using Smith Chart Impedance Matching issues can be analyzed as trajectories on the Smith Chart, where the addition of a series or shunt component moves the total impedance along constant impedance, admittance, or resistance circles.

If the task is to match specific impedance to a reference impedance (generally to 50 ), then the target of the impedance matching is to arrive at the center of the Smith Chart by moving along the arcs from the initial point. If the task is to provide impedance matching to an impedance other than the reference impedance, then the end point of the matching trajectory must be the conjugate of the target impedance.

Constant-Q lines can be plotted on the Smith Chart to estimate the matching network bandwidth.

The closer an Impedance Matching trajectory comes to the edge of the Smith Chart, the narrower the bandwidth. Maximum bandwidth for a given matching network can be obtained by keeping the trajectories short, well away from the edges of the Smith Chart, and as close as possible to the real axis. If the target is to design a circuit with a specific bandwidth (equal to a certain Q), one vertex of the matching trajectory must touch the desired constant-Q arc, and all other trajectory points should be well inside of lower Q regions.

Impedance Matching of Balanced Circuits Introducing a virtual ground between the terminals of the balanced circuit ports, the Impedance Matching of balanced circuits can be reduced to the situation of single-ended circuits. Then we can match the individual halves of the balanced circuits the same was as in single-ended circuits. After the networks are derived, the virtual ground may be eliminated to save components.

Example: I we have to match at 850MHz the 10 differential output ZOUT of an amplifier, to the 100 impedance ZIN of the second amplifier, we can use the following approach.

input

With the help of a virtual ground the balanced ports can be split into unbalanced ports. Input and output impedances of the unbalanced ports are half of the balanced ports.

The unbalanced L-C circuit used to match 5 to 50 is a standard L-type matching network using a series L and a shunt C.

After establishing the unbalanced matching circuits the virtual ground can be eliminated. The two 11.2pF capacitors can be combined into a single floating 5.6pF capacitor. The two balanced ports are now matched to each other at desired frequency.

References: Practical RF Circuit Design for Modern Wireless Systems, Vol. I, II L. Besser, R. Gilmore RF Design Guide - P. Vizmuller RF Circuit Design - C. Bowick Radio Frequency Circuit Design A. Davis, K. Agarwal Radio Frequency and Microwave Communications Circuits D. Misra High Frequency Techniques J. White Electromagnetic Waves and Antennas - S. Orfanidis Fundamentals of RF Circuit Design with Low Noise Oscillators - J. Everard High Frequency and Microwave Engineering - E. da Silva High Frequency Circuit Design - J. Hardy Impedance Matching and Smith Chart - R. Chuang Impedance Transformation and Impedance Matching F. K. Wai Lee Microwave Devices, Circuits and Subsystems for Communications Engineering - I. Glover, S. Pennock, P. Shepherd Practical MMIC Design - S. Marsh Radio Frequency Integrated Circuit Design J. Rogers, C. Plett Radio Frequency Transistors - Principles and Practical Applications- N.Dye, H. Granberg The Yin-Yang of Matching - R. Rhea EE246 - Microwave Engineering Stanford University Impedance Matching Networks - AN721 Freescale Impedance Matching Techniques for Mixers and Detectors AN 963 - Agilent Impedance Matching - Advanced Energy Industries, Inc. Microwave Journal 1996 2011 Microwaves and RF 2000 2011 High Frequency Electronics 2002 2011 ARRL Handbook 1990 - 2011

LNA Design
Iulian Rosu, YO3DAC / VA3IUL http://www.qsl.net/va3iul/
An LNA combines a low noise figure, reasonable gain, and stability without oscillation over entire useful frequency range. The Low Noise Amplifier (LNA) always operates in Class A, typically at 15-20% of its maximum useful current. Class A is characterized by a bias point more or less at the center of maximum current and voltage capability of the device used, and by RF current and voltages that are sufficiently small relative to the bias point that the bias point does not shift. The smallest signal that can be received by a receiver defines the receiver sensitivity. The largest signal can be received by a receiver establishes the upper power level limit of what can be handled by the system while preserving voice or data quality. The dynamic range of the receiver, the difference between the largest possible received signal and the smallest possible received signal, defines the quality of the receiver chain. The LNA function, play an important role in the receiver designs. Its main function is to amplify extremely low signals without adding noise, thus preserving the required Signal-to-Noise Ratio (SNR) of the system at extremely low power levels. Additionally, for large signal levels, the LNA amplifies the received signal without introducing any distortions, which eliminates channel interference. An LNA design presents a considerable challenge because of its simultaneous requirement for high gain, low noise figure, good input and output matching and unconditional stability at the lowest possible current draw from the amplifier. Although Gain, Noise Figure, Stability, Linearity and input and output match are all equally important, they are interdependent and do not always work in each others favor. Carefully selecting a transistor and understanding parameter trade-offs can meet most of these conditions. Low noise figure and good input match is really simultaneously obtained without using feedback arrangements. Unconditional stability will always require a certain gain reduction because of either shunt or series resistive loading of the collector. High IP3 requires higher current draw, although the lowest possible noise figure is usually achieved al lower current levels. Envelope termination technique can be used to improve IP3 performance while operating LNA at low current levels. Additional improvement of IP3 can also be achieved by proper power output matching (1dB compression point match or P1dB match). The P1dB match, being different from conjugate match, reduces the gain although improving IP3 performance. Transistor selection is the first and most important step in an LNA design. The designer should carefully review the transistor selection, keeping the most important LNA design trade-offs in mind. The transistor should exhibit high gain, have a low noise figure, and offer high IP3 performance at the lowest possible current consumption, while preserving relatively easy matching at frequency of operation. Examination of a data sheet is a good starting point in a transistor evaluation for LNA design.

The transistors S-parameters should be published at different collector/emitter voltages and different current levels for frequencies ranging from low to high values. The data sheet should also contain noise parameters, which are essential for low noise design. Spice models for the transistor and its package are also useful for IP3 and P1dB simulations. The designer should first look at the main design parameters as: Noise, Gain, and IP3, and decide what Vce and Ic levels will produce optimal performance. The forward transducer power gain represents the gain from transistor itself with its input and output presented with 50 impedance. The manufacturer of the transistor at multiple frequencies and different Vce and current levels provides the S21 values. Additional gain can be obtained from source and load matching circuits. Maximum Stable Gain and Maximum Power Gain (Gmax) are good indicators of additional obtainable gain from the LNA circuit. LNA linearity is another important parameter. A figure of merit for linearity is IP3. A two-tone test is used for derivation of IP3. As a rule of thumb for bipolar junction transistors (BJT), the Output-IP3 can be estimated from the following formula: OIP3[dBm] = 10 log (Vce[volt] * Ic[mA] * 5) RF performance of the LNA depends by many variables as: - Frequency - DC Biasing and Power Dissipation - Stability - Input and Output Matching - Layout and Grounding - EM Shielding - Supply decoupling - Temperature 1. DC Biasing (BJT) represent the first step in LNA design. The chosen DC bias circuit should exhibit stable thermal performance and reduce the influence of hFE spread. The resistive feedback arrangement is the simplest form of DC biasing that fulfills all the major requirements. Two bias feedback arrangements are possible: one with a combination of Rc and Rb and a second one with simple Re and Ce combination.

The operation of the Rc and Rb is simple: Rc and Rb will establish a biasing point. If the device current increases, the voltage drop across Rc increases, reducing the voltage seen by the base, thereby providing feedback. Because the operation class of the LNA is going to be Class-A (constant current draw for dynamic range of power levels), a stable biasing point over different temperatures is required. For different lot of transistors small variation in hFE can be expected. For Rb to have little influence on source matching, which is crucial for noise performance, the feedback network should be decoupled with an inductor (making biasing invisible at RF band of operation). Another possible bias feedback can be realized with emitter resistor and capacitor. Ce should be selected carefully, because Re will also have a direct effect on RF gain of LNA. Ce should present a short at frequency of operation to limit its influence on gain and noise performance of the circuit. Other biasing methods are suitable for Class-A networks. These are usually closed feedback arrangements with dynamic bias control provided by active components. Although suitable for LNA application, these active feedback bias networks increase complexity of the LNA network, introduce additional components and increase the real-estate area of the solution. 2. Stability Design should be the next step in LNA design. Unconditional stability of the circuit is the goal of the LNA designer. Unconditional stability means that with any load present to the input or output of the device, the circuit will not become unstable will not oscillate. Instabilities are primarily caused by three phenomena: internal feedback of the transistor, external feedback around the transistor caused by external circuit, or excess gain at frequencies outside of the band of operation. S-parameters provided by manufacturer of the transistor will aid in stability analysis: numerical and graphical. Numerical analysis consists of calculating a term called Rollett Stability Factor (Kfactor). When K-factor is greater than unity, the circuit will be unconditionally stable for any combinations of source and load impedance. When K-factor is less than unity, the circuit is potentially unstable and oscillation may occur with a certain combination of source and /or load impedance present to the transistor. The K-factor represents a quick check for stability at given biasing condition. A sweep of the K-factor over frequency for a given biasing point should be performed to ensure unconditional stability outside of the band of operation. The designers goal is to design an LNA circuit that is unconditionally stable for the complete range of frequencies where the device has a substantial gain. An LNA designer can use at least five methods for circuit stabilization. The first one consists of resistive loading of the input. This method, although capable of improving the stability of the circuit, also degrades the noise of the LNA and is almost never used. Output resistive loading is preferred method of circuit stabilization. This method should be carefully used because it effects are lower gain and lower P1dB point (thus IP3 point). The third method uses collector to base resistor-inductor-capacitor (RLC) feedback to lower the gain at the lower frequencies and hence improve the stability of the circuit.

 The fourth method consists of filter matching, usually used at the output of the transistor, to decrease the gain at a specific narrow bandwidth frequency. This method is frequently used for eliminating gain at high frequencies, much above the band of operation. Short circuit quarter wave lines designed for problematic frequencies, or simple capacitors with the same resonant frequency as the frequency of oscillation (or excessive gain) can be used to stabilize the circuit. The final stabilization method can be realized with a simple emitter feedback inductor. A small inductor can make the circuit more stable at higher frequencies. But if the source inductance is increased, the K-factor at higher frequencies eventually falls bellow 1. This effect limits the amount of source inductance that can safely be used. To get the best LNA stability performances have to accommodate the full range of expected variations in operating parameters as: o Component package parasitics o Component values o Temperature o Supply voltage Most common causes for LNA instability are: o Insufficient RF decoupling between supply lines of the amplifier bias. o Parasitic inductance in GND connections. o Excess in-band and/or out-of-band Gain. o Electro-Magnetic coupling and Feedback. Always check stability of your LNA well beyond band-of-interest checking for both, small-signal stability and for large-signal stability. Use stability circles on Smith Chart (for both, source and load) to verify legitimacy of chosen Zin and Zout impedances. 3. Noise Matching and Input Return Loss (IRL) The next step in LNA design consists of Noise Match and Input Return Loss (IRL). IRL defines how well the circuit is matched to 50 matching of the source. A typical approach in LNA design is to develop an input matching circuit that terminates the transistor with conjugate of Gamma optimum (!opt), which represents the terminating impedance of the transistor for the best noise match. In many cases, this means that the input return loss of the LNA will be sacrificed. The optimal IRL can be achieved only when the input-matching network terminates the device with a conjugate of S11, which in many cases is different from the conjugate of !opt. In 1928 H. Nyquist showed that the noise from any impedance is determined by its resistive component. Consequently, if an ideal lossless element is used to provide feedback, than the minimum noise measure is unaffected. An emitter (or source) inductor feedback can rotate S11 closer to !opt, which can help obtaining close to minimum Noise Figure and respectable IRL simultaneously. The additional series inductance provides lossless negative series feedback and also reduce the overall available gain of the network and can be used in balancing trade-offs between the gain, IIP3 and stability in LNA design. Have to mention that this inductive degeneration does not seriously impact Noise Figure performance, as resistive degeneration does. At high frequencies this inductance will be achieved with small strip lines (stubs) connected directly to the emitters of the transistor.

The inductive reactance of the stubs is usually no greater than 10 and the line lengths are typically ~2mm or less with characteristic impedances 50 or greater. To design an LNA for minimum Noise Figure, determine (experimentally or from the data sheet) the source resistance and bias point that produce the minimum Noise Figure for that device. Then force the actual source impedance to look like that optimum value with all stability considerations still applying. If the Rollet stability factor (K) is calculated to be less than 1 (K is defined as a figure of merit for LNA stability), then you must be careful in choosing the source and load-reflection coefficients. A typical method used in designing input matching network is to display noise circles and gain/loss circles of the input network on the same Smith chart. This provides a visual tool in establishing an input matching network for the best Input Return Loss and noise trade off.
Using Noise Figure from Datasheets Generally for microwave transistors following a datasheet the minimum Noise Figure (Fmin) at higher frequencies is based on measurements, while the Fmins at lower frequencies are extrapolated. Fmin represents the true minimum Noise Figure of the device when the device is presented with an impedance matching network that transforms the source impedance, typically 50 , to an impedance represented by the reflection coefficient !opt. The designer must develop a matching network that will present !opt to the device with minimal associated circuit losses. To accomplish this have to minimize the number of components needed on the LNA input. The Noise Figure of the completed amplifier is equal to the Noise Figure of the device plus the losses of the matching network preceding the device. The Noise Figure of the device is equal to Fmin only when the device is presented with !opt. If the reflection coefficient of the matching network is other than !opt, then the Noise Figure of the device will be greater than Fmin The losses of the matching networks are non-zero and they will also add to the noise figure of the device creating a higher amplifier noise figure. The losses of the matching networks are related to the Q of the components and associated printed circuit board loss. !opt is typically fairly low at higher frequencies and increases as frequency is lowered. For FET devices larger gate width devices will typically have a lower !opt as compared to narrower gate width devices. Typically for FETs, the higher !opt usually infers that an impedance much higher than 50 is required for the device to produce Fmin. At VHF frequencies and even lower L Band frequencies, the required impedance can be in the vicinity of several thousand ohms. Matching to such high impedance requires very hi-Q components in order to minimize circuit losses.

4. Output Matching The last step in LNA design involves output matching of the transistor. An additional resistor, either in series or parallel, has been placed on the collector of the transistor for circuit stabilization. Conjugate matching has been exclusively used for narrow band LNA design to maximize the gain out of the circuit. With additional IP3 requirement forced on the LNA, the trade-off between IP3 and gain must be considered.

Linearity matching is widely known by high-power amplifier designers. The so-called load pulling is used to establish IP3 and gain impedance contours. The load pulling can be realized by using the non-linear Spice model of the transistor with simulation software. Harmonic balance can be used for establishing two-tone environment. The load pulling method sweeps impedance of the whole Smith chart and plots contours of the constant gain and IP3 numbers. The optimal gain impedance does not match the optimal IP3 point, which means that the design will have to be realized by means of a trade off. Typically, the designer should design the LNA circuit at the point where the gain does not degrade as much, and the IP3 is still respectable. If one were to draw a line between the optimal gain and IP3 impedance points, every point on that straight line will represent a good area of trade-off, with the ends representing the two optimal points. The rule of thumb for 1dB gain compression point (P1dB) and IP3 is: IP3 = P1dB +10 [dBm] That means that by knowing the gain compression point (P1dB), can estimates the IP3 levels. The 10dB rule can further be improved with appropriate bypassing of the base and the collector. As previously indicated, the IIP3 is established by injecting two equal-in-magnitude signals with small frequency offset (S) into an active circuit. As the active circuit approaches non-linear region, close to P1dB, the two carriers will generate distortion products, both in and out of band. In example below we have two signals, with output levels Pout and frequencies F1 and F2.

OIP3[dBm] = Pout[dBm] + IM[dBc] / 2 Where IM [dBc] is the difference in amplitude between one of the two equal amplitude test tones, present at the amplifier output, and the level of the highest 3rd-order distortion product. For every dB increase in input power, the third order products (IM3) will increase 3dB. For every dB increase in input power, the second order products (IM2) will increase 2dB. Plotting third order products versus input power predicts a 3:1 response which intersects the 1:1 response at the third order intercept point.

Second and Third-Order Distortion Slopes

1dB Gain Compression Point (P1dB)

The relation between Input-IP3 (IIP3) and Output-IP3 (OIP3) is defined as: IIP3[dBm] = OIP3[dBm] Gain[dB] The low frequency IM2 products (F2-F1), can modulate the base-emitter and collector-emitter LNA supply voltages. To improve the linearity the fluctuation of the base and the collector shall be stabilized with low impedance at so called video frequencies or baseband frequencies (between DC and usually up to 40MHz). The designer should exhibit caution during bypassing design. A poor selection of the by-pass capacitors could also degrade IP3 performance. As a rule of thumb, the impedance of bypassing circuit should be lower than 25% of the input impedance of the transistor at particular frequency spacing. Although preserving the gain performance of the LNA, the bypassing method (also known as an envelope termination technique) can improve LNAs IIP3 performance without increasing current consumption.

5. LNA components and the effect on IP3

Any mismatch due to noise matching C1/L1 improves Input-IP3. Increasing L2 reduces gain and improves Input-IP3, but watch for microwave oscillation with excessive inductance. C9 can use to improve IP3- provides gain roll-off at 2*F1 or 2*F2. Printed circuit board losses R3 provide Q1 stability while reducing IP3. R3 less than 27 for about a dB reduction in IP3. C3 and C6 provide a HF/VHF termination for Q1. Depending on spacing of signals used to test IP3, values may not be large enough may necessitate additional low frequency bypassing in the form of C7 and C8. Typical values are 0.01 to 0.1 uF. The combination of C2/C5, C3/C7 and C6/C8 must provide low impedance at F2 F1. May have to add resistance between caps to decrease Q. C7 and C8 also used to minimize power supply noise from modulating the DC. Capacitor C2, C3 and C7 performs the low-frequency bypass function and an improvement in IP3 of approximately 5 to 10 dB can be expected by using this method. Using extra charge storage on the drain may see the same effect, but the results are not nearly as dramatic. The closer together the two input test tones F1 and F2 are in frequency, the lower frequency the product or beat tone (F 2 F 1) is. Therefore, as input test tones F1 and F2 come closer together, more capacitance is needed to achieve best possible bypassing of the low frequency product (F2 F1). For a test tone separation of 1MHz, 0.1 uF was found to be more adequate for this application. For best results, the transistor should see a low impedance path at low frequencies between this additional bypass caps and its terminals. For this reason, a coil rather than a high value resistor is used to bring the gate bias voltage and isolate the RF from the DC bias network. For example a value of 15nH for L1, has negligible impedance up to tens of MHz, but provides enough impedance at 2 GHz to nearly isolate the gate of the transistor from the bias network within LNAs normal operating frequency range. It is important to note that bypassing the F2 F1 product as described here does not affect the compression point of the amplifier, but only the IP3 (3rd-order intercept point). As a results, if this bypassing used, the general rule of thumb stating that are approximately a 10 dB difference between IP3 and 1 dB gain compression point (P1dB) is no longer valid.

6. Real issues in LNA design

An LNA is a design that minimizes the Noise Figure of the system by matching the device to its noise matching impedance, or Gamma optimum (!opt). Gamma optimum (!opt) occurs at impedance where the noise of the device is terminated. All devices exhibit noise energy. To minimize this noise as seen from the output port, one must match the input load to the conjugate noise impedance of the device. Otherwise the noise will be reflected back from the load to the device and amplified. While this gives a minimum noise figure, it often results in slightly reduced gain as well as possibility increasing the potential instabilities. Noise match often comes close to S11 conjugate (S11*) under non-feedback conditions. As a result, the input impedance to the amplifier will not be matched to 50 ohms. !opt, as presented in data sheets, is the actual measured load at which the minimum noise figure is found. Noise Figure for BJT LNA increases more rapidly than FET LNA, as Collector/Drain current is increased. FETs allows for better trade-off between high-linearity and low Noise Figure than BJTs. A further complication on LNA design is that the input load of the amplifier is usually less than ideal. It is either connected to an antenna, which can change its impedance with changing the environment, or to a filter, which by very physics of a reflective network will have very bad match out of band. These mismatches could cause the device to become unstable out of band and some cases in band. As the gain of the device increases, the difficulties in yielding a stable design become increasingly more challenging. To avoid overloading the LNA, an input filter is commonly used. Since the device is not matched to S11*, the input of the LNA will not be 50 ohms. This can cause distortions in the pass band of the filter when connected to the input of the LNA, as filter are intended to operated in their characteristic impedance, typically 50 ohms. Printed inductors or transmission lines are free as compared to SMT inductors, which typically cost 10 to 25 times as much as resistors or capacitors in volume. Printing an inductor is easy and results in highly repeatable results. Printed inductors usually exhibit poor Q due to the lossy dielectric, and, if a ground plane exists, they are no more than a high impedance transmission line. As shown a transmission line can replace an inductor to some degree, but inductors and high impedance transmission lines have a different trajectory on the Smith Chart. High impedance transmission line can be made to look more like printed inductors in cases where the backside of the PCB is suspended away from a grounded chassis. This is accomplished by removing the backside ground plane of the PCB directly under the printed inductor. In this case beware of digital noise coupling into the input of the LNA from circuitry on the opposite side. The next concern is what load impedance to match. Remember matching to the conjugate of S22* is only valid if the input is conjugate matched. Since S12 is non-zero, whatever load is present to the input will cause the output load change. Another issue is stability, especially if a filter is going to be used at the input. The output port can potentially give difficulties since the input is very restricted by its match. The designer must replace the ideal sources in the bias circuit and ideal values in the matching circuit with equivalent real components. This often presents the designer with a new

set of problems. First, the bias network must be robust enough to function properly over a range of power-supply voltages and temperatures. This introduces additional complexity into the bias network. The real components in the bias network the resistors and large capacitors operate at DC voltages, so frequency effects are not a problem. The matching network, however, contains real capacitors and inductors that operate at RF frequencies. Real components differ from ideal ones in several respects. First, real components have a price associated with them. There is a trade-off between price and performance of these parts. The competitiveness of today's markets often forces designers to use inexpensive components in their designs. Real discrete components have a finite resistance called Equivalent Series Resistance (ESR). The ESR introduces losses that result in lower gain and noise figure. Although typically only a few tenths of an ohm in value, ESR will affect the matching networks. Discrete components also have a Q value, measured at a particular frequency that can contribute to unwanted resonance. High-Q networks are sensitive to variations in process, voltage, temperature, and component value. A component's Series Resonant Frequency (SRF) is the frequency where it will behave erratically. For example, if an inductor is operated at or above its SRF, it might behave as a capacitor. To avoid this, select components where the SRF is much higher than the operating frequency. Also, leaded through hole parts have leads that add series inductance to a design, and surface-mount parts have pads that add shunt capacitance to a circuit. Another issue is that of packaging a completed design. If the circuit is to be integrated and sold as an Integrated Circuit (IC), it must be packaged. The package introduces several negative effects. In an IC, the bond wires add unwanted inductance (L) and the bond pads add unwanted capacitance (C). Isolation between pins in the package is also important. Lack of pin -to-pin isolation in a feedback circuit can lead to major reliability problems and stability concerns. The additional inductance in the emitter of the collector-emitter section can severely degrade the noise figure of the circuit. Additionally, several grounds are usually needed to improve the performance of RF circuits, but the package has a limited number of pins. After using the input, output, and power-supply pins, there may not be enough ground pins to accommodate an adequate design. All of these factors can degrade the circuit's performance from the ideal, and the designer must carefully take them into account. 7. CMOS LNA Design A few comparison characteristics between CMOS and BJT LNAs: o The DC currents of CMOS and BJT LNAs are close; therefore the transconductance (gm) of CMOS transistor is lower than the BJT ones. o The gm/I ratio of CMOS is lower than that of BJT. o In CMOS technologies, a high fT is achieved through a smaller Cgs, while in BJT technologies the same fT is obtained through a higher gm. o Smaller Cgs means CMOS tuned circuits tend to have higher Q, a disadvantage in withstanding component or process variation.

The CMOS LNA input quality factor (independent of Ls) is defined as follows:

There are two types of methods commonly used to design an LNA in CMOS circuits: Common-Gate Cascode amplifier While the Common-Gate stage provides a wide-band input matching and is less sensitive to parasitics, it has an inherently high noise figure.

Common-Gate CMOS LNA With the increasing of the operating frequency, the parasitic transistor capacitance Cgs starts playing roles, which degrades the amplifier performance in the high frequency. In the narrow band application, a shunt inductor is added in the input to resonate with Cgs to have a good impedance matching in the designed frequency. Due to the lower quality factor of the resonant network, Common-Gate it is more robust against the process and electrical variation. Due to the missing of the Cgd path from the input to the output, the Common-Gate LNA shows better reverse isolation and stability versus Common-Source LNA. Therefore, in most CMOS applications where the noise figure is critical issue, a cascode LNA with inductive degeneration is preferable.

Cascode CMOS LNA For a given unit-gain frequency as we lower the bias current, the noise figure decreases. For a given Q, higher gm improves the noise figure.

 For a given source resistance of 50 ohms, as we reduce Ls, unit-gain frequency increases but the minimum value of Ls is limited by parasitic and sensitivity issues. By proper choice of gm, Ls, and Cgs, the input resistance can be equal to 50 ohms source resistance and the input reactance (imaginary part of impedance) can be resonated out by a series inductor (Ls). Inductor degeneration (Ls) also improves the linearity by forming a negative series feedback. As we lower the bias current, while keeping unit-gain frequency constant, Cgs decreases, leading to higher Q. A high Q matching networks has several drawbacks: o Circuit becomes very sensitive to component variations and parasitics. o The input matching circuit which in this case contains a series inductor, inserts a large amount of loss at the input (even for a high-Q off-chip inductor) Another source of noise in the cascode topology is the noise introduced by the cascode device, M2, added to improve stability of the amplifier. o At high frequencies the capacitance at the drain of M1 reduces the impedance of this node, increasing the output noise, so to minimize the noise is very important to minimize this capacitance. o To improve the noise performance of the cascode design, the parasitic capacitance at the drain of M1 is resonated out by adding an inductor to the source of cascode. This inductor should be sized carefully in order to resonate the unwanted capacitances at the desired frequency of operation. 8. GaAs FET LNA Design In case of GaAs FETs generally the input matching network transforms 50 ohms to the input impedance of the transistor, which typically at VHF frequencies is about 3000 ohms. A high-quality circuit usually is used to transform the impedance up and in the same time to filter out unwanted signals. As frequency increases to microwave region (above 10GHz), the GaAs FET input impedance drops to few tens of ohms. HEMTs type transistors have even higher impedance at VHF frequencies (about 5000 ohms) dropping to 50 ohms above 10GHz. Biasing the GaAs FET LNA The input of a GaAs FET is a small Schottky diode, when the input of a HEMT is basically a small Tunnel diode. In normal operation these diodes are negatively biased, effectively making the gate a low value capacitor.

DC Equivalent Model of a GaAs FET

RF Equivalent of a biased GaAs FET

There are two common ways to supply the required negative voltage to the gate of a GaAs FET. This method requires power supply to be more complex than the LNA, but usually is the preferred method in most of the designs. Have the advantage to ground directly the source, and have excellent control of all DC parameters of the GaAs device. One of biggest issue of this biasing method is, the negative supply must turn ON first, and turn OFF last, making the power supply to be complex.
1.

2.

The self-bias method makes the voltage drop across the source resistor raises the substrate of the device above DC ground, giving to the gate a reverse bias. The method has the advantage using only one positive supply and also the thermal run-away is almost eliminated. The device operates in a current limiting mode; more current gives a greater negative bias to the gate, turning OFF the device. RF bypassing of the source becomes difficult at microwave frequencies, and need to use capacitors with low parasitic inductance.

GaAs FET LNA - Input Matching There are few topologies for matching of GaAs FETs, each of them having pros and cons. Remember that, not always want to tune for best Noise Figure or highest gain. This low insertion loss and simple input match circuit, works well up to UHF frequencies. There are not too many choices of tuning and a match from 50 ohms to Gamma Optimum (best Noise Figure) depends on the FETs internal stray capacitance from gate to the ground.

This input match gives a high performance below 500MHz. Can get the best Noise Figure, Gamma Optimum that can be reached. Because the input impedance of the GaAs FET below 500MHz is high, the Q or Bandwidth of the input circuit can be varied with little impact on the Noise Figure. The tapped L input is fine for VHF range high performance LNAs. It has very low loss, input is grounded, but the circuit has very wide bandwidth.

 The Pi input matching network works from low frequencies up to few GHz, and virtually can match any impedance. In the Pi matching network the second capacitor is tuned at a very low value, due to the FET input stray capacitance. This method requires high quality capacitors. The stub circuit is versatile and capable of matching almost of any input impedance, but the assembly is very large below 1GHz and relative difficult to supply the bias voltage. The microstrip stub circuit is limited to microwave frequencies, is narrowband, but has great repeatability.

Just a small inductance in the gate lead can match the impedance in the 1GHz to 2GHz region. The circuit is simple and has low loss, broad bandwidth and excellent Noise Figure.

GaAs FET LNA - Construction and Operating Tips Always leave the LNA powered up. When operating, the gate of the GaAs FET is negatively biased at 0.5V-0.7V. The FET is damaged when the gate has positive voltage and conducts current. You need enough RF at the input to overcome the negative bias before damage the transistor. Typically the circuit needs 4 times more RF leakage power to damage a turned ON GaAs than a turned OFF GaAs FET device. Use very short leads when the circuit works at microwave frequencies. Use small coils and avoid mutual coupling between them placing the inductors 90 to each other. Use Ferrite beads which behave as both, RF absorber and a low-Q RF choke. If use trimmer caps, connect their rotors to the ground or to the connectors. When the microwave LNA is placed inside of a shielded box this become a cavity at some frequency, and the LNA might become an oscillator. Absorbers placed inside of the box help preventing this happen. Typical characteristics of different configurations of High-Frequency GaAs FET LNAs
Characteristic NFmin Gain Bandwidth Stability Reverse Isolation Common-Source (CS) Best Moderate Narrow Compensation often required Lower Common-Gate (CG) Better Low Very Wide RF Decoupling of the Gate is important Moderate Cascode Good High Wide Good Best

References
1. RF Design Magazine (1994-2002) 2. Applied Microwave & Wireless Magazine (1998-2002) 3. Microwaves & RF Magazine (1998-2002) 4. U.L. Rohde, D.P. Newkirk - RF/Microwave Circuit Design John Wiley & Sons, Inc-2000 5. G. Gonzales Microwave Transistor Amplifiers Pretince-Hall 1984 6. Design of Analog CMOS Integrated Circuits B. Razavi 7. GaAs FET Pre Amp Cookbook K. Britain WA5VJB 8. Agilent Technologies IP3 Measurements Data Sheets 9. Avago Technologies Application Datasheets 10. LNA Design Trade-Offs in the Working World - Freescale

Phase Noise in Oscillators

Iulian Rosu, YO3DAC / VA3IUL http://www.qsl.net/va3iul

As well known from oscillator theory, two conditions are required to make a feedback
system oscillate: the open loop gain must be greater than unity; and total phase shift must be 360 at the frequency of oscillation. An oscillator circuit can be a combination of an amplifier with gain A (j ) and a frequency dependent feedback loop H (j ) = !A. Oscillator has positive feedback loop at selected frequency. Frequency Stability is a measure of the degree to which an oscillator maintains the same value of frequency over a given time. Phase Noise can be described as short-term random frequency fluctuations of a signal; is measured in the frequency domain, and is expressed as a ratio of signal power to noise power measured in a 1 Hz bandwidth at a given offset from the desired signal. Phase Noise is a measurement of uncertainty in phase of a signal. It is measured as the ratio of noise power in quadrature (90out of phase) with the carrier signal to the power of carrier signal. This is opposed to AM noise which is noise in phase with the carrier signal. Two measurements of Phase Noise are common: the Spectral Density (SD) of phase fluctuations, and the Single Side Band (SSB) Phase Noise. Spectral Density is twice of SSB, since this is related to total phase change, which includes both sidebands, when SSB Phase Noise corresponds to the relative level on one sideband. The Phase Noise of a signal can only be measured by a system that has equal or better noise performance.

Low oscillator Phase Noise is a necessity for many receiving and transmitting systems. Adjacent Channel Rejection as well as transmitter signal purity are dependent on the Phase Noise of the receiver local oscillator or transmit local oscillator. The local oscillator Phase Noise will limit the ultimate Signal-to-Noise ratio (SNR) which can be achieved when listening to a frequency modulated (FM) or phasemodulated (PM) signal. In a heterodyne system, mixing a clean low-phase-noise RF signal, with a poor phase noise (noisy) local oscillator, it will turn into a noisy IF.

 The oscillator Phase Noise is transferred to the carrier to which the receiver is tuned and is then demodulated. The Phase Noise results in a constant noise power output from the demodulator. Reciprocal mixing is especially important in the presence of strong nearby interferers. The skirt from the down-converted interferer raises the noise floor for the down-converted signal well above Thermal Noise kTB. In a receiver, if a blocking interferer signal is much bigger than the desired signal, than the reciprocal Phase Noise due to the blocker self noise would dominate the noise at IF.

The performance of some types of AM detectors or SSB detectors may be degraded by the local oscillator Phase Noise. Reciprocal mixing may cause the receiver noise floor to increase when strong signals are near the receivers tuned frequency; this limits the ability to recover weak signals. Local oscillator Phase Noise will affect the Bit Error Rate (BER) performance of a Phase-Shift Keyed (PSK) digital transmission system. A transmission error will occur any time if the local oscillator phase, due to its noise, becomes sufficiently large that the digital phase detection makes an incorrect decision as to the transmission phase. For instance, a QPSK transmission system (used in Microwave Links, CDMA, DVB, etc) will make a transmission error if the instantaneous oscillator phase is offset by more than 45 since the phase detector will determine that baud to be in the incorrect quadrant. Digital transmission systems with smaller phase multiples are more sensitive to degradation due to local oscillator Phase Noise. Jitter is another factor that characterizes the oscillator signal and represents a fluctuation in the timing of the signal and arises due to the Phase Noise. Due to Jitter, the zero-crossing time of a periodic signal will vary slightly from the ideal location since the signal is not strictly periodic due to noise.

All of these effects are due to local oscillator Phase Noise, and can only be reduced by careful design decreasing the Phase Noise. The Phase Noise of an oscillator is best described in the frequency domain where the spectral density is characterized by measuring the noise sidebands on either side of the output signal center frequency.

Single Side Band (SSB) Phase Noise is specified in dBc/Hz at a given frequency offset from the carrier.

SSB Phase Noise places limit on receiver Adjacent Channel Selectivity (ACS) and also affects the receiver Signal to Noise Ratio. A model for oscillator SSB Phase Noise was introduced by David B. Leeson in 1966.

where:

= Single Side Band (SSB) Phase Noise density [dBc/Hz] A = Oscillator output power [W] F = device Noise Factor at operating power level A (linear) k = Boltzmanns constant, 1.38 x 10-23 [J/K] T = Temperature [K] Q L = Loaded-Q [dimensionless] fo = Oscillator carrier frequency [Hz] fm = Frequency offset from the carrier [Hz]
PM

Leeson equation only applies between 1/f flicker noise transition frequency (f1) and a frequency (f2) where white noise (flat) dominates.

Leeson equation provides several insights about oscillator SSB Phase noise: Doubling the Loaded-Q improves Phase Noise by 6dB. Doubling the operation frequency results 6dB Phase Noise degradation. Unloaded-Q means the resonant circuit is not loaded by any external terminating impedance. In this case the Q is determined only by resonator losses. Loaded-Q represents the width of the resonance curve, or phase slope, including the effects of external components. In this case the Q is determined mostly by the external components. It is a common design mistake to achieve high Loaded-Q values by using a very loosely coupled resonator. The under-coupling results in increased overall resonator loss requiring an extra amount of gain to compensate it, which in turn, results in thermal noise increase. Resonator loss is a function of its unloaded and loaded Q-factors and is given by:

For example, in a simple feedback oscillator, the minimum Phase Noise is achieved when the resonator Loaded-Q is set to one half of its Unloaded value (QL = 0.5*QU) that corresponds to a 6 dB resonator loss. Other oscillator schemes may require different optimum coupling values due to different design goals and trade-offs.

In the figure above Phase Noise in dBc/Hz is plotted as a function of frequency offset (fm), with the frequency axis on a log scale. Note that the actual curve is approximated by a number of regions, each having a slope of 1/fx, where x = 0 corresponds to the "white" phase noise region (slope = 0 dB/decade), and x = 1 corresponds to the "flicker 1/f" phase noise region (slope = 20 dB/decade). There are also regions where x = 2, 3, 4, and these regions occur progressively closer to the carrier frequency.

 Leeson equation assumed that the 1/f3 and 1/f2 corner occurred precisely at the 1/f corner of the device. In measurements, this is not always the case. The Phase Noise of an oscillator depends by the noise of the open-loop amplifier and by the half-bandwidth of the resonator. If the amplifier has no 1/f noise region, the oscillator will have 1/f2 noise below the half-bandwidth. Unfortunately, all the active devices have some sort 1/f region. If the 1/f flicker corner frequency is low, the oscillator will have 1/f2 noise slope until that corner frequency is reached. This is the case with many LC oscillators. The 1/f region might be due to either active device or resonator. In many cases the noise of the resonator dominates, especially in the case of crystals or SAW devices. In this situation, the crystal should be presented with impedance that doesnt degrade the Q, or else the Phase Noise will also be degraded. Oscillator harmonics can be filtered out by a simple Low Pass Filter, when the spurious close to the carrier can only be minimized by careful oscillator design. Rules for designing a low Phase Noise oscillator: Maximize the resonator Loaded-Q. To do this (but trading with gain), in the series resonant circuits use a large Inductor, and in parallel circuits use a large Capacitor. Coupling the resonator tightly to the oscillating device, and minimize the coupling of the load to the circuit. A 10dB increase in Loaded-Q results in a 20dB improvement in Phase Noise. Build the resonator using high-Q components, having constant and quiet noise. Low losses are required in all of the constituent parts of the circuit including PCB. To be carefully considered the series resistance of the reactive components. Coupled losses in the rest of the circuit should be at most equal to the resonator losses. To get best Phase Noise, the resonator losses should be x3 the circuit losses. Use an active device with low noise figure at low frequencies. Use an active device with low 1/f flicker noise, with good bias circuit. The DC current set to get the best 1/f flicker noise should be the oscillator device current. There is effectively a trade-off between Gain and Phase Noise performance in microwave transistors, both for the additive or multiplicative noises. Maximize the output Signal Power vs Noise Power of the oscillator. However, the output power increase should be implemented very carefully, since severe Phase Noise degradation can occur because of the active device noise elevation at compression. Extract the output signal through the resonator to the load, thereby using the resonator transmission response selectivity to filter the carrier noise spectrum. Optimize (and do trade-offs) in noise reduction where is needed, especially consider close-in noise vs large offset noise requirements. Power Supply (VCC) and tuning voltage (Vtune) returns must be connected to the printed circuit board ground plane. VCO ground plane must be the same as that of

the printed circuit board and therefore all VCO ground pins must be soldered direct to the printed circuit board ground plane. Adequate RF grounding is required. Several chip decoupling capacitors must be provided between the VCC supply and ground. Good, low noise power supplies must be used to prevent AM noise. Ideally, DC batteries for both supply (VCC) and tuning (Vtune) voltages will provide the best overall performance. The biasing circuit of the active device should be properly regulated and filtered to avoid any unwanted signal modulation ore noise injection. Variations on the supply voltages or currents may also cause undesirable output power fluctuations and frequency drift. The active device should work in Class-A, to minimize the limitations in the stage that drives the resonator. Carefully control the limiting amplitude mechanism, so as not introduce AM noise. A signal limiter can be placed either before or after the active device, keeping its output well below the compression level. AM-PM conversion is minimized by choosing a 90 crossing angle between the device line and the load line. Phase perturbation can be minimized by using high impedance devices such as FETs, where the Signal-to-Noise ratio of the signal voltage relative to the equivalent noise voltage can be made very high. Output must be correctly terminated with good load impedance. It is also a good practice to use a resistive pad between the VCO and the external load. Connections to the tuning port must be as short as possible and must be well screened, shielded, and decoupled to prevent the VCO from being modulated by external noise sources. A low noise power supply must be used for tuning voltage. Minimize Frequency Pushing by the Gate or Base voltage of the transistor. Frequency Pushing is a shift in the oscillation frequency usually caused by a change in the transistor bias voltage. Avoid saturation of the active devices at all cost, and try to have either limiting or automatic gain control (AGC) without degradation of the Q of the resonator. Saturation of the active device can also lower the loaded-Q since the device losses will then add to those of the resonator. Use active components with low 1/f-noise. Flicker noise in active devices is also known as 1/f noise because of the 1/f slope characteristics of the noise spectrum (the amplitude varies inversely with frequency). Mainly traps associated with contamination and crystal defects in the emitter-base depletion layer cause this noise (in BJTs case). These traps capture and release carriers in a random fashion. The time constant associated with the process produce a noise signal at low frequencies. Transistors made in different processes have different 1/f noise corners. JFETs are the best (~1kHz), followed by BJTs (~5kHz), than CMOS (~1MHz), and GaAs are the worst (~10MHz). Consider using noise reduction via feedback, or feed-forward noise reduction techniques.

Rules for designing a low Phase Noise Voltage Controlled Oscillator (VCO): In a Phase-Locked Loop (PLL) a Voltage Controlled Oscillator (VCO) will always have some spurious signals present on its output. The amplitude and frequency of these spurious modulations may vary as the local oscillator is tuned.

Poor layout of the phase-locked loop oscillator circuitry (VCO) may increase the amplitude and number of the output spurious signals. Oscillator Phase Noise has two components: Phase Noise resulting from direct upconversion of white noise and flicker noise (1/f noise), and Phase Noise resulting from the changing phase of the noise sources modulating the oscillation frequency. In VCO design another source of Phase Noise increase are the non-linear capacitors (varactors) used in the LC resonator and its control lines. In a VCO, have to maintain the Q of the resonator by avoiding forward bias on the varactor tuning diodes, limiting the signal swing across the tuning diodes to prevent heating and thermal effects. This can be achieved by placing the varactor circuit in the gate or base if possible. The noise from the varactor diode resistance can also become the dominant noise source. For good Phase Noise, the carrier signal effectively appearing across the varactor noise resistance should be maximized to maintain good Signal-to-Noise ratio at this point. By transforming the noise load resistance seen by the oscillating device to a lower value in the matching circuit, the Power-to-Noise ratio across the varactor can be maximized, although at the expense of tuning bandwidth since the matching circuit will restrict the obtainable capacitance variation. There is a compromise in order to avoid breakdown, saturation, or overheating effects in the varactor. These will all reduce the Loaded-Q. When frequency of the carrier increases, it is more difficult to achieve good Phase Noise Its easy to achieve good Phase Noise when the frequency range covered by VCO is narrow; the tuning bandwidth must be small. Generated energy should be coupled from the resonator rather than from another portion of the active device so that the resonator limits the bandwidth. Increasing tuning sensitivity (measured in MHz / V) degrades Phase Noise. For a given frequency its easy to achieve good Phase Noise in VCOs using a wide tuning voltage range. Temperature affects the Phase Noise. In a range of 55C to +85C the variation is +/- 3 dB of the Phase Noise. Using of back-to-back varactor diodes in the tuning circuits has been found to eliminate effects of tuning circuit diode noise on oscillator signal spectral performance.

Characteristics of the ideal resonator for low Phase Noise oscillator: High Group Delay (high resonator Loaded-Q). High operating frequency. Low Loss. Moderate Drive Capability. Low frequency sensitivity to environmental stress (vibration, temperature, etc.). Good short-term and long-term frequency stability. Accurate frequency set-on capability. External frequency tuning capability. No undesired resonant modes or higher loss in undesired resonant modes or undesired resonant mode frequencies far from desired operating frequency. High manufacturing yield of acceptable devices. In-circuit resonator effective Q can be determined by intentionally altering the circuit phase shift by a known amount and measuring the resultant oscillator signal frequency shift. Passive components in the oscillator circuit also exhibit short-term instability. Passive components (resistors, capacitors, inductors, reverse-biased, varactor diodes) exhibit varying levels of flicker-of-impedance instability whose effects can be comparable to or higher than to that of the sustaining stage amplifier 1/f AM and PM noise in the oscillator circuit. The oscillator frequency control element (i.e., resonator) can exhibit dominant levels of flicker-of-resonant frequency instability, especially acoustic resonators. Rules to select a transistor and its bias for designing a low Phase Noise oscillator: The best oscillator transistor is a device with the lowest possible noise figure and lowest fT. A commonly used criteria is: fT " 2 * fosc. Meantime, doing a trade-off, have to use a high frequency transistor having small junction capacitance and operate at moderately high bias voltage to reduce phase modulation due to junction capacitance noise modulation. Low 1/f noise of the transistor in the oscillator is very important, because the 1/f noise appears as sideband noise around the carrier frequency of the oscillator output signal. The 1/f noise is directly related to the current density in the transistor. Transistors with high Icmax used at low currents have best 1/f performance. For low Phase Noise operation use a medium power transistor. If you need your output power to be achieved at 6-9 mA, select a transistor with Icmax of 60-90 mA. However, the ft of a transistor drops as current is decreased. Additionally, the parasitic capacitances of a high current transistor are higher due to the larger transistor structure required.

 In BJTs as VCE increases, the flicker corner increases as the white noise increases, but the magnitude of the 1/f noise is constant. As base current increases, the flicker corner frequency increases with the magnitude of the 1/f noise and the increased shot noise current. The effect of flicker noise can be reduced through RF feedback. An unbypassed emitter resistor of 10-30 # in a BJT circuit can improve the flicker noise by as much as 40 dB. The proper bias point of the active device is important. In a well-designed near-class-A oscillator, the frequency is determined primarily by the resonator. As the loaded-Q is increased, the active device parasitic reactances become less significant in determining the oscillation frequency. Thus, changes in these parameters from device to device, with temperature and with supply voltage, have less effect. A simple test of how well the active device reactances are isolated from the resonator is to observe the operating frequency as the supply voltage is varied. Precautions should be taken to prevent modulation of the input and output dynamic capacitances of the transistor; which will cause amplitude-to-phase conversion and therefore introduce noise. If phase shift in the transistor changes, the oscillation frequency will change until the loop phase shift returns to zero. Thus phase modulation in the amplifier causes frequency modulation of the oscillator. Device with low noise figure combined with a small correlation coefficient. Device with relative high output power. Device with low output conductance. Device with reasonably high input impedance. Meeting an impedance condition at the input of the active device, which can be achieved by optimization of the feedback factor and which leads to optimum impedance noise matching. Device with low multiplicative noise (1/f AM and especially 1/f PM). Device having drive capability consistent with resonator drive level and loss. Low noise in ALC/AGC circuits and/or in-compression amplifier operation. Low gain and phase sensitivity to DC supply and circuit temperature variations. Device with low Group Delay (wide bandwidth). Device with high load circuit isolation. Device with minimal number of adjustable and bias components. Ease of alignment and test. Device with good DC efficiency. In a PLL the design of the loop filter can affect the Phase Noise of the system:

Within the loop bandwidth, the Phase Noise of the oscillator will tend to cancel itself, leaving a Phase Noise essentially equal to the frequency multiplied Phase Noise of the crystal reference. Multiplied Phase Noise of the crystal reference at particular frequency offset is equal with reference Phase Noise at the same frequency offset plus 20*LOG(N VCO_divider) plus 1dB (multiplication efficiency factor).

Outside the loop bandwidth, the Phase Noise of the oscillator is not canceled, and will continue to decrease, until reaching its half bandwidth, o/2Q or 1/f corner frequency. Since the Q of the crystal reference is very large, its half bandwidth is very small, and its frequency multiplied Phase Noise will remain relatively flat down to very small frequency offsets. Further, at some moderate frequency offset, this multiplied phase noise power spectral-density will be crossed by the decreasing oscillator phase noise power spectral-density. The bandwidth of the loop should be chosen equal to the frequency offset of this crossover. The PLL loop bandwidth is not a barrier frequency with a discontinuity on either side of the barrier; it can be approximated as such with the proviso that small errors around the offset frequency equal to the loop bandwidth are accepted.

The role of the loop filter, which is a low-pass filter inserted between the phase comparator and the VCO control voltage circuit, eliminates the high frequency component of the phase correction pulse generated by the phase comparator so that the only the DC component is provided to the VCO. As a rule of thumb, the cut off frequency of the low-pass filter is chosen as equal or less than comparison frequency divided by ten; Fcutooff < (Fcomparision / 10) Usually the low-pass filter is an RC network. The analysis of the Phase Noise performance shows that the Phase Noise depends on the resistor value, part of the low-pass filter. The higher the resistor, the higher is its contribution to the Phase Noise. Phase Noise in Crystal Oscillators One of the most important characteristics of crystal oscillators, besides they can provide good frequency stability, is that they can exhibit very low Phase Noise. In many oscillators, any spectral energy at the resonant frequency will be amplified by the oscillator, resulting in a collection of tones at different phases. In a crystal oscillator, the crystal mostly vibrates in one axis, therefore only one phase is dominant.

 At lower offset frequencies approaching the carrier, the Phase Noise is determined by the quality Q of the crystal resonator. For example a 100MHz crystal has a considerably lower Q than a 10MHz crystal, so the noise is higher at the low offsets. The amplitude of 1/f flicker noise in crystal resonators is a very important parameter of oscillators used in various applications. To get accurate models of the 1/f frequency noise in the resonator itself, this should be independent of the noise generated by the afferent electronic circuit. Was discovered that the amplitude of the 1/f frequency noise in a crystal depends not only on the Q of the resonator but also on the volume between the electrodes. Since the amplitude of 1/f noise depends on active crystal volume, to get low closein Phase Noise we have to use the lowest overtone and lowest resonator frequency. Extra noise source is associated with electrode-crystal interface. A resonator having smaller electrodes would have lower 1/f flicker noise than other with the same resonant frequency and Q, but with larger diameter electrodes. The decrease in electrode area would increase the impedance and degrade the wideband noise, but for most resonators the wideband noise is dominated by the electronics of the oscillator. The increase in series resistance decreasing the electrode diameter by a factor of 4 would be probably the limit from the standpoint of wideband noise. This change might lead in a change of the oscillator loop gain. Thus for application specifically requires minimum close-in Phase Noise, lower frequency crystals may be used, when for low noise floor applications (wideband noise), the highest frequency crystal which satisfies long term stability requirements should generally be used. Also was discovered that 1/f frequency noise in a crystal is virtually independent of the loaded-Q of the resonator, when we know that in a practical oscillator circuit there is a dependence of the Phase Noise on loaded-Q, because the sustaining electronics contribute to the overall noise level. The crystal resonator plate can be cut from the source crystal in many different ways. The orientation of the crystal cut influences the crystal's frequency stability, Phase Noise characteristics, aging characteristics, thermal characteristics, and other parameters. A special cut (SC - Stress Compensated), is a double-rotated cut developed for oven stabilized oscillators with low Phase Noise, and good aging characteristics. This special cut SC is less sensitive to mechanical stresses, and has faster warm-up speed, higher Q, better close-in Phase Noise, less sensitivity to spatial orientation, and less sensitivity to vibrations. Various topologies of crystal oscillators exhibit different performances mainly due to the limiting functions of the circuit, and of the loaded-Q of the crystal resonator. In many instances decision of selection of particular type of crystal oscillator configuration is made on the basis of short-term frequency stability.

Pierce

Miller

Butler

Bridge-Tee

Driscoll

In most anti-resonant circuit configurations (such as Pierce and Miller configurations), the out-of-band impedances may become reactive due to the sharp reactance vs frequency characteristic exhibited by the crystal unit. The series-mode circuits (as Butler and Bridge-Tee configurations) are more effective in reducing the wideband noise floor (up to 10dB compared to anti-resonant circuit). The main disadvantage of series-mode circuits is the large degradation in crystal unit loaded-Q (due to limiting of the transistor). For example the effective value for crystal unit loaded-Q is about 120.000 for the Pierce circuit, and 24.000 for Bridge-Tee circuit. When limiting occurs, the transistor is turned OFF for a time portion of the signal waveform, time when the impedance seen by the crystal resonator at the transistor emitter contains a large value component at the signal frequency. This component of transistor impedance (which becomes increasingly large as the excess gain in the sustaining stage is increased) it will degrade the oscillator loaded-Q. In addition, the degradation in crystal loaded-Q can produce degradation in oscillator long-term frequency stability. This includes changes caused by environment (temperature, humidity) long-term power supply variation, and shortterm effects (vibration and power supply ripple). Thus, better output noise spectrum could be obtained using a crystal oscillator in series-mode configuration, employing class-A non-limiting action in the sustaining stage transistor. The limiting function in a crystal oscillator may be controlled by: 1. Auxiliary low-noise AGC circuits (a portion of the amplified RF signal is rectified and used to control the RF gain of the sustaining stage). 2. Back-to-back Schottky diodes incorporated in the oscillator circuit, so that the diode RF impedance presented to the sustaining stage (and hence the RF gain) decreases with increasing the RF level. 3. Incorporation of a second self-limiting transistor stage in the oscillator sustaining circuit, in a manner such that its effect on crystal unit loading is insignificant. In 1972 M.M. Driscoll developed a very low Phase Noise series-mode crystal oscillator employing two transistors connected in cascode configuration. - The quartz crystal resonator is used as an un-bypassed emitter load on Q1. - Unlike the common Butler or Bridged-Tee circuits, Q1 is ON during the full cycle of the signal waveform, since the limiting function is provided in Q2. - Connecting the crystal between emitter of Q1 and ground increase the crystal loaded-Q. Reducing the emitter impedance by increasing the bias current of Q1 avoid over-dissipating power into the crystal.

Measuring the Oscillator Phase Noise Generally the Spectral Density, or Phase Noise, of an oscillator is measured in dBc (dB below the carrier) in a bandwidth of 1Hz at an offset frequency fn. The Phase Noise, therefore, is related to the output power. The Noise Power and the curve can have different shapes based on the noise sources.

Phase_Noise[dBc/Hz] = 10*LOG (Pn / Ps) Pn = Noise Power in 1Hz Bandwidth at particular frequency offset (fn) in Watts Ps = Carrier signal power in Watts

A. The simplest and fastest method of determining the Phase Noise of an oscillator is the direct measurement using a Spectrum Analyzer. For this measurement, the tested oscillator must fulfill the following conditions: The oscillator drift must be small relative to the Spectrum Analyzer sweep time since otherwise the oscillator frequency varies during the sweep, leading to distorted results. The synthesizers commonly used in radio communications fulfill this condition since they are locked to a stable reference. The Phase Noise of the local oscillators of the Spectrum Analyzer must be low enough to ensure that the characteristics of the tested oscillator and not those of the Spectrum Analyzer are determined. Factors that limit the analyzers ability to correctly measure the Phase Noise of a signal: IF (RBW) filter bandwidth, verses noise bandwidth. IF filter type and shape factor. Analyzers local oscillator stability - residual FM. Analyzers local oscillator stability - noise sidebands. Analyzer's detector response to noise - peak detector introduces errors. Analyzer's log amplifiers response to noise. Noise floor of the analyzer. When measure the oscillator Phase Noise using a Spectrum Analyzer the following equation can be used for direct reading in dBc/Hz, for particular Resolution Bandwidth (RBW) set on the analyzer:
Phase_Noise[dBc/Hz] = Carrier_Power[dBm] Noise_Power@Freq_offset[dBm] 10*LOG (RBW[Hz])

Spectrum Analyzers generally only measure the scalar magnitude of noise sidebands of the signal and are not able to differentiate between amplitude noise and phase noise. In addition, the measurement process is complicated by having to make a noise measurement at each frequency offset of interest, sometimes a very time consuming task. B. Another Phase Noise measurement can be done using a Reference Oscillator and a Phase Detector: The Phase Detector converts phase difference between its two inputs into a voltage When the phase difference between the two inputs is 90 (quadrature) the Phase Detector output will be 0 volts. Any phase fluctuations around the quadrature point will result in a voltage fluctuation at the output of the Phase Detector. The Phase Detector output can then be digitized and processed to obtain the phase noise information desired. Additionally, the Phase Detector technique also enables residual/additive noise measurements for two-port devices. Several methods have been developed based upon the phase detector concept. Among them, the Reference Source / PLL (Phase Locked Loop) is one of the most widely used methods.

Phase Noise measurement using a Reference Oscillator and a Phase Detector

The reference oscillator is synchronized to the measured oscillator by means of a PLL of a very small bandwidth. The PLL sets the phases of the two oscillators to a difference of 90. The Phase Noise of the DUT is eliminated within the loop bandwidth. The sum noise power of the reference and the test oscillator obtained outside the loop bandwidth is present at the output of the phase detector. This output signal is amplified by means of an LNA (Low Noise Amplifier) and displayed on a Spectrum Analyzer starting at a frequency of 0Hz. This method offers the advantage of a very wide dynamic range, provided that the reference oscillator is of a very high spectral purity. Often, two identical oscillators are used for measurements on crystal oscillators, and the assumption made that the two

oscillators have the same Phase Noise. In this case, 3 dB is subtracted from the result because the noise powers add up. Also this method yields the widest measurement coverage (e.g. the frequency offset range is 0.01 Hz to 100 MHz). This method is insensitive to AM noise and capable of tacking drifting sources. The disadvantages of this method are: The method requires two oscillators at the same frequency that have to be synchronized to each other. An extra PLL and a Low Noise Amplifier are needed. Calibration is complex because the gain of all components is included in the result. Calibration is made by mistuning the two oscillators relative to each other and measuring the AC voltage obtained at the output of the LNA. Requiring a clean, electronically tunable reference source, and that measuring high drift rate sources requires reference with a wide tuning range. C. The Frequency Discriminator method is another variation of the Phase Detector technique with the requirement of a reference source being eliminated.

The signal from the tested oscillator is split into two channels. The signal in one path is delayed relative to the signal in the other path. The delay line converts the frequency fluctuations to phase fluctuations. Adjusting the delay line or the phase shifter will determine the phase quadrature of the two inputs to the mixer (phase detector). Then, the mixer (working as a phase detector) converts phase fluctuations to voltage fluctuations, which can then be read by the baseband Spectrum Analyzer as a frequency noise. The frequency noise is then converted as a phase noise reading. The Frequency Discriminator method degrades the measurement sensitivity (at close-in offset frequencies) but is useful when the tested oscillator is a noisier source that has high-level, low-rate phase noise, or has high close-in spurious sidebands which can make problems for the phase detector PLL technique. A longer delay line will improve the sensitivity but the insertion loss of the delay line may exceed the source power available and cancel any further improvement. Longer delay lines limit the maximum offset frequency that can be measured. This method is best used for free-running sources such as LC oscillators or cavity oscillators.

References:
1. Low Noise Oscillator Design and Performance M.M.Driscoll 2. Two-Stage Self-Limiting Series Mode Type Quartz-Crystal Oscillator Exhibiting Improved ShortTerm Frequency Stability (June 1973) M.M.Driscoll 3. A simple model for feed back oscillator noise- IEEE 54(2):329 (Feb 1966) D. B. Leeson 4. Oscillator Design and Computer Simulation - R.W. Rhea 5. RF/Microwave Circuit Design for Wireless Applications - U. Rohde and D. Newkirk 6. Microwave Circuit Design using Linear and Nonlinear Techniques - Vendelin, Pavio, U. Rohde 7. RF Design Guide P. Vizmuller 8. Practical RF Circuit Design for Modern Wireless Systems - vol 2 - Gilmore, Besser 9. Phase Noise Reductions in Microwave Oscillators A. Chenakin 10. California Eastern Laboratories - AN1026 - 1/f Noise Characteristics Influencing Phase Noise 11. Infineon Technologies - AN023 - Designing Oscillators with low 1/f-noise 12. Analysis and Prediction of Phase Noise in Resonators and Oscillators HP 13. A New Model of 1/f Noise in BAW Quartz Resonators Walls, Handel, Besson, Gagnepain 14. RF Oscillators - Besser Associates, Inc. 15. Mini-Circuits VCO Designers Handbook 2001 16. Applied Microwave and Wireless, 1997-2002 17. Analog Devices Application Notes, 2005 18. Phase Noise Measurements with Spectrum Analyzers of the FSE family - R&S 19. Phase Noise Measurement Methods and Techniques - Agilent 20. RF Design Magazine, 1993-2002 21. Microwave Journal, 1997-2012

Home:

http://www.qsl.net/va3iul/

Phase Shifters
Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul/ Phase Shifters are devices, in which the phase of an electromagnetic wave of a given frequency can be shifted when propagating through a transmission line. In many fields of electronics, it is often necessary to change the phase of signals. RF and microwave Phase Shifters have many applications in various equipments such as phase discriminators, beam forming networks, power dividers, linearization of power amplifiers, and phase array antennas. The major parameters which define the RF and microwave Phase Shifters are: frequency range, bandwidth (BW), total phase variance ( ), insertion loss (IL), switching speed, power handling (P), accuracy and resolution, input/output matching (VSWR) or return loss (RL), harmonics level. Relation between Propagation Constant, Phase Shift, Delay, and Wavelength In a transmission line the Propagation Constant is a complex number having two parts: - the real portion is the attenuation constant ( , neper per unit length) - the imaginary portion !x is called the phase constant (!, radians per unit length). The attenuation constant determines the way a signal is reduced in amplitude as it propagates down the line, while the phase constant ! shows the difference in phase between the voltage at the sending end of the line and at a distance x. The phase constant !x shows the phase shift of the voltage (or current) at a point located at a distance x along a transmission line with respect to the sending voltage (or current). A phase shift of 360 (or 2" radians) equals one wavelength and, as shown in figure below, marks the distance between successive points on the waveform (such as zero crossings). The wavelength # is the distance x required to make the phase angle !x increase by 2" radians. # = 2" / !

Relationship between degrees (), radians (2 ), phase shift (!), and wavelength (") From the figure above can be stated that a phase shift may also be seen as a delay. The relation between the phase shift and the time delay is given by: Time delay (seconds) = [Phase Shift ()] / [360 x frequency (Hz)] The time delay is proportional to the inverse of velocity Vp. The amount of delay a transmission line introduces per distance x is: Time delay = x / Vp = (!x / $) Group delay is the average delay time that a specified narrow range of frequencies experiences when passing through a circuit. Group delay is proportional to the rate of phase shift at each frequency of interest. Group delay (seconds) = [1 / 360] x [% / %f ]

 For a stripline, the velocity of propagation (and thus the delay per distance x) is the same for all traces, but for microstrip the velocity (and thus the delay) depends on the traces width and height above the ground plane, making this the fundamental difference between stripline and microstrip designs. A microwave Phase Shifter is a circuit which gives a preset phase shift amount to a highfrequency signal and is normally configured by combining several transmission lines, a switch circuit, or some similar circuits. Analog Phase Shifters are devices whose phase shift changes continuously with the control input and therefore offer almost unlimited resolution with monotonic performance. The most commonly semiconductor control elements used in analog Phase Shifters are varactor diodes. Varactor diode operates in a reverse-biased condition providing a junction capacitance that varies with applied voltage, and can be used as an electrically variable capacitor in a tuned circuit. Varactor analog Phase Shifters can achieve a large amount of phase shift and high speed and require fewer diodes than digital phase shifters, but at the cost of decreased accuracy, relatively narrow bandwidth, and low input power levels (less than 1 W). Schottky diodes are also used as variable elements in analog Phase Shifters, but they suffer from limited power handling capability and matching difficulty in broadband networks. Most usual methods to implement Phase Shifters are based on switched line, loaded line, and reflection theories.

The Switched-Line approach is the most straightforward approach because it uses the simple time delay difference between two direct paths to provide desired phase shift. The switching elements in digital phase shifters are: mechanical switches (or relays), PIN diodes, Field Effect Transistors (FET), or microelectromechanical systems (MEMS). PIN diodes are common used in Phase Shifters due their high speed switching time, low loss, and relative simple bias circuits, which provides changes of PIN resistance approximately from 10 kilo-ohms to 1 ohm. The PIN diode switched line Phase Shifters can be classified as follow: Type of the transmission line (regular, irregular, and coupled) number of bits structure (reflection or non-reflection) with reciprocal and non-reciprocal devices number of switched inputs/outputs (SPST, SPDT, SP3T, etc.); PIN diode connection with transmission line (series, shunt, series-shunt); bandwidth (narrow or broadband); configuration of elements (distributed, lumped-elements, or combination of lumped and distributed); The standard switched line Phase Shifter is using switched transmission line segments, getting different path length and determining in this way the amount of phase shift. The simplest switched line Phase Shifter is dependent only on the lengths of line used. One of the two transmission lines is labeled as a reference line, and the other as a delay line. An important advantage of this circuit is that the phase shift will be approximately a linear function of frequency, getting a wideband frequency range of the circuit. The phase shift created is dependent only by the length of the transmission lines, making the Phase Shifter very stable over time and temperature. PIN diodes may suffer for insertion loss tolerance or peak power capability, but both characteristics dont affect the phase shift.

Switched-line Phase Shifters

Figure above illustrates the schematics of the conventional switched-line Phase Shifter with RF input P1 and RF output P2. Schematic (a) use two SPDT mechanical switches (or relays), when figure (b) use four PIN diodes, and two transmission lines L1 and L2. Only one arm should be ON at a time. Typically, to avoid the phase errors the isolation of the switches must exceed 20dB in the required frequency band. Insertion loss of the switched-line Phase Shifter is equal to the loss of the SPDT switches plus the line losses. By switching the signal between two pre-determined lengths of transmission lines it is possible to realize a specific phase shift (#) at a given frequency. % = 2" x (%L / #) where % is the phase shift, %L is the difference between the physical lengths of the delay line (L2) and the reference line (L1), and # is the guide wavelength. The phase shift value deviate linearly from the intended value as the frequency of the signal deviates in either direction from the center (nominal) frequency. Switched-line Phase Shifters generally are used for 180 and 90 phase shifts. When path L2 is a half wavelength ("/2) longer than path L1, switching from path L1 to path L2 introduces an increased phase delay of 180. So, to get a 180 phase shift the required physical length difference should be #L = "/2. In a practical design resonances could appear in the OFF line when the line length is a multiple of "/2, and the phases will interfere in a way to reflect much of the incoming power back to the input port. Thus, both lengths (L1 and L2) must not be multiples of "/2. The resonant frequency will be slightly shifted due to the series junction capacitances of the reversed biased diodes, or of the parasitic capacitances of the SPDT mechanical switches. The lengths L1 and L2 must be carefully selected to avoid phase errors, high return loss, and high insertion loss. To reduce the number of PIN diodes could be used the circuit in figure (c), replacing the reference L1 line with a series PIN diode. In this circuit, for the 180 phase shifting, both PIN diodes are in the OFF position, and the RF signal passes through line L2 with "/2 length, providing a 180 phase shift. The shunt diode is placed at the middle of L2, at "/4 wavelength from its ends. In 1958 Bernard Schiffman published for the first time a Phase Shifter using a "/4 wavelength coupler section which provides flat wideband phase shift response. The Schiffman Phase Shifter shown in the picture below use a switched-line with two SPDT switches, one reference regular line of length 3L, and two other parallel coupled lines of equal length L = "/4, directly connected to each other at one end. Phase shift function is determined by the phase difference of signals transmitted through the coupled section of length L and the reference line of length 3L.

Schiffman Phase Shifter The contribution of the Schiffman Phase Shifter is that the phase difference between a quarterwave coupled section, compared to a 3/4 wave straight section, would provide a nearly flat 90 phase differential. For multi-octave operation, the number of coupled sections interconnected in a cascade can be used, as shown in the picture below.

Multi-octave Schiffman Phase Shifter It is a cascade of coupled sections of equal lengths (one quarter wavelength "/4 at the center operating frequency), but using different coupling coefficients (k1 $ k2 $ k3) At low frequencies, to minimize the dimensions of the circuit, the quarter-wavelength "/4 segments of the Phase Shifter delay line could be substituted with equivalent lumped element circuits as shown in the figure below. Each sine-wave component has its phase shifted by reactances within a circuit. The lumped element configuration of the 180 Phase Shifter (figure below) can be recommended for applications for low frequencies (HF) up to UHF ranges.

Lumped element Phase Shifter A single-pole RL, RC, circuit contributes up to 90 phase shift per pole, and to get 180 phase shift, at least two poles must be used. For example in oscillator design, because 180 of phase shift is required for oscillation, at least two poles must be used. Phase shift in oscillator situation determines the oscillation frequency because the circuit oscillates at whatever frequency accumulates a 180 phase shift. The sensitivity of phase to frequency, d% / d&, determines the frequency stability. In the region where the phase shift is 180, the frequency of oscillation is very sensitive to the phase shift. Thus, a tight frequency specification requires that the phase shift, d%, be kept within exceedingly narrow limits for there to be only small variations in frequency, d&, at 180. The 180 phase shift is commonly designed using switched Low-Pass and High-Pass topology as shown in the figure below:

Switched Low-Pass and High-Pass Phase Shifter The cut-off frequencies of the Low Pass and High Pass filter networks must be outside of the phase shift band for this scheme to work. Note that for higher frequencies the phase shift of LP-HP networks gets a nearly flat response, which is not possible from a switched line Phase Shifter. The equations for L and C for PI-network with characteristic length are given.

The Quadrature Phase Shifter is a load-line Phase Shifter sometimes named Reflective Phase Shifter. This is mainly a quadrature coupler which splits the input signal into two signals 90 out of phase. These signals reflect from a pair of switched loads, and combine in phase at the phase shifter output, as long as the loads are identical in reflection coefficient (both magnitude and phase).

Quadrature Phase Shifter using switched-lines The quadrature Phase Shifter can be used to provide any desired phase shift. Ideally, the loads should present purely reactive impedances, which can range from a short circuit to an open circuit or anything in between. This structure provides a bandwidth of up to an octave, depending on the bandwidth of the quadrature coupler itself. The coupler can be a Lange Coupler, a Hybrid Coupler, or a Rat-Race Coupler on microstrip, or an overlay coupler in a stripline circuit. The main type of reflective Phase Shifter uses switched-line lengths either by using a PIN diode switch or by a variable reactance (e.g. varactor) to alter electrical length.

Quadrature Phase Shifters (Hybrid and Lange) using varactors

The quadrature Phase Shifters in the figure above uses a 90 hybrid coupler (left picture), or a Lange coupler (right picture). Instead of switched-lines the circuits uses variable reactances. A variable reactance is in effect a variable electrical length; therefore using a variable reactance such as a varactor we can form a variable Phase Shifter. The varactor components act as ideal, lossless reactive loads with reflection coefficient from 0 (open circuit - zero varactor capacitance) to -180 (short circuit infinite varactor capacitance). Instead of a varactor a variable inductor can be used. For an ideal variable inductor, the phase changes from -180 to 0. If both were connected in series, the ideal result would be a 360 phase shift change. By resonating the capacitance of the varactor with a series inductor, the phase control range can be significantly increased, up to an ideal 360 phase shift change. One significant benefits of this configuration is the fact that the input and output impedance matching is preserved, although the coupler is terminated with reactive loads. In other words, the coupler serves as an impedance isolator. Other Phase Shifter circuits, as shown in the pictures below, are usually more expensive (circulator cost) or require more diodes. The loaded line circuit which had been popular in early Phase Shifter designs requires a very large number of diodes.

Phase Shifter using Isolator and switched-lines

Phase Shifter using Load-Line

Digital Multi-bit Phase Shifters can be used to vary the phase shift up to 360. Digital Phase Shifters provide a discrete set of phase states that are controlled by two states phase bits. The number of binary weighted phase shifting bits can be cascaded to realize a variable phase shifter covering the desired range. Typically, the Phase Shifters are placed in tandem, with progressively greater phase shift angles to provide phase angle selectivity. Each switched delay line comprises a plurality of fixed time delays, which are combined to produce successive increments of delay in response to binary control signals.

Two-Bit Phase Shifter The Phase Shifter in the figure above illustrates an example of a 2-bit Phase Shifter. Four differential phase states result from switching the four SPDT switches. These differential phases are 0 (reference), 22.5 45, and 67.5. One major application of the multi-bit Phase Shifters is in phased-array antennas. Figure below is a basic diagram of a 4-bit digital Phase Shifter.

Four-bit Digital Phase Shifter A 4-bit Phase Shifter employs four cascaded switched-line phase shifters. By using the proper combination of ON/OFF states, the 4-bit Phase Shifter realizes discrete phase states between 0 and 360 at 360/16 = 22.5 interval (16 steps). To minimize phase quantization error, the number of bits, and hence the number of Phase Shifters, should be increased. The greater the number of bits, the higher the complexity of the Phase Shifter and the RF loss. A Distributed Phase Shifter is created by adding tunable reactance to a transmission line TL.

Distributed Phase Shifter using a Varactor as tunable reactance

 Adjusting the reactance alters the phase velocity of the signal propagating along the line, varying its electrical length, and therefore the phase shift. Changing the phase velocity also changes the characteristic impedance of the transmission line, so an impedance mismatch can occur as the circuit is tuned. In general, it should be possible to add both series and shunt tunable reactance to the transmission line to keep an impedance match with tuning; The majority of distributed Phase Shifters focus on adding tunable shunt capacitances, because tunable inductors are harder to make. For example ferroelectric varactors, MEMS, and PIN diodes are all capable to add a periodically shunt capacitance as discrete elements to the transmission line. This capacitance loading makes the distributed Phase Shifter a periodic structure, with a pass-band and a stop-band. The design has to ensure the frequencies of interest fall into the pass-band, keeping the other parameters of the Phase Shifter. The Toroidal Ferrite Phase Shifter employs the use of a toroidal shaped ferrite bar placed in a rectangular waveguide. A drive wire is inserted longitudinally through the center core of the toroid to provide transverse magnetization in the toroid.

Toroidal Ferite Phase Shifter Phase shift values from 180 to +180 is achieved by varying the current in the drive wire, hence varying the biasing magnetic field in the toroid. The magnitude and timing of the current is carefully controlled by sophisticated drive electronics in order to maintain accurate and consistent phase shift values over a wide temperature range. This Phase Shifter can operate as an analog device by using a long toroid and varying the phase shift by means of changing the holding current in the drive wire. It can also operate as a digital device by magnetically latching the toroid (no holding current) to the various minor hysteresis loops. The amount of phase shift is determined by the magnitude and the time duration of the voltage pulse. In applications where fast switching speed is required, the long toroid can be split into smaller sections, each section corresponding to a binary phase bit. In this case each section is magnetized into saturation and is quickly switchable since the volume of ferrite material for each section is significantly smaller. The Toroidal Phase Shifter is a non-reciprocal type, since the phase shift must be reset between transmit and receive modes.

Phase Shifters in Phased Array Antennas In electronically scanned antenna arrays the Phase Shifters are the devices that allow the antenna beam to be steered in the desired direction without physically repositioning the antenna. A phased array antenna consists of two or more of radiating elements which are spatially arranged that emit phased signals to form a radio beam. Each radiating element requires a Phase Shifter that applies the necessary phase shift to steer the antenna beam. When you steer the beam, you adjust the phase of the elements so that individual signals line up at the desired beam-pointing angle (theta). Having phase settings that don't change with frequency helps keeping the beam pointed where you want when you shift frequencies. Array beam forming techniques exist that can yield multiple, simultaneously available beams. The beams can be made to have high gain and low sidelobes, or controlled beamwidth. The simplest way of controlling signal phase is to systematically vary the cable lengths to the elements. Cables delay the signal and so shift the phase. However, this does not allow the antenna to be dynamically steered. Antenna Beam forming In beam forming, both the amplitude and the phase of each antenna element are controlled. Combined amplitude and phase control can be used to adjust side lobe levels and steer nulls better than can be achieved by phase control alone. A beam former radio transmitter applies the complex weight to the transmit signal (shifts the phase and sets the amplitude) for each element of the antenna array.

Simple Phase Shift beam forming for Two-Antenna System

Vector Modulator Phase Shifter Another application of the Phase Shifters is the Vector Modulator. Vector modulators Phase Shifter structure can cover a phase shift up to 360. Figure below shows the diagram of a vector modulator with phase control range of 90.

Vector modulation with 90 phase control range and its vector diagram The input signal is divided in two paths with defined phase offsets (usually 90 or 120), which amplitudes are controlled by variable gain amplifiers or variable attenuators. After generation of phase offset between these two paths, the signals are combined. Four signal paths with phase offsets of 90, or three paths with 120 phase offset, can be used for 360 vector modulators. Every desired phase within the 360 phase control range can be obtained by weighting the amplitudes of the phase paths. The amplitude of the amplifiers can be set by analog control voltages, but the amplitude in variable gain amplifiers cannot be controlled without influencing the phase shift. In real circuits amplitude control is always associated with a certain phase variation. Typically the amplitude control should be at least 20dB. Input and output impedances of the circuit should be constant vs amplitude control, otherwise phase variations can appear when more stages are connected. The gain should be a linear function of voltage and ideally the phase deviation across the assumed gain range should be equal to zero. In the passive vector modulator approach shown in the picture below, the amplitudes of vectors are controlled by cold FETs, used as variable resistors. The 120 phase offset of the signal is generated by High-Pass and Low-Pass networks, and a 0 direct path. Varying the control voltages Vc-LP, Vc-dir and Vc-HP the amplitude of the signal paths can be controlled.

In the same time the control voltage is used to compensate for phase errors introduced by the FETs vs gain control.

Passive Vector Modulator Phase Shifter type

References: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. Electrically Tunable Switched-Line Diode Phase Shifters - L. Maloratsky High Frequency Circuit Design - J. Hardy High Speed Circuit Board Signal Integrity - S. Thierauf Lumped Elements for RF and Microwave Circuits I. Bahl Microstrip Lines and Slotlines K. Gupta, R. Garg, I. Bahl, P. Bhartia Radio Frequency Integrated Circuits and Technologies F. Ellinger RF and Microwave Wireless Systems K. Chang Understanding Microwaves A. Scott RF Variable Phase Shifters for Multiple Smart Antenna Transceivers H. Zarei Varactor Controlled Phase Shifter for PCS Base Station Alpha Applications of PIN Diodes Alpha Applications of PIN Diodes Avago Affordable Phase Shifters Agile Materials & Technologies Microwave Journal 1996 2011 High Frequency Electronics 2000 - 2011

RF Mixers
Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul

RF Mixers are 3-port active or passive devices. They are designed to yield both, a sum and a difference frequency at a single output port when two distinct input frequencies are inserted into the other two ports. In addition to this, a Mixer can be used as a phase detector or as a demodulator.

The two signals inserted into the two input ports are usually the Local Oscillator signal, and the incoming (for a receiver) or outgoing (for a transmitter) signal. To produce a new frequency (or new frequencies) requires a nonlinear device. In a mixing process if we want to produce an output frequency that is lower than the input signal frequency, then it is called down-conversion and if we want to produce an output signal that is at a higher frequency than the input signal, it is referred to as up-conversion.

A down-conversion system

An up-conversion system A common misunderstanding about mixers is that a Mixer is only a nonlinear device. Actually an RF Mixer is fundamentally a linear device, which is shifting a signal from one frequency to another, keeping (faithfully) the properties of the initial signal (phase and amplitude), and therefore doing a linear operation. An RF Mixer is a frequency translation device which: - Convert RF to a lower IF or baseband for easy signal processing in receivers - Convert IF frequency (or baseband signal) to a higher IF or RF frequency for efficient transmission in transmitters.

From the moment that we use a nonlinear device to perform the mixing operation, Mixers have relatively high levels of intermodulation distortion, spurious responses, and other undesirable nonlinear phenomena. In contrast to frequency multipliers and dividers, which also change signal frequency, mixers theoretically preserve the amplitude and phase without affecting modulation properties of the signals at its ports. Mixers creative use of nonlinearity or time-variance phenomenons, which are usually harmful and unwanted for an RF system RF Mixers generates frequencies not present at their input and used together with appropriate filtering they remove unwanted frequencies. RF Mixers use two operation mechanisms: - Nonlinear transfer function, which use device nonlinearities creatively in a matter that intermodulations creates the desired frequency and unwanted frequencies. - Switching or sampling is a time-varying process. This method is preferred because has fewer spurs and can provide higher linearity. Important properties of an RF Mixer are: Conversion Gain or Loss - lowers the noise impact of following stages. Intercept Point (Linearity) - impacts receiver blocking and interferer performance. Ports Isolation (LO-to-RF, LO-to-IF, RF-to-IF) - want to minimize interaction between the RF, IF, and LO ports. Noise Figure - impacts receiver sensitivity. High-order spurious response rejection. Image Noise suppression improves system noise figure. Operating Frequency Range. 1. Conversion Gain or Loss of the RF Mixer is dependent by the type of the mixer (active or passive), is dependent by the load of the input RF circuit as well the output impedance at the IF port, and also is dependent by the level of the LO. Conversion Gain or Loss is the ratio of the desired IF output (voltage or power) to the RF input signal value (voltage or power). If the input impedance and the load impedance of the mixer are both equal to the source impedance, then the voltage conversion gain and the power conversion gain of the mixer will be the same in dBs The typical conversion gain of an Active Mixer is approximately +10dB, when the conversion loss of a typical Diode Mixer is approximately -6dB. The Conversion Gain or Loss of the RF Mixer measured in dB is given by: Conversion[dB] = Output IF power delivered to the load[dBm] RF input power[dBm] 2. Input Intercept Point (IIP3) is the RF input power at which the output power levels of the unwanted intermodulation products and the desired IF output would be equal. From RF System point of view, Mixer linearity is more critical than its Noise Figure.

 In a receiver, the most damaging distortion products are odd-order, since those are most likely fall within the same passband as the desired signal. The highest amplitude will be the lowest order, i.e, the 3rd order products. The most common figure of merit for intermodulation distortion (IMD) is Third Order Intercept (TOI). The Third-Order Intercept point (TOI or IP3) in a Mixer is the fictional value defined by the extrapolated intersection of the primary IF response with the two-tone 3rd intermodulation IF product that results when two RF signals are applied to the RF port

In any application where IIP3 is very important, a large LO power is required. The LO (Local Oscillator) provides switching of the signal input, interrupting or redirecting the signal current. Both, Diode and FET Mixers can benefit from LO switching. Silicon bipolar transistors (BJTs) do not switch well above Ft/10, thus degrading IIP3 and NF. In a well designed passive Diode Mixer should get: IIP3[dB] ~ LO[dBm] + 9dB Because the LO voltage is applied from the gate to the source-drain, and the signal flows from source to drain, there is an independence that allows FETs to have a higher IIP3 for a given LO drive than a Diode Mixer. The gate to channel impedance is very high, while the channel drain to source resistance is low. In passive FET mixers, the gate input which is driven by the LO looks like a high-Q, capacitor. After tuning out this capacitance, the real LO power required to drive the mixer with a large voltage at frequency F is reduced by a factor of GMAX . Therefore, for FET mixers: IIP3[dBm] ~ LO[dBm] + 9dB + 20LOG(GMAX) (Where GMAX = Maximum available Gain at Frequency F) This shows why FETs with a high Fmax make better passive mixers than diodes. Nonlinearity in RF Input Path is the same as in LNA nonlinearity case. As in case of the LNA this nonlinearity can be characterized with IIP3 and using a two-test to measure. 3. Spurious Products in a Mixer are problematic, and Mixer vendors frequently provide tables showing the relative amplitudes of each response under given LO drive conditions. One way to reduce such products is to short-circuit the higher harmonics of the LO at the intrinsic Mixer terminals to lower the power in such responses. Reducing the 2nd or 3rd harmonic of the local oscillator reduces its harmonic products by 20 to 25dB, and 10 to 15dB, respectively.

4. Isolation is the amount of local oscillator power that leaks into either the IF or the RF ports. There are multiple types of isolation: LO-to-RF, LO-to-IF and RF-to-IF isolation. Self-Mixing of Reverse LO feed-through: - LO component in the RF input can pass back through the mixer and be modulated by the LO signal, and a DC and 2fo components are created at the IF output. - This has no consequence for a heterodyne system, but can cause problems for homodyne systems (i.e., zero IF) LO to RF port isolation is by far the biggest short coming 5. Noise Figure is a measure of the noise added by the Mixer itself, noise as it gets converted to the IF output. For a passive Mixer which has no gain and only loss, the Noise Figure is almost equal with the insertion loss. In a mixer noise is replicated and translated by each harmonic of the LO that is referred to as Noise Folding. In addition to the degradation in system Noise Figure introduced by the conversion loss of the Mixer, noise sources within the Mixer device itself further corrupt the Noise Figure. For example, the effect of 1/f noise in MESFETs can be severe if the IF frequency is below the corner frequency of the flicker noise (normally less than 1 MHz), as this noise will add to the output. Broadband noise from the input of the mixer will be located in both image and desired bands. Noise from both, image and desired bands, will combine in desired channel at IF output. A Mixer will convert energy in the upper or lower sidebands with equal efficiency. Consequently the noise in the side band with no signal will be added to the IF output, which will increase the Noise Figure at the IF port by 3dB, no matter how good the preceding component noise figure is. Typically Mixers are noisier than amplifiers due to the noise folding nature of Mixers. An Image Filter at the RF input of the Mixer could suppress this noise. Particular Image Reject Mixers can suppress the image noise by their topology.

Image Noise and Image Filter

The wideband noise of the Local Oscillator is another parameter that can raise the IF noise level, degrading in this way the overall Noise Figure. The wideband noise separated from the LO frequency by +/- fIF spacing, will mix to produce noise at IF frequency. Any noise that is near a multiple of the LO frequency can also be mixed down to the IF, just like the noise at the RF. This noise conversion process is related, but not the same as, the LO-to-RF isolation. Noise at frequencies of +/- fIF spacing from the LO harmonics also contributes to overall system Noise Figure. Wideband LO noise is down-converted to IF with much higher conversion loss than the desired signal and image noise. A Band Pass Filter between LO and the Mixer could help reducing the wideband LO noise. In case of Mixers, the Noise Figure is defined for both the image and RF responses, and the output noise is generated by the input termination includes only the noise arising from the principal frequency transformation of the system. When a Single Sideband Noise Figure at the RF input is to be determined, the output noise arising from the input termination, at the image frequency is not included. Furthermore, it is impossible to measure directly the noise figure thus defined, because noiseless image terminations are difficult to obtain. The use of a filter to eliminate the image response (only to do accurate NF measurement) does not help because it changes the image-frequency embedding impedance, and hence changes the noise temperature. So, an alternate definition of Mixer SSB Noise Figure has found more common use. When a noisy LO signal is applied to the Mixer, its noise components at the RF and image frequencies are down converted and appear at the IF port, just as if they had been applied to the RF input. It is important to pick the IF frequency high enough so that noise at the RF and image frequencies are well separated from the LO and can be filtered effectively. SSB NF assumes signal input from only one sideband, but noise inputs from both sidebands. Measuring SSB noise figure is relevant for super-heterodyne receiver architectures in which the image frequency is removed by filtering or cancellation. SSB NF is the ratio of SNR at the desired output frequency (IF) to the SNR at input frequency (RF) measured in a Single Side Band. DSB NF includes both signal and noise inputs from both sidebands. A DSB NF is easier to measure; wideband excess noise is introduced at both the signal and image frequencies. It will be 3dB less than the SSB noise figure in most cases. For Direct Conversion Receivers (Zero IF), there is no image band (image cannot be filtered out from the signal), therefore noise from positive and negative frequencies combine, but the signals combine as well. DSB NF is the ratio of SNR at the output (IF) to the SNR at the input measured in both signal and image side bands (input signal spectrum resides on both sides of LO frequency, a common case in a homodyne or zero-IF systems).

6. Operating Frequency Range Mixers are usually required from low frequencies up to tens of GHz. The operating frequency range is fundamental design characteristic that will in part determine the final selection of the mixer type. Mixers can be divided in classes, which all may be implemented as passive or active: a) Single-device Mixer b) Single-Balanced Mixer c) Double-Balanced Mixer. a) Single-device Mixer, which is using one nonlinear component (one diode, or one transistor), has the disadvantage of not attenuating local oscillator AM noise and always requires an injection filter. Single-device Mixers need to follow some general design rules for best performance. To get the maximum conversion gain, the LO node should be a short circuit at the RF and IF frequencies, while the RF node should be a short circuit at the LO frequency to prevent the LO leakage into the RF port. Single-device Mixer using one diode is primarily a process of matching the pumped diode to the RF input and IF output, terminating the diode properly at LO harmonics and unwanted mixing frequencies (other than the RF and IF), and isolating the RF, LO, and IF ports. That isolation, and in some cases the termination, can be provided by using filters, a balanced structure, or both. The choice depends on the frequency range and the intended application.

Single-Diode mixer is extremely useful at very high frequency (millimeter wave band). The diode used for mixing can be modeled at the RF frequency as a resistor and capacitor in parallel. The resistor is usually in a range of 50 to 150 ohms and the capacitor between 1x and 1.5x the junction capacitance. The IF output impedance is usually between 75 and 150 . At low IF frequencies the output impedance is almost pure resistive. As the LO level increases, both RF and the LO input impedances decrease. The RF and IF input impedances mentioned above (high or low end on the range) are affected by the IF port termination on unwanted and LO harmonics frequencies. The diodes termination at the image frequency is the most critical of all the terminations at unwanted mixing frequencies. Terminating the IF port in a reactance at image frequency can improve the conversion efficiency of the Single-device Mixer.

The Single-diode Mixer is particularly simple in its design and can achieve a broad bandwidth. Another approach of this mixer is to combine the RF input signal and the local oscillator pump signal (LO) via a coupler.

The circuit has losses for the RF signal as well as for the LO signal. By the choice of the coupling factor, the losses can be shifted between the RF signal and the oscillator signal. For example if a 10 dB coupling is selected, then the oscillator signal is attenuated by 10 dB while the signal is attenuated by 0.46 dB. The high-pass filter HP must pass both the high-frequency RF signal and the oscillator signal, and suppress the intermediate IF frequency, which is assumed to be much lower than the RF and the LO frequencies. The low-pass filter LP must pass the intermediate IF frequency and stop the RF signal and the LO frequency. On the diode side the low-pass filter must have high impedance for the high frequency components, while the high-pass filter at the diode side must show high impedance at the IF frequency. For selecting the mixing diode have to look for the cut-off frequency of the diode, for series resistance Rs and junction capacitance Cj. Minimizing both Rs and Cj is necessarily to achieve low conversion loss and distortion, but they are inverse trade-offs. Sometimes it helps to apply a DC bias to a single-diode mixer which can reduce the required LO power and provides a degree of freedom for adjusting the mixers input and output impedances. In active Single-device design case (i.e. one-transistor Mixer), to prevent oscillations the IF node should be a short circuit at both LO and RF frequencies, and RF should be low impedance at IF frequency. This also prevent that the noise at the IF frequency is not amplified and added to the output. The circuit structure of a Mixer with a Field Effect Transistor (FET) as the nonlinear element is particularly simple, because the FET as a three-terminal component already provides an inherent isolation between the RF and LO port or the gate and drain respectively. Normally, the FET is operated passively, i.e. without a drain-source bias voltage and within the ohmic part of the current-voltage characteristic. This type of operation has the advantage that the Mixer has good large signal properties, is unconditionally stable and, to a first approximation does not exhibit 1/f flicker noise. The bias voltage together with the LO signal amplitude at the gate typically is chosen such that the modulation of the channel admittance varies between the open and the closed channel conditions.

 A single FET mixer is inherently noise balanced, because the LO-signal at the gate is not rectified. This is not valid for very high frequencies, because a part of the LOsignal may couple into the drain-source conducting channel via the gate-drain capacitance and may be rectified there by means of non-linear current voltage relations. At high frequencies, the noise balance effect will decrease by 20dB/decade with increasing frequency.

Single-device Mixers using FETs (two approaches for LO input) The conversion gain of a single BJT Mixer (LO feeding to emitter) can be approximated at room temperature by: (Icq*VLO) / VT2 where Icq is quiescent current, and VT ~ 0.025V The input filters, which are necessary to achieve RF-to-LO isolation and prevent radiation of the LO back through the antenna or other RF input, should attempt to short-circuit all unwanted frequencies (i.e., those other than the RF-and-LO) so there are no interfering voltages appearing at the input. The input should be matched to the RF to maximize conversion gain and noise figure, and if possible, to the LO as well for LO power transfer. The Image Frequency should be short-circuited (if possible), as well as the IF, so neither noise nor spurious signals are amplified by the device. It is important that the device not behave as an amplifier at the IF, especially if the IF is low where the device gain is high. As a general rule in active Mixer design, all undesired frequencies should be shortcircuited at both the input and the output to minimize distortion, noise, and for stability. The IF port impedance at IF frequency should be relative high for best conversion gain, but in this way decreasing the IM distortion performance. The IF port should provide enough rejection of the LO frequency in order to do not overload any further IF amplifiers down the chain. FET mixers, especially single-gate FET mixers with LO and RF applied to the gate, have more serious LO-to-RF isolation problem because the LO signal is amplified by the FET.

Single-device Mixers using one Diode The dual gate mixer, or more commonly a cascade amplifier, can be turned into a mixer by applying the LO at the gate of M2 and the RF signal at the gate of M1. A Dual-gate MOSFET will give much improvement for LO-to-RF isolation (approx 20dB).

Dual-gate MOSFET Mixer

Dual-gate GaAs FET Mixer

High Frequency Dual-gate GaAs FET Mixer Design The source shall be well bypassed (with C5 and C6) for the broadest range of frequencies possible. This is critical for maintaining stability. The gates are matched to 50 ohms with a shunt inductor and series capacitor. The shunt inductor will provide the desired short circuit at the IF frequency. The shunt inductors at the gates also provide a DC ground to bias the transistor. R1 in the source sets the drain current. R2 helps to isolate the mixer circuit from the power supply and very little voltage is dropped across it. The drain is matched to 50 ohms with a ! circuit. Using a ! topology lowers the Q of the matching and also serves as a low pass filter to attenuate LO feed through. C7 provides the short circuit at the LO and RF frequencies. Required LO input for a dual-gate mixer is about +3dBm, when the LO-to-RF isolation is about 20dB and the LO-to-IF isolation is about 30dB.

 Conjugate impedance matching of all ports, and adjusting the proper drain current, gives the best Noise Figure and gain. Meantime, higher IP3 can be achieved by increasing the drain current; however, an increase in Noise Figure will result. - As an example, tuning for best Noise Figure can get: NF=5dB, Gain=12dB, P1dB=-1dBm, IP3=+7dBm. - And the same, tuning for best IP3 can get: NF=11dB, Gain=11dB, P1dB=+4dBm, IP3=+14dBm The input and output impedances of the dual-gate FETare very high. This makes the matching to be narrow band. In narrow band super-heterodyne receivers (where the RF bandwidth is less than 50 MHz) this can be advantageous because the mixer has low conversion gain at image frequency. So, the image rejection performance of a receiver (including image noise rejection) could be improved by as much as 16dB without adding any cost to the preselector filter (image filter). Balanced Mixers are grossly divided into two classes, called Single-Balanced Mixers (SBM) and Double-Balanced Mixers (DBM). b) Single-Balanced Mixer goes some way to solve the problems of single-device mixer by providing isolation between LO and RF inputs. It use two devices, and are usually realized as two single-device mixers connected via a 180-degree or 90-degree hybrid. Double balanced mixers usually consist of four un-tuned devices interconnected by multiple hybrids, transformers or baluns. The advantages of balanced mixers over single-device mixers are: - Rejection of spurious responses and intermodulation products. - Better LO-to-RF, RF-to-IF, and LO-to-IF isolation. - Rejection of AM noise in the LO The disadvantage of balanced mixers is their greater LO power requirements. Balanced mixers often used to separate the RF and LO ports when their frequency overlaps and filtering is impossible. In practice a perfect doubly balanced mixer give 10dB up to 30dB isolation without any filtering (depends by frequency and structure). A Single-Balanced Mixer consists of two single-diode mixing elements, which may be two diodes or two transistors. In a single-balanced diode Mixer it is essential that the DC path through the diodes to be continuous. If the diodes are open-circuited at DC, the Mixer it will not work. Often, the hybrid provides that continuous path.

Single-Balanced Diode Mixers In single-balanced using a quadrature hybrid, the LO power reflected from the individual mixers does not return to the LO port, but instead exits the RF port; similarly, reflected RF power exits the LO port. The LO-to-RF and RF-to-LO isolation is therefore equal to the input return loss of the individual mixers at the LO and RF frequencies, respectively; the port isolation of the quadrature hybrid mixer depends primarily on the input VSWRs of the two individual mixers, not on the isolation of the hybrid itself. Isolation of 10dB is typical. If the RF port termination has a poor VSWR at the LO frequency, the circuits balance can be upset and the LO pumping of the individual mixers becomes unequal. The same, a poor LO port termination at the RF frequency can upset RF balance. The even LO harmonics rejection depends by which port is used for LO input (Sigma or Delta). Whatever input is used for LO, the mixer reject the even LO harmonics that mix with the even RF harmonics. To reduce the overall Noise Figure of the Mixer the two diodes shall be well matched. Diodes can be matched on RF characteristics (conversion loss, IF impedance and VSWR), but are more easily matched on DC parameters (junction capacitance, series resistance and forward voltage) that can be measured readily for all diode outlines, including beam lead types. For practical mixers the single-balancing effect is in the order of 20dB to 40dB. This is normally sufficient to eliminate the influence of the LO signal amplitude noise to the noise figure of the mixer. Then, the noise figure of the mixer can be determined by its intrinsic noise. c) Double-Balanced Mixer have higher conversion loss (or lower gain) than singlebalanced Mixer and lower limit in maximum frequency, but has broader bandwidth. Double-Balanced Mixer or ring modulator with four diodes arranged in a ring shows a similar noise balancing effect as the two-diode mixer. Two most common types of double-balanced mixers are the Ring Mixer and the Star Mixer. The Ring Mixer is more suitable for low-frequency applications, in which transformers can be used, but it is also practical at high frequencies.

Double-Balanced Mixers (Ring Diodes, Gilbert BJTs, Gilbert FETs)

Ring double-balanced Mixers can be described by treating its non-linear components (diode or transistors) as switches, which are turned ON and OFF by the LO. This approach assumes that the conductance waveform of the diodes is a square wave, which is approximately true, as long as the LO level is great enough and its frequency is not too high. The advantages of a double-balanced mixer over a single balanced mixer are increased linearity, improved suppression of spurious products (all even order products of the LO and/or the RF are suppressed) ant the inherent isolation between all ports. The disadvantages are that they require a higher level LO drive, and require two transformer baluns. In Double-Balanced diode Mixers because of the symmetry, even-order spurious responses are rejected. The two transformers cause a ground-symmetrical excitation of the four diodes for the RF signal and the LO signal. The center tapping of the transformers acts as a direct galvanic connection to the diodes for the low intermediate IF frequency. Because the RF voltage is split between four diodes, the RF power in each diode is one-quarter that of a single-balanced mixer, so the 1-dB compression point and thirdorder intercept point are almost 6 dB higher. However, four times as much LO power is now required to pump the diodes to the same degree. The conversion loss is the same, because the RF power is split four ways and the IF power recombined four ways; therefore, the increase in intercept point provides a true increase in dynamic range due to the increase in output compared to a single diode. The performance of double-balanced diode mixer is dependent on a variety of factors as: operating frequency, local oscillator power, impedance matching and temperature. Proper matching of the IF output is essential to gain optimum performance from double-balanced diode mixer. Failure to ensure proper matching will result in higher conversion losses and generation of unwanted harmonics.

Beyond about +10dBm LO power, the increase in intercept point does not rise as fast as the LO power, because the ON diodes begin to limit the LO voltage across the OFF diodes, which are in parallel. To each diode, the RF current is indistinguishable from the LO current, and the total RF swing is therefore limited in the OFF condition. This can be improved by using two or more diodes in series in place of the single diodes shown. At higher frequencies, the transformers might be replaced by 180 - 3dB couplers:

In the figure above, the 180 - 3dB couplers are realized by 90 branch-line couplers with additional 90 Phase Shifters (PS). The low-pass filters should have high impedance for the RF signal at the diodes side. The RF and LO ports are isolated. Many of the advantages of balanced structures, such as improved isolation, reduced spurious response, and improved intercept point, can be achieved for Active Mixers in the same way as for Diode Mixers.

Gilbert Cell Mixer (proposed by Barrie Gilbert in 1968) is basically an amplifier followed by a phase reversing switch: For the best Noise Figure and IIP3, the LO voltage must drives the transistors rapidly through the crossover, or phase reversing region. Note that, in a diode balanced mixer the diodes are all OFF at the LO zero crossing, with no excess noise added. Differential output removes even-order nonlinearities. Also, overall linearity is improved because half of the signal is processed by each side. Typical performances of a Gilbert Mixer are: NF~10dB, Gain ~12dB, IIP3~2dBm, DC Current~20mA, LO drive~0dBm.

Noise due to loads in a Gilbert mixer: each RL contributes to thermal noise. Since they are uncorrelated with each other, their noise powers add.

When Q2 is OFF and Q1 is ON, acting like a cascode or more like a resistor if LO is strong, can show that Q1s noise has little effect on Vout.. How to improve Noise Figure of Gilbert mixer: - Reduce RL - Increase gm of the transistors and reduce rb of QB. - Faster switches - Steeper rise or fall edge in LO - Less jitter in LO Noise Figure of dual-balanced Gilbert cell is higher than single-balanced Gilbert cell since no cancellation occurs. The benefits of Double-Balanced Gilbert mixer are: - Fully differential. - No output signal at "*LO. - IIP3 improved by 3 dB. Design issues of the Double-Balanced BJT Mixer are: - Emitter degeneration. - Base resistance. - Device Ft. - Quiescent current of the circuit. Gilbert cell mixer can equally well use FET transistors. The same basic concepts apply as BJTs, the only real difference is in the biasing arrangements used. Symmetric or anti-symmetric pairing of identical mixers provides an effective attenuation of some unwanted frequency components in the spectra of the input and output signals. The suppression is especially needed for the large local oscillator signal, which could saturate or seriously reduce the performances of an IF amplifier stage, but it is important for components with smaller amplitude also. Intermodulation within external systems of these unwanted components could mix with wanted signal and produce spurious signals that can interfere with other circuits of the system. Double-balanced FET Mixers can be designed for both passive and active use. Active FET Mixers based on Gilbert Cell architecture with biased semiconductor devices, can work with low LO levels and often provide conversion gain, but with decreased linearity compared to passive mixers. Passive FET Mixers, usually based on FET quads (ring connection), provide good linearity but require high LO levels and exhibit high conversion loss.

The operation of this type of Mixer is similar to that of a conventional Diode-based doublebalanced Mixer (DBM). The main difference is that the FET Mixer has six terminals, compared to the four terminals of the double-balanced Diode Mixer. During the positive half-cycle of the LO signal to the FET mixer, two of the FETs are in conduction while the other two are turned OFF. As a result, the secondary winding of the RF balun is connected to the secondary winding of the IF balun through the FETs that are switched ON. During the LO signals negative half-cycle, the FETs which were ON during the positive half-cycle are turned OFF and vice versa. This results in a reversal of the polarity of the RF signal reaching the IF balun. The frequency at which the FETs are turned ON and OFF is determined by the frequency of the LO signal. This is mathematically equivalent to a multiplication of the RF and LO signals, resulting in the generation of sum and difference frequencies at the IF port. Compared to Diode Mixers, passive resistive FET Mixers have higher P1dB compression point. The P1dB compression point of a Diode Mixer is generally 4dB to 6 dB lower than the power level of the LO signal, whereas the P1dB compression point of a passive FET Mixer is typically 3dB higher than the power level of the LO signal. The linearity performance of a FET resistive Mixer, as evaluated in terms of the thirdorder intercept point (IP3), is affected by variations in the load impedance. Thus, the most predictable performance occurs with a purely resistance termination as the load. This type of stable termination can be achieved by terminating the mixer with a filter, but the filter appears purely resistive only within its 3dB passband. As the filter's impedance rises beyond its passband, the mixer's intercept performance degrades. A good rule of thumb is that the passive dual-balanced Mixer (regardless, with diodes or with FETs) should be correctly terminated from the lowest frequency in use, to at least five times the highest frequency in use. A good solution is to use at the output of the mixer a Diplexer, which provides the correct termination impedance over a wide frequency range and also provides a degree of frequency selectivity at the IF. In a Quad-FET passive Mixer, the IP3 is mainly a function of the switch transition time. The transition time is mainly a function of the LO voltage, and in the case of a resonant drive is also function of the Q of the resonant circuit. For a given LO power, the higher the Q, the higher the IP3. A quad-FET passive mixer (cold operation) has the important advantage, as has been mentioned in the single-FET passive mixer, that 1/f flicker noise is practically not induced.

JFET Mixers The Junction-FET (JFET) active mixers offer potential good performance. Conversion Gain and Intermodulation Distortion (IMD) characteristics are superior to typical passive mixers, similar to that of high-level diode mixers. In an active JFET mixer, the devices are biased for gain, but at the expense of intercept-point performance. Passive mixers require higher LO power levels, but provide better third-order intercept performance. JFETs have an inherent square-law response which reduces third-order IMD. Like passive mixers, active JFET mixers have a high burn-out level. The main disadvantage of JFET mixers is that they need physically-matched transformers, and also they require relative high-level of local oscillator drive. In active JFET mixers the optimum power gain and noise do not occur at operating point. The bias currents, local oscillator drive level and matching transformers must be properly selected to ensure that the FETs operate in the square-law region and that distortion is minimized. The lowest achievable Noise Figure of an active JFET mixer is about 6dB. For optimum performance of double-balanced JFET mixer, the transistors should be perfectly matched, which is relative difficult due characteristics between batches. Today there are available Quad-FETs in single package, specifically designed for mixer applications. For Single-Balanced JFET mixers, the requirement for matched components is less stringent, allowing the use of transistors matched to within 10%. Quad MOSFET Mixers If there is a need for very high-level performance, than the JFETs can be substituted for either monolithic DMOS-FET quads, or combination of RF Power MOSFETs. Double-balanced MOSFET mixers may operate the transistors as switches with no drain voltage applied resulting in an insertion loss of about -6dB. Alternatively, drain voltage supplied to the MOSFET may be used to give a mixer gain about +15dB. The LO waveform applied to this kind of mixer is of great importance. To achieve a high intercept point, the LO drive must approach an ideal square wave with a 50% duty-cycle. One advantage of MOSFET is that the gate drive voltages are roughly the same for all MOSFET types. This means, the local oscillator power needed for a very highlevel MOSFET mixer is less than the power required for an equivalent diode mixer. MOSFET mixers suffer from the same problem as JFET mixers in terms of using transformers and high-part surrounding circuits, which use of large area circuit board. Such kind of MOSFET mixers would be found in high performance HF receivers, in a frequency range from 1MHz to 50MHz. The high-speed low-capacitance DMOS switches offers significant performance improvements over JFETs and diode balanced mixers when low third order harmonic distortion is required. The example below is using a quad-ring DMOS switch (SD8901).

IP3 performance comparison between DMOS (SD8901), JFET (U350), and Diode Ring Mixers

The H-Mode Mixer is a type of mixer using CMOS bus-switches (e.g. FSA3157), switches that have high-speed enable and disable times, and low ON resistance.

H-Mode Mixer using high-speed CMOS bus-switches

H-Mode mixer can reach very good IP3 (better than +40dBm), and insertion loss (~5dB) if: - the circuit use very good symmetry and wideband transformers. - the circuit use switches with low parasitic capacity, fast switching times, and very low RDS series resistance. - the device is supplied with high Vcc (about 7V in the example above). - the RF and IF ports are properly terminated. The LO squarer signal needs adjustable 50% duty-cycle for RF to IF isolation improvement. Image-Reject Mixers The Image-rejection Mixer is realized as the interconnection of a pair of balanced mixers. It is especially useful for applications where the image and RF bands overlap, or the image is too close to the RF to be rejected by a filter. The LO ports of the balanced mixers are driven in phase, but the signals applied to the RF ports have 90 phase difference. A 90 IF hybrid is used to separate the RF and image bands.

Image-Reject Mixer and Plot of the Image-Rejection vs Phase Error

Characteristics of Image-Reject Mixers are: Image Rejection improves with higher LO. Image Rejection depends more strongly on phase mismatch. Image Reject Mixer can reach better than 20 dB of image rejection. Image Reject Mixer it is particularly useful for Low-IF frequencies. Image Reject Mixer it is complex and needs more current. Usually can parallel the RF inputs, and phase shift the LO, which is not very amplitude sensitive. The IF outputs can be combined with a quadrature hybrid. The signal and the image (USB and LSB) are separately available in this case, at the 2 hybrid ports. If two amplifiers are used on the RF path, in the front of the two mixers, the image noise introduced by these two amplifiers is not rejected. Single-Sideband (SSB), or In-Phase / Quadrature (I/Q) Mixers IQ Mixers play an increasing role in the processing of high-frequency signals, especially as modulators and demodulators. In addition, they allow to measure the amplitude and the phase of a high-frequency signal with respect to a reference signal or to control the phase during an amplitude measurement.

SSB or I/Q modulators are useful in discriminating and removing the lower sideband (LSB) or upper sideband (USB) generated during frequency conversion, especially when sidebands are very close in frequency and attenuation of one of the sidebands cannot be achieved with filtering. With an I/Q modulator, one of the sidebands is attenuated along with its carrier. I/Q modulators basically consist of two Double-balanced Mixers. The Mixers are fed at the LO ports by a carrier phase-shifted with 90 degrees (0 to one mixer and 90 to the other mixer). Modulation signals are fed externally in phase quadrature to the two mixers IF ports. The modulated mixers outputs are combined through a two-way in-phase combiner.

I/Q Modulator

The circuit forms a phase cancellation network to one sidebands and a phase addition network to the other sideband. The carrier is also attenuated and is directly dependent on the LO-to-RF isolation of the two mixers. Phase and Amplitude imbalance errors affect the side band suppression. Errors of an IQ-Mixer All errors of real structures can be divided into three categories: DC-offsets: They are mainly caused by the mixers and by DC-signals introduced through the additional IF amplifiers. A DC-offset causes the circle to be shifted from the origin of the IQ-coordinate system. Amplitude errors: The amplifications or the attenuations of both channels are slightly different, due to unbalances in both hybrids, different conversion losses in the mixers, and different gains in both IF-amplifiers. The resulting curve in the IQ is an ellipse. Phase errors: These errors are caused by phase unbalances in the 90 hybrid and by different electrical length. The effect of these errors on amplitude or in phase can be estimated and corrected. There are two ways to correct for the errors mentioned above: in the hardware by adjusting all gains and phases in a test setup, and in the software. In the later, a calibration signal is used to measure the response of the mixer under test. Sub-Harmonic Mixers A Sub-harmonic Mixer has an LO input at frequency = LO/n. They are useful at higher frequencies when it can be difficult to produce a suitable LO signal (low phase noise, tuning

range and output power all become more difficult to achieve with increasing frequency, whilst cost increases). Sub-harmonic mixers us anti-parallel diode pairs. These mixers produce most of their power at odd products of the input signals. Even products are rejected due to the I-V characteristics of the diodes. Attenuation of even harmonics is determined by diodes balance. Diode match is critical.

The short circuit #LO/2 stub at the LO port is a quarter of a wavelength long at the input frequency of LO/2 and so is open circuit. However, at RF frequency this stub is approximately a half wavelength long, so providing a short circuit to the RF signal. At the RF input the open circuit #LO/2 stub presents a good open circuit to the RF but is a quarter wavelength long at the frequency LO/2 and so is short circuit. The IF is normally far enough away from the RF frequency to allow easy realization of an IF filter presenting an open circuit output to the RF port. Harmonic mixer has low self-mixing DC offset, which very attractive for Direct Conversion applications. The RF signal will mix with the second harmonic of the LO. So the LO can run at half rate, which makes VCO design easier. Because of the harmonic mixing, conversion gain is usually small. Mixers as Phase Detectors In a Double-balanced Mixer the output at the IF port contains the sum and difference of the frequencies of the signals input to the LO and RF ports. If the RF and LO signals have identical frequencies, then their difference is zero Hz, or DC, which is the desired output for a phase detector. Their sum, which is twice the input frequency, can be selectively filtered out if it is not already beyond the frequency response of the IF port. The voltage at the IF port will be DC and will vary as the cosine of the phase difference between the LO and RF signals. Null readings for IF voltage are thus obtained whenever the phase difference between the LO and RF signals is equal to n*PI/2 with n = 1, 3, ..., while maximum and minimum readings are obtained for phase difference equal with n*PI where n = 0, 1, 2,

Practical mixers that are used as Phase Detectors often display some characteristics which differ from those of idealized mixers. The characteristics of most interest are DC offset and/or mixer-induced phase shift of the signals due to circuit imbalance. Parameters that affect these characteristics are: frequency, LO and RF drive levels, load resistance, and temperature. The origin of DC offset voltages is a combination of diode imbalance and transformer asymmetry and can come from either or both input signals. In addition to isolation and LO drive level, DC offset is also affected by the load resistance and temperature. Even after the effects of DC offset have been minimized, it is still possible that a null reading will be obtained at some relative phase other than PI/2 (90 degrees). This is because the mixer itself may change the relative phase of the two input signals due to the fact that the electrical length from the LO-to-IF port is not identical to that from the RF-to-IF port. Frequency affects the DC offset by virtue of its effect upon isolation. Higher the isolation between ports, lower the DC offset. Also, as conversion loss decreases, maximum output DC voltage increases.

References: 1. RF Circuit Design for Wireless Applications U. Rohde, D. Newkirk 2. Microawave Mixers - Stephen Maas 3. Nonlinear Microwave and RF Circuits - Stephen Maas 4. RF Design Guide P. Vizmuller 5. RF Circuits Design - Theory and Applications - Ludwig, Bretchko 6. Practical Rf Circuit Design for Modern Wireless Systems R. Gilmore, L. Besser 7. RF Circuit Design - W. Davis, Krishna Agarval 8. Mixers and Frequency Conversion Besser Associates, Inc. 9. Designing a Super-High Dynamic Range Double-Balanced Mixer - Ed Oxner 10. High Level RF Mixers D. Conway 11. Noise in High-Frequency Circuits and Oscillators - B. Schiek, I. Rolfes, H. Siweris 12. Novel Passive FET Mixers Provide Superior Dynamic Range Minicircuits 13. Active Mixer Design Using Dual Gate MESFET - California Eastern Laboratories 14. Microwave Journal Magazine 1997 2007 15. RF Design Magazine 1992 - 2000

RF Power Amplifiers
Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul RF Power Amplifiers are used in a wide variety of applications including Wireless Communication, TV transmissions, Radar, and RF heating. The basic techniques for RF power amplification can use classes as A, B, C, D, E, and F, for frequencies ranging from VLF (Very Low Frequency) through Microwave Frequencies. RF Output Power can range from a few mW to MW, depend by application. The introduction of solid-state RF power devices brought the use of lower voltages, higher currents, and relatively low load resistances.

Most important parameters that defines an RF Power Amplifier are: 1. Output Power 2. Gain 3. Linearity 4. Stability 5. DC supply voltage 6. Efficiency 7. Ruggedness

Choosing the bias points of an RF Power Amplifier can determine the level of performance ultimately possible with that PA. By comparing PA bias approaches, can evaluate the tradeoffs for: Output Power, Efficiency, Linearity, or other parameters for different applications.

The Power Class of the amplification determines the type of bias applied to an RF power transistor. The Power Amplifiers Efficiency is a measure of its ability to convert the DC power of the supply into the signal power delivered to the load. The definition of the efficiency can be represented in an equation form as:

or Power Added Efficiency: Power that is not converted to useful signal is dissipated as heat. Power Amplifiers that has low efficiency have high levels of heat dissipation, which could be a limiting factor in particular design. In addition to the class of operation, the overall efficiency of a Power Amplifier is affected by factors such as dielectric and conductor losses. First quantify any loss in the circuit, then attempt to minimize it, and finally ensure that the mechanical and thermal design is adequate under all conditions.

Power Classes Class - A Is defined, as an amplifier that is biased so that the output current flows at all the time, and the input signal drive level is kept small enough to avoid driving the transistor in cut-off. Another way of stating this is to say that the conduction angle of the transistor is 360, meaning that the transistor conducts for the full cycle of the input signal. That makes Class-A the most linear of all amplifier types, where linearity means simply how closely the output signal of the amplifier resembles the input signal.

Always have to remember this:

No transistor is perfectly linear; however the output signal of an amplifier is never an exact replica of the input signal.

Linear amplification is required when the signal contains AM Amplitude Modulation or a combination of both, Amplitude and Phase Modulation (SSB, TV video carriers, QPSK, QAM, OFDM).

Signals such as CW, FM or PM have constant envelopes (amplitudes) and therefore do not require linear amplification.

The DC-power input is constant and the efficiency of an ideal Class-A PA is 50 % at PEP. The DC power consumption of a Class-A amplifier is independent of the output signal amplitude. PDC = VCC2 / R = VCC x ICQ and ICQ ~ IMAX / 2

The amplification process in Class-A is inherently linear, hence increasing the quiescent current or decreasing the input signal level monotonically decreases IMD and harmonic levels. Since both positive and negative excursions of the drive affect the drain current, it has the highest gain of any PA. The absence of harmonics in the amplification process, allows Class-A to be used at frequencies close to the maximum capability (fmax) of the transistor. However, the efficiency is low. Class-A PAs are therefore typically used in applications requiring low power, high linearity, high gain, broadband operation, or high-frequency operation. The efficiency of real Class-A Pas is degraded by the on-state resistance or saturation voltage of the transistor. It is also degraded by the presence of load reactance, which in essence requires the PA to generate more output voltage or current to deliver the same power to the load. (Efficiency_Class-A) = Max_Load_Voltage / (2*Vcc2) One important thing to mentioned is that: small signal S-parameters can be used in simulations if the large-signal amplifier is operating in Class-A.

Class - B This is an amplifier in which the conduction angle for the transistor is approximately 180. Thus the transistor conducts only half of the time, either on positive or negative half cycle of the input signal. The same as in Class-A, the DC bias applied to the transistor determines the Class-B operation. Class-B amplifiers are more efficient than Class-A amplifiers. The instantaneous efficiency of a Class-B PA varies with the output voltage and for an ideal PA reaches !/4 (78.5 %) at PEP. However they are much less linear. Therefore a typical Class-B amplifier will produce quite a bit harmonic distortion that must be filtered from the amplified signal. PDC = (2*VCC*V) / ("*R); PLOAD = V2 / (2*R); (Efficiency_Class-B) = ("*V) / (4*VCC) Common configuration of Class-B amplifier is push-pull amplifier. In this configuration one transistor conducts during positive half cycles of the input signal and the second transistor conducts during the negative half cycle. In this way the entire input signal is reproduced at the output.

A single transistor may be used in a Class-B configuration. The only requirement in this case is that a resonant circuit must be placed in the output network of the transistor in order to reproduce the other half of the input signal.

In practice, the quiescent current is on the order of 10 % of the peak collector current and adjusted to minimize crossover distortion caused by transistor nonlinearities at low outputs. In theory 6dB or more drive power is needed to achieve Class-B compared with ClassA. In practice this 6dB reduction in power gain is lower; for BJT amplifiers is lower than FETs, approximately 2dB. The efficiency of the push-pull power amplifier is the same as that of the single ended power amplifier with the same conduction angle, and the output power capability of the push-pull power amplifier is twice that of the single-ended power amplifier (3dB higher). In the push-pull arrangement, the DC components and even harmonics cancel, but odd harmonics add, thus the output contains the fundamental only. Note that the cancellation of odd harmonics is only valid if the amplifier is not driven hard.

Class - AB This amplifier is a compromise between Class-A and Class-B in terms of efficiency and linearity. The transistor is biased typically to a quiescent point, which is somewhere in the region between the cutoff point and the Class A bias point, at 10 to 15 percent of ICmax. In this case, the transistor will be ON for more than half a cycle, but less than a full cycle of the input signal. Conduction angle in Class-AB is between 180 and 360 and Efficiency is between 50 % and 78.5 % Class-AB has higher efficiency than Class-A at price of linearity. Class-AB is not a linear amplifier; a signal with an amplitude-modulated envelope will be distorted significantly at this peak power level. The reason is in fact that in ClassAB operation the conduction angle is a function of drive level. Experimentally was found that Class-AB often offers a wider dynamic range than either Class-A or Class-B operation. This is because gain compression in Class-AB comes from a different, and additional, source than Class-A. Saturation effects are primarily caused by the clipping of the RF voltage on the supply rails.

Linearizing the response of a BJT PA in Class-AB includes the use of specific, and very low, impedance for the base bias supply voltage. This is a very different bias design issue in comparison to the simple current bias used in small signal BJT amplifiers, or the simple high impedance voltage bias used in FET PAs. Running the PA in a mid-AB condition the power gain may be 3dB higher than ClassB. Conventional Class-AB operation incurs odd degree nonlinearities in the process of improving efficiency. Theoretically to increases efficiency all the way up to 78.5 %, the device shall generate only even order nonlinearities. Such a device will not generate undesirable close-to-carrier intermodulation distortion.

Class - C Is an amplifier where the conduction angle for the transistor is significantly less than 180. The transistor is biased such that under steady-state conditions no collector current flows. The transistor idles at cut-off. Class C Amplifier

Linearity of the Class-C amplifier is the poorest of the classes of amplifiers. The Efficiency of Class-C can approach 85 %, which is much better than either the Class-B or the Class-A amplifier.

In order to bias a transistor for Class-C operation, it is necessary to reverse bias of base-emitter junction. External biasing is usually not needed, because is possible to force the transistor to provide its own bias, using an RF choke from base to ground. One of the major problems with utilizing Class-C in solid-state applications is the large negative swing of the input voltage, which coincides with the collector/drain output voltage peaks. This is the worst condition for reverse breakdown in any kind of transistor, and even small amounts of leakage current flowing at this point of the cycle have an important effect on the efficiency. For this reason true Class-C operation is not often use in solid-state at higher RF and Microwave frequencies. In order to survive Class-C operation, the transistor should have a collector voltage breakdown that is at least three times the active devices own DC voltage supply. The reason: Class-C amplifiers have low average output power (since the transistor conducts only for short, pulse-like periods), but demand very high input drive levels. Thus, the transistors main Class-C failure mode is the low value of the active devices own reverse breakdown voltage, which is unfortunately exacerbated by the RF input signal voltage going negative just as the transistors collector voltage reaches its positive peak. This is especially problematic and dangerous if the load changes from design expectations, such as occurs if the system sustains a damaged or missing antenna or feed line during operation. Class - D The voltage mode Class D amplifier is defined as a switching circuit that results in the generation of a half-sinusoidal current waveform and a square voltage waveform. Class-D PAs use two or more transistors as switches to generate a square drain-voltage waveform. A series-tuned output filter passes only the fundamental-frequency component to the load,

Class-D amplifier

Class-D Voltage and Current waveforms

Class-D amplifiers suffer from a number of problems that make them difficult to realize, especially at high frequencies. First, the availability of suitable devices for the upper switch is limited. Secondly, device parasitics such as drain-source capacitance and lead inductance result in losses in each cycle. If realized, (they are common at low RF and audio frequencies) Class-D amplifiers theoretically can reach 100% efficiency, as there is no period during a cycle where the voltage and current waveforms overlap (current is drawn only through the transistor that is on).

No real amplifier can be a true Class-D, as non-zero switch resistances and capacitive as well as inductive parasitics restrict the shape of the drain voltage waveform. A unique aspect of Class-D (with infinitely fast switching) is that efficiency is not degraded by the presence of reactance in the load.

Class - E Class-E employs a single transistor operated as a switch. The collector/drain voltage waveform is the result of the sum of the DC and RF currents charging the drain-shunt capacitance Cp which is parallel with transistor internal capacitance co. In optimum class E, the drain voltage drops to zero and has zero slope just as the transistor turns on. The result is an ideal efficiency of 100 %, elimination of the losses associated with charging the drain capacitance in class D, reduction of switching losses, and good tolerance of component variation.

Class-E amplifier

Class-E Voltage and Current waveforms

A Class-E amplifier will exhibit an upper limit on its frequency of operation based on the output capacitance required for the output matching circuit that produces the waveforms described and shown above. Specifically, a Class-E amplifier for optimum efficiency requires an upper limit on capacitance Cs. The radio frequency choke (RFC) is large, with the result that only DC current Idc flows through it. The Q of the output circuit consisting of Ls and Cs is high enough so that the output current io and output voltage vo consist of only the fundamental component. That is, all harmonics are removed by this filter. The transistor behaves as a perfect switch. When it is on, the collector/drain voltage is zero, and when it is off the collector current is zero. The transistor output capacitance co, and hence Cp, is independent of voltage. If a given transistor has an intrinsic capacitance co greater than Cp_max, it is not useable at the desired frequency. This Cs requirement implies that for high power at high frequencies, higher current densities are required, as the cross-sectional area of the switch corresponds directly to the devices intrinsic capacitance.

Class - F Class-F boosts both efficiency and output by using harmonic resonators in the output network to shape the drain waveforms. The voltage waveform includes one or more odd harmonics and approximates a square wave, while the current includes even harmonics and approximates a half sine wave. Alternately (inverse class F), the voltage can approximate a half sine wave and the current a square wave.

Class-F amplifier

Class-F Voltage and Current waveforms

The required harmonics can in principle be produced by current source operation of the transistor. However, in practice the transistor is driven into saturation during part of the RF cycle and the harmonics are produced by a self-regulating mechanism similar to that of saturating Class-C. Use of a harmonic voltage requires creating a high impedance (3 to 10 times the load impedance) at the collector/drain, while use of a harmonic current requires a low impedance (1/3 to 1/10 of the load impedance). While Class-F requires a more complex output filter than other PAs, the impedances must be correct at only a few specific frequencies. Lumped-element traps are used at lower frequencies and transmission lines are used at microwave frequencies. Typically, a shorting stub is placed a quarter or half-wavelength away from the collector/drain. Class-F amplifier designs intentionally squaring the voltage waveform through controlling the harmonic content of the output waveform. This is accomplished by implementing an output matching network which provides high impedance open circuit to the odd harmonics and low impedance shorts to even harmonics. This results in a squared off (though for Class-F, truly squared) voltage waveform. The third harmonic only is peaked. Class-F amplifiers are capable of high efficiency (88.4% for traditionally defined Class-F, or 100% if infinite harmonic tuning is used). Class-F amplifier design is difficult mainly due to the complex design of the output matching network.

A Class-F amplifier can also be built with a quarter-wave transmission line as shown below.

A #/4 transmission line transforms an open circuit into a short circuit and a short circuit into an open circuit. At the center frequency, the tuned circuit (Lo and Co) is an open circuit, but at all other frequencies, the impedance is close to zero. Thus, at the fundamental frequency the impedance into the transmission line is RL . At even harmonics, the #/4 transmission line leaves the short circuit as a short circuit. At odd harmonics, the short circuit is transformed into an open circuit. This is equivalent to having a resonator at all odd harmonics, with the result that the collector voltage waveform is a square wave (odd harmonics should be at the right levels). Power Classes definition

Classical definition of Power Amplifier classes

Power Amplifier Linearity When two or more signals are input to an amplifier simultaneously, the second, third, and higher-order intermodulation components (IM) are caused by the sum and difference products of each of the fundamental input signals and their associated harmonics. The rated PEP of a Power Amplifier is the maximum envelope power of a two-tone signal for which the amplifier intermodulation level is -30dBc. When two signals at frequencies f1 and f2 are input to any nonlinear amplifier, the following output components will result: Fundamental: f1, f2 Second order: 2f1, 2f2, f1 + f2, f1 - f2 Third order: 3f1, 3f2, 2f1 f2, 2f2 f1, Fourth order: 4f1, 4f2, 2f2 2f1, Fifth order: 5f1, 5f2, 3f1 2f2, 3f2 2f1, + Higher order terms The odd order intermodulation products (2f1-f2, 2f2-f1, 3f1-2f2, 3f2-2f1, etc) are close to the two fundamental tone frequencies f1 and f2.

The nonlinearity of a Power Amplifier can be measured on the basis of generated spectra than on variations of the fundamental signal. The estimation of the amplitude change (in dB), of the intermodulation components (IM) versus fundamental level change, is equal to the order of nonlinearity. For 1dB increase of fundamental level (f1 and f2), the level of IM2 will go up with 2dB, the level of IM3 will go up with 3dB, and so on. This is valid only for an amplifier that is not in compression. As a relation between the degree of the nonlinearity (third, fifth, etc) and the frequency of the side tone (such as IM3, IM5, etc), can be mentioned that the IM5 tones are not affected by third-degree nonlinearities, but IM3 tones are functions of both third- and fifth-degree (and higher) nonlinearities. That means at low signal amplitudes, where the fifth-order distortion products can be neglected, the amplitudes of the IM3 tones are proportional to the third power of the input amplitude.

With fairly large signal amplitude, 5th order products (which are dependent on a power of five) will start to affect the IM3 responses. As a result, the 3:1 amplitude estimate will no longer hold.

If the phases of the third- and fifth-degree coefficients are equal, the fifth-degree nonlinearity will expand the IM3 responses. However, if the phases are the opposite, the IM3 distortion will be locally reduced. This explains why notches (sweet-spots) in the IM3 (and high-order) sidebands have been reported at certain amplitudes of output power.

IM(n) products vs Input

Re-growth of harmonic content vs Conduction Angle

Second- and third-order input and output intercept points Power

Since the amount of device nonlinearities cannot be changed much, distortion is most effectively minimized by optimizing the impedances seen by the distortion current sources. In all the Power Amplifiers, the output level is a compressive or saturating function of the input level. The gain of the Power Amplifier approaches zero for sufficiently high input levels. In RF circuits this effect is quantified by the 1dB

compression point, defined as the input signal level that causes the small-signal gain to drop by 1dB. This can be plotted in a log-log scale vs input level.

Sometimes this Output Power vs Input Power characteristic is referred as AM-AM distortion. The asymmetry of side-band intermodiulation products (IM) in a two-tone test is often dependent on the carrier spacing, but not in a monotonic fashion. The effect can be explained as an interaction between AM-AM and AM-PM distortion processes. On the other hand, the mere presence of both processes does not guarantee that asymmetry will occur. If there is a time lag, or phase shift as measured in the envelope time domain between the AM-AM and AM-PM responses, or their individual frequency components, IM asymmetry will occur. Reduction of AM-PM in the PA design would alleviate the IM asymmetry issue.

For RF power transistors, a primary cause of AM-PM effects appears to be the dynamic mistuning of the input match. Some deliberate mistuning on the high Q factor input match of RF power transistors might pay off in terms of improved AM-PM performance for the loss of a decibel or two of gain. Nonlinear Power Amplifiers can cause signals to be spread into adjacent channels, which can cause Cross Modulation. This is based on the same phenomena as thirdorder intermodulation for nonlinear amplifiers with two-tone inputs. Was mention that the level of the harmonic and intermodulation products decreases stronger than the fundamental, with decreasing the input power. This deduces a crude method for linearization named Backoff Power Optimization for Linearity. Increasing of the backup ratio of an over dimensioned PA enhances linearity at the expense of the efficiency.

Memory Effect

In a two or multi tone IMD test if the amplitude and/or phase of the IM signals is affected by the tone difference, the amplifier exhibits memory effects. Memory is caused by the storage of energy that has to be charged or discharged. Memory Effect could be explained as a time lag between AM-AM and AM-PM response of the amplifier. The Electrical Memory Effect is introduced by poor gate/base and drain/collector decoupling at low frequencies causing a distortion of the envelope currents which results in IMD asymmetry. Low frequencies mean baseband/video frequencies or the spacing between two tones.

The most significant Memory Effect appears in Class AB amplifiers, with reduced conduction angle where drain/collector varies with output power. In Class A amplifiers the Memory Effect reduces. Smooth memory effects are not usually harmful to the linearity of the PA itself. A phase rotation of 10 to 20 or an amplitude change of less than 0.5 dB, as a function of modulation frequency, has no dramatic effect on the linearity of the device, There are two memory effects: electrical and thermal.

Electrical memory effects are produced by non-constant node impedances within frequency bands as DC, Fundamental, and Harmonics. Most of these effects are generated by frequency dependent envelope impedance, and those within the DC band are the most harmful, because bias impedances are strongly frequency dependent. Thermal memory effects are generated by the junction temperature, which is modulated by the applied signal. Thermal effects will be much more prominent in a slow sweep, or a stepped CW test. The analysis and simulation show that the drain envelope impedance is the most important factor for reducing the memory effect and nonlinearity. A new matching topology is proposed for minimizing the drain and gate envelope impedances. The matching topology consists of a series LC circuit for shorting the device at a low frequency while maintaining a matchable impedance at the operating frequency. The circuits are connected to the gate and drain terminals, rather than to the bias lines, since the circuit can produce a very low impedance, not limited by the quarterwavelength bias line. The amplifier, with the reduced envelope impedances, provides drastically reduced memory effects and very linear amplification performance for wideband signals. Simultaneous amplitude and delayed phase modulation does generate asymmetric sidebands.

Input/Output Matching and Load Line

The input matching configuration, including the bias circuit, has an important impact on the operation of the RF Power Amplifiers. The input match will show different optima for maximum gain, best linearity, and highest efficiency. Optimization of the efficiency may involve substantial reduction in power gain.

Correct handling of harmonics is a necessary feature on the input, as well as the output, match. Device used well below its cutoff frequency may require specific harmonic terminating circuit elements on the input. The performance of the output matching circuit is critical for a Power Amplifier. In a PA, impedances control how much power is delivered to the output and how much gain and noise are produced in the process, therefore matching network is critical for maximum performance. One aspect that's sometimes overlooked is the power dissipation in the output matching circuit. This power is lost in the capacitors, inductors, and other lossy elements that are part of the matching network. This "dissipation loss" degrades the PA's efficiency and output power capability. Different implementations of the output match result in different losses and there are still significant design tradeoffs to be made between bandwidth and dissipation loss. For a PA, the loss of the output match is always a concern because of the large power levels involved. A capacitor's quality factor is reversal proportional to its capacitance. To minimize the dissipation loss of the output match, it's therefore necessary to design the output match with the lowest possible value of C. The tradeoff is between bandwidth and dissipation loss. Different capacitor technologies give different losses when used in output matching circuits. One way of understanding the loss mechanisms of an output match and to dont mix up mismatch loss and dissipation loss, is to simulate the match with loss-less components, then introduce loss into one component at a time. Mismatch Loss [dB] = 10*LOG (1- 2)

where reflection coefficient $ = (VSWR-1) / (VSWR+1)

Because the dissipation loss doesn't depend on the source impedance it's possible to use S21 to find the correct dissipation loss in a circuit simulation. The procedure involves using the complex conjugate of the simulated load line as the source impedance. Running at a low efficiency not only reduces talk time in a portable device, but it also creates significant problems with heating and reliability. The load line is set based on the needed Power Amplifier output power and available supply voltage. For example low voltage PAs (~3.5V for mobile devices) have a load line ranging from 1 to 5 %. RL = Vmax / Imax

Matching for maximum Gain occurs when the amplifier is unconditional stable and load impedance is equal to the complex conjugate of the same source impedance (conjugate matching). Complex conjugate simply refers to complex impedance having the same real part with an opposite reactance.

e.g. - if the source impedance is Zs=R+jX, then its complex conjugate would be Zs*=R-jX

If matched: Zin = Zo, $s = S11*, and Zout = Zo, $L = S22*

Matching for maximum Output Power occurs when Optimum Load impedance (RL) is equal to Source impedance (Rgen). In order to obtain maximum output power, typically the power amplifier is not conjugate matched. Instead, the load is designed such that the amplifier has the correct voltage and current to deliver the required power. If operation is at the optimal Power Added Efficiency point, optimal-power tuning produces about 1 dB to 3 dB of higher power. Gain is reduced (for small Pin) typically by a slightly smaller amount. The transistors input and output impedances will also decrease with an increase in frequency, which further complicates the design of a PAs matching networks, especially since these impedances can be as low as 0.5 %. Thus, when matching a discrete driver stage to its PA with maximum efficiency, we would normally want to implement a direct match from the true output impedance of the driver to the true input impedance of the PA, instead of first forming a 50-% match at the output of the driver, and then another 50-% match for the input of the power amplifier, as this would needlessly transform the impedances from low to high, and then back from high to low. By selecting a transistor with a high collector voltage requirement, we can increase its output impedance over a transistor that operates at lower values of collector voltage. Output matching network for most high-powered amplifiers should normally consist of the T type, rather than the PI type. PI matching networks for high powered amplifiers sometimes result in unrealistic component values when matching for the higher operating frequencies encountered into a 50 % load. Indeed, T networks are capable of much higher-frequency operation before this becomes a major problem. Both T and PI networks can be used, however, if the output impedance of the transistor is higher than its load. It is possible to increase the bandwidth by using a higher order of output matching network. For example, instead of an L network, a double-L network can be used to convert first to an intermediate impedance, and then to the final value.

Smith Chart representation for maximum gain and power matching

Load Line for different classes Optimum Load Resistance In the absence of collector output resistance information on the datasheet, it becomes necessary to make a simple calculation to determine the optimum load resistance for the transistor. The value of load resistance is dependent upon power level required and is given by:

where, VCC = the supply voltage VSAT = the saturation voltage of the transistor P = the output power level required in Watts Note that this equation provides only the load resistance, when usually in the datasheets the manufacturer provides values of shunt output capacitance vs frequency for the RF power transistor.

Power Amplifier Bias Design

There are many different ways to bias an amplifier, depending on the required temperature stability, efficiency, cost, device, power output, linearity, and so on. Power BJT transistor biasing: o Must force the DC (average) value of VCE and IC to desired values and keep them constant using feedback techniques. o Whether employing diode or transistor bias, it is essential to thermally connect these components to the RF transistor itself. This allows the semiconductor bias components to track the power amplifiers temperature variations. o It is also possible to decrease input voltage as temperature increases, for example, by using a diode in the input circuit, using a current mirror, or using a more complex arrangement of thermal sensors and bandgap biasing circuits.

In the above example, all diodes and transistors are assumed to be at the same temperature. As temperature rises, VD falls, reducing VBE and keeping I constant.

Power FET transistor biasing: The gate biasing circuit has several functions: o To maintain a constant gate-to-source voltage, Vgs. o To be able to supply a negative and positive gate current, Igs. o To protect the gate by limiting Igs when the device goes into breakdown (draintogate or gate-to-source) or when the gate-tosource junction is biased with a positive voltage. These abnormal operating conditions for the devices can be due to an operator error, an overdrive, a system problem or ESDs. o To stabilize the device in case a negative resistance appears in the gate at any frequency where the device has a positive gain. o To filter the signal, the products and the harmonics generated by the device input from low to high frequencies without affecting the device input matching circuit. o To isolate the gate from any signal coming from the drain through the bias circuits. Power LDMOS transistor biasing The main consideration of the power LDMOS biasing is to to achieve the linearity.

o o

o o

This is done DC biasing of the LDMOS transistor for optimal drain current for a given power output. This bias needs to be held constant over temperature and time. Typically the target accuracy for bias current over temperature is 5% but 3% is much more desirable for a high performance design. The DC Bias on LDMOS amplifiers is set by applying a DC voltage to the gate (Vgs) and monitoring the Drain current (Idd). Ideally, this Idd will be constant over temperature, but since the Vgs of LDMOS amplifier devices varies with temperature, some type of temperature compensation is required. For optimal temperature compensation, in-circuit adjustments need to be made for both the temperature compensation as well as the Vgs bias itself.

Power Amplifier Design Issues

Reflected power caused by a high VSWR condition between a PA and its load does not, in and of itself, cause a transistors destruction or damage. Rather, a PA can be damaged or destroyed in a high VSWR environment simply because it is now looking at completely different load impedance than it was designed for. High device power dissipation can then produce elevated heating of the transistor and/or excessively high voltages. Some of the DC bias voltage would be wasted if the resistance in the chokes were too high. Also the collector chokes must supply a very high impedance to the RF. If this impedance is not high enough, then some of the valuable RF output power generated by the PA will be wasted. Use low-ESR electrolytic capacitors at the PAs power supply, as this type of capacitor can immediately supply the needed current to the amplifier stage, and without pulling down the entire voltage supply during this critical transient turn-on time. When in saturation, a nonlinear PAs gain, PAE, and linearity are most affected by the reflections of its own harmonics back into its output port. These reflections are caused by the next stage, which will normally be a band-pass or low-pass filter, as well as an antenna. Instability in RF amplifiers can take the form of oscillations at almost any frequency, and may even damage or destroy the transistor. These spurious oscillations will arise at specific or very wide ranging, frequency or frequencies, and over a particular bias, drive level, temperature, or output load impedance. RF PA oscillation problems can be broadly categorized into two kinds: Bias oscillations and RF oscillations. Bias oscillations occur at low frequencies, in the MHz to VHF range, and are caused by inappropriate and unintentional terminations at those frequencies by the bias insertion circuitry, such as the addition of a large-value decoupling capacitors. The oscillations have little to do with the details of the RF matching circuitry, where the RF blocking and decoupling capacitors become open circuit terminations at lower frequencies. RF oscillations, on the other hand, typically occur either in band or commonly out of band but still quite close to the desired bandwidth from the low frequency side. Decreasing the low-frequency gain of a PA stage, which is naturally at an increased level, will assist in amplifier stability.

The unavailability of a sufficient ground-plane, or a ground-plane that is excessively segmented, can create uncontrollable instability in a PA.

RF Power Amplifiers for Wideband Modulations RF Power Amplifiers for wideband modulations as CDMA or WCDMA, which operate in the linear region, are not very efficient. Only a portion of the D.C. current is used to generate the RF power; a much larger portion turns into heat. LDMOS and GaN (Gallium Nitride) devices are best suited for the output and driver stages because of higher gain, improved linearity, and very low on-resistance. High gain reduces the number of stages needed in the amplifier to attain the same output power, compared to the old generation systems built with bipolar transistors. In a multi-stage linear power amplifier there are various factors that need to be considered for choosing the right transistor for each of the stages of the amplifier.

The pre-driver is biased Class-A for attaining consistent performance for minimal effect on the linearity of the device due to minor changes in bias supply. Drain efficiency is not as much of a concern for the pre-driver as it is for the latter stages in the amplifier. The driver and the output stage for such a system are typically biased Class AB, for achieving best tradeoff between linearity and efficiency of the amplifier. The most common method used to determine the linearity of a transistor is to characterize the Intermodulation Distortion (IMD) measured with two tones spaced. Typically, tone spacing up to 20 MHz should be used while tuning amplifiers for wideband modulation applications. When transistors are used significantly backed-off from their peak power levels, it is all the more necessary that the IMD characteristics of the transistor at lower output power levels be taken into account. The profile of an IMD vs. Pout (drive-up) curve for a good transistor should have a large positive slope, even while attaining similar peak power capability, to get maximum Adjacent Channel Power Ratio (ACPR). The transistor used in the driver stage has similar linearity requirements as the output stage. In terms of ACPR, it needs be operated at an output power that gives a margin of at least 4 dB from the maximum allowed value for the output stage. In addition, it needs to have an input bandwidth about 2 to 2.5 times greater than the bandwidth of the modulating signal in order to maintain constant group delay and flat gain. One of the major factors determining the performance of the high power transistor in the wide modulation environment is the gain flatness. The transistor needs to have a flat gain across the band for its use in multiple channel amplifiers. Very flat gain response greatly simplifies the design of linearization schemes systems. Fast roll-off of gain at the edges of the band causes deterioration in the ACPR performance. To attain the intrinsic device linearity, the 3 dB bandwidth of bias networks needs to be at least two times greater than the modulation bandwidth. For attaining best ACPR response, it is necessary to have an excellent decoupling network at the Drain of the transistor, down to very low modulation frequencies. This

can be achieved by using a high quality shunt capacitor. This technique helps in achieving maximal gain flatness, which is very critical for wideband applications. It is advisable to avoid ferrite components in the biasing network and to use a series resistor on the Gate bias network to prevent instability. To achieve flat gain response across the band, the traditional inductive feed should be avoided on both the Gate and Drain. Instead, a quarter wave line at the frequency of interest, properly decoupled with a chip-capacitor, has been shown to provide very flat gain across the entire bandwidth.

References: 1. RF Circuit Design C. Bowick 2. RF Power Amplifiers for Wireless Communications S. Cripps 3. Advanced Techniques in RF Power Amplifier Design S. Cripps 4. Distortion in RF Power Amplifiers J. Vuolevi 5. Circuit Design for RF Transceivers D. Leenaerts, J. Tang, C. Vaucher 6. Radio Frequency Transistors - N. Dye, H. Granberg 7. High Frequency Current Mode Class-D Amplifiers - A. L. Long 8. Complete Wireless Design - C. Sayre 9. Feedforward linear power amplifiers N. Pothecary 10. Radio Frequency Integrated Circuit Design - Rogers, Plett 11. RF CMOS Power Amplifiers - Theory design and implementation - Hella, Ismail 12. Microwave Journal Magazine; 1996 2005 13. Portable Design Magazine; 2002 - 2005 14. High Frequency Electronics Magazine; 2002 2007

RF System Formulas
Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul/
Noise_Floor[dBm] = 174 + 10*LOG (BW [Hz]) + Noise_Figure[dB] + Gain[dB] Minimum_Detectable_Signal[dBm] = [174 + 3dB] + 10*LOG(BW [Hz]) + Noise_Figure[dB] Spurious_Free_Dynamic_Range[dB] ord 2 = (1/2) * [174 + IIP2[dBm] Noise_Figure[dB] 10*LOG(BW [Hz])] Spurious_Free_Dynamic_Range[dB] ord 3 = (2/3) * [174 + IIP3[dBm] Noise_Figure(dB) 10*LOG(BW [Hz])] Noise_Figure[dB] = 174 + RX_Sensitivity[dBm] 10*LOG(BW [Hz]) Signal/Noise[dB] RX_Sensitivity[dBm] = 174 + 10*LOG(BW [Hz]) + Noise_Figure[dB] + Signal/Noise[dB] Signal/Noise[dB] = 174 + RX_Sensitivity[dBm] 10*LOG(BW [Hz]) Noise_Figure[dB] RX_Dynamic_Range[dB] = RX_Sensitivity[dBm] P1dB[dBm] Blocking_Dynamic_Range[dB] = P1dB[dBm] - Noise_Floor[dBm] - Signal/Noise[dB] Co-channel_rejection[dB] = Co-channel_interferer[dBm] - RX_Sensitivity[dBm] RX_selectivity[dB] = - Co-ch_rejection[dB] 10*LOG[10(-IF_filter_rej[dB]/10) +10(-LO_spur[dBc]/10) +IF_BW [Hz] * 10(SB_Noise[dBc/Hz]/10)] Image_frequency[MHz] = RF_frequency[MHz] 2*IF_frequency[MHz] Half_IF[MHz] = RF_frequency[MHz] IF_frequency[MHz] / 2 Half_IF[dBm] = [OIP2[dBm] RX_Sensitivity[dBm] Co-channel_rejection[dB] ] / 2 IM_rejection[dB] = [2*IIP3[dBm] 2* RX_Sensitivity[dBm] Co-Channel_rejection[dB] ] / 3 IIP3[dBm] = Interferer_level[dBm] + [Interferer_level[dBm] RX_level[dBm] + Signal/Noise[dB] ] / 2 OIP3[dBm] = Pout[dBm] + [IM3[dBc] / 2] = Pout[dBm] + [Pout[dBm] IM3[dBm]] / 2 IM3[dBm] = 3* Pout[dBm] 2*OIP3[dBm] IM3out unequal_input_levels(left_side)[dBm] = Pout_Left[dBm] 2*[OIP3[dBm] Pout_Right[dBm]] OIP2[dBm] = Pout[dBm] + IM2[dBc] = 2 * Pout[dBm] IM2[dBm] IM2[dBm] = 2 * Pout[dBm] - OIP2[dBm] IIP2(cascaded_stages)[dBm] = IIP2last stage[dBm] Gaintotal[dB] + Selectivity @ 1/2 IF[dB] IIP2(Direct_Conversion_Receiver)[dBm] 2*AM_Interferer[dBm] Noise_Floor[dBm]

Full_Duplex_Noise@RX_inp[dBm] = 174 TX_Noise@RX_band[dBm/Hz] Duplexer_rejection[dB] Crest_Factor[dB] = 10*LOG[Peak_Power(w) / Average_Power[w]] = Peak_Power[dBm] Average_Power[dBm] MultiCarrier_Peak_to_Average_Ratio[dB] = 10*LOG(Number_of_Carriers) MultiCarrier_Total_Power[dBm] = 10*LOG(Number_of_Carriers) + Carrier_Power[dBm]

Processing_Gain[dB] = 10*LOG[BW [Hz] / Data_Rate[Hz]] Eb/No[dB] = S/N[dB] + 10*LOG[BW [Hz] / Data_Rate[Hz]] RX_Input_Noise_Power_max[dBm] = Sensitivity[dBm] + Processing_Gain[dB] - Eb/No[dB] Carrier_Noise_Ratio[dB] = 10*LOG[Eb/No] + 10*LOG[Bit_Rate[bps] / BW [Hz]] Bandwidth_Efficiency[bps/Hz] = Bit_Rate[bps] / BW [Hz] Integer_PLL_freq_out[MHz] = [N (VCO_divider) / R (Ref_divider)] * Reference_frequency[MHz] Required_LO_PhaseNoise[dBc/Hz] = RX_level[dBm] Blocking_level[dBm] Signal/Noise[dB] 10*LOG(BW [Hz]) PLL_PhaseNoise[dBc/Hz] = 1Hz_Normalized_PhaiseNoise[dBc/Hz] + 10*LOG(Comparison Frequency[Hz]) + 20*LOG(N) PLL_Lock_Time[usec] = [400 / Loop_BW [kHz]] * [1-10*LOG(Frequency_tolerance[Hz] / Frequency_jump[Hz])] PLL_Switching_Time[usec] = 50 / F_comparison[MHz] = 2.5 / Loop_Bandwidth[MHz] PhaseNoise_on_SpectrumAnalyzer[dBc/Hz] = Carrier_Power[dBm] Noise_Power@Freq_offset[dBm] 10*LOG(RBW [Hz]) PLL_Phase_ErrorRMS [] = 107 * 10(PhaseNoise[dBc/Hz] / 20) *

Loop_BW[Hz]

PLL_Jitter[seconds] = PLL_Phase_ErrorRMS [] / (360*Frequency[Hz]) EVMRMS [%] = 1.74 * PLL_Phase_ErrorRMS [] TX_PhaseNoise_limit[dBc/Hz] = Power_limit@Offset_from_carrier[dBc] + 10*LOG(BW [Hz]) ACLR[dBc] = 20.75 + 1.6*Crest_Factor[dB] + 2*[Input_Power[dBm] PA_IIP3[dBm] sine] EVM[%] = [10(-Signal/Noise[dB] / 20)]*100 EVM[dB] = 20*LOG(EVM[%] / 100) Signal/Noise[dB] = 20*LOG(EVM[%] / 100) Corrected_EVM[%] =

Re sidual _ EVM [%] * Measured _ EVM [%]

ADC_SNR[dB] = (Nr_of_Bits*6.02) + 1.76 + 10*LOG(Sampling_Frequency[Hz] / 2*BW [Hz]) ADC_Nyquist_frequency[Hz] = Sampling_Frequency[Hz] / 2 ADC_NoiseFigure[dB] = Full_Scale_Pin[dBm] SNR[dB] 10*LOG(FS_sampling_rate / 2 ) Thermal_Noise[dBm/Hz] ADC_NoiseFloor[dBFS] = SNR[dB] + 10*LOG(FS_sampling_rate / 2) ADC_Spurious_Free_Dynamic_Range[dB] = Desired_Input_Signal[0dB] Highest_Amplitude_Spurious[dB] ADC_Input_Dynamic_Range[dB] = 20*LOG(2Nr_of_Bits -1) VSWR = (1+!) / (1 !) = (Vinc + Vref) / (Vinc Vref) = (ZL Zo) / (ZL + Zo) Reflection_Coefficient ! = (VSWR 1) / (VSWR + 1) = Vref / Vinc Return_Loss [dB] = - 20*LOG(!) Missmatch_Loss[dB] = - 10*LOG [1 ! 2]

Reflected_Power[W] = Incident_Power[W] * ! 2 Power_Absorbed_by_the_Load[W] = 4 * Incident_Power[W] * [VSWR/(1+VSWR2)] Characteristic_Impedance Zo = L / C

Resonant_Frequency[Hz] = 1 / [2** L * C ] L = Xs / ; C = 1 / (*Xp) ; = 1 / L*C

Q (series LC) = Xs / Rs

Q (parallel LC) = Rp / Xp

Free_Space_Path_Loss[dB] = 27.6 20*LOG[Frequency[MHz]] 20*LOG[Distance[m]] RX_inp_level[dBm] = TX_Power[dBm] + TX_Ant_Gain[dB] Free_Space_Path_Loss[dB] Cable_loss[dB]+ Rx_Ant_Gain[dB] Antenna_Polarization_Mismatch_Loss[dB] = 20*LOG(cos ") Antenna_Factor[dB] = 20*LOG[(12.56 / #[m]) * EIRP[W] = Power[W] * 10Antenna_Factor[dB] / 10 Antenna_Near_Field[m] = 2 * Antenna_Dimension2[m] / #[m] Te = (Noise Factor[lin] 1) * To [290K] ENR(Excess_Noise_Ratio) = 10*LOG [(TENR To [290K]) / To [290K] ] Noise_Figure_Test(Y_Factor_Method)[dB] = 10*LOG[(10(ENR/10))/(10(Y/10))] ; Y = NFout - NFinp RMS Noise Voltage across a Resistor (V) = [for linear polarized antennas]

30 ] R _ load[ohms ] *10^ ( Antenna _ Gain[dBi] / 10)

[4 * R[ohms] * k[Boltzman] * Temp[K] * BW[Hz]]

Noise Factor (all linear) - Cascaded Stages

IP3 (all linear) Cascaded Stages

Noise_Figure[dB] = 10*LOG(F)
Noise Factor (all linear) Identical Cascaded Stages

Noise Temperature Cascaded Stages

T(1,2,3n) = (Noise Factor[lin] 1) * To [290K]

NF[dB] = 10*LOG (1 + Teq / To [290K])

AM_Modulation_Index =

V max[Vpp] V min[Vpp] =2* V max[Vpp] + V min[Vpp]

Power _ sideband (usb _ lsb)[W ] Power _ carrier [W ]

AM_Total_Power[W] = Power_carrier[W] * [(1+AM_Modulation_Index2) / 2] AM_Bandwidth[Hz] = 2 * Highest_Modulation_Frequency[Hz] FM_Modulation_Index = Max_Frequency_Deviation[Hz] / Max_Modulation_Frequency[Hz] FM_Bandwidth[Hz] = 2 * Max_Modulation_Frequency[Hz] * [1+ FM_Modulation_Index]

Understanding Noise Figure

Iulian Rosu, YO3DAC / VA3IUL, http://www.qsl.net/va3iul One of the most frequently discussed forms of noise is known as Thermal Noise. Thermal noise is a random fluctuation in voltage caused by the random motion of charge carriers in any conducting medium at a temperature above absolute zero (K=273 + Celsius). This cannot exist at absolute zero because charge carriers cannot move at absolute zero. As the name implies, the amount of the thermal noise is to imagine a simple resistor at a temperature above absolute zero. If we'll use a very sensitive oscilloscope probe across the resistor, we'll see a very small AC noise being generated by the resistor. The RMS voltage is proportional to the temperature of the resistor and how resistive it is. Larger resistances and higher temperatures generate more noise. The formula to find the RMS thermal noise voltage of a resistor is:

Vn = 4kTRB
k = Boltzman constant (1.38*10-23 Joules/Kelvin) T = Temperature in degrees Kelvin (K= +273 Celsius) R = Resistance in ohms B = Bandwidth in Hz in which the noise is observed (RMS voltage measured across the resistor is also function of the bandwidth in which the measurement is made). As an example, that 100 k resistor with 1MHz bandwidth will add noise to the circuit as below:
where:

Vn = (4*1.38*10-23*300*100*103*1*106) = 40.7 !V RMS Low impedances are desirable in low noise circuits. For an easier job we may actually measure the noise of a device in a 1MHz bandwidth (it is easier), we usually convert the number to 1Hz bandwidth (the lowest band denominator) in order to compare it to other sources. Noise Bandwidth, B, is defined as the equivalent rectangular pass-band that passes the same amount of noise power as is passed in the usable receiver band, and that has the same peak in-band gain as the actual device has. It is the same as the integral of the gain of the device over the usable frequency bandwidth. Typically, B is approximately equal to the 3 dB bandwidth. For best sensitivity, B should be no greater than required for the information bandwidth. In RF applications, we usually deal with circuits having matched input and output impedances, and are therefore more concerned with the power available from a device than the voltage. In this case, it is common to express the noise of a device in terms of the available noise power. The Maximum Power Transfer Theorem predicts that the noise power delivered from a source to a matched load can be delivered: P = (Voc/2)2/R = kTB = -174dBm/Hz (the reference noise level in a 1Hz bandwidth, at room temperature) Temperatures correspond to power levels. When the temperature of a resistor is doubled the power output from it is doubled (the voltage is proportional to the square root of the temperature).

Powers from uncorrelated sources are additive so noise temperatures are additive. In addition to thermal noise, amplifiers and other devices with semiconductors in them also contribute other forms to signal. Noise Figure To characterize the receiver alone, Harald T. Friis introduced in 1944 the Noise Figure (NF) concept which characterized the degradation in Signal to Noise Ratio (SNR) by the receiver.

Noise Figure (NF) is a measure of how much a device (such an amplifier) degrades the Signal to Noise ratio (SNR). SNR_input[linear] = Input_Signal[Watt] / Input_Noise[Watt] SNR_input[dB] = Input_Signal[dB] - Input_Noise[dB] SNR_output[linear] = Output_Signal[Watt] / Output_Noise[Watt] SNR_output[dB] = Output_Signal[dB] - Output_Noise[dB]

Noise Factor (linear not dB) of a receiver is the ratio of the SNR at its input to the ratio of the SNR at its output. NoiseFactor_F(linear) = SNR_input[linear] / SNR_output[linear] NoiseFactor_F[dB] = SNR_input[dB] - SNR_output[dB] NoiseFigure_NF[dB] = 10*LOG (NoiseFactor_F(linear))

Note that SNR at the output will always be smaller than the SNR at the input , due to the fact that circuits always add to the noise in a system. The Noise Factor, at a specified input frequency, is defined as the ratio of the total Noise Power per unit bandwidth available at the output port when noise temperature of the input termination is standard (290 K) to that portion of engendered at the input frequency by the input termination. NoiseFactor_F = (Available_Output_Noise_Power) / (Available_Output_Noise_due_to_Source) The maximum Noise Figure of the receiver when is given the required Sensitivity and the required Bandwidth: Receiver_Noise_Figure[dB] = 174 + Receiver_Sensitivity[dBm] 10*LOG(BW[Hz]) SNR[dB] As can be seen from the formula above, narrow Bandwidth and smaller SNR will relax the required receiver Noise Figure requirements. When designing circuits for use with extremely weak signals, noise is an important consideration. The noise contribution of each device in the signal path must be low enough that it will not significantly degrade the Signal to Noise Ratio. Noise found in a microwave system can be generated from external sources, or the system itself.

The Noise level of a system sets the lower limit on the magnitude of a signal that can be detected in the presence of the noise. So, to achieve the best performance you need to have a minimum residual noise level. Noise Figure is used to describe the noise contribution of a device. An ideal amplifier would have no noise of its own, but would simply amplify what went in to it. For example a 10dB amplifier would amplify the Signal (and the Noise) at its input by 10dB. Therefore, although the noise floor at the output of the amplifier would be 10dB higher than at the input.

The ideal noiseless" amplifier would not change the Signal to Noise ratio (SNR). A "real world" amplifier will not amplify only the noise at its input, but will contribute its own noise to signal. This reduces the Signal to Noise ratio at the output of the amplifier. So, the "real world" amplifier has two major internal components: an "ideal noiseless" amplifier and a noise source. The noise source adds noise to any signal what enters to the amplifier and then the ideal amplifier amplifies the whole thing by an amount equal to its gain, with no noise contribution of its own.

For example a 10dB attenuator placed at the input of an amplifier will increase the total Noise Figure of the system with 10dB.

An attenuator placed at the input of a system will increase the total Noise Figure with the same amount of its attenuation. An attenuator placed at the input of a receiver would not affect the SNR if the level at its output is inside of the input dynamic range of the receiver.

As an example let's assume that we have an amplifier at room temperature with 10dB of gain which has only a matched resistor at its input and output. The noise at the input of the amplifier must be -174dBm/Hz. If the amplifier is known to have a 3dB NF, the internal noise source adds an equal noise to the input noise before amplification. Then 10dB of gain increases the noise by 10dB. Therefore, the noise at the output of the amplifier is 13dB higher than at the input, or (-174dBm/Hz + 10dB gain +3dB NF) = -161dBm/Hz.

The noise contribution of the amplifier's noise source is fixed and does not change with input signal. Therefore, when more noise is present at the amplifier input, the contribution of the internal noise source is less significant in comparison.

When the noise into an amplifier is higher than kTB (-174dBm/Hz), the amplifier 's Noise Figure plays a smaller role in the amplifier's noise contribution. The Noise Figure (NF) of a device is only calculated with the input noise level at kTB. The Noise Temperature at the output of an amplifier is the sum of the Noise Temperature of the source and the Noise Temperature of the amplifier itself multiplied by the Power Gain of the amplifier. Tout = G * ( Tampl + Tsource ) Tout = Noise Temperature at amplifier output in degrees Kelvin. G = Power Gain in linear scale not in dB. Tampl = Noise Temperature of amplifier. Tsource = Noise Temperature of source. The same formula is valid for attenuators. Tout = Gatt * ( Tatt + Tsource )

The Noise Figure of an attenuator is the same as the attenuation in dB. The Noise Figure of an attenuator preceding an amplifier is the Noise Figure of the amplifier plus the attenuation of the attenuator in dB.

If we use cascaded amplifiers:

For above example both amplifiers has 10dB gain and NF=3dB. The signal goes in at -40dBm with a noise floor at kTB (-174dBm/Hz). We can calculate that the signal at the output of the first amplifier is -30dBm and the noise is: (-174dBm/Hz input noise) + (10dB of gain) + (3dB NF) = -161dBm/Hz. Let see how many kTBs are entering in the second amplifier: (-161dBm/Hz) is 13dB greater than kTB (-174dBm). 13dB is a power ratio of 20x. So, the noise floor at the second amplifier is 20 times kTB or 20kTB. Next calculate how many kTBs are added by the noise source of the second amplifier (in this case, 1kTB because the NF=3dB). Finally calculate the increase in noise floor at the second amplifier as a ratio and convert to dB.

Ratio of (input noise floor) + (added noise) to (input noise floor) is: (20kTB+1kTB) / (20kTB) = 20/21 In dB = 10LOG (21/20) = 0.21dB Therefore, the second amplifier only increases the noise floor by 0.21dB even though it has a noise figure of 3dB, simply because the noise floor at its input is significantly higher than kTB. The first amplifier degrades the signal to noise ratio by 3dB, while the second amplifier degrades it only 0.21dB. When amplifiers are cascaded together in order to amplify very weak signals, it is generally the first amplifier in the chain which will have the greatest influence upon the signal to noise ratio because the noise floor is lowest at that point in the chain. Determining the total Noise Figure of a chain of amplifiers (or other devices): NFactor_total = NFact1 + (NFact2-1)/G1 + (NFact3-1)/(G1*G2) + (NFact3-1)/(G1*G2*.Gn-1) where NFactor = Noise factor of each stage (Linear not in dB). Noise Figure[dB] = 10*LOG(NFactor) G = Gain of each stage as a ratio, not dB (for example 4x, not 6dB)

The first amplifier in a chain has the most significant effect on the total noise figure than any other amplifier in the chain. The lower noise figure amplifier should usually go first in a line of amplifiers (assuming all else is equal). If we have two amplifiers with equal gain, but with different noise figures. Assume 10dB gain in each amplifier. One amp is NF = 3dB and the other 6dB. When the 3dB NF amplifier is first in cascade, the total noise figure, the total NF is 3.62dB. When the 6dB amplifier is first, the total NF is 6.3dB. This also applies to gain.

If two amplifiers have the same Noise Figure but different gains, the higher gain amplifier should precede the lower gain amplifier to achieve the best overall Noise Nigure. The overall Noise Factor of an infinite number of identical cascaded amplifiers is: NFactor_total = 1 + M with: M = (F-1) / [1 - (1/G)] where: F is Noise_Factor(linear) of each stage, and G is Gain(linear) of each stage. NoiseFigure_total[dB] = 10*LOG (NFactor_total(linear))

Noise Figure of a Device The Noise Figure of a device is the degradation in the Signal to Noise Ratio (SNR) as a signal passes through the device. The equation of the Noise Figure of a device adopted by the IEEE (Institute of Electrical and Electronics Engineers) is: Device NF[dB] = 10*LOG [(Na + k*To*B*G) / (k*To*B*G)] Na=Added Noise Power [W], To =290K, B=Bandwidth[Hz], G=Gain[Linear not dB] , k=Boltzman ct. Therefore, the Noise Figure of a device is the ratio of the total Noise Power at the output, to that portion of the Noise Power at the output due to noise at the input when the input source temperature is 290Kelvin. The Noise Figure of a device is independent of the signal level as long as the device is linear (output power vs. input power). Equivalent Input Noise Temperature Initially used in Satellite Receivers, the Equivalent Input Noise Temperature (Te), is used to describe the noise performance of a device rather than the Noise Figure. Te is the Equivalent Temperature of a source impedance into a perfect (noiseless) device that would produce the same Added Noise Power (Na). Te is mostly used as a system parameter, and is defined as: Te = Na / (k*G*B) the relation with the Noise Factor (F) is: Te = To (F-1) F = 1 + (Te / To) For example a device with 0.5dB Noise Figure (Noise Factor, F = 1.12), at To = 290k, would have an Equivalent Input Noise Temperature, Te = 35.4k Resulting noise temperature referred to the input (Teq) of cascaded stages is given by: Teq = T1 + (T2/G1) + [T3/ (G1*G2)] + .. Noise temperature (in Kelvin) of each component in the cascade is: T(1,2,3) = To (F(1,2,3) 1) Power gain (Linear not dB) of each component in the cascade is: G1,2,3 The Noise Figure of the cascade is: NF[dB] = 10*LOG [1+ (Teq / To)] In Satellite and Space Receiving Systems, the noise level coming from the antenna can be very low, limited by the ground noise (due to the side-lobe radiation of the antenna), and by the background sky temperature (with values often below 100k). In these situations, small changes in the Noise Figure of the receiving system may result in much more change of the Signal to Noise Ratio (SNR).

Noise Figure of Other Devices

All the devices which process a signal contribute noise and thus have noise figure. Amplifiers, Mixers, transistors, diodes, etc all have noise figures. For example, RF attenuators have a Noise Figure floor equal to their attenuation value. A 10dB pad has a 10dB NF. If a signal enters in a pad and the noise floor is at -174 dBm/Hz the signal is attenuated by 10dB while the noise floor remains constantly (it cannot get any lower than -174 dBm/Hz at room temperature). Therefore the signal to noise ratio through the pad is degraded by 10dB. Like amplifiers, if the noise floor is above kTB, the signal to noise ratio degradation of the pad will be less than its noise figure. The Radiation Resistance of the antenna does not convert power to heat, and so is not a source of thermal noise. The load impedance of the input of the receiver does not contribute directly to receive noise. Therefore, it is indeed possible, and even common, for a receiver to have a Noise Factor of less than 2x (or equivalently, a Noise Figure of less than 3dB). Types of Noise sources There are several types of noise sources in electrical circuits. However, we discuss only three important noise sources here. 1. Thermal or Johnson - Nyquist Noise 2. Shot Noise 3. 1/f Noise (Also called Flicker or Pink noise) 4. White Noise 5. Burst Noise

1. Thermal Noise This is the noise generated by thermal agitation of electrons in a conductor. Also called Johnson-Nyquist Noise, is the random white noise (flat with frequency) generated by thermal agitation of electrons in a conductor or electronic device. It is produced by the thermal agitation of the charges in an electric conductor and is proportional to the absolute temperature of the conductor. It manifests itself in the input circuits of audio equipment such as microphone pre amps, or antenna input of a receiver, where the signal levels are low. The Thermal Noise level is the limiting minimum noise any circuit can attain at a given temperature.

Note that thermal Noise Power, per Hertz, is equal throughout the frequency spectrum, depends only on k and T. Thermal noise in the resistance of the signal source is the fundamental limit on achievable signal sensitivity. Thermal Noise has a Gaussian amplitude distribution in the time domain and is evenly distributed across the spectrum. Thermal noises spectral breadth and its sources ubiquity lead it to dominate other noise types in many applications. 2. Shot Noise Shot Noise normally occurs when there is a potential barrier (voltage differential). PN junction diode is an example that has potential barrier. When the electrons and holes cross the barrier, Shot Noise is produced. For example, a diode, a transistor, and vacuum tube, all will produce Shot noise. A junction diode will typically have two components of noise. One is Thermal Noise, and the other is Shot Noise. Note that if the active device provides amplification, the noise also gets amplified along with the signal. On the other hand, a resistor normally does not produce Shot Noise since there is no potential barrier built within a resistor. Current flowing through a resistor will not exhibit any fluctuations. However, current flowing through a diode produces small fluctuations. This is due to electrons (in turn, the charge) arriving in quanta, one electron at a time. The current flow is not continuous, but limited by the quantum of the electron charges. Shot Noise is proportional to the current passing through the device. Shot Noise characteristic is white. 3. Flicker Noise - 1/f (one-over-f) Noise Flicker Noise is found in many natural phenomena such as nuclear radiation, electron flow through a conductor, or even in the environment. In electrical engineering, it is called also 1/f (one-over-f) Noise. Flicker Noise is associated with crystal surface defects in semiconductors and is also found in vacuum tubes due to the oxide coating on the cathode. The noise power is proportional to the bias current, and, unlike Thermal and Shot Noise, Flicker Noise decreases with frequency. An exact mathematical model does not exist for flicker noise because it is so device-specific. However, the inverse proportionality with frequency is almost exactly 1/f for low frequencies, whereas for frequencies above a few kilohertz, the noise power is weak but essentially flat. Flicker Noise is essentially random, but because its frequency spectrum is not flat, it is not a white noise. It is often referred to as pink noise because most of the power is concentrated at the lower end of the frequency spectrum. Flicker Noise is more prominent in FETs (smaller the channel length, greater the Flicker Noise), and in bulky carbon resistors. The objection to carbon resistors mentioned earlier for critical low noise applications is due to their tendency to produce flicker noise when carrying a direct current. In this connection, metal film resistors are a better choice for low frequency, low noise applications. Flicker Noise is usually defined by the corner frequency fc, point where Flicker Noise is equal with White Noise.

Under typical operating conditions, precision bipolar processes offer the lowest 1/f corners: around 1Hz to 10Hz. The corner for devices fabricated in high-frequency bipolar processes is often 1Hz to 10kHz. The1/f corner frequency in MOSFETs goes as the reciprocal of the channel length, with typical values of 100kHz to 1MHz, and even up to 1GHz for latest nano-meter channel length processes. Devices built on III-V processes, such as GaAs FET's and Indium-Gallium-Phosphorous HBT, offer extremely wide bandwidths but yield higher frequency 1/f corners in the region of 100 MHz. 4. White Noise White Noise is the noise that has constant magnitude of power over frequency. Examples of White Noise are Thermal Noise, and Shot Noise. 5. Burst Noise Burst Noise or Popcorn Noise is another low frequency noise that seems to be associated with heavy metal ion contamination. Measurements show a sudden shift in the bias current level that lasts for a short duration before suddenly returning to the initial state. Such a randomly occurring discrete level burst would have a popping sound if amplified in an audio system. Like Flicker Noise, Popcorn Noise is very device specific, so a mathematical model is not very useful. However, this noise increases with bias current level and is inversely proportional to the square of the frequency 1/f2. Noise reduction strategies Noise is a serious problem, especially where low signal levels are experienced, there are a number of common sense approaches to minimize the effects of noise on a system. In this section we will examine several of these methods.

Keep the source resistance and the amplifier input resistance as low as possible. Using high value resistances will increase thermal noise voltage. Total thermal noise is a function of the bandwidth of the circuit. Therefore, reducing the bandwidth of the circuit to a minimum will also minimize noise. There is also a requirement to match the bandwidth to the frequency response required for the input signal. Prevent external noise from affecting the performance of the system by appropriate use of grounding, shielding and filtering. Use a Low Noise Amplifier (LNA) in the input stage of the system. For some semiconductor circuits, use the lowest DC power supply potentials that will do the job. At the transistor level, device noise can be sensed and reduced with negative feedback. Current fluctuations in the transistor contribute to phase and amplitude noise. An unbypassed emitter resistor (RE ~10..30 ohms) reduces noise, but further noise improvement is achieved by sensing the emitter current and feeding back a signal to the base terminal. Successful PM and AM noise reduction of 20 dB has been demonstrated.

 At higher frequencies, the feedback capacitance of the device couples the shot noise of the base/collector junction (BJT) or thermal noise of the channel resistance (MOSFET) to the input and contributes to frequency-dependent noise. Optimum noise matching is achieved with BJTs in applications requiring low source resistance, whereas MOSFETs become viable for high source resistance applications.

References: 1. Friis, H.T., Noise Figures of Radio Receivers, Proc. Of the IRE, July, 1944, pp 419-422. 2. RF Design Magazine, 1988-2000 3. Microwave Journal, 1998-2000 4. Applied Microwave Magazine, 1995-2000 5. RF Components and Circuits - J.Carr 6. Device Noise in Silicon RF Technologies - S. Martin, V. Archer, D. Boulin 7. Fundamentals of RF and Microwave Noise Figure Measurements App.Note 57-1 - Agilent http://www.qsl.net/va3iul