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516

IEEE Indicon 2005 Conference, Chennai, India, 11-13 Dec. 2005

Neural

Network Based Control of Reduced Rating

DSTATCOM

Bhim Singhl, Jitendra Solankil and Vishal Verma2


Abstract - This paper presents a DSTATCOM controlled by a neural network based reference current extractor (NNREC) and rating reduction by use of shunt connected capacitor bank for three-phase three-wire system. The working of DSTATCOM with self supported dc bus is used in two different modes; one is, unity power factor (UPF) mode and second is, zero voltage regulation (ZVR) mode. The hear-t of the control of DSTATCOM is the derivation of reference currents, which decide the switching of three legs of voltage source inverter (VSI) used in DSTATCOM. The NNRCE is used for control of DSTATCOM, which operates on LMS algorithm. The real positive sequence current component of current is extracted using NNRCE without any phase shift. A PI controller is used to regulate the voltage across the capacitor connected at the dc bus of the VSI. In the ac voltage regulation mode, second P1 controller is used to maintain the constant voltage at PCC with variation of load. To reduce the rating of DSTATCOM, an ac capacitor bank of almost half rating of the VAR required is connected at the load end. The simulations are carried out in MATLAB environment for unity power factor operation and ac voltage regulation through leading power factor operation. Simulation results verify the effectiveness of the DSTATCOM system to meet the requirements of distribution system Keywords - DSTATCOM, Power-Factor Correction, voltage Regulation, Rating Reduction.

1. INTRODUCTION
T he problems such as reactive power burden, unbalance loading and voltage regulation in electrical power distribution system, are very well known [1]. The reactive power burden increases line losses and affects the loading capability. The problem of voltage regulation is also very grave as sensitive loads like computers, medical and telecommunication equipments etc, which need substantially constant voltage [2]. The use of capacitor bank for reactive power compensation is well known but the metlhod lacks flexibility in case of varying reactive power demand. Further due to FelTanti effect the voltage at PCC may go very high at light load conditions. These capacitor banks do not cater the problein of load balancing. With the advent of custom power de'Departnent of Electrical Engineering, IIT Delhi, New Delhi, India,
email: bsinghlee.iitd.ernet.in & ejitendra@yahoo.com

vice technology, the concept of DSTATCOM has appeared, which has served the purpose of dynamic reactive power compensation. With a few modifications, DSTATCOM can also be used for load balancing and voltage regulation. The method of generation of reference signals is a major issue which affects the performance of the DSTATCOM. Instantaneous reactive power theory, modified p-q theory, synchronous reference frame theory, instantaneous id-iq theory and method for estimation of current reference by maintaining constant dc link voltage of DSTATCOM are generally reported in literature for estimation ofreference signals [3, 4]. Estimation based on neural network is also reported in literature [5]. Reported control schemes envisage complex control and do not compensate the ripples or delay realized in computation of reference signals, and the neural network based scheme requires off-line training of weights for a set of loads. This paper deals withi the control of DSTATCOM for load balancing with unity power factor (U-PF) or zero voltage regulation (ZVR) modes anid to reduce the rating of DSTATCOM using ac capacitor banks. In UPF mode, DSTATCOM supplies reactive power just sufficient to operate the system at unity power factor. However for ac voltage regulation, the DSTATCOM supplies some extra amount of reactive power than the need of load, this extra reactive power goes to utility and system to compensate the line drop. The performance of DSTATCOM system depends upon how the reference currents are extracted for control of DSTATCOM. Together with indirect current control, proposed control scheme uses a fast adaptive linear element (Adaline) based nieural network reference current extractor, which extracts the real positive sequence current component without any phase shift [6-7]. The estimation of the reference current through Adaline utilizes LMS algorithm for continuous online calculation of weights [8]. For maintaining the constant voltage at dc bus of DSTATCOM, a closed loop PI controller is used. The performance of the DSTATCOM system is studied through simulation under MATLAB environment anid the results verify the effectiveness and the dynanmics of the scheme during varying load conditions.

2Department of Electrical Engineering, Delhi College of Engineering, New Delhi, Inidia, email: vishalvermal@hotinail.com
07803-9503-4/05/$20.00 02005 IEEE

11. SYSTEM CONFIGURATION Fig. I shows the basic block diagram of the D)STATCOM system witlh resistive-iniductive load connected to the distri-

IEEE Indicon 2005 Conference, Chennai, India, 1 1-13 Dec. 2005 bution lines. DSTATCOM is represented by the voltage source inverter (VSI) with dc bus capacitor. The switching of this VSI is decided using hysteresis current controller. It controls source currents to follow the reference currents. The reference currents are extracted by the neural network based reference current generator and PI controllers take care of maintaining constant dc bus voltage and ac voltage regulaZs

517

The control algorithm estimates based on the proposed theory requires unit vector template corresponding to fundamental positive sequence component of current in phase with phase voltage waveform. For proper estimation of components of load current unit voltages templates must be undistorted and can be represented as: Vp (t) =Usinot (2)
In case of voltage being distorted, the zero crossing of phase voltage is detected to generate sinusoid (sincot) vector template, synchronized with ac mains. The signal is generated from look-up table by adjustment of delay to track the change

'sa
s

| |b.

XLb
1 0

Isc

~~~~~~~~~Load

Vdc ~~~~~~

Lr

TT

in frequency of the ac mains. The initial estimates of active and reactive part of current on single-phase basis can be chosen as:

ip(t) Wpvp(t)
=

(3)

Neural-Network Estimator and PI

can be represented in terms of voltage and current given as:

where weight (Wp) is estimated using Adaline. The weight

Vsa Vsb Vs Vdc 1a ILb Il.e Fig. 1. Basic block diagram of the system with D-STATCOM.

t t I JT

controllers

Wp=I1cosqp1U

(4)

tion. To reduce the rating of DSTATCOM, an ac capacitor bank is connected at the load end. Each branch of the capacitor bank is provided with a small damping resistor to avoid its interaction with source and DSTATCOM. The related component values are given in Table I.
Table I: System Parameters Supply condition Line to line voltage 400V
Zs

The weight is variable and changes as per the load current and magnitude of phase voltage. The scheme for estimating weights corresponding to fundamental frequency real component of current (for three-phase system), based on LMS algorithm tuned Adaline tracks the unit vector templates to maintain minimum error[ 10]. The estimation of weight is given as per the following iterations:
Wp(k+l)WPW(k)+st{iL(k)-W,(k)vP(k)}vp(k)

(5)

Frequency

50Hz

5.0%

Load
Max kVA rating 10k 0kVAat 0.78 PF DSTATCOM

The value of i (convergence coefficient) decides the rate of convergence and accuracy of estimation. The practical range of convergence coefficient lies from 0.1 to 1.0. Three-phase reference currents corresponding to positive sequence real component may be computed as:

DC Link Capacitor Interfacing Inductor AC Capacitor Bank

9400iF 9.0mH

i, (t) = W+ sinwt

ipb (t) = Wp sin(Oft-1200)


i + (t) = W+ sin(mt-2400)

(6)

Capacitance per P TheORY

1II. BASIC THEORY


The load current consists of activ e current (ip), reactive current (iq) for positive sequence and negative sequence current (i-) can be decomposed in parts as:
+ i, (I.)+i-(t) il (t) i'(t) p
=

Wp =(W,,+Wp,+Wp,Y)f3

(7)

For proper estimation of reference signals, the weights are averaged to compute the equivalent weight for positive sequence and negative sequence current component in the decomposed. form. The averaging of weights helps in removing the unbalance froni the current components. hlese estim(ated reference cUITents are ujtilized to switch the VSI (..f

518

IEEE Indicon 2005 Conference, Chennai, India, 11-13 Dec. 2005

DSTATCOM through a hysteresis current controller by forcing the source currents to follow these reference three-phase currents. Fig.2a shows the basic control scheme for unity power factor mode of operation. The output signal given by PI controller to maintain the constant dc bus voltage is added to the average weight. Fig.2b shows the basic control scheme for ac voltage regulation mode of operation. The output signal
Refeec

capacitor bank on the rating of required DSTATCOM, which is reduced due to part of reactive power supplied by ac capacitor bank. By supplying the reactive power to the source (i.e. operating at leading power factor) the variation of system rms voltage is minimized through DSTATCOM in voltage regulation mode as shown in Fig.4a. Results are obtained for similar load and
^

Ig.V5

20

20
200

.20
12
018

Timesec.)

04

03

Fig.3a Dynamic performance of DSTATCOM without ac capacitor bank in UPF mode for load change (38kW to 71kW) at t=0. 12s, for operation under unbalance from t=0. 1 8s to t=0.24s similar dynamics in rever sequence henceforth from t=0.24s to t=0.36s.

(b)

Fig. 2 Control scheme (a) for unity power factor mode of operation (b) for voltage regulation mode of operation

given by PI controller is multiplied by the unit templates quadrature with phase voltage and added to the real reference current component calculated using neural network.

IV. RESULTS AND DISCUSSION


The operation of DSTATCOM under unity power factor operation without using capacitor bank is shown in Fig.3a. To demonstrate the dynamic behaviour of the DSTATCOM controlled by NNRCE, the load is increased and decreased in steps respectively at time t=0. 12 sec and t=0.30 sec. It can be seen easily that within half cycle of sine wave, DSTSTCOM is able to responds to the load current changes. For demonstrating the response ofDSTATCOM to the unbalance condition, at t=0. 18 sec load unbalanced is created in the system. It can be seen from Fig.3a that source current is still at unity power factor and balanced. Fig. 3b shows the effect of an ac
I

0.

0.12

018

0.24

0.3

Fig.3b Dynamic performnance of DSTATCOM with ac capacitor bank in UPF mode for load change (38kW to 71kW) at t=0.12s, for operation under unbalance from t=O. 1 8s to t-0.24s similar dynamics in reverse sequence henceforth from t=0.24s to t=0.36s

source conditions without any capacitor bank in ZVR mode and similar load perturbations as in UPF made is simulated.

IEEE Indicon 2005 Conference, Chennai, India, 11-13 Dec. 2005

519

Fig.4b shows the effect of insertion of an ac capacitor bank in the system when the DSTATCOM is working in ZVR mode. The capacitor bank reduces the rating of DSTATCOM.

duced to nearly 70% (from 91kVA to 64kVA) for ZVR mode due to coordinated operation with ac capacitor bank.

V. CONCLUSION
The effectiveness of the DSTATCOM with the proposed NNREC control technique has been demonstrated to meet severe load change and unbalance conditions. Further the aspect of rating reduction by use of shunt connected capacitor bank together with flexibility of operation under UPF mode or ZVR mode has been validated through simulation results. The rating reduction of DSTATCOM is an important feature as it not only reduces the cost of the system but also gives freedom to operate with power electronic devises like IGBT for high power application at higher PWM switching frequency. As the online calculation of weights has been performed, the proposed scheme envisages nearly zero phase shift to extract the reference current with simplicity. The indirect current control alongwith Neural Network based extraction has no need of any feed forward compensation for the delay caused by LC ripple filter.
Table II: Power rating of load, source and DSTATCOM under balanced 3-phase full load operation without ac capacitor bank Unity power factor Voltag reguation correction mode mode
Load

r 0

00

000

a
03

012

0.18

04.

Fig. 4a Dynamic performance of DSTATCOM without ac capacitor bank in zero voltage regulation (ZVR) mode for load change (38kW to 71kW) at t=0. 12s, for operation under unbalance from t=0. 1 8s to t=0.24s similar dynamics in reverse sequence henceforth from t==0.24s to t=0.36s.

3o

DSTATCOM

Source

kW kVAR kVA 71 5 91

72

77

-57

72 7

kW kVAR kVA 82 63 103

83
1

-28
-91

88

00

Table III: Power rating of load, source and DSTATCOM under balanced 3-phase full load operation with ac capacitor bank Unity power fictor Voltage regulation
Load Source DSTATCOM comtction mode kW kVAR kVA 71 57 91 72 0 72 57 1 -57

kW
1
82 83

mode

kVAR kVA 63 103

-91

-28

88

REFERENCES
0.10
0 A

sec.)

Fig.

4b

Dynamic performance of DSTATCOM without


zero

ac

capacitor

bank under

voltage regulation (ZVR)


dynamics in
to

mode for load

change (38kW to 71kW) at t,0. 12s, for operation under unbalance

from t=0.

8s to tI0.24s similar

reverse

sequence

henceforth

from

t==0.24s

tD0.36s

The rating

of DSTATCOM for balanced load condition


an

without and with

ac

capacitor bank

for UPF

ZVR mode is given in Table II and Table III. An inference can be drawn very easily that rating of DSTATCOM reduces to nearly 56% (from 57kVA to 32kVA) for UPF mode and re-

mode and

[1] A. Ghosh and G.Ledwich, Power quality enhancement using custom power devices, London, Kluwer Academic Publishers, 2002. [2] S.Y. Jung, T.H. Kim, S. I1 Moon and B. M. Han, "Analysis and Control of DSTATCOM for a line voltage regulation," Proc. IEEE Power Engineering Society Winter Meeting, 2002, Vol. 2, pp.729 - 734. [3] B. Singh, K. Al-Haddad, A. Chandra, "A review of active power filters for power quality improvement," IEEE Trans. Industrial Electronics. Vol. 46, No 5, October 1999, pp. 960-97 1. [4] H. Akagi, Y. Kanazawa and A. Nabae "Generalized theory of the instantaneous reactive power in three-plhase circuits," Proc. IEEE & JIEE IPEC Tokyo, 1983, pp. 821-827.

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2005 -- -- - 1 1-13 - Dec. IEEE Indicon 2005 Conference, - - --- I India, -I Chennai,
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[5] N. Pechanranin, H Uitsui and M. Sone, "Harmonic detection by using neural network," Proc. IEEE Conf. on Neural Network, vol 2, 1995, pp. 923-926. [6] B. Singh, V. Verma and J. Solanki, "Active power filter selective compensation of current using neural network" Proc. IEEE ISIE'04, May 2004, CD copy.

[7] B. Singh, V. Verma, J. Solanki., A. Chandra and K. Al Haddad, "Neural network controlled power conditioner with battery energy storage feature for isolated offshore power system" Proc. IEEE PCIC'04, Nov. 2004, pp. 127-133. [8] B. Widrow, J.M. McCool and M. Ball, "The complex LMS algorithm," Proc. IEEE 1975, vol. 63, pp-719-720.

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