DESIGN OF CMOS ANALOG INTEGRATED CIRCUITS

Franco Maloberti Integrated Microsistems Laboratory University of Pavia

CMOS COMPARATORS
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PERFORMANCE CHARACTERISTICS
A comparator detect when its input is larger or smaller than a reference voltage. Its output is a large voltage with an appropriate sign.
vin vref + vout

vref

vin

The output is assumed to represent a digital 1or 0 level.

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PERFORMANCE
Voltage gain: is the DC differential gain of the comparator. The output peak-to-peak swing is in the range of 3-5 V. Therefore, for low speed, in order to detect a 1 mV signal a voltage gain of 5000 is sufficient. Input offset: is the voltage that must be applied to the input to get the transition between the low and the high state (same as the op-amp).
8

Response time: is the time interval between the application of a step input and the time when the output reaches the respective logic level. The response time depends on the amplitude of the step input.

Response Time [nsec]

7 6 5 4 3 0 2 4 6 8 Input Step Amplitude [mV] 10

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Overdrive recovery time: if the input is driven with a voltage larger than the one required to cause the output saturation, the comparator is over driven. The response time for a given input amplitude, depends on the value of the overdrive voltage at which the comparator was driven.
2 mV vov 50
Response Time [nsec]

40 30 20 10 0 0 20 40 60 80 100 Overdrive Voltage [mV] 120

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Latching compatibility. A latch command and an unlatch command stores and releases the output logic state. Typically the load set-up time is around 2 nsec. Power supply rejection. Transfer function between the supply rails and the output of the comparator. Power consumption. Power dissipated at DC (static) and during the comparison (dynamic). Hysteresis. The threshold voltage for rising input signals is different from the threshold voltage for falling input signals.

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BASIC CONSIDERATION
A comparator is basically an open loop gain stage. The required DC gain is 80 dB (sometime more). Key points: Gain obtained by the use of complex schemes or by the use of the cascade of simple schemes. How to do Vos cancellation. Power supply rejection. Overdrive recovery. Power consumption
All solution are strongly conditioned by the offset cancellation (Vos 3 - 10 mV).
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Comparator Gain: Due to the finite bandwidth of the circuit, the output voltage reaches AvVin with a delay with respect to the time when the input is applied (response time tr).
1,0 0,8 0,6 0,4 0,2 0,0 0 tr 1 2 time (arbitrary scale) 3 4 Av vin

The same output voltage is get, with the same response time, by the use of stages having different speed but different DC gain.
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Single stage: if:

t = RL CL
+ Out gm vi

V out = g m R L V i ( 1 e

t ( RL CL )

gm -t ) V i -----CL

RL

CL

The speed is increase by increasing gm/CL. typically: gm = 0.5 mA/V CL = 0.5 pF Hence, the gain after a delay of 10 nsec is 10.

gm/CL = 1/nsec

An improvement is get by the use of a chain of identical stages. Under the same assumption:
V out g m n t - ---= V in ----- C L n!
6/8 n

F. Maloberti: Design of CMOS Analog Integrated Circuits - CMOS Comparators

For a given gain, it exists an optimum number of stages which gives the best response time. For example: a very small gain is reached using one only stage with a response time t1 smaller than the one obtained with a chain of n identical gain stages. For a given gain an optimum n results:
(n + 1) A n = ------------------n! CL t n = ( n + 1 ) -----gm
n

n An

4.5

10.6

26

64.8

163

416

1067

2755
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F. Maloberti: Design of CMOS Analog Integrated Circuits - CMOS Comparators

OFFSET CANCELLATION
Autozero technique Autozero in multistage comparators Differential schemes Compensation by auxiliary input stages

AUTOZERO TECHNIQUE
Basic idea:
sample the offset during one phase and sum it to the signal during the measure phase.
vx 2 + + S/H 1 vin + vos v out

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Two phase are required:

Phase 1: Autozero Phase 2: Measure

1 t 2 t 0 T

Time domain analysis:

if the offset changes slowly Vos(0) Vos(T)

V in ( T ) = V + ( T ) V - ( T ) = V os ( T ) ( V x ( T ) V os ( 0 ) )

Frequency domain analysis (Laplace Transform):

V in ( s ) = V x ( s ) + V os ( s ) ( 1 e F os ( s ) = 1 e
sT sT

Fos(f)

)
1

= 2je

sT 2

sin ( sT 2 )
0 0.0 0.25 0.5

fT 0.75

The low freq.of the offset are cancelled.

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Autozero in single stage, implementation:

S1 vx S3 2 1 S2 vos + 1 vout

During phase 1 the gain stage is in unity gain closed-loop conguration. During phase1 C acts as an output load of the gain stage. During phase 2 the gain stage is in open loop conguration.
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 The nite gain Av of the gain stage produces a residual offset error
V os, res Av 1 - = V os --------------= V os V os --------------1 + Av 1 + Av

Exists the problem of the clock feedthrough at the opening of S1; it

determines an equivalent offset error (Vos,ck).
1 V os, res = V os --------------- + V os, ck 1 + Av

If the complex gain stages are used it is worth to compensate the stage only during the autozero phase.
S1 S3 Vi 2 1 S2 C + Vos S4 1 Vout 1

CC

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Clock feedthrough and signal attenuation:

S1 vx S3 2 1 S2 Cin vos + 1 C v out

The charge injected by the switch S1 is integrated onto C and the input capacitance of the gain stage. The input signal is attenuated by the factor C/(C + Cin). In order to reduce the attenuation and the equivalent offset [Vos,ck = Qck/(C + Cin)] C must be chosen large and >> Cin
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Autozero in multistage comparators:

S1 1 vx 2 1 S3 C1 A1 C2 A2 A3 An S2 1

A = A1A2......An

The offset of the third stage is referred to the input attenuated by the
factor A1A2. Usually its contribution is negligible.

The clock feedthrough from S1 and S2 causes the rising of two

equivalent offset voltages, Vos,1 and Vos,2 at the input of A1 and A2. The resulting input offset is:
1 V os = V os, 1 + ------ V os, 2 A1
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Improved solution (sequential offset and feedthrough cancellation): Drive S1 with 1 and S2, S3 with 1

The charge injected by S1 is collected on C2, the equivalent offset is amplied by A1. Since S2 is still on, the output voltage of A1 is sampled and stored onto C2. An autozero of the effect of Vos,1 results.
The offset becomes:
1 V os = ------ V os, 2 A1

Vos,1 and Vos,2 must be such to not saturate A1 and A2 (gain of A1 and A2 low, suitable values of C1 and C2).
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Implementation:
Each gain stage can be implemented with a CMOS Inverter : (Av = 5 - 20)
M2 in 2 1 C1 1 M1 C2 1 M3 M5 M7 M4 M6 M8 out

Differential schemes:
S1 1 1 V out+ + C 1 1 S2 V out-

The clock feedthrough due to the opening of S1 and S2 gives a common mode signal. Its effect is cancelled. Residual offset is due to the mismatching.

C Vin VR 2 2

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Fully differential blocks:

Very low gain Low gain with CMFB Conventional fully differential amplier

Very low gain: Advantage:

M3 M4 out M2

CMFB not necessary

M1 in

Disadvantage:
The capacitance Cgs of the loads M3 and M4 act as load of the output.

I1

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Low gain with CMFB:

M3 M4 VB1 out M1 in M2

Low capacitive load at the output

1 -C -+ ....... 2 gs, A

VB2 MA MB

Two bias lines

M3 M4 VB1 M7 M9 M1 in M11 VB2 M5 M6 M8 M12 M2 M10 Out

Improved solution:
Minimum capacitive load at
the nodes A and B.

Low impedance output. Optionally the CMFB stage

can be used as gain stage with single ended output.

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Compensation by auxiliary input stages:

Basic idea: store the offset at the output of the gain stage and use it in feedback connection to cancel the input offset.
A1 + S1 1 vos,1 + + S2 1 A2 + vos,2 CAZ Out

During phase 1 the inputs of A1 are short circuited. The output of A1 goes to A1Vos,1
A 1 V os, 1 + A 2 ( V os, 2 V o ) = V o A1 A2 -V -V + --------------V o = --------------1 + A 2 os, 1 1 + A 2 os, 2
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Referred to the input of A1, the equivalent offset is:

V eq, os V os, 1 V os, 2 = --------------- + ------------1 + A2 A1

The switch at the input of A1, S1 is opened while S2 is closed. The offset, caused by charge injection from S1, is attenuated by (1 + A2). When the switch S2 is opened the charge that it inject is collected onto CAZ and an offset Vos,inj appears. It is amplied by A2 and appears at the output; it is equivalent to an input offset equal to:
A2 V in, os = V os, inj ------ A 1

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gm1 gm6 in order to have A1 10 A2

VB1

M3

M4 out M2 M7 aux in

M1 in

M6

M8 VB2 M5

Degenerated current mirror:

M10 M3 M4 M11

J No additional supply current L Bad PSRR

+ in _

M1

M2 Out

M5

M6

M7 VB2 M9

aux in M8

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LATCHES
A comparator can be followed by a latch. The input can be differential or
single ended; in the latter case one of the inputs can be replaced by a reference voltage.
M3 VB 1 out in + M1 strobe M7 M5 M6 M2 M4 2 out + in -

During 1 M1, M3 and M2, M4 form two inverters with active load. The
parasitic capacitances incident nodes 1 and 2 are pre-charged to a logic signals.
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 During 2 the latch is enabled and it assumes a stable state.

strobe M6

M3 out -

M4 out + M2

in +

M1

in -

VB

M5

Typically: latching time 2- 10 nsec with Vin = 10 mV

When 1 comes along, the output voltages will both try to rise. Because
of the difference in input voltages one is faster and starts the regenerative action.
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M7 strobe out strobe M5 M6 M8 M9

M10 strobe

out + strobe

in + M1

M2

M3 M4

in -

J Strobed at the drain: carrier mobility faster at zero substrate bias. J Small load capacitance of the ip-op.
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Combination gain stage / latch:

M3 VB2 M4 out out +

in in +

M7

M7

M6

M7

strobe

M5

M8

strobe

VB1

M9

When the strobe signal is down, the gain stage pre-charge the parasitic capacitances of the latch, when the strobe goes up, starts the regenerative action of the latch.
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Combination gain stage / latch with double regenerative loop and output flip-flop:
M20 Vb
strobe

M3

M4

M10

M11 M12

M13 M14

M15

M1 M2 Vin Vin+

M5 strobe M7

M6 M16 M17

M8

M9

M18

Vout+ Vout

M19

When the latch signal is on, the bias current is switched from the gain stage to the latch.
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POWER CONSUMPTION
Comparator gain including offset compensation and output latch
1 2 Vi 1 Vin

Cin

A1
+

A2 gm, 1 Vin C1
+

gm, 2 Vo C2

The voltage swing at the output of the rst stage is

g m, 1 t - V (t) dt V o(t) = ----------C1 i
0

The voltage swing at the output of the second stage is:

g m, 2 t - V (t) dt V out(t) = ----------C2 o
0

F. Maloberti: Design of CMOS Analog Integrated Circuits - CMOS Comparators

Latch

Vo

Vout

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 For constant or slowly varying signal at the end of the comparison phase ( / fck) the output voltage Vout is
1 g m, 1 g m, 2 2 - ------ V -----------------------V out = -2 i C 1 C 2 f ck

Theoretical minimum of power consumption MOS transistors in strong inversion ( ID > Ilim )
gm = 2 C ox I D W ---------------------------nL

MOS transistors in weak inversion ( ID < Ilim )

gm qI D = --------nkT

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 The limit between strong and weak inversion is

I lim W kT 2 - -----= 2n C oc ---L q

If the input voltage of a gain stage exceeds the critical value V crit = nkT q or ( V GS V th ) 2 the output current saturates to the maximum value ID To achieve a given Vout the current in the second stage must be
V out C 2 f ck I D, 2 > ------------------------

j The current in the rst stage can be obtained from

V crit C 1 f ck g m, 1 > ------------------------V i, min

for

V i, min < V crit

or
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F. Maloberti: Design of CMOS Analog Integrated Circuits - CMOS Comparators

V crit C 1 f ck I D, 1 > ------------------------

for

V i, min > V crit

j Theoretical minimum of power consumption In practical cases security margins have to be taken into account

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CONCLUSIONS
Key issues in comparator design j Optimization of the number of stages to achieve the desired

response time with a given power consumption

j Offset cancellation Autozero technique j Clock feedthrough, power supply and common mode rejection ratios Fully differential structures j Overdrive recovery Limit the voltage swing at critical nodes or when possible introduce a reset phase

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